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Linux 2.6.26-rc1
[cris-mirror.git] / drivers / ata / ahci.c
blob8cace9aa9c0398bafe101115ba511bb5dd29f0fb
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <scsi/scsi_host.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <linux/libata.h>
48
49 #define DRV_NAME "ahci"
50 #define DRV_VERSION "3.0"
51
52 static int ahci_skip_host_reset;
53 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
54 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
55
56 static int ahci_enable_alpm(struct ata_port *ap,
57 enum link_pm policy);
58 static void ahci_disable_alpm(struct ata_port *ap);
59
60 enum {
61 AHCI_PCI_BAR = 5,
62 AHCI_MAX_PORTS = 32,
63 AHCI_MAX_SG = 168, /* hardware max is 64K */
64 AHCI_DMA_BOUNDARY = 0xffffffff,
65 AHCI_MAX_CMDS = 32,
66 AHCI_CMD_SZ = 32,
67 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
68 AHCI_RX_FIS_SZ = 256,
69 AHCI_CMD_TBL_CDB = 0x40,
70 AHCI_CMD_TBL_HDR_SZ = 0x80,
71 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
72 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
73 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
74 AHCI_RX_FIS_SZ,
75 AHCI_IRQ_ON_SG = (1 << 31),
76 AHCI_CMD_ATAPI = (1 << 5),
77 AHCI_CMD_WRITE = (1 << 6),
78 AHCI_CMD_PREFETCH = (1 << 7),
79 AHCI_CMD_RESET = (1 << 8),
80 AHCI_CMD_CLR_BUSY = (1 << 10),
81
82 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
83 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
84 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
85
86 board_ahci = 0,
87 board_ahci_vt8251 = 1,
88 board_ahci_ign_iferr = 2,
89 board_ahci_sb600 = 3,
90 board_ahci_mv = 4,
91 board_ahci_sb700 = 5,
92
93 /* global controller registers */
94 HOST_CAP = 0x00, /* host capabilities */
95 HOST_CTL = 0x04, /* global host control */
96 HOST_IRQ_STAT = 0x08, /* interrupt status */
97 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
98 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
99
100 /* HOST_CTL bits */
101 HOST_RESET = (1 << 0), /* reset controller; self-clear */
102 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
103 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
104
105 /* HOST_CAP bits */
106 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
107 HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
108 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
109 HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */
110 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
111 HOST_CAP_SNTF = (1 << 29), /* SNotification register */
112 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
113 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
114
115 /* registers for each SATA port */
116 PORT_LST_ADDR = 0x00, /* command list DMA addr */
117 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
118 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
119 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
120 PORT_IRQ_STAT = 0x10, /* interrupt status */
121 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
122 PORT_CMD = 0x18, /* port command */
123 PORT_TFDATA = 0x20, /* taskfile data */
124 PORT_SIG = 0x24, /* device TF signature */
125 PORT_CMD_ISSUE = 0x38, /* command issue */
126 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
127 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
128 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
129 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
130 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
131
132 /* PORT_IRQ_{STAT,MASK} bits */
133 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
134 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
135 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
136 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
137 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
138 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
139 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
140 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
141
142 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
143 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
144 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
145 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
146 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
147 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
148 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
149 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
150 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
151
152 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
153 PORT_IRQ_IF_ERR |
154 PORT_IRQ_CONNECT |
155 PORT_IRQ_PHYRDY |
156 PORT_IRQ_UNK_FIS |
157 PORT_IRQ_BAD_PMP,
158 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
159 PORT_IRQ_TF_ERR |
160 PORT_IRQ_HBUS_DATA_ERR,
161 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
162 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
163 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
164
165 /* PORT_CMD bits */
166 PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */
167 PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */
168 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
169 PORT_CMD_PMP = (1 << 17), /* PMP attached */
170 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
171 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
172 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
173 PORT_CMD_CLO = (1 << 3), /* Command list override */
174 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
175 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
176 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
177
178 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
179 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
180 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
181 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
182
183 /* hpriv->flags bits */
184 AHCI_HFLAG_NO_NCQ = (1 << 0),
185 AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */
186 AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */
187 AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */
188 AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */
189 AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */
190 AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */
191 AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */
192 AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */
193
194 /* ap->flags bits */
195
196 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
197 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
198 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN |
199 ATA_FLAG_IPM,
200
201 ICH_MAP = 0x90, /* ICH MAP register */
202 };
203
204 struct ahci_cmd_hdr {
205 __le32 opts;
206 __le32 status;
207 __le32 tbl_addr;
208 __le32 tbl_addr_hi;
209 __le32 reserved[4];
210 };
211
212 struct ahci_sg {
213 __le32 addr;
214 __le32 addr_hi;
215 __le32 reserved;
216 __le32 flags_size;
217 };
218
219 struct ahci_host_priv {
220 unsigned int flags; /* AHCI_HFLAG_* */
221 u32 cap; /* cap to use */
222 u32 port_map; /* port map to use */
223 u32 saved_cap; /* saved initial cap */
224 u32 saved_port_map; /* saved initial port_map */
225 };
226
227 struct ahci_port_priv {
228 struct ata_link *active_link;
229 struct ahci_cmd_hdr *cmd_slot;
230 dma_addr_t cmd_slot_dma;
231 void *cmd_tbl;
232 dma_addr_t cmd_tbl_dma;
233 void *rx_fis;
234 dma_addr_t rx_fis_dma;
235 /* for NCQ spurious interrupt analysis */
236 unsigned int ncq_saw_d2h:1;
237 unsigned int ncq_saw_dmas:1;
238 unsigned int ncq_saw_sdb:1;
239 u32 intr_mask; /* interrupts to enable */
240 };
241
242 static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
243 static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
244 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
245 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
246 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
247 static int ahci_port_start(struct ata_port *ap);
248 static void ahci_port_stop(struct ata_port *ap);
249 static void ahci_qc_prep(struct ata_queued_cmd *qc);
250 static void ahci_freeze(struct ata_port *ap);
251 static void ahci_thaw(struct ata_port *ap);
252 static void ahci_pmp_attach(struct ata_port *ap);
253 static void ahci_pmp_detach(struct ata_port *ap);
254 static int ahci_softreset(struct ata_link *link, unsigned int *class,
255 unsigned long deadline);
256 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
257 unsigned long deadline);
258 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
259 unsigned long deadline);
260 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
261 unsigned long deadline);
262 static void ahci_postreset(struct ata_link *link, unsigned int *class);
263 static void ahci_error_handler(struct ata_port *ap);
264 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
265 static int ahci_port_resume(struct ata_port *ap);
266 static void ahci_dev_config(struct ata_device *dev);
267 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl);
268 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
269 u32 opts);
270 #ifdef CONFIG_PM
271 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
272 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
273 static int ahci_pci_device_resume(struct pci_dev *pdev);
274 #endif
275
276 static struct device_attribute *ahci_shost_attrs[] = {
277 &dev_attr_link_power_management_policy,
278 NULL
279 };
280
281 static struct scsi_host_template ahci_sht = {
282 ATA_NCQ_SHT(DRV_NAME),
283 .can_queue = AHCI_MAX_CMDS - 1,
284 .sg_tablesize = AHCI_MAX_SG,
285 .dma_boundary = AHCI_DMA_BOUNDARY,
286 .shost_attrs = ahci_shost_attrs,
287 };
288
289 static struct ata_port_operations ahci_ops = {
290 .inherits = &sata_pmp_port_ops,
291
292 .qc_defer = sata_pmp_qc_defer_cmd_switch,
293 .qc_prep = ahci_qc_prep,
294 .qc_issue = ahci_qc_issue,
295 .qc_fill_rtf = ahci_qc_fill_rtf,
296
297 .freeze = ahci_freeze,
298 .thaw = ahci_thaw,
299 .softreset = ahci_softreset,
300 .hardreset = ahci_hardreset,
301 .postreset = ahci_postreset,
302 .pmp_softreset = ahci_softreset,
303 .error_handler = ahci_error_handler,
304 .post_internal_cmd = ahci_post_internal_cmd,
305 .dev_config = ahci_dev_config,
306
307 .scr_read = ahci_scr_read,
308 .scr_write = ahci_scr_write,
309 .pmp_attach = ahci_pmp_attach,
310 .pmp_detach = ahci_pmp_detach,
311
312 .enable_pm = ahci_enable_alpm,
313 .disable_pm = ahci_disable_alpm,
314 #ifdef CONFIG_PM
315 .port_suspend = ahci_port_suspend,
316 .port_resume = ahci_port_resume,
317 #endif
318 .port_start = ahci_port_start,
319 .port_stop = ahci_port_stop,
320 };
321
322 static struct ata_port_operations ahci_vt8251_ops = {
323 .inherits = &ahci_ops,
324 .hardreset = ahci_vt8251_hardreset,
325 };
326
327 static struct ata_port_operations ahci_p5wdh_ops = {
328 .inherits = &ahci_ops,
329 .hardreset = ahci_p5wdh_hardreset,
330 };
331
332 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
333
334 static const struct ata_port_info ahci_port_info[] = {
335 /* board_ahci */
336 {
337 .flags = AHCI_FLAG_COMMON,
338 .pio_mask = 0x1f, /* pio0-4 */
339 .udma_mask = ATA_UDMA6,
340 .port_ops = &ahci_ops,
341 },
342 /* board_ahci_vt8251 */
343 {
344 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
345 .flags = AHCI_FLAG_COMMON,
346 .pio_mask = 0x1f, /* pio0-4 */
347 .udma_mask = ATA_UDMA6,
348 .port_ops = &ahci_vt8251_ops,
349 },
350 /* board_ahci_ign_iferr */
351 {
352 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
353 .flags = AHCI_FLAG_COMMON,
354 .pio_mask = 0x1f, /* pio0-4 */
355 .udma_mask = ATA_UDMA6,
356 .port_ops = &ahci_ops,
357 },
358 /* board_ahci_sb600 */
359 {
360 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
361 AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_MSI |
362 AHCI_HFLAG_SECT255 | AHCI_HFLAG_NO_PMP),
363 .flags = AHCI_FLAG_COMMON,
364 .pio_mask = 0x1f, /* pio0-4 */
365 .udma_mask = ATA_UDMA6,
366 .port_ops = &ahci_ops,
367 },
368 /* board_ahci_mv */
369 {
370 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
371 AHCI_HFLAG_MV_PATA),
372 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
373 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
374 .pio_mask = 0x1f, /* pio0-4 */
375 .udma_mask = ATA_UDMA6,
376 .port_ops = &ahci_ops,
377 },
378 /* board_ahci_sb700 */
379 {
380 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
381 AHCI_HFLAG_NO_PMP),
382 .flags = AHCI_FLAG_COMMON,
383 .pio_mask = 0x1f, /* pio0-4 */
384 .udma_mask = ATA_UDMA6,
385 .port_ops = &ahci_ops,
386 },
387 };
388
389 static const struct pci_device_id ahci_pci_tbl[] = {
390 /* Intel */
391 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
392 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
393 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
394 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
395 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
396 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
397 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
398 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
399 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
400 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
401 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
402 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
403 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
404 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
405 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
406 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
407 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
408 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
409 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
410 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
411 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
412 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
413 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
414 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
415 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
416 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
417 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
418 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
419 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
420 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
421 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
422
423 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
424 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
425 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
426
427 /* ATI */
428 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
429 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
430 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
431 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
432 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
433 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
434 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
435
436 /* VIA */
437 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
438 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
439
440 /* NVIDIA */
441 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */
442 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */
443 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */
444 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */
445 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */
446 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */
447 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */
448 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */
449 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
450 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
451 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
452 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
453 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
454 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
455 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
456 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
457 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
458 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
459 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
460 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
461 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */
462 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */
463 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */
464 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */
465 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */
466 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */
467 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */
468 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */
469 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */
470 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */
471 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */
472 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */
473 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
474 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
475 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
476 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
477 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
478 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
479 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
480 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
481 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
482 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
483 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
484 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
485 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci }, /* MCP79 */
486 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci }, /* MCP79 */
487 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci }, /* MCP79 */
488 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci }, /* MCP79 */
489 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */
490 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */
491 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */
492 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */
493 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */
494 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */
495 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */
496 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */
497 { PCI_VDEVICE(NVIDIA, 0x0bc8), board_ahci }, /* MCP7B */
498 { PCI_VDEVICE(NVIDIA, 0x0bc9), board_ahci }, /* MCP7B */
499 { PCI_VDEVICE(NVIDIA, 0x0bca), board_ahci }, /* MCP7B */
500 { PCI_VDEVICE(NVIDIA, 0x0bcb), board_ahci }, /* MCP7B */
501 { PCI_VDEVICE(NVIDIA, 0x0bcc), board_ahci }, /* MCP7B */
502 { PCI_VDEVICE(NVIDIA, 0x0bcd), board_ahci }, /* MCP7B */
503 { PCI_VDEVICE(NVIDIA, 0x0bce), board_ahci }, /* MCP7B */
504 { PCI_VDEVICE(NVIDIA, 0x0bcf), board_ahci }, /* MCP7B */
505 { PCI_VDEVICE(NVIDIA, 0x0bd0), board_ahci }, /* MCP7B */
506 { PCI_VDEVICE(NVIDIA, 0x0bd1), board_ahci }, /* MCP7B */
507 { PCI_VDEVICE(NVIDIA, 0x0bd2), board_ahci }, /* MCP7B */
508 { PCI_VDEVICE(NVIDIA, 0x0bd3), board_ahci }, /* MCP7B */
509
510 /* SiS */
511 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
512 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
513 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
514
515 /* Marvell */
516 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
517 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
518
519 /* Generic, PCI class code for AHCI */
520 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
521 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
522
523 { } /* terminate list */
524 };
525
526
527 static struct pci_driver ahci_pci_driver = {
528 .name = DRV_NAME,
529 .id_table = ahci_pci_tbl,
530 .probe = ahci_init_one,
531 .remove = ata_pci_remove_one,
532 #ifdef CONFIG_PM
533 .suspend = ahci_pci_device_suspend,
534 .resume = ahci_pci_device_resume,
535 #endif
536 };
537
538
539 static inline int ahci_nr_ports(u32 cap)
540 {
541 return (cap & 0x1f) + 1;
542 }
543
544 static inline void __iomem *__ahci_port_base(struct ata_host *host,
545 unsigned int port_no)
546 {
547 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
548
549 return mmio + 0x100 + (port_no * 0x80);
550 }
551
552 static inline void __iomem *ahci_port_base(struct ata_port *ap)
553 {
554 return __ahci_port_base(ap->host, ap->port_no);
555 }
556
557 static void ahci_enable_ahci(void __iomem *mmio)
558 {
559 int i;
560 u32 tmp;
561
562 /* turn on AHCI_EN */
563 tmp = readl(mmio + HOST_CTL);
564 if (tmp & HOST_AHCI_EN)
565 return;
566
567 /* Some controllers need AHCI_EN to be written multiple times.
568 * Try a few times before giving up.
569 */
570 for (i = 0; i < 5; i++) {
571 tmp |= HOST_AHCI_EN;
572 writel(tmp, mmio + HOST_CTL);
573 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
574 if (tmp & HOST_AHCI_EN)
575 return;
576 msleep(10);
577 }
578
579 WARN_ON(1);
580 }
581
582 /**
583 * ahci_save_initial_config - Save and fixup initial config values
584 * @pdev: target PCI device
585 * @hpriv: host private area to store config values
586 *
587 * Some registers containing configuration info might be setup by
588 * BIOS and might be cleared on reset. This function saves the
589 * initial values of those registers into @hpriv such that they
590 * can be restored after controller reset.
591 *
592 * If inconsistent, config values are fixed up by this function.
593 *
594 * LOCKING:
595 * None.
596 */
597 static void ahci_save_initial_config(struct pci_dev *pdev,
598 struct ahci_host_priv *hpriv)
599 {
600 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
601 u32 cap, port_map;
602 int i;
603 int mv;
604
605 /* make sure AHCI mode is enabled before accessing CAP */
606 ahci_enable_ahci(mmio);
607
608 /* Values prefixed with saved_ are written back to host after
609 * reset. Values without are used for driver operation.
610 */
611 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
612 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
613
614 /* some chips have errata preventing 64bit use */
615 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
616 dev_printk(KERN_INFO, &pdev->dev,
617 "controller can't do 64bit DMA, forcing 32bit\n");
618 cap &= ~HOST_CAP_64;
619 }
620
621 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
622 dev_printk(KERN_INFO, &pdev->dev,
623 "controller can't do NCQ, turning off CAP_NCQ\n");
624 cap &= ~HOST_CAP_NCQ;
625 }
626
627 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
628 dev_printk(KERN_INFO, &pdev->dev,
629 "controller can't do PMP, turning off CAP_PMP\n");
630 cap &= ~HOST_CAP_PMP;
631 }
632
633 /*
634 * Temporary Marvell 6145 hack: PATA port presence
635 * is asserted through the standard AHCI port
636 * presence register, as bit 4 (counting from 0)
637 */
638 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
639 if (pdev->device == 0x6121)
640 mv = 0x3;
641 else
642 mv = 0xf;
643 dev_printk(KERN_ERR, &pdev->dev,
644 "MV_AHCI HACK: port_map %x -> %x\n",
645 port_map,
646 port_map & mv);
647
648 port_map &= mv;
649 }
650
651 /* cross check port_map and cap.n_ports */
652 if (port_map) {
653 int map_ports = 0;
654
655 for (i = 0; i < AHCI_MAX_PORTS; i++)
656 if (port_map & (1 << i))
657 map_ports++;
658
659 /* If PI has more ports than n_ports, whine, clear
660 * port_map and let it be generated from n_ports.
661 */
662 if (map_ports > ahci_nr_ports(cap)) {
663 dev_printk(KERN_WARNING, &pdev->dev,
664 "implemented port map (0x%x) contains more "
665 "ports than nr_ports (%u), using nr_ports\n",
666 port_map, ahci_nr_ports(cap));
667 port_map = 0;
668 }
669 }
670
671 /* fabricate port_map from cap.nr_ports */
672 if (!port_map) {
673 port_map = (1 << ahci_nr_ports(cap)) - 1;
674 dev_printk(KERN_WARNING, &pdev->dev,
675 "forcing PORTS_IMPL to 0x%x\n", port_map);
676
677 /* write the fixed up value to the PI register */
678 hpriv->saved_port_map = port_map;
679 }
680
681 /* record values to use during operation */
682 hpriv->cap = cap;
683 hpriv->port_map = port_map;
684 }
685
686 /**
687 * ahci_restore_initial_config - Restore initial config
688 * @host: target ATA host
689 *
690 * Restore initial config stored by ahci_save_initial_config().
691 *
692 * LOCKING:
693 * None.
694 */
695 static void ahci_restore_initial_config(struct ata_host *host)
696 {
697 struct ahci_host_priv *hpriv = host->private_data;
698 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
699
700 writel(hpriv->saved_cap, mmio + HOST_CAP);
701 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
702 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
703 }
704
705 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
706 {
707 static const int offset[] = {
708 [SCR_STATUS] = PORT_SCR_STAT,
709 [SCR_CONTROL] = PORT_SCR_CTL,
710 [SCR_ERROR] = PORT_SCR_ERR,
711 [SCR_ACTIVE] = PORT_SCR_ACT,
712 [SCR_NOTIFICATION] = PORT_SCR_NTF,
713 };
714 struct ahci_host_priv *hpriv = ap->host->private_data;
715
716 if (sc_reg < ARRAY_SIZE(offset) &&
717 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
718 return offset[sc_reg];
719 return 0;
720 }
721
722 static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
723 {
724 void __iomem *port_mmio = ahci_port_base(ap);
725 int offset = ahci_scr_offset(ap, sc_reg);
726
727 if (offset) {
728 *val = readl(port_mmio + offset);
729 return 0;
730 }
731 return -EINVAL;
732 }
733
734 static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
735 {
736 void __iomem *port_mmio = ahci_port_base(ap);
737 int offset = ahci_scr_offset(ap, sc_reg);
738
739 if (offset) {
740 writel(val, port_mmio + offset);
741 return 0;
742 }
743 return -EINVAL;
744 }
745
746 static void ahci_start_engine(struct ata_port *ap)
747 {
748 void __iomem *port_mmio = ahci_port_base(ap);
749 u32 tmp;
750
751 /* start DMA */
752 tmp = readl(port_mmio + PORT_CMD);
753 tmp |= PORT_CMD_START;
754 writel(tmp, port_mmio + PORT_CMD);
755 readl(port_mmio + PORT_CMD); /* flush */
756 }
757
758 static int ahci_stop_engine(struct ata_port *ap)
759 {
760 void __iomem *port_mmio = ahci_port_base(ap);
761 u32 tmp;
762
763 tmp = readl(port_mmio + PORT_CMD);
764
765 /* check if the HBA is idle */
766 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
767 return 0;
768
769 /* setting HBA to idle */
770 tmp &= ~PORT_CMD_START;
771 writel(tmp, port_mmio + PORT_CMD);
772
773 /* wait for engine to stop. This could be as long as 500 msec */
774 tmp = ata_wait_register(port_mmio + PORT_CMD,
775 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
776 if (tmp & PORT_CMD_LIST_ON)
777 return -EIO;
778
779 return 0;
780 }
781
782 static void ahci_start_fis_rx(struct ata_port *ap)
783 {
784 void __iomem *port_mmio = ahci_port_base(ap);
785 struct ahci_host_priv *hpriv = ap->host->private_data;
786 struct ahci_port_priv *pp = ap->private_data;
787 u32 tmp;
788
789 /* set FIS registers */
790 if (hpriv->cap & HOST_CAP_64)
791 writel((pp->cmd_slot_dma >> 16) >> 16,
792 port_mmio + PORT_LST_ADDR_HI);
793 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
794
795 if (hpriv->cap & HOST_CAP_64)
796 writel((pp->rx_fis_dma >> 16) >> 16,
797 port_mmio + PORT_FIS_ADDR_HI);
798 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
799
800 /* enable FIS reception */
801 tmp = readl(port_mmio + PORT_CMD);
802 tmp |= PORT_CMD_FIS_RX;
803 writel(tmp, port_mmio + PORT_CMD);
804
805 /* flush */
806 readl(port_mmio + PORT_CMD);
807 }
808
809 static int ahci_stop_fis_rx(struct ata_port *ap)
810 {
811 void __iomem *port_mmio = ahci_port_base(ap);
812 u32 tmp;
813
814 /* disable FIS reception */
815 tmp = readl(port_mmio + PORT_CMD);
816 tmp &= ~PORT_CMD_FIS_RX;
817 writel(tmp, port_mmio + PORT_CMD);
818
819 /* wait for completion, spec says 500ms, give it 1000 */
820 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
821 PORT_CMD_FIS_ON, 10, 1000);
822 if (tmp & PORT_CMD_FIS_ON)
823 return -EBUSY;
824
825 return 0;
826 }
827
828 static void ahci_power_up(struct ata_port *ap)
829 {
830 struct ahci_host_priv *hpriv = ap->host->private_data;
831 void __iomem *port_mmio = ahci_port_base(ap);
832 u32 cmd;
833
834 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
835
836 /* spin up device */
837 if (hpriv->cap & HOST_CAP_SSS) {
838 cmd |= PORT_CMD_SPIN_UP;
839 writel(cmd, port_mmio + PORT_CMD);
840 }
841
842 /* wake up link */
843 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
844 }
845
846 static void ahci_disable_alpm(struct ata_port *ap)
847 {
848 struct ahci_host_priv *hpriv = ap->host->private_data;
849 void __iomem *port_mmio = ahci_port_base(ap);
850 u32 cmd;
851 struct ahci_port_priv *pp = ap->private_data;
852
853 /* IPM bits should be disabled by libata-core */
854 /* get the existing command bits */
855 cmd = readl(port_mmio + PORT_CMD);
856
857 /* disable ALPM and ASP */
858 cmd &= ~PORT_CMD_ASP;
859 cmd &= ~PORT_CMD_ALPE;
860
861 /* force the interface back to active */
862 cmd |= PORT_CMD_ICC_ACTIVE;
863
864 /* write out new cmd value */
865 writel(cmd, port_mmio + PORT_CMD);
866 cmd = readl(port_mmio + PORT_CMD);
867
868 /* wait 10ms to be sure we've come out of any low power state */
869 msleep(10);
870
871 /* clear out any PhyRdy stuff from interrupt status */
872 writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
873
874 /* go ahead and clean out PhyRdy Change from Serror too */
875 ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
876
877 /*
878 * Clear flag to indicate that we should ignore all PhyRdy
879 * state changes
880 */
881 hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;
882
883 /*
884 * Enable interrupts on Phy Ready.
885 */
886 pp->intr_mask |= PORT_IRQ_PHYRDY;
887 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
888
889 /*
890 * don't change the link pm policy - we can be called
891 * just to turn of link pm temporarily
892 */
893 }
894
895 static int ahci_enable_alpm(struct ata_port *ap,
896 enum link_pm policy)
897 {
898 struct ahci_host_priv *hpriv = ap->host->private_data;
899 void __iomem *port_mmio = ahci_port_base(ap);
900 u32 cmd;
901 struct ahci_port_priv *pp = ap->private_data;
902 u32 asp;
903
904 /* Make sure the host is capable of link power management */
905 if (!(hpriv->cap & HOST_CAP_ALPM))
906 return -EINVAL;
907
908 switch (policy) {
909 case MAX_PERFORMANCE:
910 case NOT_AVAILABLE:
911 /*
912 * if we came here with NOT_AVAILABLE,
913 * it just means this is the first time we
914 * have tried to enable - default to max performance,
915 * and let the user go to lower power modes on request.
916 */
917 ahci_disable_alpm(ap);
918 return 0;
919 case MIN_POWER:
920 /* configure HBA to enter SLUMBER */
921 asp = PORT_CMD_ASP;
922 break;
923 case MEDIUM_POWER:
924 /* configure HBA to enter PARTIAL */
925 asp = 0;
926 break;
927 default:
928 return -EINVAL;
929 }
930
931 /*
932 * Disable interrupts on Phy Ready. This keeps us from
933 * getting woken up due to spurious phy ready interrupts
934 * TBD - Hot plug should be done via polling now, is
935 * that even supported?
936 */
937 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
938 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
939
940 /*
941 * Set a flag to indicate that we should ignore all PhyRdy
942 * state changes since these can happen now whenever we
943 * change link state
944 */
945 hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG;
946
947 /* get the existing command bits */
948 cmd = readl(port_mmio + PORT_CMD);
949
950 /*
951 * Set ASP based on Policy
952 */
953 cmd |= asp;
954
955 /*
956 * Setting this bit will instruct the HBA to aggressively
957 * enter a lower power link state when it's appropriate and
958 * based on the value set above for ASP
959 */
960 cmd |= PORT_CMD_ALPE;
961
962 /* write out new cmd value */
963 writel(cmd, port_mmio + PORT_CMD);
964 cmd = readl(port_mmio + PORT_CMD);
965
966 /* IPM bits should be set by libata-core */
967 return 0;
968 }
969
970 #ifdef CONFIG_PM
971 static void ahci_power_down(struct ata_port *ap)
972 {
973 struct ahci_host_priv *hpriv = ap->host->private_data;
974 void __iomem *port_mmio = ahci_port_base(ap);
975 u32 cmd, scontrol;
976
977 if (!(hpriv->cap & HOST_CAP_SSS))
978 return;
979
980 /* put device into listen mode, first set PxSCTL.DET to 0 */
981 scontrol = readl(port_mmio + PORT_SCR_CTL);
982 scontrol &= ~0xf;
983 writel(scontrol, port_mmio + PORT_SCR_CTL);
984
985 /* then set PxCMD.SUD to 0 */
986 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
987 cmd &= ~PORT_CMD_SPIN_UP;
988 writel(cmd, port_mmio + PORT_CMD);
989 }
990 #endif
991
992 static void ahci_start_port(struct ata_port *ap)
993 {
994 /* enable FIS reception */
995 ahci_start_fis_rx(ap);
996
997 /* enable DMA */
998 ahci_start_engine(ap);
999 }
1000
1001 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
1002 {
1003 int rc;
1004
1005 /* disable DMA */
1006 rc = ahci_stop_engine(ap);
1007 if (rc) {
1008 *emsg = "failed to stop engine";
1009 return rc;
1010 }
1011
1012 /* disable FIS reception */
1013 rc = ahci_stop_fis_rx(ap);
1014 if (rc) {
1015 *emsg = "failed stop FIS RX";
1016 return rc;
1017 }
1018
1019 return 0;
1020 }
1021
1022 static int ahci_reset_controller(struct ata_host *host)
1023 {
1024 struct pci_dev *pdev = to_pci_dev(host->dev);
1025 struct ahci_host_priv *hpriv = host->private_data;
1026 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1027 u32 tmp;
1028
1029 /* we must be in AHCI mode, before using anything
1030 * AHCI-specific, such as HOST_RESET.
1031 */
1032 ahci_enable_ahci(mmio);
1033
1034 /* global controller reset */
1035 if (!ahci_skip_host_reset) {
1036 tmp = readl(mmio + HOST_CTL);
1037 if ((tmp & HOST_RESET) == 0) {
1038 writel(tmp | HOST_RESET, mmio + HOST_CTL);
1039 readl(mmio + HOST_CTL); /* flush */
1040 }
1041
1042 /* reset must complete within 1 second, or
1043 * the hardware should be considered fried.
1044 */
1045 ssleep(1);
1046
1047 tmp = readl(mmio + HOST_CTL);
1048 if (tmp & HOST_RESET) {
1049 dev_printk(KERN_ERR, host->dev,
1050 "controller reset failed (0x%x)\n", tmp);
1051 return -EIO;
1052 }
1053
1054 /* turn on AHCI mode */
1055 ahci_enable_ahci(mmio);
1056
1057 /* Some registers might be cleared on reset. Restore
1058 * initial values.
1059 */
1060 ahci_restore_initial_config(host);
1061 } else
1062 dev_printk(KERN_INFO, host->dev,
1063 "skipping global host reset\n");
1064
1065 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
1066 u16 tmp16;
1067
1068 /* configure PCS */
1069 pci_read_config_word(pdev, 0x92, &tmp16);
1070 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1071 tmp16 |= hpriv->port_map;
1072 pci_write_config_word(pdev, 0x92, tmp16);
1073 }
1074 }
1075
1076 return 0;
1077 }
1078
1079 static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
1080 int port_no, void __iomem *mmio,
1081 void __iomem *port_mmio)
1082 {
1083 const char *emsg = NULL;
1084 int rc;
1085 u32 tmp;
1086
1087 /* make sure port is not active */
1088 rc = ahci_deinit_port(ap, &emsg);
1089 if (rc)
1090 dev_printk(KERN_WARNING, &pdev->dev,
1091 "%s (%d)\n", emsg, rc);
1092
1093 /* clear SError */
1094 tmp = readl(port_mmio + PORT_SCR_ERR);
1095 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1096 writel(tmp, port_mmio + PORT_SCR_ERR);
1097
1098 /* clear port IRQ */
1099 tmp = readl(port_mmio + PORT_IRQ_STAT);
1100 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1101 if (tmp)
1102 writel(tmp, port_mmio + PORT_IRQ_STAT);
1103
1104 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1105 }
1106
1107 static void ahci_init_controller(struct ata_host *host)
1108 {
1109 struct ahci_host_priv *hpriv = host->private_data;
1110 struct pci_dev *pdev = to_pci_dev(host->dev);
1111 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1112 int i;
1113 void __iomem *port_mmio;
1114 u32 tmp;
1115 int mv;
1116
1117 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
1118 if (pdev->device == 0x6121)
1119 mv = 2;
1120 else
1121 mv = 4;
1122 port_mmio = __ahci_port_base(host, mv);
1123
1124 writel(0, port_mmio + PORT_IRQ_MASK);
1125
1126 /* clear port IRQ */
1127 tmp = readl(port_mmio + PORT_IRQ_STAT);
1128 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1129 if (tmp)
1130 writel(tmp, port_mmio + PORT_IRQ_STAT);
1131 }
1132
1133 for (i = 0; i < host->n_ports; i++) {
1134 struct ata_port *ap = host->ports[i];
1135
1136 port_mmio = ahci_port_base(ap);
1137 if (ata_port_is_dummy(ap))
1138 continue;
1139
1140 ahci_port_init(pdev, ap, i, mmio, port_mmio);
1141 }
1142
1143 tmp = readl(mmio + HOST_CTL);
1144 VPRINTK("HOST_CTL 0x%x\n", tmp);
1145 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1146 tmp = readl(mmio + HOST_CTL);
1147 VPRINTK("HOST_CTL 0x%x\n", tmp);
1148 }
1149
1150 static void ahci_dev_config(struct ata_device *dev)
1151 {
1152 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1153
1154 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1155 dev->max_sectors = 255;
1156 ata_dev_printk(dev, KERN_INFO,
1157 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1158 }
1159 }
1160
1161 static unsigned int ahci_dev_classify(struct ata_port *ap)
1162 {
1163 void __iomem *port_mmio = ahci_port_base(ap);
1164 struct ata_taskfile tf;
1165 u32 tmp;
1166
1167 tmp = readl(port_mmio + PORT_SIG);
1168 tf.lbah = (tmp >> 24) & 0xff;
1169 tf.lbam = (tmp >> 16) & 0xff;
1170 tf.lbal = (tmp >> 8) & 0xff;
1171 tf.nsect = (tmp) & 0xff;
1172
1173 return ata_dev_classify(&tf);
1174 }
1175
1176 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1177 u32 opts)
1178 {
1179 dma_addr_t cmd_tbl_dma;
1180
1181 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1182
1183 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1184 pp->cmd_slot[tag].status = 0;
1185 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1186 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1187 }
1188
1189 static int ahci_kick_engine(struct ata_port *ap, int force_restart)
1190 {
1191 void __iomem *port_mmio = ahci_port_base(ap);
1192 struct ahci_host_priv *hpriv = ap->host->private_data;
1193 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1194 u32 tmp;
1195 int busy, rc;
1196
1197 /* do we need to kick the port? */
1198 busy = status & (ATA_BUSY | ATA_DRQ);
1199 if (!busy && !force_restart)
1200 return 0;
1201
1202 /* stop engine */
1203 rc = ahci_stop_engine(ap);
1204 if (rc)
1205 goto out_restart;
1206
1207 /* need to do CLO? */
1208 if (!busy) {
1209 rc = 0;
1210 goto out_restart;
1211 }
1212
1213 if (!(hpriv->cap & HOST_CAP_CLO)) {
1214 rc = -EOPNOTSUPP;
1215 goto out_restart;
1216 }
1217
1218 /* perform CLO */
1219 tmp = readl(port_mmio + PORT_CMD);
1220 tmp |= PORT_CMD_CLO;
1221 writel(tmp, port_mmio + PORT_CMD);
1222
1223 rc = 0;
1224 tmp = ata_wait_register(port_mmio + PORT_CMD,
1225 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1226 if (tmp & PORT_CMD_CLO)
1227 rc = -EIO;
1228
1229 /* restart engine */
1230 out_restart:
1231 ahci_start_engine(ap);
1232 return rc;
1233 }
1234
1235 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1236 struct ata_taskfile *tf, int is_cmd, u16 flags,
1237 unsigned long timeout_msec)
1238 {
1239 const u32 cmd_fis_len = 5; /* five dwords */
1240 struct ahci_port_priv *pp = ap->private_data;
1241 void __iomem *port_mmio = ahci_port_base(ap);
1242 u8 *fis = pp->cmd_tbl;
1243 u32 tmp;
1244
1245 /* prep the command */
1246 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1247 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1248
1249 /* issue & wait */
1250 writel(1, port_mmio + PORT_CMD_ISSUE);
1251
1252 if (timeout_msec) {
1253 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1254 1, timeout_msec);
1255 if (tmp & 0x1) {
1256 ahci_kick_engine(ap, 1);
1257 return -EBUSY;
1258 }
1259 } else
1260 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1261
1262 return 0;
1263 }
1264
1265 static int ahci_check_ready(struct ata_link *link)
1266 {
1267 void __iomem *port_mmio = ahci_port_base(link->ap);
1268 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1269
1270 if (!(status & ATA_BUSY))
1271 return 1;
1272 return 0;
1273 }
1274
1275 static int ahci_softreset(struct ata_link *link, unsigned int *class,
1276 unsigned long deadline)
1277 {
1278 struct ata_port *ap = link->ap;
1279 int pmp = sata_srst_pmp(link);
1280 const char *reason = NULL;
1281 unsigned long now, msecs;
1282 struct ata_taskfile tf;
1283 int rc;
1284
1285 DPRINTK("ENTER\n");
1286
1287 /* prepare for SRST (AHCI-1.1 10.4.1) */
1288 rc = ahci_kick_engine(ap, 1);
1289 if (rc && rc != -EOPNOTSUPP)
1290 ata_link_printk(link, KERN_WARNING,
1291 "failed to reset engine (errno=%d)\n", rc);
1292
1293 ata_tf_init(link->device, &tf);
1294
1295 /* issue the first D2H Register FIS */
1296 msecs = 0;
1297 now = jiffies;
1298 if (time_after(now, deadline))
1299 msecs = jiffies_to_msecs(deadline - now);
1300
1301 tf.ctl |= ATA_SRST;
1302 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1303 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1304 rc = -EIO;
1305 reason = "1st FIS failed";
1306 goto fail;
1307 }
1308
1309 /* spec says at least 5us, but be generous and sleep for 1ms */
1310 msleep(1);
1311
1312 /* issue the second D2H Register FIS */
1313 tf.ctl &= ~ATA_SRST;
1314 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1315
1316 /* wait for link to become ready */
1317 rc = ata_wait_after_reset(link, deadline, ahci_check_ready);
1318 /* link occupied, -ENODEV too is an error */
1319 if (rc) {
1320 reason = "device not ready";
1321 goto fail;
1322 }
1323 *class = ahci_dev_classify(ap);
1324
1325 DPRINTK("EXIT, class=%u\n", *class);
1326 return 0;
1327
1328 fail:
1329 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
1330 return rc;
1331 }
1332
1333 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1334 unsigned long deadline)
1335 {
1336 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1337 struct ata_port *ap = link->ap;
1338 struct ahci_port_priv *pp = ap->private_data;
1339 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1340 struct ata_taskfile tf;
1341 bool online;
1342 int rc;
1343
1344 DPRINTK("ENTER\n");
1345
1346 ahci_stop_engine(ap);
1347
1348 /* clear D2H reception area to properly wait for D2H FIS */
1349 ata_tf_init(link->device, &tf);
1350 tf.command = 0x80;
1351 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1352
1353 rc = sata_link_hardreset(link, timing, deadline, &online,
1354 ahci_check_ready);
1355
1356 ahci_start_engine(ap);
1357
1358 if (online)
1359 *class = ahci_dev_classify(ap);
1360
1361 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1362 return rc;
1363 }
1364
1365 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
1366 unsigned long deadline)
1367 {
1368 struct ata_port *ap = link->ap;
1369 bool online;
1370 int rc;
1371
1372 DPRINTK("ENTER\n");
1373
1374 ahci_stop_engine(ap);
1375
1376 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1377 deadline, &online, NULL);
1378
1379 ahci_start_engine(ap);
1380
1381 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1382
1383 /* vt8251 doesn't clear BSY on signature FIS reception,
1384 * request follow-up softreset.
1385 */
1386 return online ? -EAGAIN : rc;
1387 }
1388
1389 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
1390 unsigned long deadline)
1391 {
1392 struct ata_port *ap = link->ap;
1393 struct ahci_port_priv *pp = ap->private_data;
1394 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1395 struct ata_taskfile tf;
1396 bool online;
1397 int rc;
1398
1399 ahci_stop_engine(ap);
1400
1401 /* clear D2H reception area to properly wait for D2H FIS */
1402 ata_tf_init(link->device, &tf);
1403 tf.command = 0x80;
1404 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1405
1406 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1407 deadline, &online, NULL);
1408
1409 ahci_start_engine(ap);
1410
1411 /* The pseudo configuration device on SIMG4726 attached to
1412 * ASUS P5W-DH Deluxe doesn't send signature FIS after
1413 * hardreset if no device is attached to the first downstream
1414 * port && the pseudo device locks up on SRST w/ PMP==0. To
1415 * work around this, wait for !BSY only briefly. If BSY isn't
1416 * cleared, perform CLO and proceed to IDENTIFY (achieved by
1417 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
1418 *
1419 * Wait for two seconds. Devices attached to downstream port
1420 * which can't process the following IDENTIFY after this will
1421 * have to be reset again. For most cases, this should
1422 * suffice while making probing snappish enough.
1423 */
1424 if (online) {
1425 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
1426 ahci_check_ready);
1427 if (rc)
1428 ahci_kick_engine(ap, 0);
1429 }
1430 return rc;
1431 }
1432
1433 static void ahci_postreset(struct ata_link *link, unsigned int *class)
1434 {
1435 struct ata_port *ap = link->ap;
1436 void __iomem *port_mmio = ahci_port_base(ap);
1437 u32 new_tmp, tmp;
1438
1439 ata_std_postreset(link, class);
1440
1441 /* Make sure port's ATAPI bit is set appropriately */
1442 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1443 if (*class == ATA_DEV_ATAPI)
1444 new_tmp |= PORT_CMD_ATAPI;
1445 else
1446 new_tmp &= ~PORT_CMD_ATAPI;
1447 if (new_tmp != tmp) {
1448 writel(new_tmp, port_mmio + PORT_CMD);
1449 readl(port_mmio + PORT_CMD); /* flush */
1450 }
1451 }
1452
1453 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1454 {
1455 struct scatterlist *sg;
1456 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1457 unsigned int si;
1458
1459 VPRINTK("ENTER\n");
1460
1461 /*
1462 * Next, the S/G list.
1463 */
1464 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1465 dma_addr_t addr = sg_dma_address(sg);
1466 u32 sg_len = sg_dma_len(sg);
1467
1468 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1469 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1470 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1471 }
1472
1473 return si;
1474 }
1475
1476 static void ahci_qc_prep(struct ata_queued_cmd *qc)
1477 {
1478 struct ata_port *ap = qc->ap;
1479 struct ahci_port_priv *pp = ap->private_data;
1480 int is_atapi = ata_is_atapi(qc->tf.protocol);
1481 void *cmd_tbl;
1482 u32 opts;
1483 const u32 cmd_fis_len = 5; /* five dwords */
1484 unsigned int n_elem;
1485
1486 /*
1487 * Fill in command table information. First, the header,
1488 * a SATA Register - Host to Device command FIS.
1489 */
1490 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1491
1492 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1493 if (is_atapi) {
1494 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1495 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1496 }
1497
1498 n_elem = 0;
1499 if (qc->flags & ATA_QCFLAG_DMAMAP)
1500 n_elem = ahci_fill_sg(qc, cmd_tbl);
1501
1502 /*
1503 * Fill in command slot information.
1504 */
1505 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1506 if (qc->tf.flags & ATA_TFLAG_WRITE)
1507 opts |= AHCI_CMD_WRITE;
1508 if (is_atapi)
1509 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1510
1511 ahci_fill_cmd_slot(pp, qc->tag, opts);
1512 }
1513
1514 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1515 {
1516 struct ahci_host_priv *hpriv = ap->host->private_data;
1517 struct ahci_port_priv *pp = ap->private_data;
1518 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1519 struct ata_link *link = NULL;
1520 struct ata_queued_cmd *active_qc;
1521 struct ata_eh_info *active_ehi;
1522 u32 serror;
1523
1524 /* determine active link */
1525 ata_port_for_each_link(link, ap)
1526 if (ata_link_active(link))
1527 break;
1528 if (!link)
1529 link = &ap->link;
1530
1531 active_qc = ata_qc_from_tag(ap, link->active_tag);
1532 active_ehi = &link->eh_info;
1533
1534 /* record irq stat */
1535 ata_ehi_clear_desc(host_ehi);
1536 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1537
1538 /* AHCI needs SError cleared; otherwise, it might lock up */
1539 ahci_scr_read(ap, SCR_ERROR, &serror);
1540 ahci_scr_write(ap, SCR_ERROR, serror);
1541 host_ehi->serror |= serror;
1542
1543 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1544 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1545 irq_stat &= ~PORT_IRQ_IF_ERR;
1546
1547 if (irq_stat & PORT_IRQ_TF_ERR) {
1548 /* If qc is active, charge it; otherwise, the active
1549 * link. There's no active qc on NCQ errors. It will
1550 * be determined by EH by reading log page 10h.
1551 */
1552 if (active_qc)
1553 active_qc->err_mask |= AC_ERR_DEV;
1554 else
1555 active_ehi->err_mask |= AC_ERR_DEV;
1556
1557 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1558 host_ehi->serror &= ~SERR_INTERNAL;
1559 }
1560
1561 if (irq_stat & PORT_IRQ_UNK_FIS) {
1562 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1563
1564 active_ehi->err_mask |= AC_ERR_HSM;
1565 active_ehi->action |= ATA_EH_RESET;
1566 ata_ehi_push_desc(active_ehi,
1567 "unknown FIS %08x %08x %08x %08x" ,
1568 unk[0], unk[1], unk[2], unk[3]);
1569 }
1570
1571 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
1572 active_ehi->err_mask |= AC_ERR_HSM;
1573 active_ehi->action |= ATA_EH_RESET;
1574 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1575 }
1576
1577 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1578 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1579 host_ehi->action |= ATA_EH_RESET;
1580 ata_ehi_push_desc(host_ehi, "host bus error");
1581 }
1582
1583 if (irq_stat & PORT_IRQ_IF_ERR) {
1584 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1585 host_ehi->action |= ATA_EH_RESET;
1586 ata_ehi_push_desc(host_ehi, "interface fatal error");
1587 }
1588
1589 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1590 ata_ehi_hotplugged(host_ehi);
1591 ata_ehi_push_desc(host_ehi, "%s",
1592 irq_stat & PORT_IRQ_CONNECT ?
1593 "connection status changed" : "PHY RDY changed");
1594 }
1595
1596 /* okay, let's hand over to EH */
1597
1598 if (irq_stat & PORT_IRQ_FREEZE)
1599 ata_port_freeze(ap);
1600 else
1601 ata_port_abort(ap);
1602 }
1603
1604 static void ahci_port_intr(struct ata_port *ap)
1605 {
1606 void __iomem *port_mmio = ahci_port_base(ap);
1607 struct ata_eh_info *ehi = &ap->link.eh_info;
1608 struct ahci_port_priv *pp = ap->private_data;
1609 struct ahci_host_priv *hpriv = ap->host->private_data;
1610 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
1611 u32 status, qc_active;
1612 int rc;
1613
1614 status = readl(port_mmio + PORT_IRQ_STAT);
1615 writel(status, port_mmio + PORT_IRQ_STAT);
1616
1617 /* ignore BAD_PMP while resetting */
1618 if (unlikely(resetting))
1619 status &= ~PORT_IRQ_BAD_PMP;
1620
1621 /* If we are getting PhyRdy, this is
1622 * just a power state change, we should
1623 * clear out this, plus the PhyRdy/Comm
1624 * Wake bits from Serror
1625 */
1626 if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
1627 (status & PORT_IRQ_PHYRDY)) {
1628 status &= ~PORT_IRQ_PHYRDY;
1629 ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
1630 }
1631
1632 if (unlikely(status & PORT_IRQ_ERROR)) {
1633 ahci_error_intr(ap, status);
1634 return;
1635 }
1636
1637 if (status & PORT_IRQ_SDB_FIS) {
1638 /* If SNotification is available, leave notification
1639 * handling to sata_async_notification(). If not,
1640 * emulate it by snooping SDB FIS RX area.
1641 *
1642 * Snooping FIS RX area is probably cheaper than
1643 * poking SNotification but some constrollers which
1644 * implement SNotification, ICH9 for example, don't
1645 * store AN SDB FIS into receive area.
1646 */
1647 if (hpriv->cap & HOST_CAP_SNTF)
1648 sata_async_notification(ap);
1649 else {
1650 /* If the 'N' bit in word 0 of the FIS is set,
1651 * we just received asynchronous notification.
1652 * Tell libata about it.
1653 */
1654 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1655 u32 f0 = le32_to_cpu(f[0]);
1656
1657 if (f0 & (1 << 15))
1658 sata_async_notification(ap);
1659 }
1660 }
1661
1662 /* pp->active_link is valid iff any command is in flight */
1663 if (ap->qc_active && pp->active_link->sactive)
1664 qc_active = readl(port_mmio + PORT_SCR_ACT);
1665 else
1666 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1667
1668 rc = ata_qc_complete_multiple(ap, qc_active);
1669
1670 /* while resetting, invalid completions are expected */
1671 if (unlikely(rc < 0 && !resetting)) {
1672 ehi->err_mask |= AC_ERR_HSM;
1673 ehi->action |= ATA_EH_RESET;
1674 ata_port_freeze(ap);
1675 }
1676 }
1677
1678 static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1679 {
1680 struct ata_host *host = dev_instance;
1681 struct ahci_host_priv *hpriv;
1682 unsigned int i, handled = 0;
1683 void __iomem *mmio;
1684 u32 irq_stat, irq_ack = 0;
1685
1686 VPRINTK("ENTER\n");
1687
1688 hpriv = host->private_data;
1689 mmio = host->iomap[AHCI_PCI_BAR];
1690
1691 /* sigh. 0xffffffff is a valid return from h/w */
1692 irq_stat = readl(mmio + HOST_IRQ_STAT);
1693 irq_stat &= hpriv->port_map;
1694 if (!irq_stat)
1695 return IRQ_NONE;
1696
1697 spin_lock(&host->lock);
1698
1699 for (i = 0; i < host->n_ports; i++) {
1700 struct ata_port *ap;
1701
1702 if (!(irq_stat & (1 << i)))
1703 continue;
1704
1705 ap = host->ports[i];
1706 if (ap) {
1707 ahci_port_intr(ap);
1708 VPRINTK("port %u\n", i);
1709 } else {
1710 VPRINTK("port %u (no irq)\n", i);
1711 if (ata_ratelimit())
1712 dev_printk(KERN_WARNING, host->dev,
1713 "interrupt on disabled port %u\n", i);
1714 }
1715
1716 irq_ack |= (1 << i);
1717 }
1718
1719 if (irq_ack) {
1720 writel(irq_ack, mmio + HOST_IRQ_STAT);
1721 handled = 1;
1722 }
1723
1724 spin_unlock(&host->lock);
1725
1726 VPRINTK("EXIT\n");
1727
1728 return IRQ_RETVAL(handled);
1729 }
1730
1731 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1732 {
1733 struct ata_port *ap = qc->ap;
1734 void __iomem *port_mmio = ahci_port_base(ap);
1735 struct ahci_port_priv *pp = ap->private_data;
1736
1737 /* Keep track of the currently active link. It will be used
1738 * in completion path to determine whether NCQ phase is in
1739 * progress.
1740 */
1741 pp->active_link = qc->dev->link;
1742
1743 if (qc->tf.protocol == ATA_PROT_NCQ)
1744 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1745 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1746 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1747
1748 return 0;
1749 }
1750
1751 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
1752 {
1753 struct ahci_port_priv *pp = qc->ap->private_data;
1754 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1755
1756 ata_tf_from_fis(d2h_fis, &qc->result_tf);
1757 return true;
1758 }
1759
1760 static void ahci_freeze(struct ata_port *ap)
1761 {
1762 void __iomem *port_mmio = ahci_port_base(ap);
1763
1764 /* turn IRQ off */
1765 writel(0, port_mmio + PORT_IRQ_MASK);
1766 }
1767
1768 static void ahci_thaw(struct ata_port *ap)
1769 {
1770 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1771 void __iomem *port_mmio = ahci_port_base(ap);
1772 u32 tmp;
1773 struct ahci_port_priv *pp = ap->private_data;
1774
1775 /* clear IRQ */
1776 tmp = readl(port_mmio + PORT_IRQ_STAT);
1777 writel(tmp, port_mmio + PORT_IRQ_STAT);
1778 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
1779
1780 /* turn IRQ back on */
1781 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1782 }
1783
1784 static void ahci_error_handler(struct ata_port *ap)
1785 {
1786 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1787 /* restart engine */
1788 ahci_stop_engine(ap);
1789 ahci_start_engine(ap);
1790 }
1791
1792 sata_pmp_error_handler(ap);
1793 }
1794
1795 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1796 {
1797 struct ata_port *ap = qc->ap;
1798
1799 /* make DMA engine forget about the failed command */
1800 if (qc->flags & ATA_QCFLAG_FAILED)
1801 ahci_kick_engine(ap, 1);
1802 }
1803
1804 static void ahci_pmp_attach(struct ata_port *ap)
1805 {
1806 void __iomem *port_mmio = ahci_port_base(ap);
1807 struct ahci_port_priv *pp = ap->private_data;
1808 u32 cmd;
1809
1810 cmd = readl(port_mmio + PORT_CMD);
1811 cmd |= PORT_CMD_PMP;
1812 writel(cmd, port_mmio + PORT_CMD);
1813
1814 pp->intr_mask |= PORT_IRQ_BAD_PMP;
1815 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1816 }
1817
1818 static void ahci_pmp_detach(struct ata_port *ap)
1819 {
1820 void __iomem *port_mmio = ahci_port_base(ap);
1821 struct ahci_port_priv *pp = ap->private_data;
1822 u32 cmd;
1823
1824 cmd = readl(port_mmio + PORT_CMD);
1825 cmd &= ~PORT_CMD_PMP;
1826 writel(cmd, port_mmio + PORT_CMD);
1827
1828 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
1829 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1830 }
1831
1832 static int ahci_port_resume(struct ata_port *ap)
1833 {
1834 ahci_power_up(ap);
1835 ahci_start_port(ap);
1836
1837 if (sata_pmp_attached(ap))
1838 ahci_pmp_attach(ap);
1839 else
1840 ahci_pmp_detach(ap);
1841
1842 return 0;
1843 }
1844
1845 #ifdef CONFIG_PM
1846 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1847 {
1848 const char *emsg = NULL;
1849 int rc;
1850
1851 rc = ahci_deinit_port(ap, &emsg);
1852 if (rc == 0)
1853 ahci_power_down(ap);
1854 else {
1855 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
1856 ahci_start_port(ap);
1857 }
1858
1859 return rc;
1860 }
1861
1862 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1863 {
1864 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1865 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1866 u32 ctl;
1867
1868 if (mesg.event & PM_EVENT_SLEEP) {
1869 /* AHCI spec rev1.1 section 8.3.3:
1870 * Software must disable interrupts prior to requesting a
1871 * transition of the HBA to D3 state.
1872 */
1873 ctl = readl(mmio + HOST_CTL);
1874 ctl &= ~HOST_IRQ_EN;
1875 writel(ctl, mmio + HOST_CTL);
1876 readl(mmio + HOST_CTL); /* flush */
1877 }
1878
1879 return ata_pci_device_suspend(pdev, mesg);
1880 }
1881
1882 static int ahci_pci_device_resume(struct pci_dev *pdev)
1883 {
1884 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1885 int rc;
1886
1887 rc = ata_pci_device_do_resume(pdev);
1888 if (rc)
1889 return rc;
1890
1891 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
1892 rc = ahci_reset_controller(host);
1893 if (rc)
1894 return rc;
1895
1896 ahci_init_controller(host);
1897 }
1898
1899 ata_host_resume(host);
1900
1901 return 0;
1902 }
1903 #endif
1904
1905 static int ahci_port_start(struct ata_port *ap)
1906 {
1907 struct device *dev = ap->host->dev;
1908 struct ahci_port_priv *pp;
1909 void *mem;
1910 dma_addr_t mem_dma;
1911
1912 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1913 if (!pp)
1914 return -ENOMEM;
1915
1916 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
1917 GFP_KERNEL);
1918 if (!mem)
1919 return -ENOMEM;
1920 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
1921
1922 /*
1923 * First item in chunk of DMA memory: 32-slot command table,
1924 * 32 bytes each in size
1925 */
1926 pp->cmd_slot = mem;
1927 pp->cmd_slot_dma = mem_dma;
1928
1929 mem += AHCI_CMD_SLOT_SZ;
1930 mem_dma += AHCI_CMD_SLOT_SZ;
1931
1932 /*
1933 * Second item: Received-FIS area
1934 */
1935 pp->rx_fis = mem;
1936 pp->rx_fis_dma = mem_dma;
1937
1938 mem += AHCI_RX_FIS_SZ;
1939 mem_dma += AHCI_RX_FIS_SZ;
1940
1941 /*
1942 * Third item: data area for storing a single command
1943 * and its scatter-gather table
1944 */
1945 pp->cmd_tbl = mem;
1946 pp->cmd_tbl_dma = mem_dma;
1947
1948 /*
1949 * Save off initial list of interrupts to be enabled.
1950 * This could be changed later
1951 */
1952 pp->intr_mask = DEF_PORT_IRQ;
1953
1954 ap->private_data = pp;
1955
1956 /* engage engines, captain */
1957 return ahci_port_resume(ap);
1958 }
1959
1960 static void ahci_port_stop(struct ata_port *ap)
1961 {
1962 const char *emsg = NULL;
1963 int rc;
1964
1965 /* de-initialize port */
1966 rc = ahci_deinit_port(ap, &emsg);
1967 if (rc)
1968 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
1969 }
1970
1971 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1972 {
1973 int rc;
1974
1975 if (using_dac &&
1976 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1977 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1978 if (rc) {
1979 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1980 if (rc) {
1981 dev_printk(KERN_ERR, &pdev->dev,
1982 "64-bit DMA enable failed\n");
1983 return rc;
1984 }
1985 }
1986 } else {
1987 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1988 if (rc) {
1989 dev_printk(KERN_ERR, &pdev->dev,
1990 "32-bit DMA enable failed\n");
1991 return rc;
1992 }
1993 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1994 if (rc) {
1995 dev_printk(KERN_ERR, &pdev->dev,
1996 "32-bit consistent DMA enable failed\n");
1997 return rc;
1998 }
1999 }
2000 return 0;
2001 }
2002
2003 static void ahci_print_info(struct ata_host *host)
2004 {
2005 struct ahci_host_priv *hpriv = host->private_data;
2006 struct pci_dev *pdev = to_pci_dev(host->dev);
2007 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
2008 u32 vers, cap, impl, speed;
2009 const char *speed_s;
2010 u16 cc;
2011 const char *scc_s;
2012
2013 vers = readl(mmio + HOST_VERSION);
2014 cap = hpriv->cap;
2015 impl = hpriv->port_map;
2016
2017 speed = (cap >> 20) & 0xf;
2018 if (speed == 1)
2019 speed_s = "1.5";
2020 else if (speed == 2)
2021 speed_s = "3";
2022 else
2023 speed_s = "?";
2024
2025 pci_read_config_word(pdev, 0x0a, &cc);
2026 if (cc == PCI_CLASS_STORAGE_IDE)
2027 scc_s = "IDE";
2028 else if (cc == PCI_CLASS_STORAGE_SATA)
2029 scc_s = "SATA";
2030 else if (cc == PCI_CLASS_STORAGE_RAID)
2031 scc_s = "RAID";
2032 else
2033 scc_s = "unknown";
2034
2035 dev_printk(KERN_INFO, &pdev->dev,
2036 "AHCI %02x%02x.%02x%02x "
2037 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2038 ,
2039
2040 (vers >> 24) & 0xff,
2041 (vers >> 16) & 0xff,
2042 (vers >> 8) & 0xff,
2043 vers & 0xff,
2044
2045 ((cap >> 8) & 0x1f) + 1,
2046 (cap & 0x1f) + 1,
2047 speed_s,
2048 impl,
2049 scc_s);
2050
2051 dev_printk(KERN_INFO, &pdev->dev,
2052 "flags: "
2053 "%s%s%s%s%s%s%s"
2054 "%s%s%s%s%s%s%s\n"
2055 ,
2056
2057 cap & (1 << 31) ? "64bit " : "",
2058 cap & (1 << 30) ? "ncq " : "",
2059 cap & (1 << 29) ? "sntf " : "",
2060 cap & (1 << 28) ? "ilck " : "",
2061 cap & (1 << 27) ? "stag " : "",
2062 cap & (1 << 26) ? "pm " : "",
2063 cap & (1 << 25) ? "led " : "",
2064
2065 cap & (1 << 24) ? "clo " : "",
2066 cap & (1 << 19) ? "nz " : "",
2067 cap & (1 << 18) ? "only " : "",
2068 cap & (1 << 17) ? "pmp " : "",
2069 cap & (1 << 15) ? "pio " : "",
2070 cap & (1 << 14) ? "slum " : "",
2071 cap & (1 << 13) ? "part " : ""
2072 );
2073 }
2074
2075 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
2076 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
2077 * support PMP and the 4726 either directly exports the device
2078 * attached to the first downstream port or acts as a hardware storage
2079 * controller and emulate a single ATA device (can be RAID 0/1 or some
2080 * other configuration).
2081 *
2082 * When there's no device attached to the first downstream port of the
2083 * 4726, "Config Disk" appears, which is a pseudo ATA device to
2084 * configure the 4726. However, ATA emulation of the device is very
2085 * lame. It doesn't send signature D2H Reg FIS after the initial
2086 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
2087 *
2088 * The following function works around the problem by always using
2089 * hardreset on the port and not depending on receiving signature FIS
2090 * afterward. If signature FIS isn't received soon, ATA class is
2091 * assumed without follow-up softreset.
2092 */
2093 static void ahci_p5wdh_workaround(struct ata_host *host)
2094 {
2095 static struct dmi_system_id sysids[] = {
2096 {
2097 .ident = "P5W DH Deluxe",
2098 .matches = {
2099 DMI_MATCH(DMI_SYS_VENDOR,
2100 "ASUSTEK COMPUTER INC"),
2101 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
2102 },
2103 },
2104 { }
2105 };
2106 struct pci_dev *pdev = to_pci_dev(host->dev);
2107
2108 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
2109 dmi_check_system(sysids)) {
2110 struct ata_port *ap = host->ports[1];
2111
2112 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
2113 "Deluxe on-board SIMG4726 workaround\n");
2114
2115 ap->ops = &ahci_p5wdh_ops;
2116 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
2117 }
2118 }
2119
2120 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2121 {
2122 static int printed_version;
2123 struct ata_port_info pi = ahci_port_info[ent->driver_data];
2124 const struct ata_port_info *ppi[] = { &pi, NULL };
2125 struct device *dev = &pdev->dev;
2126 struct ahci_host_priv *hpriv;
2127 struct ata_host *host;
2128 int n_ports, i, rc;
2129
2130 VPRINTK("ENTER\n");
2131
2132 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
2133
2134 if (!printed_version++)
2135 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
2136
2137 /* acquire resources */
2138 rc = pcim_enable_device(pdev);
2139 if (rc)
2140 return rc;
2141
2142 /* AHCI controllers often implement SFF compatible interface.
2143 * Grab all PCI BARs just in case.
2144 */
2145 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
2146 if (rc == -EBUSY)
2147 pcim_pin_device(pdev);
2148 if (rc)
2149 return rc;
2150
2151 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
2152 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
2153 u8 map;
2154
2155 /* ICH6s share the same PCI ID for both piix and ahci
2156 * modes. Enabling ahci mode while MAP indicates
2157 * combined mode is a bad idea. Yield to ata_piix.
2158 */
2159 pci_read_config_byte(pdev, ICH_MAP, &map);
2160 if (map & 0x3) {
2161 dev_printk(KERN_INFO, &pdev->dev, "controller is in "
2162 "combined mode, can't enable AHCI mode\n");
2163 return -ENODEV;
2164 }
2165 }
2166
2167 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
2168 if (!hpriv)
2169 return -ENOMEM;
2170 hpriv->flags |= (unsigned long)pi.private_data;
2171
2172 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
2173 pci_intx(pdev, 1);
2174
2175 /* save initial config */
2176 ahci_save_initial_config(pdev, hpriv);
2177
2178 /* prepare host */
2179 if (hpriv->cap & HOST_CAP_NCQ)
2180 pi.flags |= ATA_FLAG_NCQ;
2181
2182 if (hpriv->cap & HOST_CAP_PMP)
2183 pi.flags |= ATA_FLAG_PMP;
2184
2185 /* CAP.NP sometimes indicate the index of the last enabled
2186 * port, at other times, that of the last possible port, so
2187 * determining the maximum port number requires looking at
2188 * both CAP.NP and port_map.
2189 */
2190 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
2191
2192 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
2193 if (!host)
2194 return -ENOMEM;
2195 host->iomap = pcim_iomap_table(pdev);
2196 host->private_data = hpriv;
2197
2198 for (i = 0; i < host->n_ports; i++) {
2199 struct ata_port *ap = host->ports[i];
2200
2201 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
2202 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
2203 0x100 + ap->port_no * 0x80, "port");
2204
2205 /* set initial link pm policy */
2206 ap->pm_policy = NOT_AVAILABLE;
2207
2208 /* disabled/not-implemented port */
2209 if (!(hpriv->port_map & (1 << i)))
2210 ap->ops = &ata_dummy_port_ops;
2211 }
2212
2213 /* apply workaround for ASUS P5W DH Deluxe mainboard */
2214 ahci_p5wdh_workaround(host);
2215
2216 /* initialize adapter */
2217 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
2218 if (rc)
2219 return rc;
2220
2221 rc = ahci_reset_controller(host);
2222 if (rc)
2223 return rc;
2224
2225 ahci_init_controller(host);
2226 ahci_print_info(host);
2227
2228 pci_set_master(pdev);
2229 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
2230 &ahci_sht);
2231 }
2232
2233 static int __init ahci_init(void)
2234 {
2235 return pci_register_driver(&ahci_pci_driver);
2236 }
2237
2238 static void __exit ahci_exit(void)
2239 {
2240 pci_unregister_driver(&ahci_pci_driver);
2241 }
2242
2243
2244 MODULE_AUTHOR("Jeff Garzik");
2245 MODULE_DESCRIPTION("AHCI SATA low-level driver");
2246 MODULE_LICENSE("GPL");
2247 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
2248 MODULE_VERSION(DRV_VERSION);
2249
2250 module_init(ahci_init);
2251 module_exit(ahci_exit);
CRIS linux kernel tree