drivers/ata/pata_hpt3x3.c

   1 /*
   2  *      pata_hpt3x3             -       HPT3x3 driver
   3  *      (c) Copyright 2005-2006 Red Hat
   4  *
   5  *      Was pata_hpt34x but the naming was confusing as it supported the
   6  *      343 and 363 so it has been renamed.
   7  *
   8  *      Based on:
   9  *      linux/drivers/ide/pci/hpt34x.c          Version 0.40    Sept 10, 2002
  10  *      Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
  11  *
  12  *      May be copied or modified under the terms of the GNU General Public
  13  *      License
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/module.h>
  18 #include <linux/pci.h>
  19 #include <linux/init.h>
  20 #include <linux/blkdev.h>
  21 #include <linux/delay.h>
  22 #include <scsi/scsi_host.h>
  23 #include <linux/libata.h>
  24
  25 #define DRV_NAME        "pata_hpt3x3"
  26 #define DRV_VERSION     "0.5.3"
  27
  28 /**
  29  *      hpt3x3_set_piomode              -       PIO setup
  30  *      @ap: ATA interface
  31  *      @adev: device on the interface
  32  *
  33  *      Set our PIO requirements. This is fairly simple on the HPT3x3 as
  34  *      all we have to do is clear the MWDMA and UDMA bits then load the
  35  *      mode number.
  36  */
  37
  38 static void hpt3x3_set_piomode(struct ata_port *ap, struct ata_device *adev)
  39 {
  40         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  41         u32 r1, r2;
  42         int dn = 2 * ap->port_no + adev->devno;
  43
  44         pci_read_config_dword(pdev, 0x44, &r1);
  45         pci_read_config_dword(pdev, 0x48, &r2);
  46         /* Load the PIO timing number */
  47         r1 &= ~(7 << (3 * dn));
  48         r1 |= (adev->pio_mode - XFER_PIO_0) << (3 * dn);
  49         r2 &= ~(0x11 << dn);    /* Clear MWDMA and UDMA bits */
  50
  51         pci_write_config_dword(pdev, 0x44, r1);
  52         pci_write_config_dword(pdev, 0x48, r2);
  53 }
  54
  55 #if defined(CONFIG_PATA_HPT3X3_DMA)
  56 /**
  57  *      hpt3x3_set_dmamode              -       DMA timing setup
  58  *      @ap: ATA interface
  59  *      @adev: Device being configured
  60  *
  61  *      Set up the channel for MWDMA or UDMA modes. Much the same as with
  62  *      PIO, load the mode number and then set MWDMA or UDMA flag.
  63  *
  64  *      0x44 : bit 0-2 master mode, 3-5 slave mode, etc
  65  *      0x48 : bit 4/0 DMA/UDMA bit 5/1 for slave etc
  66  */
  67
  68 static void hpt3x3_set_dmamode(struct ata_port *ap, struct ata_device *adev)
  69 {
  70         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  71         u32 r1, r2;
  72         int dn = 2 * ap->port_no + adev->devno;
  73         int mode_num = adev->dma_mode & 0x0F;
  74
  75         pci_read_config_dword(pdev, 0x44, &r1);
  76         pci_read_config_dword(pdev, 0x48, &r2);
  77         /* Load the timing number */
  78         r1 &= ~(7 << (3 * dn));
  79         r1 |= (mode_num << (3 * dn));
  80         r2 &= ~(0x11 << dn);    /* Clear MWDMA and UDMA bits */
  81
  82         if (adev->dma_mode >= XFER_UDMA_0)
  83                 r2 |= (0x10 << dn);     /* Ultra mode */
  84         else
  85                 r2 |= (0x01 << dn);     /* MWDMA */
  86
  87         pci_write_config_dword(pdev, 0x44, r1);
  88         pci_write_config_dword(pdev, 0x48, r2);
  89 }
  90 #endif /* CONFIG_PATA_HPT3X3_DMA */
  91
  92 /**
  93  *      hpt3x3_atapi_dma        -       ATAPI DMA check
  94  *      @qc: Queued command
  95  *
  96  *      Just say no - we don't do ATAPI DMA
  97  */
  98
  99 static int hpt3x3_atapi_dma(struct ata_queued_cmd *qc)
 100 {
 101         return 1;
 102 }
 103
 104 static struct scsi_host_template hpt3x3_sht = {
 105         ATA_BMDMA_SHT(DRV_NAME),
 106 };
 107
 108 static struct ata_port_operations hpt3x3_port_ops = {
 109         .inherits       = &ata_bmdma_port_ops,
 110         .check_atapi_dma= hpt3x3_atapi_dma,
 111         .cable_detect   = ata_cable_40wire,
 112         .set_piomode    = hpt3x3_set_piomode,
 113 #if defined(CONFIG_PATA_HPT3X3_DMA)
 114         .set_dmamode    = hpt3x3_set_dmamode,
 115 #endif
 116 };
 117
 118 /**
 119  *      hpt3x3_init_chipset     -       chip setup
 120  *      @dev: PCI device
 121  *
 122  *      Perform the setup required at boot and on resume.
 123  */
 124
 125 static void hpt3x3_init_chipset(struct pci_dev *dev)
 126 {
 127         u16 cmd;
 128         /* Initialize the board */
 129         pci_write_config_word(dev, 0x80, 0x00);
 130         /* Check if it is a 343 or a 363. 363 has COMMAND_MEMORY set */
 131         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 132         if (cmd & PCI_COMMAND_MEMORY)
 133                 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xF0);
 134         else
 135                 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20);
 136 }
 137
 138 /**
 139  *      hpt3x3_init_one         -       Initialise an HPT343/363
 140  *      @pdev: PCI device
 141  *      @id: Entry in match table
 142  *
 143  *      Perform basic initialisation. We set the device up so we access all
 144  *      ports via BAR4. This is neccessary to work around errata.
 145  */
 146
 147 static int hpt3x3_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
 148 {
 149         static int printed_version;
 150         static const struct ata_port_info info = {
 151                 .flags = ATA_FLAG_SLAVE_POSS,
 152                 .pio_mask = 0x1f,
 153 #if defined(CONFIG_PATA_HPT3X3_DMA)
 154                 /* Further debug needed */
 155                 .mwdma_mask = 0x07,
 156                 .udma_mask = 0x07,
 157 #endif
 158                 .port_ops = &hpt3x3_port_ops
 159         };
 160         /* Register offsets of taskfiles in BAR4 area */
 161         static const u8 offset_cmd[2] = { 0x20, 0x28 };
 162         static const u8 offset_ctl[2] = { 0x36, 0x3E };
 163         const struct ata_port_info *ppi[] = { &info, NULL };
 164         struct ata_host *host;
 165         int i, rc;
 166         void __iomem *base;
 167
 168         hpt3x3_init_chipset(pdev);
 169
 170         if (!printed_version++)
 171                 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
 172
 173         host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
 174         if (!host)
 175                 return -ENOMEM;
 176         /* acquire resources and fill host */
 177         rc = pcim_enable_device(pdev);
 178         if (rc)
 179                 return rc;
 180
 181         /* Everything is relative to BAR4 if we set up this way */
 182         rc = pcim_iomap_regions(pdev, 1 << 4, DRV_NAME);
 183         if (rc == -EBUSY)
 184                 pcim_pin_device(pdev);
 185         if (rc)
 186                 return rc;
 187         host->iomap = pcim_iomap_table(pdev);
 188         rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
 189         if (rc)
 190                 return rc;
 191         rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
 192         if (rc)
 193                 return rc;
 194
 195         base = host->iomap[4];  /* Bus mastering base */
 196
 197         for (i = 0; i < host->n_ports; i++) {
 198                 struct ata_port *ap = host->ports[i];
 199                 struct ata_ioports *ioaddr = &ap->ioaddr;
 200
 201                 ioaddr->cmd_addr = base + offset_cmd[i];
 202                 ioaddr->altstatus_addr =
 203                 ioaddr->ctl_addr = base + offset_ctl[i];
 204                 ioaddr->scr_addr = NULL;
 205                 ata_sff_std_ports(ioaddr);
 206                 ioaddr->bmdma_addr = base + 8 * i;
 207
 208                 ata_port_pbar_desc(ap, 4, -1, "ioport");
 209                 ata_port_pbar_desc(ap, 4, offset_cmd[i], "cmd");
 210         }
 211         pci_set_master(pdev);
 212         return ata_host_activate(host, pdev->irq, ata_sff_interrupt,
 213                                  IRQF_SHARED, &hpt3x3_sht);
 214 }
 215
 216 #ifdef CONFIG_PM
 217 static int hpt3x3_reinit_one(struct pci_dev *dev)
 218 {
 219         hpt3x3_init_chipset(dev);
 220         return ata_pci_device_resume(dev);
 221 }
 222 #endif
 223
 224 static const struct pci_device_id hpt3x3[] = {
 225         { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT343), },
 226
 227         { },
 228 };
 229
 230 static struct pci_driver hpt3x3_pci_driver = {
 231         .name           = DRV_NAME,
 232         .id_table       = hpt3x3,
 233         .probe          = hpt3x3_init_one,
 234         .remove         = ata_pci_remove_one,
 235 #ifdef CONFIG_PM
 236         .suspend        = ata_pci_device_suspend,
 237         .resume         = hpt3x3_reinit_one,
 238 #endif
 239 };
 240
 241 static int __init hpt3x3_init(void)
 242 {
 243         return pci_register_driver(&hpt3x3_pci_driver);
 244 }
 245
 246
 247 static void __exit hpt3x3_exit(void)
 248 {
 249         pci_unregister_driver(&hpt3x3_pci_driver);
 250 }
 251
 252
 253 MODULE_AUTHOR("Alan Cox");
 254 MODULE_DESCRIPTION("low-level driver for the Highpoint HPT343/363");
 255 MODULE_LICENSE("GPL");
 256 MODULE_DEVICE_TABLE(pci, hpt3x3);
 257 MODULE_VERSION(DRV_VERSION);
 258
 259 module_init(hpt3x3_init);
 260 module_exit(hpt3x3_exit);