drivers/mtd/nand/rtc_from4.c

   1 /*
   2  *  drivers/mtd/nand/rtc_from4.c
   3  *
   4  *  Copyright (C) 2004  Red Hat, Inc.
   5  *
   6  *  Derived from drivers/mtd/nand/spia.c
   7  *       Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
   8  *
   9  * $Id: rtc_from4.c,v 1.10 2005/11/07 11:14:31 gleixner Exp $
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  *
  15  * Overview:
  16  *   This is a device driver for the AG-AND flash device found on the
  17  *   Renesas Technology Corp. Flash ROM 4-slot interface board (FROM_BOARD4),
  18  *   which utilizes the Renesas HN29V1G91T-30 part.
  19  *   This chip is a 1 GBibit (128MiB x 8 bits) AG-AND flash device.
  20  */
  21
  22 #include <linux/delay.h>
  23 #include <linux/kernel.h>
  24 #include <linux/init.h>
  25 #include <linux/slab.h>
  26 #include <linux/rslib.h>
  27 #include <linux/bitrev.h>
  28 #include <linux/module.h>
  29 #include <linux/mtd/compatmac.h>
  30 #include <linux/mtd/mtd.h>
  31 #include <linux/mtd/nand.h>
  32 #include <linux/mtd/partitions.h>
  33 #include <asm/io.h>
  34
  35 /*
  36  * MTD structure for Renesas board
  37  */
  38 static struct mtd_info *rtc_from4_mtd = NULL;
  39
  40 #define RTC_FROM4_MAX_CHIPS     2
  41
  42 /* HS77x9 processor register defines */
  43 #define SH77X9_BCR1     ((volatile unsigned short *)(0xFFFFFF60))
  44 #define SH77X9_BCR2     ((volatile unsigned short *)(0xFFFFFF62))
  45 #define SH77X9_WCR1     ((volatile unsigned short *)(0xFFFFFF64))
  46 #define SH77X9_WCR2     ((volatile unsigned short *)(0xFFFFFF66))
  47 #define SH77X9_MCR      ((volatile unsigned short *)(0xFFFFFF68))
  48 #define SH77X9_PCR      ((volatile unsigned short *)(0xFFFFFF6C))
  49 #define SH77X9_FRQCR    ((volatile unsigned short *)(0xFFFFFF80))
  50
  51 /*
  52  * Values specific to the Renesas Technology Corp. FROM_BOARD4 (used with HS77x9 processor)
  53  */
  54 /* Address where flash is mapped */
  55 #define RTC_FROM4_FIO_BASE      0x14000000
  56
  57 /* CLE and ALE are tied to address lines 5 & 4, respectively */
  58 #define RTC_FROM4_CLE           (1 << 5)
  59 #define RTC_FROM4_ALE           (1 << 4)
  60
  61 /* address lines A24-A22 used for chip selection */
  62 #define RTC_FROM4_NAND_ADDR_SLOT3       (0x00800000)
  63 #define RTC_FROM4_NAND_ADDR_SLOT4       (0x00C00000)
  64 #define RTC_FROM4_NAND_ADDR_FPGA        (0x01000000)
  65 /* mask address lines A24-A22 used for chip selection */
  66 #define RTC_FROM4_NAND_ADDR_MASK        (RTC_FROM4_NAND_ADDR_SLOT3 | RTC_FROM4_NAND_ADDR_SLOT4 | RTC_FROM4_NAND_ADDR_FPGA)
  67
  68 /* FPGA status register for checking device ready (bit zero) */
  69 #define RTC_FROM4_FPGA_SR               (RTC_FROM4_NAND_ADDR_FPGA | 0x00000002)
  70 #define RTC_FROM4_DEVICE_READY          0x0001
  71
  72 /* FPGA Reed-Solomon ECC Control register */
  73
  74 #define RTC_FROM4_RS_ECC_CTL            (RTC_FROM4_NAND_ADDR_FPGA | 0x00000050)
  75 #define RTC_FROM4_RS_ECC_CTL_CLR        (1 << 7)
  76 #define RTC_FROM4_RS_ECC_CTL_GEN        (1 << 6)
  77 #define RTC_FROM4_RS_ECC_CTL_FD_E       (1 << 5)
  78
  79 /* FPGA Reed-Solomon ECC code base */
  80 #define RTC_FROM4_RS_ECC                (RTC_FROM4_NAND_ADDR_FPGA | 0x00000060)
  81 #define RTC_FROM4_RS_ECCN               (RTC_FROM4_NAND_ADDR_FPGA | 0x00000080)
  82
  83 /* FPGA Reed-Solomon ECC check register */
  84 #define RTC_FROM4_RS_ECC_CHK            (RTC_FROM4_NAND_ADDR_FPGA | 0x00000070)
  85 #define RTC_FROM4_RS_ECC_CHK_ERROR      (1 << 7)
  86
  87 #define ERR_STAT_ECC_AVAILABLE          0x20
  88
  89 /* Undefine for software ECC */
  90 #define RTC_FROM4_HWECC 1
  91
  92 /* Define as 1 for no virtual erase blocks (in JFFS2) */
  93 #define RTC_FROM4_NO_VIRTBLOCKS 0
  94
  95 /*
  96  * Module stuff
  97  */
  98 static void __iomem *rtc_from4_fio_base = (void *)P2SEGADDR(RTC_FROM4_FIO_BASE);
  99
 100 static const struct mtd_partition partition_info[] = {
 101         {
 102          .name = "Renesas flash partition 1",
 103          .offset = 0,
 104          .size = MTDPART_SIZ_FULL},
 105 };
 106
 107 #define NUM_PARTITIONS 1
 108
 109 /*
 110  *      hardware specific flash bbt decriptors
 111  *      Note: this is to allow debugging by disabling
 112  *              NAND_BBT_CREATE and/or NAND_BBT_WRITE
 113  *
 114  */
 115 static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
 116 static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
 117
 118 static struct nand_bbt_descr rtc_from4_bbt_main_descr = {
 119         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
 120                 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
 121         .offs = 40,
 122         .len = 4,
 123         .veroffs = 44,
 124         .maxblocks = 4,
 125         .pattern = bbt_pattern
 126 };
 127
 128 static struct nand_bbt_descr rtc_from4_bbt_mirror_descr = {
 129         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
 130                 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
 131         .offs = 40,
 132         .len = 4,
 133         .veroffs = 44,
 134         .maxblocks = 4,
 135         .pattern = mirror_pattern
 136 };
 137
 138 #ifdef RTC_FROM4_HWECC
 139
 140 /* the Reed Solomon control structure */
 141 static struct rs_control *rs_decoder;
 142
 143 /*
 144  *      hardware specific Out Of Band information
 145  */
 146 static struct nand_ecclayout rtc_from4_nand_oobinfo = {
 147         .eccbytes = 32,
 148         .eccpos = {
 149                    0, 1, 2, 3, 4, 5, 6, 7,
 150                    8, 9, 10, 11, 12, 13, 14, 15,
 151                    16, 17, 18, 19, 20, 21, 22, 23,
 152                    24, 25, 26, 27, 28, 29, 30, 31},
 153         .oobfree = {{32, 32}}
 154 };
 155
 156 #endif
 157
 158 /*
 159  * rtc_from4_hwcontrol - hardware specific access to control-lines
 160  * @mtd:        MTD device structure
 161  * @cmd:        hardware control command
 162  *
 163  * Address lines (A5 and A4) are used to control Command and Address Latch
 164  * Enable on this board, so set the read/write address appropriately.
 165  *
 166  * Chip Enable is also controlled by the Chip Select (CS5) and
 167  * Address lines (A24-A22), so no action is required here.
 168  *
 169  */
 170 static void rtc_from4_hwcontrol(struct mtd_info *mtd, int cmd,
 171                                 unsigned int ctrl)
 172 {
 173         struct nand_chip *chip = (mtd->priv);
 174
 175         if (cmd == NAND_CMD_NONE)
 176                 return;
 177
 178         if (ctrl & NAND_CLE)
 179                 writeb(cmd, chip->IO_ADDR_W | RTC_FROM4_CLE);
 180         else
 181                 writeb(cmd, chip->IO_ADDR_W | RTC_FROM4_ALE);
 182 }
 183
 184 /*
 185  * rtc_from4_nand_select_chip - hardware specific chip select
 186  * @mtd:        MTD device structure
 187  * @chip:       Chip to select (0 == slot 3, 1 == slot 4)
 188  *
 189  * The chip select is based on address lines A24-A22.
 190  * This driver uses flash slots 3 and 4 (A23-A22).
 191  *
 192  */
 193 static void rtc_from4_nand_select_chip(struct mtd_info *mtd, int chip)
 194 {
 195         struct nand_chip *this = mtd->priv;
 196
 197         this->IO_ADDR_R = (void __iomem *)((unsigned long)this->IO_ADDR_R & ~RTC_FROM4_NAND_ADDR_MASK);
 198         this->IO_ADDR_W = (void __iomem *)((unsigned long)this->IO_ADDR_W & ~RTC_FROM4_NAND_ADDR_MASK);
 199
 200         switch (chip) {
 201
 202         case 0:         /* select slot 3 chip */
 203                 this->IO_ADDR_R = (void __iomem *)((unsigned long)this->IO_ADDR_R | RTC_FROM4_NAND_ADDR_SLOT3);
 204                 this->IO_ADDR_W = (void __iomem *)((unsigned long)this->IO_ADDR_W | RTC_FROM4_NAND_ADDR_SLOT3);
 205                 break;
 206         case 1:         /* select slot 4 chip */
 207                 this->IO_ADDR_R = (void __iomem *)((unsigned long)this->IO_ADDR_R | RTC_FROM4_NAND_ADDR_SLOT4);
 208                 this->IO_ADDR_W = (void __iomem *)((unsigned long)this->IO_ADDR_W | RTC_FROM4_NAND_ADDR_SLOT4);
 209                 break;
 210
 211         }
 212 }
 213
 214 /*
 215  * rtc_from4_nand_device_ready - hardware specific ready/busy check
 216  * @mtd:        MTD device structure
 217  *
 218  * This board provides the Ready/Busy state in the status register
 219  * of the FPGA.  Bit zero indicates the RDY(1)/BSY(0) signal.
 220  *
 221  */
 222 static int rtc_from4_nand_device_ready(struct mtd_info *mtd)
 223 {
 224         unsigned short status;
 225
 226         status = *((volatile unsigned short *)(rtc_from4_fio_base + RTC_FROM4_FPGA_SR));
 227
 228         return (status & RTC_FROM4_DEVICE_READY);
 229
 230 }
 231
 232 /*
 233  * deplete - code to perform device recovery in case there was a power loss
 234  * @mtd:        MTD device structure
 235  * @chip:       Chip to select (0 == slot 3, 1 == slot 4)
 236  *
 237  * If there was a sudden loss of power during an erase operation, a
 238  * "device recovery" operation must be performed when power is restored
 239  * to ensure correct operation.  This routine performs the required steps
 240  * for the requested chip.
 241  *
 242  * See page 86 of the data sheet for details.
 243  *
 244  */
 245 static void deplete(struct mtd_info *mtd, int chip)
 246 {
 247         struct nand_chip *this = mtd->priv;
 248
 249         /* wait until device is ready */
 250         while (!this->dev_ready(mtd)) ;
 251
 252         this->select_chip(mtd, chip);
 253
 254         /* Send the commands for device recovery, phase 1 */
 255         this->cmdfunc(mtd, NAND_CMD_DEPLETE1, 0x0000, 0x0000);
 256         this->cmdfunc(mtd, NAND_CMD_DEPLETE2, -1, -1);
 257
 258         /* Send the commands for device recovery, phase 2 */
 259         this->cmdfunc(mtd, NAND_CMD_DEPLETE1, 0x0000, 0x0004);
 260         this->cmdfunc(mtd, NAND_CMD_DEPLETE2, -1, -1);
 261
 262 }
 263
 264 #ifdef RTC_FROM4_HWECC
 265 /*
 266  * rtc_from4_enable_hwecc - hardware specific hardware ECC enable function
 267  * @mtd:        MTD device structure
 268  * @mode:       I/O mode; read or write
 269  *
 270  * enable hardware ECC for data read or write
 271  *
 272  */
 273 static void rtc_from4_enable_hwecc(struct mtd_info *mtd, int mode)
 274 {
 275         volatile unsigned short *rs_ecc_ctl = (volatile unsigned short *)(rtc_from4_fio_base + RTC_FROM4_RS_ECC_CTL);
 276         unsigned short status;
 277
 278         switch (mode) {
 279         case NAND_ECC_READ:
 280                 status = RTC_FROM4_RS_ECC_CTL_CLR | RTC_FROM4_RS_ECC_CTL_FD_E;
 281
 282                 *rs_ecc_ctl = status;
 283                 break;
 284
 285         case NAND_ECC_READSYN:
 286                 status = 0x00;
 287
 288                 *rs_ecc_ctl = status;
 289                 break;
 290
 291         case NAND_ECC_WRITE:
 292                 status = RTC_FROM4_RS_ECC_CTL_CLR | RTC_FROM4_RS_ECC_CTL_GEN | RTC_FROM4_RS_ECC_CTL_FD_E;
 293
 294                 *rs_ecc_ctl = status;
 295                 break;
 296
 297         default:
 298                 BUG();
 299                 break;
 300         }
 301
 302 }
 303
 304 /*
 305  * rtc_from4_calculate_ecc - hardware specific code to read ECC code
 306  * @mtd:        MTD device structure
 307  * @dat:        buffer containing the data to generate ECC codes
 308  * @ecc_code    ECC codes calculated
 309  *
 310  * The ECC code is calculated by the FPGA.  All we have to do is read the values
 311  * from the FPGA registers.
 312  *
 313  * Note: We read from the inverted registers, since data is inverted before
 314  * the code is calculated. So all 0xff data (blank page) results in all 0xff rs code
 315  *
 316  */
 317 static void rtc_from4_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
 318 {
 319         volatile unsigned short *rs_eccn = (volatile unsigned short *)(rtc_from4_fio_base + RTC_FROM4_RS_ECCN);
 320         unsigned short value;
 321         int i;
 322
 323         for (i = 0; i < 8; i++) {
 324                 value = *rs_eccn;
 325                 ecc_code[i] = (unsigned char)value;
 326                 rs_eccn++;
 327         }
 328         ecc_code[7] |= 0x0f;    /* set the last four bits (not used) */
 329 }
 330
 331 /*
 332  * rtc_from4_correct_data - hardware specific code to correct data using ECC code
 333  * @mtd:        MTD device structure
 334  * @buf:        buffer containing the data to generate ECC codes
 335  * @ecc1        ECC codes read
 336  * @ecc2        ECC codes calculated
 337  *
 338  * The FPGA tells us fast, if there's an error or not. If no, we go back happy
 339  * else we read the ecc results from the fpga and call the rs library to decode
 340  * and hopefully correct the error.
 341  *
 342  */
 343 static int rtc_from4_correct_data(struct mtd_info *mtd, const u_char *buf, u_char *ecc1, u_char *ecc2)
 344 {
 345         int i, j, res;
 346         unsigned short status;
 347         uint16_t par[6], syn[6];
 348         uint8_t ecc[8];
 349         volatile unsigned short *rs_ecc;
 350
 351         status = *((volatile unsigned short *)(rtc_from4_fio_base + RTC_FROM4_RS_ECC_CHK));
 352
 353         if (!(status & RTC_FROM4_RS_ECC_CHK_ERROR)) {
 354                 return 0;
 355         }
 356
 357         /* Read the syndrom pattern from the FPGA and correct the bitorder */
 358         rs_ecc = (volatile unsigned short *)(rtc_from4_fio_base + RTC_FROM4_RS_ECC);
 359         for (i = 0; i < 8; i++) {
 360                 ecc[i] = bitrev8(*rs_ecc);
 361                 rs_ecc++;
 362         }
 363
 364         /* convert into 6 10bit syndrome fields */
 365         par[5] = rs_decoder->index_of[(((uint16_t) ecc[0] >> 0) & 0x0ff) | (((uint16_t) ecc[1] << 8) & 0x300)];
 366         par[4] = rs_decoder->index_of[(((uint16_t) ecc[1] >> 2) & 0x03f) | (((uint16_t) ecc[2] << 6) & 0x3c0)];
 367         par[3] = rs_decoder->index_of[(((uint16_t) ecc[2] >> 4) & 0x00f) | (((uint16_t) ecc[3] << 4) & 0x3f0)];
 368         par[2] = rs_decoder->index_of[(((uint16_t) ecc[3] >> 6) & 0x003) | (((uint16_t) ecc[4] << 2) & 0x3fc)];
 369         par[1] = rs_decoder->index_of[(((uint16_t) ecc[5] >> 0) & 0x0ff) | (((uint16_t) ecc[6] << 8) & 0x300)];
 370         par[0] = (((uint16_t) ecc[6] >> 2) & 0x03f) | (((uint16_t) ecc[7] << 6) & 0x3c0);
 371
 372         /* Convert to computable syndrome */
 373         for (i = 0; i < 6; i++) {
 374                 syn[i] = par[0];
 375                 for (j = 1; j < 6; j++)
 376                         if (par[j] != rs_decoder->nn)
 377                                 syn[i] ^= rs_decoder->alpha_to[rs_modnn(rs_decoder, par[j] + i * j)];
 378
 379                 /* Convert to index form */
 380                 syn[i] = rs_decoder->index_of[syn[i]];
 381         }
 382
 383         /* Let the library code do its magic. */
 384         res = decode_rs8(rs_decoder, (uint8_t *) buf, par, 512, syn, 0, NULL, 0xff, NULL);
 385         if (res > 0) {
 386                 DEBUG(MTD_DEBUG_LEVEL0, "rtc_from4_correct_data: " "ECC corrected %d errors on read\n", res);
 387         }
 388         return res;
 389 }
 390
 391 /**
 392  * rtc_from4_errstat - perform additional error status checks
 393  * @mtd:        MTD device structure
 394  * @this:       NAND chip structure
 395  * @state:      state or the operation
 396  * @status:     status code returned from read status
 397  * @page:       startpage inside the chip, must be called with (page & this->pagemask)
 398  *
 399  * Perform additional error status checks on erase and write failures
 400  * to determine if errors are correctable.  For this device, correctable
 401  * 1-bit errors on erase and write are considered acceptable.
 402  *
 403  * note: see pages 34..37 of data sheet for details.
 404  *
 405  */
 406 static int rtc_from4_errstat(struct mtd_info *mtd, struct nand_chip *this,
 407                              int state, int status, int page)
 408 {
 409         int er_stat = 0;
 410         int rtn, retlen;
 411         size_t len;
 412         uint8_t *buf;
 413         int i;
 414
 415         this->cmdfunc(mtd, NAND_CMD_STATUS_CLEAR, -1, -1);
 416
 417         if (state == FL_ERASING) {
 418
 419                 for (i = 0; i < 4; i++) {
 420                         if (!(status & 1 << (i + 1)))
 421                                 continue;
 422                         this->cmdfunc(mtd, (NAND_CMD_STATUS_ERROR + i + 1),
 423                                       -1, -1);
 424                         rtn = this->read_byte(mtd);
 425                         this->cmdfunc(mtd, NAND_CMD_STATUS_RESET, -1, -1);
 426
 427                         /* err_ecc_not_avail */
 428                         if (!(rtn & ERR_STAT_ECC_AVAILABLE))
 429                                 er_stat |= 1 << (i + 1);
 430                 }
 431
 432         } else if (state == FL_WRITING) {
 433
 434                 unsigned long corrected = mtd->ecc_stats.corrected;
 435
 436                 /* single bank write logic */
 437                 this->cmdfunc(mtd, NAND_CMD_STATUS_ERROR, -1, -1);
 438                 rtn = this->read_byte(mtd);
 439                 this->cmdfunc(mtd, NAND_CMD_STATUS_RESET, -1, -1);
 440
 441                 if (!(rtn & ERR_STAT_ECC_AVAILABLE)) {
 442                         /* err_ecc_not_avail */
 443                         er_stat |= 1 << 1;
 444                         goto out;
 445                 }
 446
 447                 len = mtd->writesize;
 448                 buf = kmalloc(len, GFP_KERNEL);
 449                 if (!buf) {
 450                         printk(KERN_ERR "rtc_from4_errstat: Out of memory!\n");
 451                         er_stat = 1;
 452                         goto out;
 453                 }
 454
 455                 /* recovery read */
 456                 rtn = nand_do_read(mtd, page, len, &retlen, buf);
 457
 458                 /* if read failed or > 1-bit error corrected */
 459                 if (rtn || (mtd->ecc_stats.corrected - corrected) > 1)
 460                         er_stat |= 1 << 1;
 461                 kfree(buf);
 462         }
 463 out:
 464         rtn = status;
 465         if (er_stat == 0) {     /* if ECC is available   */
 466                 rtn = (status & ~NAND_STATUS_FAIL);     /*   clear the error bit */
 467         }
 468
 469         return rtn;
 470 }
 471 #endif
 472
 473 /*
 474  * Main initialization routine
 475  */
 476 static int __init rtc_from4_init(void)
 477 {
 478         struct nand_chip *this;
 479         unsigned short bcr1, bcr2, wcr2;
 480         int i;
 481         int ret;
 482
 483         /* Allocate memory for MTD device structure and private data */
 484         rtc_from4_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);
 485         if (!rtc_from4_mtd) {
 486                 printk("Unable to allocate Renesas NAND MTD device structure.\n");
 487                 return -ENOMEM;
 488         }
 489
 490         /* Get pointer to private data */
 491         this = (struct nand_chip *)(&rtc_from4_mtd[1]);
 492
 493         /* Initialize structures */
 494         memset(rtc_from4_mtd, 0, sizeof(struct mtd_info));
 495         memset(this, 0, sizeof(struct nand_chip));
 496
 497         /* Link the private data with the MTD structure */
 498         rtc_from4_mtd->priv = this;
 499         rtc_from4_mtd->owner = THIS_MODULE;
 500
 501         /* set area 5 as PCMCIA mode to clear the spec of tDH(Data hold time;9ns min) */
 502         bcr1 = *SH77X9_BCR1 & ~0x0002;
 503         bcr1 |= 0x0002;
 504         *SH77X9_BCR1 = bcr1;
 505
 506         /* set */
 507         bcr2 = *SH77X9_BCR2 & ~0x0c00;
 508         bcr2 |= 0x0800;
 509         *SH77X9_BCR2 = bcr2;
 510
 511         /* set area 5 wait states */
 512         wcr2 = *SH77X9_WCR2 & ~0x1c00;
 513         wcr2 |= 0x1c00;
 514         *SH77X9_WCR2 = wcr2;
 515
 516         /* Set address of NAND IO lines */
 517         this->IO_ADDR_R = rtc_from4_fio_base;
 518         this->IO_ADDR_W = rtc_from4_fio_base;
 519         /* Set address of hardware control function */
 520         this->cmd_ctrl = rtc_from4_hwcontrol;
 521         /* Set address of chip select function */
 522         this->select_chip = rtc_from4_nand_select_chip;
 523         /* command delay time (in us) */
 524         this->chip_delay = 100;
 525         /* return the status of the Ready/Busy line */
 526         this->dev_ready = rtc_from4_nand_device_ready;
 527
 528 #ifdef RTC_FROM4_HWECC
 529         printk(KERN_INFO "rtc_from4_init: using hardware ECC detection.\n");
 530
 531         this->ecc.mode = NAND_ECC_HW_SYNDROME;
 532         this->ecc.size = 512;
 533         this->ecc.bytes = 8;
 534         /* return the status of extra status and ECC checks */
 535         this->errstat = rtc_from4_errstat;
 536         /* set the nand_oobinfo to support FPGA H/W error detection */
 537         this->ecc.layout = &rtc_from4_nand_oobinfo;
 538         this->ecc.hwctl = rtc_from4_enable_hwecc;
 539         this->ecc.calculate = rtc_from4_calculate_ecc;
 540         this->ecc.correct = rtc_from4_correct_data;
 541
 542         /* We could create the decoder on demand, if memory is a concern.
 543          * This way we have it handy, if an error happens
 544          *
 545          * Symbolsize is 10 (bits)
 546          * Primitve polynomial is x^10+x^3+1
 547          * first consecutive root is 0
 548          * primitve element to generate roots = 1
 549          * generator polinomial degree = 6
 550          */
 551         rs_decoder = init_rs(10, 0x409, 0, 1, 6);
 552         if (!rs_decoder) {
 553                 printk(KERN_ERR "Could not create a RS decoder\n");
 554                 ret = -ENOMEM;
 555                 goto err_1;
 556         }
 557 #else
 558         printk(KERN_INFO "rtc_from4_init: using software ECC detection.\n");
 559
 560         this->ecc.mode = NAND_ECC_SOFT;
 561 #endif
 562
 563         /* set the bad block tables to support debugging */
 564         this->bbt_td = &rtc_from4_bbt_main_descr;
 565         this->bbt_md = &rtc_from4_bbt_mirror_descr;
 566
 567         /* Scan to find existence of the device */
 568         if (nand_scan(rtc_from4_mtd, RTC_FROM4_MAX_CHIPS)) {
 569                 ret = -ENXIO;
 570                 goto err_2;
 571         }
 572
 573         /* Perform 'device recovery' for each chip in case there was a power loss. */
 574         for (i = 0; i < this->numchips; i++) {
 575                 deplete(rtc_from4_mtd, i);
 576         }
 577
 578 #if RTC_FROM4_NO_VIRTBLOCKS
 579         /* use a smaller erase block to minimize wasted space when a block is bad */
 580         /* note: this uses eight times as much RAM as using the default and makes */
 581         /*       mounts take four times as long. */
 582         rtc_from4_mtd->flags |= MTD_NO_VIRTBLOCKS;
 583 #endif
 584
 585         /* Register the partitions */
 586         ret = add_mtd_partitions(rtc_from4_mtd, partition_info, NUM_PARTITIONS);
 587         if (ret)
 588                 goto err_3;
 589
 590         /* Return happy */
 591         return 0;
 592 err_3:
 593         nand_release(rtc_from4_mtd);
 594 err_2:
 595         free_rs(rs_decoder);
 596 err_1:
 597         kfree(rtc_from4_mtd);
 598         return ret;
 599 }
 600
 601 module_init(rtc_from4_init);
 602
 603 /*
 604  * Clean up routine
 605  */
 606 static void __exit rtc_from4_cleanup(void)
 607 {
 608         /* Release resource, unregister partitions */
 609         nand_release(rtc_from4_mtd);
 610
 611         /* Free the MTD device structure */
 612         kfree(rtc_from4_mtd);
 613
 614 #ifdef RTC_FROM4_HWECC
 615         /* Free the reed solomon resources */
 616         if (rs_decoder) {
 617                 free_rs(rs_decoder);
 618         }
 619 #endif
 620 }
 621
 622 module_exit(rtc_from4_cleanup);
 623
 624 MODULE_LICENSE("GPL");
 625 MODULE_AUTHOR("d.marlin <dmarlin@redhat.com");
 626 MODULE_DESCRIPTION("Board-specific glue layer for AG-AND flash on Renesas FROM_BOARD4");