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FRV: Use generic show_interrupts()
[cris-mirror.git] / drivers / gpu / drm / nouveau / nouveau_state.c
blob4fcbd091a117caea61fb684374a4fe9f0e661886
1 /*
2 * Copyright 2005 Stephane Marchesin
3 * Copyright 2008 Stuart Bennett
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 */
25
26 #include <linux/swab.h>
27 #include <linux/slab.h>
28 #include "drmP.h"
29 #include "drm.h"
30 #include "drm_sarea.h"
31 #include "drm_crtc_helper.h"
32 #include <linux/vgaarb.h>
33 #include <linux/vga_switcheroo.h>
34
35 #include "nouveau_drv.h"
36 #include "nouveau_drm.h"
37 #include "nouveau_fbcon.h"
38 #include "nouveau_ramht.h"
39 #include "nouveau_pm.h"
40 #include "nv50_display.h"
41
42 static void nouveau_stub_takedown(struct drm_device *dev) {}
43 static int nouveau_stub_init(struct drm_device *dev) { return 0; }
44
45 static int nouveau_init_engine_ptrs(struct drm_device *dev)
46 {
47 struct drm_nouveau_private *dev_priv = dev->dev_private;
48 struct nouveau_engine *engine = &dev_priv->engine;
49
50 switch (dev_priv->chipset & 0xf0) {
51 case 0x00:
52 engine->instmem.init = nv04_instmem_init;
53 engine->instmem.takedown = nv04_instmem_takedown;
54 engine->instmem.suspend = nv04_instmem_suspend;
55 engine->instmem.resume = nv04_instmem_resume;
56 engine->instmem.get = nv04_instmem_get;
57 engine->instmem.put = nv04_instmem_put;
58 engine->instmem.map = nv04_instmem_map;
59 engine->instmem.unmap = nv04_instmem_unmap;
60 engine->instmem.flush = nv04_instmem_flush;
61 engine->mc.init = nv04_mc_init;
62 engine->mc.takedown = nv04_mc_takedown;
63 engine->timer.init = nv04_timer_init;
64 engine->timer.read = nv04_timer_read;
65 engine->timer.takedown = nv04_timer_takedown;
66 engine->fb.init = nv04_fb_init;
67 engine->fb.takedown = nv04_fb_takedown;
68 engine->graph.init = nv04_graph_init;
69 engine->graph.takedown = nv04_graph_takedown;
70 engine->graph.fifo_access = nv04_graph_fifo_access;
71 engine->graph.channel = nv04_graph_channel;
72 engine->graph.create_context = nv04_graph_create_context;
73 engine->graph.destroy_context = nv04_graph_destroy_context;
74 engine->graph.load_context = nv04_graph_load_context;
75 engine->graph.unload_context = nv04_graph_unload_context;
76 engine->fifo.channels = 16;
77 engine->fifo.init = nv04_fifo_init;
78 engine->fifo.takedown = nv04_fifo_fini;
79 engine->fifo.disable = nv04_fifo_disable;
80 engine->fifo.enable = nv04_fifo_enable;
81 engine->fifo.reassign = nv04_fifo_reassign;
82 engine->fifo.cache_pull = nv04_fifo_cache_pull;
83 engine->fifo.channel_id = nv04_fifo_channel_id;
84 engine->fifo.create_context = nv04_fifo_create_context;
85 engine->fifo.destroy_context = nv04_fifo_destroy_context;
86 engine->fifo.load_context = nv04_fifo_load_context;
87 engine->fifo.unload_context = nv04_fifo_unload_context;
88 engine->display.early_init = nv04_display_early_init;
89 engine->display.late_takedown = nv04_display_late_takedown;
90 engine->display.create = nv04_display_create;
91 engine->display.init = nv04_display_init;
92 engine->display.destroy = nv04_display_destroy;
93 engine->gpio.init = nouveau_stub_init;
94 engine->gpio.takedown = nouveau_stub_takedown;
95 engine->gpio.get = NULL;
96 engine->gpio.set = NULL;
97 engine->gpio.irq_enable = NULL;
98 engine->pm.clock_get = nv04_pm_clock_get;
99 engine->pm.clock_pre = nv04_pm_clock_pre;
100 engine->pm.clock_set = nv04_pm_clock_set;
101 engine->crypt.init = nouveau_stub_init;
102 engine->crypt.takedown = nouveau_stub_takedown;
103 engine->vram.init = nouveau_mem_detect;
104 engine->vram.flags_valid = nouveau_mem_flags_valid;
105 break;
106 case 0x10:
107 engine->instmem.init = nv04_instmem_init;
108 engine->instmem.takedown = nv04_instmem_takedown;
109 engine->instmem.suspend = nv04_instmem_suspend;
110 engine->instmem.resume = nv04_instmem_resume;
111 engine->instmem.get = nv04_instmem_get;
112 engine->instmem.put = nv04_instmem_put;
113 engine->instmem.map = nv04_instmem_map;
114 engine->instmem.unmap = nv04_instmem_unmap;
115 engine->instmem.flush = nv04_instmem_flush;
116 engine->mc.init = nv04_mc_init;
117 engine->mc.takedown = nv04_mc_takedown;
118 engine->timer.init = nv04_timer_init;
119 engine->timer.read = nv04_timer_read;
120 engine->timer.takedown = nv04_timer_takedown;
121 engine->fb.init = nv10_fb_init;
122 engine->fb.takedown = nv10_fb_takedown;
123 engine->fb.init_tile_region = nv10_fb_init_tile_region;
124 engine->fb.set_tile_region = nv10_fb_set_tile_region;
125 engine->fb.free_tile_region = nv10_fb_free_tile_region;
126 engine->graph.init = nv10_graph_init;
127 engine->graph.takedown = nv10_graph_takedown;
128 engine->graph.channel = nv10_graph_channel;
129 engine->graph.create_context = nv10_graph_create_context;
130 engine->graph.destroy_context = nv10_graph_destroy_context;
131 engine->graph.fifo_access = nv04_graph_fifo_access;
132 engine->graph.load_context = nv10_graph_load_context;
133 engine->graph.unload_context = nv10_graph_unload_context;
134 engine->graph.set_tile_region = nv10_graph_set_tile_region;
135 engine->fifo.channels = 32;
136 engine->fifo.init = nv10_fifo_init;
137 engine->fifo.takedown = nv04_fifo_fini;
138 engine->fifo.disable = nv04_fifo_disable;
139 engine->fifo.enable = nv04_fifo_enable;
140 engine->fifo.reassign = nv04_fifo_reassign;
141 engine->fifo.cache_pull = nv04_fifo_cache_pull;
142 engine->fifo.channel_id = nv10_fifo_channel_id;
143 engine->fifo.create_context = nv10_fifo_create_context;
144 engine->fifo.destroy_context = nv04_fifo_destroy_context;
145 engine->fifo.load_context = nv10_fifo_load_context;
146 engine->fifo.unload_context = nv10_fifo_unload_context;
147 engine->display.early_init = nv04_display_early_init;
148 engine->display.late_takedown = nv04_display_late_takedown;
149 engine->display.create = nv04_display_create;
150 engine->display.init = nv04_display_init;
151 engine->display.destroy = nv04_display_destroy;
152 engine->gpio.init = nouveau_stub_init;
153 engine->gpio.takedown = nouveau_stub_takedown;
154 engine->gpio.get = nv10_gpio_get;
155 engine->gpio.set = nv10_gpio_set;
156 engine->gpio.irq_enable = NULL;
157 engine->pm.clock_get = nv04_pm_clock_get;
158 engine->pm.clock_pre = nv04_pm_clock_pre;
159 engine->pm.clock_set = nv04_pm_clock_set;
160 engine->crypt.init = nouveau_stub_init;
161 engine->crypt.takedown = nouveau_stub_takedown;
162 engine->vram.init = nouveau_mem_detect;
163 engine->vram.flags_valid = nouveau_mem_flags_valid;
164 break;
165 case 0x20:
166 engine->instmem.init = nv04_instmem_init;
167 engine->instmem.takedown = nv04_instmem_takedown;
168 engine->instmem.suspend = nv04_instmem_suspend;
169 engine->instmem.resume = nv04_instmem_resume;
170 engine->instmem.get = nv04_instmem_get;
171 engine->instmem.put = nv04_instmem_put;
172 engine->instmem.map = nv04_instmem_map;
173 engine->instmem.unmap = nv04_instmem_unmap;
174 engine->instmem.flush = nv04_instmem_flush;
175 engine->mc.init = nv04_mc_init;
176 engine->mc.takedown = nv04_mc_takedown;
177 engine->timer.init = nv04_timer_init;
178 engine->timer.read = nv04_timer_read;
179 engine->timer.takedown = nv04_timer_takedown;
180 engine->fb.init = nv10_fb_init;
181 engine->fb.takedown = nv10_fb_takedown;
182 engine->fb.init_tile_region = nv10_fb_init_tile_region;
183 engine->fb.set_tile_region = nv10_fb_set_tile_region;
184 engine->fb.free_tile_region = nv10_fb_free_tile_region;
185 engine->graph.init = nv20_graph_init;
186 engine->graph.takedown = nv20_graph_takedown;
187 engine->graph.channel = nv10_graph_channel;
188 engine->graph.create_context = nv20_graph_create_context;
189 engine->graph.destroy_context = nv20_graph_destroy_context;
190 engine->graph.fifo_access = nv04_graph_fifo_access;
191 engine->graph.load_context = nv20_graph_load_context;
192 engine->graph.unload_context = nv20_graph_unload_context;
193 engine->graph.set_tile_region = nv20_graph_set_tile_region;
194 engine->fifo.channels = 32;
195 engine->fifo.init = nv10_fifo_init;
196 engine->fifo.takedown = nv04_fifo_fini;
197 engine->fifo.disable = nv04_fifo_disable;
198 engine->fifo.enable = nv04_fifo_enable;
199 engine->fifo.reassign = nv04_fifo_reassign;
200 engine->fifo.cache_pull = nv04_fifo_cache_pull;
201 engine->fifo.channel_id = nv10_fifo_channel_id;
202 engine->fifo.create_context = nv10_fifo_create_context;
203 engine->fifo.destroy_context = nv04_fifo_destroy_context;
204 engine->fifo.load_context = nv10_fifo_load_context;
205 engine->fifo.unload_context = nv10_fifo_unload_context;
206 engine->display.early_init = nv04_display_early_init;
207 engine->display.late_takedown = nv04_display_late_takedown;
208 engine->display.create = nv04_display_create;
209 engine->display.init = nv04_display_init;
210 engine->display.destroy = nv04_display_destroy;
211 engine->gpio.init = nouveau_stub_init;
212 engine->gpio.takedown = nouveau_stub_takedown;
213 engine->gpio.get = nv10_gpio_get;
214 engine->gpio.set = nv10_gpio_set;
215 engine->gpio.irq_enable = NULL;
216 engine->pm.clock_get = nv04_pm_clock_get;
217 engine->pm.clock_pre = nv04_pm_clock_pre;
218 engine->pm.clock_set = nv04_pm_clock_set;
219 engine->crypt.init = nouveau_stub_init;
220 engine->crypt.takedown = nouveau_stub_takedown;
221 engine->vram.init = nouveau_mem_detect;
222 engine->vram.flags_valid = nouveau_mem_flags_valid;
223 break;
224 case 0x30:
225 engine->instmem.init = nv04_instmem_init;
226 engine->instmem.takedown = nv04_instmem_takedown;
227 engine->instmem.suspend = nv04_instmem_suspend;
228 engine->instmem.resume = nv04_instmem_resume;
229 engine->instmem.get = nv04_instmem_get;
230 engine->instmem.put = nv04_instmem_put;
231 engine->instmem.map = nv04_instmem_map;
232 engine->instmem.unmap = nv04_instmem_unmap;
233 engine->instmem.flush = nv04_instmem_flush;
234 engine->mc.init = nv04_mc_init;
235 engine->mc.takedown = nv04_mc_takedown;
236 engine->timer.init = nv04_timer_init;
237 engine->timer.read = nv04_timer_read;
238 engine->timer.takedown = nv04_timer_takedown;
239 engine->fb.init = nv30_fb_init;
240 engine->fb.takedown = nv30_fb_takedown;
241 engine->fb.init_tile_region = nv30_fb_init_tile_region;
242 engine->fb.set_tile_region = nv10_fb_set_tile_region;
243 engine->fb.free_tile_region = nv30_fb_free_tile_region;
244 engine->graph.init = nv30_graph_init;
245 engine->graph.takedown = nv20_graph_takedown;
246 engine->graph.fifo_access = nv04_graph_fifo_access;
247 engine->graph.channel = nv10_graph_channel;
248 engine->graph.create_context = nv20_graph_create_context;
249 engine->graph.destroy_context = nv20_graph_destroy_context;
250 engine->graph.load_context = nv20_graph_load_context;
251 engine->graph.unload_context = nv20_graph_unload_context;
252 engine->graph.set_tile_region = nv20_graph_set_tile_region;
253 engine->fifo.channels = 32;
254 engine->fifo.init = nv10_fifo_init;
255 engine->fifo.takedown = nv04_fifo_fini;
256 engine->fifo.disable = nv04_fifo_disable;
257 engine->fifo.enable = nv04_fifo_enable;
258 engine->fifo.reassign = nv04_fifo_reassign;
259 engine->fifo.cache_pull = nv04_fifo_cache_pull;
260 engine->fifo.channel_id = nv10_fifo_channel_id;
261 engine->fifo.create_context = nv10_fifo_create_context;
262 engine->fifo.destroy_context = nv04_fifo_destroy_context;
263 engine->fifo.load_context = nv10_fifo_load_context;
264 engine->fifo.unload_context = nv10_fifo_unload_context;
265 engine->display.early_init = nv04_display_early_init;
266 engine->display.late_takedown = nv04_display_late_takedown;
267 engine->display.create = nv04_display_create;
268 engine->display.init = nv04_display_init;
269 engine->display.destroy = nv04_display_destroy;
270 engine->gpio.init = nouveau_stub_init;
271 engine->gpio.takedown = nouveau_stub_takedown;
272 engine->gpio.get = nv10_gpio_get;
273 engine->gpio.set = nv10_gpio_set;
274 engine->gpio.irq_enable = NULL;
275 engine->pm.clock_get = nv04_pm_clock_get;
276 engine->pm.clock_pre = nv04_pm_clock_pre;
277 engine->pm.clock_set = nv04_pm_clock_set;
278 engine->pm.voltage_get = nouveau_voltage_gpio_get;
279 engine->pm.voltage_set = nouveau_voltage_gpio_set;
280 engine->crypt.init = nouveau_stub_init;
281 engine->crypt.takedown = nouveau_stub_takedown;
282 engine->vram.init = nouveau_mem_detect;
283 engine->vram.flags_valid = nouveau_mem_flags_valid;
284 break;
285 case 0x40:
286 case 0x60:
287 engine->instmem.init = nv04_instmem_init;
288 engine->instmem.takedown = nv04_instmem_takedown;
289 engine->instmem.suspend = nv04_instmem_suspend;
290 engine->instmem.resume = nv04_instmem_resume;
291 engine->instmem.get = nv04_instmem_get;
292 engine->instmem.put = nv04_instmem_put;
293 engine->instmem.map = nv04_instmem_map;
294 engine->instmem.unmap = nv04_instmem_unmap;
295 engine->instmem.flush = nv04_instmem_flush;
296 engine->mc.init = nv40_mc_init;
297 engine->mc.takedown = nv40_mc_takedown;
298 engine->timer.init = nv04_timer_init;
299 engine->timer.read = nv04_timer_read;
300 engine->timer.takedown = nv04_timer_takedown;
301 engine->fb.init = nv40_fb_init;
302 engine->fb.takedown = nv40_fb_takedown;
303 engine->fb.init_tile_region = nv30_fb_init_tile_region;
304 engine->fb.set_tile_region = nv40_fb_set_tile_region;
305 engine->fb.free_tile_region = nv30_fb_free_tile_region;
306 engine->graph.init = nv40_graph_init;
307 engine->graph.takedown = nv40_graph_takedown;
308 engine->graph.fifo_access = nv04_graph_fifo_access;
309 engine->graph.channel = nv40_graph_channel;
310 engine->graph.create_context = nv40_graph_create_context;
311 engine->graph.destroy_context = nv40_graph_destroy_context;
312 engine->graph.load_context = nv40_graph_load_context;
313 engine->graph.unload_context = nv40_graph_unload_context;
314 engine->graph.set_tile_region = nv40_graph_set_tile_region;
315 engine->fifo.channels = 32;
316 engine->fifo.init = nv40_fifo_init;
317 engine->fifo.takedown = nv04_fifo_fini;
318 engine->fifo.disable = nv04_fifo_disable;
319 engine->fifo.enable = nv04_fifo_enable;
320 engine->fifo.reassign = nv04_fifo_reassign;
321 engine->fifo.cache_pull = nv04_fifo_cache_pull;
322 engine->fifo.channel_id = nv10_fifo_channel_id;
323 engine->fifo.create_context = nv40_fifo_create_context;
324 engine->fifo.destroy_context = nv04_fifo_destroy_context;
325 engine->fifo.load_context = nv40_fifo_load_context;
326 engine->fifo.unload_context = nv40_fifo_unload_context;
327 engine->display.early_init = nv04_display_early_init;
328 engine->display.late_takedown = nv04_display_late_takedown;
329 engine->display.create = nv04_display_create;
330 engine->display.init = nv04_display_init;
331 engine->display.destroy = nv04_display_destroy;
332 engine->gpio.init = nouveau_stub_init;
333 engine->gpio.takedown = nouveau_stub_takedown;
334 engine->gpio.get = nv10_gpio_get;
335 engine->gpio.set = nv10_gpio_set;
336 engine->gpio.irq_enable = NULL;
337 engine->pm.clock_get = nv04_pm_clock_get;
338 engine->pm.clock_pre = nv04_pm_clock_pre;
339 engine->pm.clock_set = nv04_pm_clock_set;
340 engine->pm.voltage_get = nouveau_voltage_gpio_get;
341 engine->pm.voltage_set = nouveau_voltage_gpio_set;
342 engine->pm.temp_get = nv40_temp_get;
343 engine->crypt.init = nouveau_stub_init;
344 engine->crypt.takedown = nouveau_stub_takedown;
345 engine->vram.init = nouveau_mem_detect;
346 engine->vram.flags_valid = nouveau_mem_flags_valid;
347 break;
348 case 0x50:
349 case 0x80: /* gotta love NVIDIA's consistency.. */
350 case 0x90:
351 case 0xA0:
352 engine->instmem.init = nv50_instmem_init;
353 engine->instmem.takedown = nv50_instmem_takedown;
354 engine->instmem.suspend = nv50_instmem_suspend;
355 engine->instmem.resume = nv50_instmem_resume;
356 engine->instmem.get = nv50_instmem_get;
357 engine->instmem.put = nv50_instmem_put;
358 engine->instmem.map = nv50_instmem_map;
359 engine->instmem.unmap = nv50_instmem_unmap;
360 if (dev_priv->chipset == 0x50)
361 engine->instmem.flush = nv50_instmem_flush;
362 else
363 engine->instmem.flush = nv84_instmem_flush;
364 engine->mc.init = nv50_mc_init;
365 engine->mc.takedown = nv50_mc_takedown;
366 engine->timer.init = nv04_timer_init;
367 engine->timer.read = nv04_timer_read;
368 engine->timer.takedown = nv04_timer_takedown;
369 engine->fb.init = nv50_fb_init;
370 engine->fb.takedown = nv50_fb_takedown;
371 engine->graph.init = nv50_graph_init;
372 engine->graph.takedown = nv50_graph_takedown;
373 engine->graph.fifo_access = nv50_graph_fifo_access;
374 engine->graph.channel = nv50_graph_channel;
375 engine->graph.create_context = nv50_graph_create_context;
376 engine->graph.destroy_context = nv50_graph_destroy_context;
377 engine->graph.load_context = nv50_graph_load_context;
378 engine->graph.unload_context = nv50_graph_unload_context;
379 if (dev_priv->chipset != 0x86)
380 engine->graph.tlb_flush = nv50_graph_tlb_flush;
381 else {
382 /* from what i can see nvidia do this on every
383 * pre-NVA3 board except NVAC, but, we've only
384 * ever seen problems on NV86
385 */
386 engine->graph.tlb_flush = nv86_graph_tlb_flush;
387 }
388 engine->fifo.channels = 128;
389 engine->fifo.init = nv50_fifo_init;
390 engine->fifo.takedown = nv50_fifo_takedown;
391 engine->fifo.disable = nv04_fifo_disable;
392 engine->fifo.enable = nv04_fifo_enable;
393 engine->fifo.reassign = nv04_fifo_reassign;
394 engine->fifo.channel_id = nv50_fifo_channel_id;
395 engine->fifo.create_context = nv50_fifo_create_context;
396 engine->fifo.destroy_context = nv50_fifo_destroy_context;
397 engine->fifo.load_context = nv50_fifo_load_context;
398 engine->fifo.unload_context = nv50_fifo_unload_context;
399 engine->fifo.tlb_flush = nv50_fifo_tlb_flush;
400 engine->display.early_init = nv50_display_early_init;
401 engine->display.late_takedown = nv50_display_late_takedown;
402 engine->display.create = nv50_display_create;
403 engine->display.init = nv50_display_init;
404 engine->display.destroy = nv50_display_destroy;
405 engine->gpio.init = nv50_gpio_init;
406 engine->gpio.takedown = nv50_gpio_fini;
407 engine->gpio.get = nv50_gpio_get;
408 engine->gpio.set = nv50_gpio_set;
409 engine->gpio.irq_register = nv50_gpio_irq_register;
410 engine->gpio.irq_unregister = nv50_gpio_irq_unregister;
411 engine->gpio.irq_enable = nv50_gpio_irq_enable;
412 switch (dev_priv->chipset) {
413 case 0x84:
414 case 0x86:
415 case 0x92:
416 case 0x94:
417 case 0x96:
418 case 0x98:
419 case 0xa0:
420 case 0xaa:
421 case 0xac:
422 case 0x50:
423 engine->pm.clock_get = nv50_pm_clock_get;
424 engine->pm.clock_pre = nv50_pm_clock_pre;
425 engine->pm.clock_set = nv50_pm_clock_set;
426 break;
427 default:
428 engine->pm.clock_get = nva3_pm_clock_get;
429 engine->pm.clock_pre = nva3_pm_clock_pre;
430 engine->pm.clock_set = nva3_pm_clock_set;
431 break;
432 }
433 engine->pm.voltage_get = nouveau_voltage_gpio_get;
434 engine->pm.voltage_set = nouveau_voltage_gpio_set;
435 if (dev_priv->chipset >= 0x84)
436 engine->pm.temp_get = nv84_temp_get;
437 else
438 engine->pm.temp_get = nv40_temp_get;
439 switch (dev_priv->chipset) {
440 case 0x84:
441 case 0x86:
442 case 0x92:
443 case 0x94:
444 case 0x96:
445 case 0xa0:
446 engine->crypt.init = nv84_crypt_init;
447 engine->crypt.takedown = nv84_crypt_fini;
448 engine->crypt.create_context = nv84_crypt_create_context;
449 engine->crypt.destroy_context = nv84_crypt_destroy_context;
450 engine->crypt.tlb_flush = nv84_crypt_tlb_flush;
451 break;
452 default:
453 engine->crypt.init = nouveau_stub_init;
454 engine->crypt.takedown = nouveau_stub_takedown;
455 break;
456 }
457 engine->vram.init = nv50_vram_init;
458 engine->vram.get = nv50_vram_new;
459 engine->vram.put = nv50_vram_del;
460 engine->vram.flags_valid = nv50_vram_flags_valid;
461 break;
462 case 0xC0:
463 engine->instmem.init = nvc0_instmem_init;
464 engine->instmem.takedown = nvc0_instmem_takedown;
465 engine->instmem.suspend = nvc0_instmem_suspend;
466 engine->instmem.resume = nvc0_instmem_resume;
467 engine->instmem.get = nv50_instmem_get;
468 engine->instmem.put = nv50_instmem_put;
469 engine->instmem.map = nv50_instmem_map;
470 engine->instmem.unmap = nv50_instmem_unmap;
471 engine->instmem.flush = nv84_instmem_flush;
472 engine->mc.init = nv50_mc_init;
473 engine->mc.takedown = nv50_mc_takedown;
474 engine->timer.init = nv04_timer_init;
475 engine->timer.read = nv04_timer_read;
476 engine->timer.takedown = nv04_timer_takedown;
477 engine->fb.init = nvc0_fb_init;
478 engine->fb.takedown = nvc0_fb_takedown;
479 engine->graph.init = nvc0_graph_init;
480 engine->graph.takedown = nvc0_graph_takedown;
481 engine->graph.fifo_access = nvc0_graph_fifo_access;
482 engine->graph.channel = nvc0_graph_channel;
483 engine->graph.create_context = nvc0_graph_create_context;
484 engine->graph.destroy_context = nvc0_graph_destroy_context;
485 engine->graph.load_context = nvc0_graph_load_context;
486 engine->graph.unload_context = nvc0_graph_unload_context;
487 engine->fifo.channels = 128;
488 engine->fifo.init = nvc0_fifo_init;
489 engine->fifo.takedown = nvc0_fifo_takedown;
490 engine->fifo.disable = nvc0_fifo_disable;
491 engine->fifo.enable = nvc0_fifo_enable;
492 engine->fifo.reassign = nvc0_fifo_reassign;
493 engine->fifo.channel_id = nvc0_fifo_channel_id;
494 engine->fifo.create_context = nvc0_fifo_create_context;
495 engine->fifo.destroy_context = nvc0_fifo_destroy_context;
496 engine->fifo.load_context = nvc0_fifo_load_context;
497 engine->fifo.unload_context = nvc0_fifo_unload_context;
498 engine->display.early_init = nv50_display_early_init;
499 engine->display.late_takedown = nv50_display_late_takedown;
500 engine->display.create = nv50_display_create;
501 engine->display.init = nv50_display_init;
502 engine->display.destroy = nv50_display_destroy;
503 engine->gpio.init = nv50_gpio_init;
504 engine->gpio.takedown = nouveau_stub_takedown;
505 engine->gpio.get = nv50_gpio_get;
506 engine->gpio.set = nv50_gpio_set;
507 engine->gpio.irq_register = nv50_gpio_irq_register;
508 engine->gpio.irq_unregister = nv50_gpio_irq_unregister;
509 engine->gpio.irq_enable = nv50_gpio_irq_enable;
510 engine->crypt.init = nouveau_stub_init;
511 engine->crypt.takedown = nouveau_stub_takedown;
512 engine->vram.init = nvc0_vram_init;
513 engine->vram.get = nvc0_vram_new;
514 engine->vram.put = nv50_vram_del;
515 engine->vram.flags_valid = nvc0_vram_flags_valid;
516 break;
517 default:
518 NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset);
519 return 1;
520 }
521
522 return 0;
523 }
524
525 static unsigned int
526 nouveau_vga_set_decode(void *priv, bool state)
527 {
528 struct drm_device *dev = priv;
529 struct drm_nouveau_private *dev_priv = dev->dev_private;
530
531 if (dev_priv->chipset >= 0x40)
532 nv_wr32(dev, 0x88054, state);
533 else
534 nv_wr32(dev, 0x1854, state);
535
536 if (state)
537 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
538 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
539 else
540 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
541 }
542
543 static int
544 nouveau_card_init_channel(struct drm_device *dev)
545 {
546 struct drm_nouveau_private *dev_priv = dev->dev_private;
547 int ret;
548
549 ret = nouveau_channel_alloc(dev, &dev_priv->channel,
550 (struct drm_file *)-2, NvDmaFB, NvDmaTT);
551 if (ret)
552 return ret;
553
554 mutex_unlock(&dev_priv->channel->mutex);
555 return 0;
556 }
557
558 static void nouveau_switcheroo_set_state(struct pci_dev *pdev,
559 enum vga_switcheroo_state state)
560 {
561 struct drm_device *dev = pci_get_drvdata(pdev);
562 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
563 if (state == VGA_SWITCHEROO_ON) {
564 printk(KERN_ERR "VGA switcheroo: switched nouveau on\n");
565 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
566 nouveau_pci_resume(pdev);
567 drm_kms_helper_poll_enable(dev);
568 dev->switch_power_state = DRM_SWITCH_POWER_ON;
569 } else {
570 printk(KERN_ERR "VGA switcheroo: switched nouveau off\n");
571 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
572 drm_kms_helper_poll_disable(dev);
573 nouveau_pci_suspend(pdev, pmm);
574 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
575 }
576 }
577
578 static void nouveau_switcheroo_reprobe(struct pci_dev *pdev)
579 {
580 struct drm_device *dev = pci_get_drvdata(pdev);
581 nouveau_fbcon_output_poll_changed(dev);
582 }
583
584 static bool nouveau_switcheroo_can_switch(struct pci_dev *pdev)
585 {
586 struct drm_device *dev = pci_get_drvdata(pdev);
587 bool can_switch;
588
589 spin_lock(&dev->count_lock);
590 can_switch = (dev->open_count == 0);
591 spin_unlock(&dev->count_lock);
592 return can_switch;
593 }
594
595 int
596 nouveau_card_init(struct drm_device *dev)
597 {
598 struct drm_nouveau_private *dev_priv = dev->dev_private;
599 struct nouveau_engine *engine;
600 int ret;
601
602 vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode);
603 vga_switcheroo_register_client(dev->pdev, nouveau_switcheroo_set_state,
604 nouveau_switcheroo_reprobe,
605 nouveau_switcheroo_can_switch);
606
607 /* Initialise internal driver API hooks */
608 ret = nouveau_init_engine_ptrs(dev);
609 if (ret)
610 goto out;
611 engine = &dev_priv->engine;
612 spin_lock_init(&dev_priv->channels.lock);
613 spin_lock_init(&dev_priv->tile.lock);
614 spin_lock_init(&dev_priv->context_switch_lock);
615
616 /* Make the CRTCs and I2C buses accessible */
617 ret = engine->display.early_init(dev);
618 if (ret)
619 goto out;
620
621 /* Parse BIOS tables / Run init tables if card not POSTed */
622 ret = nouveau_bios_init(dev);
623 if (ret)
624 goto out_display_early;
625
626 nouveau_pm_init(dev);
627
628 ret = nouveau_mem_vram_init(dev);
629 if (ret)
630 goto out_bios;
631
632 ret = nouveau_gpuobj_init(dev);
633 if (ret)
634 goto out_vram;
635
636 ret = engine->instmem.init(dev);
637 if (ret)
638 goto out_gpuobj;
639
640 ret = nouveau_mem_gart_init(dev);
641 if (ret)
642 goto out_instmem;
643
644 /* PMC */
645 ret = engine->mc.init(dev);
646 if (ret)
647 goto out_gart;
648
649 /* PGPIO */
650 ret = engine->gpio.init(dev);
651 if (ret)
652 goto out_mc;
653
654 /* PTIMER */
655 ret = engine->timer.init(dev);
656 if (ret)
657 goto out_gpio;
658
659 /* PFB */
660 ret = engine->fb.init(dev);
661 if (ret)
662 goto out_timer;
663
664 if (nouveau_noaccel)
665 engine->graph.accel_blocked = true;
666 else {
667 /* PGRAPH */
668 ret = engine->graph.init(dev);
669 if (ret)
670 goto out_fb;
671
672 /* PCRYPT */
673 ret = engine->crypt.init(dev);
674 if (ret)
675 goto out_graph;
676
677 /* PFIFO */
678 ret = engine->fifo.init(dev);
679 if (ret)
680 goto out_crypt;
681 }
682
683 ret = engine->display.create(dev);
684 if (ret)
685 goto out_fifo;
686
687 ret = drm_vblank_init(dev, nv_two_heads(dev) ? 2 : 1);
688 if (ret)
689 goto out_vblank;
690
691 ret = nouveau_irq_init(dev);
692 if (ret)
693 goto out_vblank;
694
695 /* what about PVIDEO/PCRTC/PRAMDAC etc? */
696
697 if (!engine->graph.accel_blocked) {
698 ret = nouveau_fence_init(dev);
699 if (ret)
700 goto out_irq;
701
702 ret = nouveau_card_init_channel(dev);
703 if (ret)
704 goto out_fence;
705 }
706
707 nouveau_fbcon_init(dev);
708 drm_kms_helper_poll_init(dev);
709 return 0;
710
711 out_fence:
712 nouveau_fence_fini(dev);
713 out_irq:
714 nouveau_irq_fini(dev);
715 out_vblank:
716 drm_vblank_cleanup(dev);
717 engine->display.destroy(dev);
718 out_fifo:
719 if (!nouveau_noaccel)
720 engine->fifo.takedown(dev);
721 out_crypt:
722 if (!nouveau_noaccel)
723 engine->crypt.takedown(dev);
724 out_graph:
725 if (!nouveau_noaccel)
726 engine->graph.takedown(dev);
727 out_fb:
728 engine->fb.takedown(dev);
729 out_timer:
730 engine->timer.takedown(dev);
731 out_gpio:
732 engine->gpio.takedown(dev);
733 out_mc:
734 engine->mc.takedown(dev);
735 out_gart:
736 nouveau_mem_gart_fini(dev);
737 out_instmem:
738 engine->instmem.takedown(dev);
739 out_gpuobj:
740 nouveau_gpuobj_takedown(dev);
741 out_vram:
742 nouveau_mem_vram_fini(dev);
743 out_bios:
744 nouveau_pm_fini(dev);
745 nouveau_bios_takedown(dev);
746 out_display_early:
747 engine->display.late_takedown(dev);
748 out:
749 vga_client_register(dev->pdev, NULL, NULL, NULL);
750 return ret;
751 }
752
753 static void nouveau_card_takedown(struct drm_device *dev)
754 {
755 struct drm_nouveau_private *dev_priv = dev->dev_private;
756 struct nouveau_engine *engine = &dev_priv->engine;
757
758 if (!engine->graph.accel_blocked) {
759 nouveau_fence_fini(dev);
760 nouveau_channel_put_unlocked(&dev_priv->channel);
761 }
762
763 if (!nouveau_noaccel) {
764 engine->fifo.takedown(dev);
765 engine->crypt.takedown(dev);
766 engine->graph.takedown(dev);
767 }
768 engine->fb.takedown(dev);
769 engine->timer.takedown(dev);
770 engine->gpio.takedown(dev);
771 engine->mc.takedown(dev);
772 engine->display.late_takedown(dev);
773
774 mutex_lock(&dev->struct_mutex);
775 ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
776 ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_TT);
777 mutex_unlock(&dev->struct_mutex);
778 nouveau_mem_gart_fini(dev);
779
780 engine->instmem.takedown(dev);
781 nouveau_gpuobj_takedown(dev);
782 nouveau_mem_vram_fini(dev);
783
784 nouveau_irq_fini(dev);
785 drm_vblank_cleanup(dev);
786
787 nouveau_pm_fini(dev);
788 nouveau_bios_takedown(dev);
789
790 vga_client_register(dev->pdev, NULL, NULL, NULL);
791 }
792
793 /* here a client dies, release the stuff that was allocated for its
794 * file_priv */
795 void nouveau_preclose(struct drm_device *dev, struct drm_file *file_priv)
796 {
797 nouveau_channel_cleanup(dev, file_priv);
798 }
799
800 /* first module load, setup the mmio/fb mapping */
801 /* KMS: we need mmio at load time, not when the first drm client opens. */
802 int nouveau_firstopen(struct drm_device *dev)
803 {
804 return 0;
805 }
806
807 /* if we have an OF card, copy vbios to RAMIN */
808 static void nouveau_OF_copy_vbios_to_ramin(struct drm_device *dev)
809 {
810 #if defined(__powerpc__)
811 int size, i;
812 const uint32_t *bios;
813 struct device_node *dn = pci_device_to_OF_node(dev->pdev);
814 if (!dn) {
815 NV_INFO(dev, "Unable to get the OF node\n");
816 return;
817 }
818
819 bios = of_get_property(dn, "NVDA,BMP", &size);
820 if (bios) {
821 for (i = 0; i < size; i += 4)
822 nv_wi32(dev, i, bios[i/4]);
823 NV_INFO(dev, "OF bios successfully copied (%d bytes)\n", size);
824 } else {
825 NV_INFO(dev, "Unable to get the OF bios\n");
826 }
827 #endif
828 }
829
830 static struct apertures_struct *nouveau_get_apertures(struct drm_device *dev)
831 {
832 struct pci_dev *pdev = dev->pdev;
833 struct apertures_struct *aper = alloc_apertures(3);
834 if (!aper)
835 return NULL;
836
837 aper->ranges[0].base = pci_resource_start(pdev, 1);
838 aper->ranges[0].size = pci_resource_len(pdev, 1);
839 aper->count = 1;
840
841 if (pci_resource_len(pdev, 2)) {
842 aper->ranges[aper->count].base = pci_resource_start(pdev, 2);
843 aper->ranges[aper->count].size = pci_resource_len(pdev, 2);
844 aper->count++;
845 }
846
847 if (pci_resource_len(pdev, 3)) {
848 aper->ranges[aper->count].base = pci_resource_start(pdev, 3);
849 aper->ranges[aper->count].size = pci_resource_len(pdev, 3);
850 aper->count++;
851 }
852
853 return aper;
854 }
855
856 static int nouveau_remove_conflicting_drivers(struct drm_device *dev)
857 {
858 struct drm_nouveau_private *dev_priv = dev->dev_private;
859 bool primary = false;
860 dev_priv->apertures = nouveau_get_apertures(dev);
861 if (!dev_priv->apertures)
862 return -ENOMEM;
863
864 #ifdef CONFIG_X86
865 primary = dev->pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
866 #endif
867
868 remove_conflicting_framebuffers(dev_priv->apertures, "nouveaufb", primary);
869 return 0;
870 }
871
872 int nouveau_load(struct drm_device *dev, unsigned long flags)
873 {
874 struct drm_nouveau_private *dev_priv;
875 uint32_t reg0;
876 resource_size_t mmio_start_offs;
877 int ret;
878
879 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
880 if (!dev_priv) {
881 ret = -ENOMEM;
882 goto err_out;
883 }
884 dev->dev_private = dev_priv;
885 dev_priv->dev = dev;
886
887 dev_priv->flags = flags & NOUVEAU_FLAGS;
888
889 NV_DEBUG(dev, "vendor: 0x%X device: 0x%X class: 0x%X\n",
890 dev->pci_vendor, dev->pci_device, dev->pdev->class);
891
892 /* resource 0 is mmio regs */
893 /* resource 1 is linear FB */
894 /* resource 2 is RAMIN (mmio regs + 0x1000000) */
895 /* resource 6 is bios */
896
897 /* map the mmio regs */
898 mmio_start_offs = pci_resource_start(dev->pdev, 0);
899 dev_priv->mmio = ioremap(mmio_start_offs, 0x00800000);
900 if (!dev_priv->mmio) {
901 NV_ERROR(dev, "Unable to initialize the mmio mapping. "
902 "Please report your setup to " DRIVER_EMAIL "\n");
903 ret = -EINVAL;
904 goto err_priv;
905 }
906 NV_DEBUG(dev, "regs mapped ok at 0x%llx\n",
907 (unsigned long long)mmio_start_offs);
908
909 #ifdef __BIG_ENDIAN
910 /* Put the card in BE mode if it's not */
911 if (nv_rd32(dev, NV03_PMC_BOOT_1))
912 nv_wr32(dev, NV03_PMC_BOOT_1, 0x00000001);
913
914 DRM_MEMORYBARRIER();
915 #endif
916
917 /* Time to determine the card architecture */
918 reg0 = nv_rd32(dev, NV03_PMC_BOOT_0);
919
920 /* We're dealing with >=NV10 */
921 if ((reg0 & 0x0f000000) > 0) {
922 /* Bit 27-20 contain the architecture in hex */
923 dev_priv->chipset = (reg0 & 0xff00000) >> 20;
924 /* NV04 or NV05 */
925 } else if ((reg0 & 0xff00fff0) == 0x20004000) {
926 if (reg0 & 0x00f00000)
927 dev_priv->chipset = 0x05;
928 else
929 dev_priv->chipset = 0x04;
930 } else
931 dev_priv->chipset = 0xff;
932
933 switch (dev_priv->chipset & 0xf0) {
934 case 0x00:
935 case 0x10:
936 case 0x20:
937 case 0x30:
938 dev_priv->card_type = dev_priv->chipset & 0xf0;
939 break;
940 case 0x40:
941 case 0x60:
942 dev_priv->card_type = NV_40;
943 break;
944 case 0x50:
945 case 0x80:
946 case 0x90:
947 case 0xa0:
948 dev_priv->card_type = NV_50;
949 break;
950 case 0xc0:
951 dev_priv->card_type = NV_C0;
952 break;
953 default:
954 NV_INFO(dev, "Unsupported chipset 0x%08x\n", reg0);
955 ret = -EINVAL;
956 goto err_mmio;
957 }
958
959 NV_INFO(dev, "Detected an NV%2x generation card (0x%08x)\n",
960 dev_priv->card_type, reg0);
961
962 ret = nouveau_remove_conflicting_drivers(dev);
963 if (ret)
964 goto err_mmio;
965
966 /* Map PRAMIN BAR, or on older cards, the aperture withing BAR0 */
967 if (dev_priv->card_type >= NV_40) {
968 int ramin_bar = 2;
969 if (pci_resource_len(dev->pdev, ramin_bar) == 0)
970 ramin_bar = 3;
971
972 dev_priv->ramin_size = pci_resource_len(dev->pdev, ramin_bar);
973 dev_priv->ramin =
974 ioremap(pci_resource_start(dev->pdev, ramin_bar),
975 dev_priv->ramin_size);
976 if (!dev_priv->ramin) {
977 NV_ERROR(dev, "Failed to PRAMIN BAR");
978 ret = -ENOMEM;
979 goto err_mmio;
980 }
981 } else {
982 dev_priv->ramin_size = 1 * 1024 * 1024;
983 dev_priv->ramin = ioremap(mmio_start_offs + NV_RAMIN,
984 dev_priv->ramin_size);
985 if (!dev_priv->ramin) {
986 NV_ERROR(dev, "Failed to map BAR0 PRAMIN.\n");
987 ret = -ENOMEM;
988 goto err_mmio;
989 }
990 }
991
992 nouveau_OF_copy_vbios_to_ramin(dev);
993
994 /* Special flags */
995 if (dev->pci_device == 0x01a0)
996 dev_priv->flags |= NV_NFORCE;
997 else if (dev->pci_device == 0x01f0)
998 dev_priv->flags |= NV_NFORCE2;
999
1000 /* For kernel modesetting, init card now and bring up fbcon */
1001 ret = nouveau_card_init(dev);
1002 if (ret)
1003 goto err_ramin;
1004
1005 return 0;
1006
1007 err_ramin:
1008 iounmap(dev_priv->ramin);
1009 err_mmio:
1010 iounmap(dev_priv->mmio);
1011 err_priv:
1012 kfree(dev_priv);
1013 dev->dev_private = NULL;
1014 err_out:
1015 return ret;
1016 }
1017
1018 void nouveau_lastclose(struct drm_device *dev)
1019 {
1020 vga_switcheroo_process_delayed_switch();
1021 }
1022
1023 int nouveau_unload(struct drm_device *dev)
1024 {
1025 struct drm_nouveau_private *dev_priv = dev->dev_private;
1026 struct nouveau_engine *engine = &dev_priv->engine;
1027
1028 drm_kms_helper_poll_fini(dev);
1029 nouveau_fbcon_fini(dev);
1030 engine->display.destroy(dev);
1031 nouveau_card_takedown(dev);
1032
1033 iounmap(dev_priv->mmio);
1034 iounmap(dev_priv->ramin);
1035
1036 kfree(dev_priv);
1037 dev->dev_private = NULL;
1038 return 0;
1039 }
1040
1041 int nouveau_ioctl_getparam(struct drm_device *dev, void *data,
1042 struct drm_file *file_priv)
1043 {
1044 struct drm_nouveau_private *dev_priv = dev->dev_private;
1045 struct drm_nouveau_getparam *getparam = data;
1046
1047 switch (getparam->param) {
1048 case NOUVEAU_GETPARAM_CHIPSET_ID:
1049 getparam->value = dev_priv->chipset;
1050 break;
1051 case NOUVEAU_GETPARAM_PCI_VENDOR:
1052 getparam->value = dev->pci_vendor;
1053 break;
1054 case NOUVEAU_GETPARAM_PCI_DEVICE:
1055 getparam->value = dev->pci_device;
1056 break;
1057 case NOUVEAU_GETPARAM_BUS_TYPE:
1058 if (drm_pci_device_is_agp(dev))
1059 getparam->value = NV_AGP;
1060 else if (drm_pci_device_is_pcie(dev))
1061 getparam->value = NV_PCIE;
1062 else
1063 getparam->value = NV_PCI;
1064 break;
1065 case NOUVEAU_GETPARAM_FB_SIZE:
1066 getparam->value = dev_priv->fb_available_size;
1067 break;
1068 case NOUVEAU_GETPARAM_AGP_SIZE:
1069 getparam->value = dev_priv->gart_info.aper_size;
1070 break;
1071 case NOUVEAU_GETPARAM_VM_VRAM_BASE:
1072 getparam->value = 0; /* deprecated */
1073 break;
1074 case NOUVEAU_GETPARAM_PTIMER_TIME:
1075 getparam->value = dev_priv->engine.timer.read(dev);
1076 break;
1077 case NOUVEAU_GETPARAM_HAS_BO_USAGE:
1078 getparam->value = 1;
1079 break;
1080 case NOUVEAU_GETPARAM_HAS_PAGEFLIP:
1081 getparam->value = 1;
1082 break;
1083 case NOUVEAU_GETPARAM_GRAPH_UNITS:
1084 /* NV40 and NV50 versions are quite different, but register
1085 * address is the same. User is supposed to know the card
1086 * family anyway... */
1087 if (dev_priv->chipset >= 0x40) {
1088 getparam->value = nv_rd32(dev, NV40_PMC_GRAPH_UNITS);
1089 break;
1090 }
1091 /* FALLTHRU */
1092 default:
1093 NV_DEBUG(dev, "unknown parameter %lld\n", getparam->param);
1094 return -EINVAL;
1095 }
1096
1097 return 0;
1098 }
1099
1100 int
1101 nouveau_ioctl_setparam(struct drm_device *dev, void *data,
1102 struct drm_file *file_priv)
1103 {
1104 struct drm_nouveau_setparam *setparam = data;
1105
1106 switch (setparam->param) {
1107 default:
1108 NV_DEBUG(dev, "unknown parameter %lld\n", setparam->param);
1109 return -EINVAL;
1110 }
1111
1112 return 0;
1113 }
1114
1115 /* Wait until (value(reg) & mask) == val, up until timeout has hit */
1116 bool
1117 nouveau_wait_eq(struct drm_device *dev, uint64_t timeout,
1118 uint32_t reg, uint32_t mask, uint32_t val)
1119 {
1120 struct drm_nouveau_private *dev_priv = dev->dev_private;
1121 struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1122 uint64_t start = ptimer->read(dev);
1123
1124 do {
1125 if ((nv_rd32(dev, reg) & mask) == val)
1126 return true;
1127 } while (ptimer->read(dev) - start < timeout);
1128
1129 return false;
1130 }
1131
1132 /* Wait until (value(reg) & mask) != val, up until timeout has hit */
1133 bool
1134 nouveau_wait_ne(struct drm_device *dev, uint64_t timeout,
1135 uint32_t reg, uint32_t mask, uint32_t val)
1136 {
1137 struct drm_nouveau_private *dev_priv = dev->dev_private;
1138 struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1139 uint64_t start = ptimer->read(dev);
1140
1141 do {
1142 if ((nv_rd32(dev, reg) & mask) != val)
1143 return true;
1144 } while (ptimer->read(dev) - start < timeout);
1145
1146 return false;
1147 }
1148
1149 /* Waits for PGRAPH to go completely idle */
1150 bool nouveau_wait_for_idle(struct drm_device *dev)
1151 {
1152 struct drm_nouveau_private *dev_priv = dev->dev_private;
1153 uint32_t mask = ~0;
1154
1155 if (dev_priv->card_type == NV_40)
1156 mask &= ~NV40_PGRAPH_STATUS_SYNC_STALL;
1157
1158 if (!nv_wait(dev, NV04_PGRAPH_STATUS, mask, 0)) {
1159 NV_ERROR(dev, "PGRAPH idle timed out with status 0x%08x\n",
1160 nv_rd32(dev, NV04_PGRAPH_STATUS));
1161 return false;
1162 }
1163
1164 return true;
1165 }
1166
CRIS linux kernel tree