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FRV: Use generic show_interrupts()
[cris-mirror.git] / drivers / gpu / drm / nouveau / nv20_graph.c
blob8464b76798d5e4746af344ef260526a4b97fdee9
1 #include "drmP.h"
2 #include "drm.h"
3 #include "nouveau_drv.h"
4 #include "nouveau_drm.h"
5
6 /*
7 * NV20
8 * -----
9 * There are 3 families :
10 * NV20 is 0x10de:0x020*
11 * NV25/28 is 0x10de:0x025* / 0x10de:0x028*
12 * NV2A is 0x10de:0x02A0
13 *
14 * NV30
15 * -----
16 * There are 3 families :
17 * NV30/31 is 0x10de:0x030* / 0x10de:0x031*
18 * NV34 is 0x10de:0x032*
19 * NV35/36 is 0x10de:0x033* / 0x10de:0x034*
20 *
21 * Not seen in the wild, no dumps (probably NV35) :
22 * NV37 is 0x10de:0x00fc, 0x10de:0x00fd
23 * NV38 is 0x10de:0x0333, 0x10de:0x00fe
24 *
25 */
26
27 #define NV20_GRCTX_SIZE (3580*4)
28 #define NV25_GRCTX_SIZE (3529*4)
29 #define NV2A_GRCTX_SIZE (3500*4)
30
31 #define NV30_31_GRCTX_SIZE (24392)
32 #define NV34_GRCTX_SIZE (18140)
33 #define NV35_36_GRCTX_SIZE (22396)
34
35 static int nv20_graph_register(struct drm_device *);
36 static int nv30_graph_register(struct drm_device *);
37 static void nv20_graph_isr(struct drm_device *);
38
39 static void
40 nv20_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx)
41 {
42 int i;
43
44 nv_wo32(ctx, 0x033c, 0xffff0000);
45 nv_wo32(ctx, 0x03a0, 0x0fff0000);
46 nv_wo32(ctx, 0x03a4, 0x0fff0000);
47 nv_wo32(ctx, 0x047c, 0x00000101);
48 nv_wo32(ctx, 0x0490, 0x00000111);
49 nv_wo32(ctx, 0x04a8, 0x44400000);
50 for (i = 0x04d4; i <= 0x04e0; i += 4)
51 nv_wo32(ctx, i, 0x00030303);
52 for (i = 0x04f4; i <= 0x0500; i += 4)
53 nv_wo32(ctx, i, 0x00080000);
54 for (i = 0x050c; i <= 0x0518; i += 4)
55 nv_wo32(ctx, i, 0x01012000);
56 for (i = 0x051c; i <= 0x0528; i += 4)
57 nv_wo32(ctx, i, 0x000105b8);
58 for (i = 0x052c; i <= 0x0538; i += 4)
59 nv_wo32(ctx, i, 0x00080008);
60 for (i = 0x055c; i <= 0x0598; i += 4)
61 nv_wo32(ctx, i, 0x07ff0000);
62 nv_wo32(ctx, 0x05a4, 0x4b7fffff);
63 nv_wo32(ctx, 0x05fc, 0x00000001);
64 nv_wo32(ctx, 0x0604, 0x00004000);
65 nv_wo32(ctx, 0x0610, 0x00000001);
66 nv_wo32(ctx, 0x0618, 0x00040000);
67 nv_wo32(ctx, 0x061c, 0x00010000);
68 for (i = 0x1c1c; i <= 0x248c; i += 16) {
69 nv_wo32(ctx, (i + 0), 0x10700ff9);
70 nv_wo32(ctx, (i + 4), 0x0436086c);
71 nv_wo32(ctx, (i + 8), 0x000c001b);
72 }
73 nv_wo32(ctx, 0x281c, 0x3f800000);
74 nv_wo32(ctx, 0x2830, 0x3f800000);
75 nv_wo32(ctx, 0x285c, 0x40000000);
76 nv_wo32(ctx, 0x2860, 0x3f800000);
77 nv_wo32(ctx, 0x2864, 0x3f000000);
78 nv_wo32(ctx, 0x286c, 0x40000000);
79 nv_wo32(ctx, 0x2870, 0x3f800000);
80 nv_wo32(ctx, 0x2878, 0xbf800000);
81 nv_wo32(ctx, 0x2880, 0xbf800000);
82 nv_wo32(ctx, 0x34a4, 0x000fe000);
83 nv_wo32(ctx, 0x3530, 0x000003f8);
84 nv_wo32(ctx, 0x3540, 0x002fe000);
85 for (i = 0x355c; i <= 0x3578; i += 4)
86 nv_wo32(ctx, i, 0x001c527c);
87 }
88
89 static void
90 nv25_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx)
91 {
92 int i;
93
94 nv_wo32(ctx, 0x035c, 0xffff0000);
95 nv_wo32(ctx, 0x03c0, 0x0fff0000);
96 nv_wo32(ctx, 0x03c4, 0x0fff0000);
97 nv_wo32(ctx, 0x049c, 0x00000101);
98 nv_wo32(ctx, 0x04b0, 0x00000111);
99 nv_wo32(ctx, 0x04c8, 0x00000080);
100 nv_wo32(ctx, 0x04cc, 0xffff0000);
101 nv_wo32(ctx, 0x04d0, 0x00000001);
102 nv_wo32(ctx, 0x04e4, 0x44400000);
103 nv_wo32(ctx, 0x04fc, 0x4b800000);
104 for (i = 0x0510; i <= 0x051c; i += 4)
105 nv_wo32(ctx, i, 0x00030303);
106 for (i = 0x0530; i <= 0x053c; i += 4)
107 nv_wo32(ctx, i, 0x00080000);
108 for (i = 0x0548; i <= 0x0554; i += 4)
109 nv_wo32(ctx, i, 0x01012000);
110 for (i = 0x0558; i <= 0x0564; i += 4)
111 nv_wo32(ctx, i, 0x000105b8);
112 for (i = 0x0568; i <= 0x0574; i += 4)
113 nv_wo32(ctx, i, 0x00080008);
114 for (i = 0x0598; i <= 0x05d4; i += 4)
115 nv_wo32(ctx, i, 0x07ff0000);
116 nv_wo32(ctx, 0x05e0, 0x4b7fffff);
117 nv_wo32(ctx, 0x0620, 0x00000080);
118 nv_wo32(ctx, 0x0624, 0x30201000);
119 nv_wo32(ctx, 0x0628, 0x70605040);
120 nv_wo32(ctx, 0x062c, 0xb0a09080);
121 nv_wo32(ctx, 0x0630, 0xf0e0d0c0);
122 nv_wo32(ctx, 0x0664, 0x00000001);
123 nv_wo32(ctx, 0x066c, 0x00004000);
124 nv_wo32(ctx, 0x0678, 0x00000001);
125 nv_wo32(ctx, 0x0680, 0x00040000);
126 nv_wo32(ctx, 0x0684, 0x00010000);
127 for (i = 0x1b04; i <= 0x2374; i += 16) {
128 nv_wo32(ctx, (i + 0), 0x10700ff9);
129 nv_wo32(ctx, (i + 4), 0x0436086c);
130 nv_wo32(ctx, (i + 8), 0x000c001b);
131 }
132 nv_wo32(ctx, 0x2704, 0x3f800000);
133 nv_wo32(ctx, 0x2718, 0x3f800000);
134 nv_wo32(ctx, 0x2744, 0x40000000);
135 nv_wo32(ctx, 0x2748, 0x3f800000);
136 nv_wo32(ctx, 0x274c, 0x3f000000);
137 nv_wo32(ctx, 0x2754, 0x40000000);
138 nv_wo32(ctx, 0x2758, 0x3f800000);
139 nv_wo32(ctx, 0x2760, 0xbf800000);
140 nv_wo32(ctx, 0x2768, 0xbf800000);
141 nv_wo32(ctx, 0x308c, 0x000fe000);
142 nv_wo32(ctx, 0x3108, 0x000003f8);
143 nv_wo32(ctx, 0x3468, 0x002fe000);
144 for (i = 0x3484; i <= 0x34a0; i += 4)
145 nv_wo32(ctx, i, 0x001c527c);
146 }
147
148 static void
149 nv2a_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx)
150 {
151 int i;
152
153 nv_wo32(ctx, 0x033c, 0xffff0000);
154 nv_wo32(ctx, 0x03a0, 0x0fff0000);
155 nv_wo32(ctx, 0x03a4, 0x0fff0000);
156 nv_wo32(ctx, 0x047c, 0x00000101);
157 nv_wo32(ctx, 0x0490, 0x00000111);
158 nv_wo32(ctx, 0x04a8, 0x44400000);
159 for (i = 0x04d4; i <= 0x04e0; i += 4)
160 nv_wo32(ctx, i, 0x00030303);
161 for (i = 0x04f4; i <= 0x0500; i += 4)
162 nv_wo32(ctx, i, 0x00080000);
163 for (i = 0x050c; i <= 0x0518; i += 4)
164 nv_wo32(ctx, i, 0x01012000);
165 for (i = 0x051c; i <= 0x0528; i += 4)
166 nv_wo32(ctx, i, 0x000105b8);
167 for (i = 0x052c; i <= 0x0538; i += 4)
168 nv_wo32(ctx, i, 0x00080008);
169 for (i = 0x055c; i <= 0x0598; i += 4)
170 nv_wo32(ctx, i, 0x07ff0000);
171 nv_wo32(ctx, 0x05a4, 0x4b7fffff);
172 nv_wo32(ctx, 0x05fc, 0x00000001);
173 nv_wo32(ctx, 0x0604, 0x00004000);
174 nv_wo32(ctx, 0x0610, 0x00000001);
175 nv_wo32(ctx, 0x0618, 0x00040000);
176 nv_wo32(ctx, 0x061c, 0x00010000);
177 for (i = 0x1a9c; i <= 0x22fc; i += 16) { /*XXX: check!! */
178 nv_wo32(ctx, (i + 0), 0x10700ff9);
179 nv_wo32(ctx, (i + 4), 0x0436086c);
180 nv_wo32(ctx, (i + 8), 0x000c001b);
181 }
182 nv_wo32(ctx, 0x269c, 0x3f800000);
183 nv_wo32(ctx, 0x26b0, 0x3f800000);
184 nv_wo32(ctx, 0x26dc, 0x40000000);
185 nv_wo32(ctx, 0x26e0, 0x3f800000);
186 nv_wo32(ctx, 0x26e4, 0x3f000000);
187 nv_wo32(ctx, 0x26ec, 0x40000000);
188 nv_wo32(ctx, 0x26f0, 0x3f800000);
189 nv_wo32(ctx, 0x26f8, 0xbf800000);
190 nv_wo32(ctx, 0x2700, 0xbf800000);
191 nv_wo32(ctx, 0x3024, 0x000fe000);
192 nv_wo32(ctx, 0x30a0, 0x000003f8);
193 nv_wo32(ctx, 0x33fc, 0x002fe000);
194 for (i = 0x341c; i <= 0x3438; i += 4)
195 nv_wo32(ctx, i, 0x001c527c);
196 }
197
198 static void
199 nv30_31_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx)
200 {
201 int i;
202
203 nv_wo32(ctx, 0x0410, 0x00000101);
204 nv_wo32(ctx, 0x0424, 0x00000111);
205 nv_wo32(ctx, 0x0428, 0x00000060);
206 nv_wo32(ctx, 0x0444, 0x00000080);
207 nv_wo32(ctx, 0x0448, 0xffff0000);
208 nv_wo32(ctx, 0x044c, 0x00000001);
209 nv_wo32(ctx, 0x0460, 0x44400000);
210 nv_wo32(ctx, 0x048c, 0xffff0000);
211 for (i = 0x04e0; i < 0x04e8; i += 4)
212 nv_wo32(ctx, i, 0x0fff0000);
213 nv_wo32(ctx, 0x04ec, 0x00011100);
214 for (i = 0x0508; i < 0x0548; i += 4)
215 nv_wo32(ctx, i, 0x07ff0000);
216 nv_wo32(ctx, 0x0550, 0x4b7fffff);
217 nv_wo32(ctx, 0x058c, 0x00000080);
218 nv_wo32(ctx, 0x0590, 0x30201000);
219 nv_wo32(ctx, 0x0594, 0x70605040);
220 nv_wo32(ctx, 0x0598, 0xb8a89888);
221 nv_wo32(ctx, 0x059c, 0xf8e8d8c8);
222 nv_wo32(ctx, 0x05b0, 0xb0000000);
223 for (i = 0x0600; i < 0x0640; i += 4)
224 nv_wo32(ctx, i, 0x00010588);
225 for (i = 0x0640; i < 0x0680; i += 4)
226 nv_wo32(ctx, i, 0x00030303);
227 for (i = 0x06c0; i < 0x0700; i += 4)
228 nv_wo32(ctx, i, 0x0008aae4);
229 for (i = 0x0700; i < 0x0740; i += 4)
230 nv_wo32(ctx, i, 0x01012000);
231 for (i = 0x0740; i < 0x0780; i += 4)
232 nv_wo32(ctx, i, 0x00080008);
233 nv_wo32(ctx, 0x085c, 0x00040000);
234 nv_wo32(ctx, 0x0860, 0x00010000);
235 for (i = 0x0864; i < 0x0874; i += 4)
236 nv_wo32(ctx, i, 0x00040004);
237 for (i = 0x1f18; i <= 0x3088 ; i += 16) {
238 nv_wo32(ctx, i + 0, 0x10700ff9);
239 nv_wo32(ctx, i + 1, 0x0436086c);
240 nv_wo32(ctx, i + 2, 0x000c001b);
241 }
242 for (i = 0x30b8; i < 0x30c8; i += 4)
243 nv_wo32(ctx, i, 0x0000ffff);
244 nv_wo32(ctx, 0x344c, 0x3f800000);
245 nv_wo32(ctx, 0x3808, 0x3f800000);
246 nv_wo32(ctx, 0x381c, 0x3f800000);
247 nv_wo32(ctx, 0x3848, 0x40000000);
248 nv_wo32(ctx, 0x384c, 0x3f800000);
249 nv_wo32(ctx, 0x3850, 0x3f000000);
250 nv_wo32(ctx, 0x3858, 0x40000000);
251 nv_wo32(ctx, 0x385c, 0x3f800000);
252 nv_wo32(ctx, 0x3864, 0xbf800000);
253 nv_wo32(ctx, 0x386c, 0xbf800000);
254 }
255
256 static void
257 nv34_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx)
258 {
259 int i;
260
261 nv_wo32(ctx, 0x040c, 0x01000101);
262 nv_wo32(ctx, 0x0420, 0x00000111);
263 nv_wo32(ctx, 0x0424, 0x00000060);
264 nv_wo32(ctx, 0x0440, 0x00000080);
265 nv_wo32(ctx, 0x0444, 0xffff0000);
266 nv_wo32(ctx, 0x0448, 0x00000001);
267 nv_wo32(ctx, 0x045c, 0x44400000);
268 nv_wo32(ctx, 0x0480, 0xffff0000);
269 for (i = 0x04d4; i < 0x04dc; i += 4)
270 nv_wo32(ctx, i, 0x0fff0000);
271 nv_wo32(ctx, 0x04e0, 0x00011100);
272 for (i = 0x04fc; i < 0x053c; i += 4)
273 nv_wo32(ctx, i, 0x07ff0000);
274 nv_wo32(ctx, 0x0544, 0x4b7fffff);
275 nv_wo32(ctx, 0x057c, 0x00000080);
276 nv_wo32(ctx, 0x0580, 0x30201000);
277 nv_wo32(ctx, 0x0584, 0x70605040);
278 nv_wo32(ctx, 0x0588, 0xb8a89888);
279 nv_wo32(ctx, 0x058c, 0xf8e8d8c8);
280 nv_wo32(ctx, 0x05a0, 0xb0000000);
281 for (i = 0x05f0; i < 0x0630; i += 4)
282 nv_wo32(ctx, i, 0x00010588);
283 for (i = 0x0630; i < 0x0670; i += 4)
284 nv_wo32(ctx, i, 0x00030303);
285 for (i = 0x06b0; i < 0x06f0; i += 4)
286 nv_wo32(ctx, i, 0x0008aae4);
287 for (i = 0x06f0; i < 0x0730; i += 4)
288 nv_wo32(ctx, i, 0x01012000);
289 for (i = 0x0730; i < 0x0770; i += 4)
290 nv_wo32(ctx, i, 0x00080008);
291 nv_wo32(ctx, 0x0850, 0x00040000);
292 nv_wo32(ctx, 0x0854, 0x00010000);
293 for (i = 0x0858; i < 0x0868; i += 4)
294 nv_wo32(ctx, i, 0x00040004);
295 for (i = 0x15ac; i <= 0x271c ; i += 16) {
296 nv_wo32(ctx, i + 0, 0x10700ff9);
297 nv_wo32(ctx, i + 1, 0x0436086c);
298 nv_wo32(ctx, i + 2, 0x000c001b);
299 }
300 for (i = 0x274c; i < 0x275c; i += 4)
301 nv_wo32(ctx, i, 0x0000ffff);
302 nv_wo32(ctx, 0x2ae0, 0x3f800000);
303 nv_wo32(ctx, 0x2e9c, 0x3f800000);
304 nv_wo32(ctx, 0x2eb0, 0x3f800000);
305 nv_wo32(ctx, 0x2edc, 0x40000000);
306 nv_wo32(ctx, 0x2ee0, 0x3f800000);
307 nv_wo32(ctx, 0x2ee4, 0x3f000000);
308 nv_wo32(ctx, 0x2eec, 0x40000000);
309 nv_wo32(ctx, 0x2ef0, 0x3f800000);
310 nv_wo32(ctx, 0x2ef8, 0xbf800000);
311 nv_wo32(ctx, 0x2f00, 0xbf800000);
312 }
313
314 static void
315 nv35_36_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx)
316 {
317 int i;
318
319 nv_wo32(ctx, 0x040c, 0x00000101);
320 nv_wo32(ctx, 0x0420, 0x00000111);
321 nv_wo32(ctx, 0x0424, 0x00000060);
322 nv_wo32(ctx, 0x0440, 0x00000080);
323 nv_wo32(ctx, 0x0444, 0xffff0000);
324 nv_wo32(ctx, 0x0448, 0x00000001);
325 nv_wo32(ctx, 0x045c, 0x44400000);
326 nv_wo32(ctx, 0x0488, 0xffff0000);
327 for (i = 0x04dc; i < 0x04e4; i += 4)
328 nv_wo32(ctx, i, 0x0fff0000);
329 nv_wo32(ctx, 0x04e8, 0x00011100);
330 for (i = 0x0504; i < 0x0544; i += 4)
331 nv_wo32(ctx, i, 0x07ff0000);
332 nv_wo32(ctx, 0x054c, 0x4b7fffff);
333 nv_wo32(ctx, 0x0588, 0x00000080);
334 nv_wo32(ctx, 0x058c, 0x30201000);
335 nv_wo32(ctx, 0x0590, 0x70605040);
336 nv_wo32(ctx, 0x0594, 0xb8a89888);
337 nv_wo32(ctx, 0x0598, 0xf8e8d8c8);
338 nv_wo32(ctx, 0x05ac, 0xb0000000);
339 for (i = 0x0604; i < 0x0644; i += 4)
340 nv_wo32(ctx, i, 0x00010588);
341 for (i = 0x0644; i < 0x0684; i += 4)
342 nv_wo32(ctx, i, 0x00030303);
343 for (i = 0x06c4; i < 0x0704; i += 4)
344 nv_wo32(ctx, i, 0x0008aae4);
345 for (i = 0x0704; i < 0x0744; i += 4)
346 nv_wo32(ctx, i, 0x01012000);
347 for (i = 0x0744; i < 0x0784; i += 4)
348 nv_wo32(ctx, i, 0x00080008);
349 nv_wo32(ctx, 0x0860, 0x00040000);
350 nv_wo32(ctx, 0x0864, 0x00010000);
351 for (i = 0x0868; i < 0x0878; i += 4)
352 nv_wo32(ctx, i, 0x00040004);
353 for (i = 0x1f1c; i <= 0x308c ; i += 16) {
354 nv_wo32(ctx, i + 0, 0x10700ff9);
355 nv_wo32(ctx, i + 4, 0x0436086c);
356 nv_wo32(ctx, i + 8, 0x000c001b);
357 }
358 for (i = 0x30bc; i < 0x30cc; i += 4)
359 nv_wo32(ctx, i, 0x0000ffff);
360 nv_wo32(ctx, 0x3450, 0x3f800000);
361 nv_wo32(ctx, 0x380c, 0x3f800000);
362 nv_wo32(ctx, 0x3820, 0x3f800000);
363 nv_wo32(ctx, 0x384c, 0x40000000);
364 nv_wo32(ctx, 0x3850, 0x3f800000);
365 nv_wo32(ctx, 0x3854, 0x3f000000);
366 nv_wo32(ctx, 0x385c, 0x40000000);
367 nv_wo32(ctx, 0x3860, 0x3f800000);
368 nv_wo32(ctx, 0x3868, 0xbf800000);
369 nv_wo32(ctx, 0x3870, 0xbf800000);
370 }
371
372 int
373 nv20_graph_create_context(struct nouveau_channel *chan)
374 {
375 struct drm_device *dev = chan->dev;
376 struct drm_nouveau_private *dev_priv = dev->dev_private;
377 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
378 void (*ctx_init)(struct drm_device *, struct nouveau_gpuobj *);
379 unsigned int idoffs = 0x28;
380 int ret;
381
382 switch (dev_priv->chipset) {
383 case 0x20:
384 ctx_init = nv20_graph_context_init;
385 idoffs = 0;
386 break;
387 case 0x25:
388 case 0x28:
389 ctx_init = nv25_graph_context_init;
390 break;
391 case 0x2a:
392 ctx_init = nv2a_graph_context_init;
393 idoffs = 0;
394 break;
395 case 0x30:
396 case 0x31:
397 ctx_init = nv30_31_graph_context_init;
398 break;
399 case 0x34:
400 ctx_init = nv34_graph_context_init;
401 break;
402 case 0x35:
403 case 0x36:
404 ctx_init = nv35_36_graph_context_init;
405 break;
406 default:
407 BUG_ON(1);
408 }
409
410 ret = nouveau_gpuobj_new(dev, chan, pgraph->grctx_size, 16,
411 NVOBJ_FLAG_ZERO_ALLOC, &chan->ramin_grctx);
412 if (ret)
413 return ret;
414
415 /* Initialise default context values */
416 ctx_init(dev, chan->ramin_grctx);
417
418 /* nv20: nv_wo32(dev, chan->ramin_grctx->gpuobj, 10, chan->id<<24); */
419 nv_wo32(chan->ramin_grctx, idoffs,
420 (chan->id << 24) | 0x1); /* CTX_USER */
421
422 nv_wo32(pgraph->ctx_table, chan->id * 4, chan->ramin_grctx->pinst >> 4);
423 return 0;
424 }
425
426 void
427 nv20_graph_destroy_context(struct nouveau_channel *chan)
428 {
429 struct drm_device *dev = chan->dev;
430 struct drm_nouveau_private *dev_priv = dev->dev_private;
431 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
432 unsigned long flags;
433
434 spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
435 pgraph->fifo_access(dev, false);
436
437 /* Unload the context if it's the currently active one */
438 if (pgraph->channel(dev) == chan)
439 pgraph->unload_context(dev);
440
441 pgraph->fifo_access(dev, true);
442 spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
443
444 /* Free the context resources */
445 nv_wo32(pgraph->ctx_table, chan->id * 4, 0);
446 nouveau_gpuobj_ref(NULL, &chan->ramin_grctx);
447 }
448
449 int
450 nv20_graph_load_context(struct nouveau_channel *chan)
451 {
452 struct drm_device *dev = chan->dev;
453 uint32_t inst;
454
455 if (!chan->ramin_grctx)
456 return -EINVAL;
457 inst = chan->ramin_grctx->pinst >> 4;
458
459 nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);
460 nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_XFER,
461 NV20_PGRAPH_CHANNEL_CTX_XFER_LOAD);
462 nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10010100);
463
464 nouveau_wait_for_idle(dev);
465 return 0;
466 }
467
468 int
469 nv20_graph_unload_context(struct drm_device *dev)
470 {
471 struct drm_nouveau_private *dev_priv = dev->dev_private;
472 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
473 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
474 struct nouveau_channel *chan;
475 uint32_t inst, tmp;
476
477 chan = pgraph->channel(dev);
478 if (!chan)
479 return 0;
480 inst = chan->ramin_grctx->pinst >> 4;
481
482 nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);
483 nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_XFER,
484 NV20_PGRAPH_CHANNEL_CTX_XFER_SAVE);
485
486 nouveau_wait_for_idle(dev);
487
488 nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10000000);
489 tmp = nv_rd32(dev, NV10_PGRAPH_CTX_USER) & 0x00ffffff;
490 tmp |= (pfifo->channels - 1) << 24;
491 nv_wr32(dev, NV10_PGRAPH_CTX_USER, tmp);
492 return 0;
493 }
494
495 static void
496 nv20_graph_rdi(struct drm_device *dev)
497 {
498 struct drm_nouveau_private *dev_priv = dev->dev_private;
499 int i, writecount = 32;
500 uint32_t rdi_index = 0x2c80000;
501
502 if (dev_priv->chipset == 0x20) {
503 rdi_index = 0x3d0000;
504 writecount = 15;
505 }
506
507 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, rdi_index);
508 for (i = 0; i < writecount; i++)
509 nv_wr32(dev, NV10_PGRAPH_RDI_DATA, 0);
510
511 nouveau_wait_for_idle(dev);
512 }
513
514 void
515 nv20_graph_set_tile_region(struct drm_device *dev, int i)
516 {
517 struct drm_nouveau_private *dev_priv = dev->dev_private;
518 struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
519
520 nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), tile->limit);
521 nv_wr32(dev, NV20_PGRAPH_TSIZE(i), tile->pitch);
522 nv_wr32(dev, NV20_PGRAPH_TILE(i), tile->addr);
523
524 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0030 + 4 * i);
525 nv_wr32(dev, NV10_PGRAPH_RDI_DATA, tile->limit);
526 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0050 + 4 * i);
527 nv_wr32(dev, NV10_PGRAPH_RDI_DATA, tile->pitch);
528 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0010 + 4 * i);
529 nv_wr32(dev, NV10_PGRAPH_RDI_DATA, tile->addr);
530
531 if (dev_priv->card_type == NV_20) {
532 nv_wr32(dev, NV20_PGRAPH_ZCOMP(i), tile->zcomp);
533 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00ea0090 + 4 * i);
534 nv_wr32(dev, NV10_PGRAPH_RDI_DATA, tile->zcomp);
535 }
536 }
537
538 int
539 nv20_graph_init(struct drm_device *dev)
540 {
541 struct drm_nouveau_private *dev_priv = dev->dev_private;
542 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
543 uint32_t tmp, vramsz;
544 int ret, i;
545
546 switch (dev_priv->chipset) {
547 case 0x20:
548 pgraph->grctx_size = NV20_GRCTX_SIZE;
549 break;
550 case 0x25:
551 case 0x28:
552 pgraph->grctx_size = NV25_GRCTX_SIZE;
553 break;
554 case 0x2a:
555 pgraph->grctx_size = NV2A_GRCTX_SIZE;
556 break;
557 default:
558 NV_ERROR(dev, "unknown chipset, disabling acceleration\n");
559 pgraph->accel_blocked = true;
560 return 0;
561 }
562
563 nv_wr32(dev, NV03_PMC_ENABLE,
564 nv_rd32(dev, NV03_PMC_ENABLE) & ~NV_PMC_ENABLE_PGRAPH);
565 nv_wr32(dev, NV03_PMC_ENABLE,
566 nv_rd32(dev, NV03_PMC_ENABLE) | NV_PMC_ENABLE_PGRAPH);
567
568 if (!pgraph->ctx_table) {
569 /* Create Context Pointer Table */
570 ret = nouveau_gpuobj_new(dev, NULL, 32 * 4, 16,
571 NVOBJ_FLAG_ZERO_ALLOC,
572 &pgraph->ctx_table);
573 if (ret)
574 return ret;
575 }
576
577 nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_TABLE,
578 pgraph->ctx_table->pinst >> 4);
579
580 nv20_graph_rdi(dev);
581
582 ret = nv20_graph_register(dev);
583 if (ret) {
584 nouveau_gpuobj_ref(NULL, &pgraph->ctx_table);
585 return ret;
586 }
587
588 nouveau_irq_register(dev, 12, nv20_graph_isr);
589 nv_wr32(dev, NV03_PGRAPH_INTR , 0xFFFFFFFF);
590 nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
591
592 nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
593 nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0x00000000);
594 nv_wr32(dev, NV04_PGRAPH_DEBUG_1, 0x00118700);
595 nv_wr32(dev, NV04_PGRAPH_DEBUG_3, 0xF3CE0475); /* 0x4 = auto ctx switch */
596 nv_wr32(dev, NV10_PGRAPH_DEBUG_4, 0x00000000);
597 nv_wr32(dev, 0x40009C , 0x00000040);
598
599 if (dev_priv->chipset >= 0x25) {
600 nv_wr32(dev, 0x400890, 0x00a8cfff);
601 nv_wr32(dev, 0x400610, 0x304B1FB6);
602 nv_wr32(dev, 0x400B80, 0x1cbd3883);
603 nv_wr32(dev, 0x400B84, 0x44000000);
604 nv_wr32(dev, 0x400098, 0x40000080);
605 nv_wr32(dev, 0x400B88, 0x000000ff);
606
607 } else {
608 nv_wr32(dev, 0x400880, 0x0008c7df);
609 nv_wr32(dev, 0x400094, 0x00000005);
610 nv_wr32(dev, 0x400B80, 0x45eae20e);
611 nv_wr32(dev, 0x400B84, 0x24000000);
612 nv_wr32(dev, 0x400098, 0x00000040);
613 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00E00038);
614 nv_wr32(dev, NV10_PGRAPH_RDI_DATA , 0x00000030);
615 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00E10038);
616 nv_wr32(dev, NV10_PGRAPH_RDI_DATA , 0x00000030);
617 }
618
619 /* Turn all the tiling regions off. */
620 for (i = 0; i < NV10_PFB_TILE__SIZE; i++)
621 nv20_graph_set_tile_region(dev, i);
622
623 nv_wr32(dev, 0x4009a0, nv_rd32(dev, 0x100324));
624 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA000C);
625 nv_wr32(dev, NV10_PGRAPH_RDI_DATA, nv_rd32(dev, 0x100324));
626
627 nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10000100);
628 nv_wr32(dev, NV10_PGRAPH_STATE , 0xFFFFFFFF);
629
630 tmp = nv_rd32(dev, NV10_PGRAPH_SURFACE) & 0x0007ff00;
631 nv_wr32(dev, NV10_PGRAPH_SURFACE, tmp);
632 tmp = nv_rd32(dev, NV10_PGRAPH_SURFACE) | 0x00020100;
633 nv_wr32(dev, NV10_PGRAPH_SURFACE, tmp);
634
635 /* begin RAM config */
636 vramsz = pci_resource_len(dev->pdev, 0) - 1;
637 nv_wr32(dev, 0x4009A4, nv_rd32(dev, NV04_PFB_CFG0));
638 nv_wr32(dev, 0x4009A8, nv_rd32(dev, NV04_PFB_CFG1));
639 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0000);
640 nv_wr32(dev, NV10_PGRAPH_RDI_DATA , nv_rd32(dev, NV04_PFB_CFG0));
641 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0004);
642 nv_wr32(dev, NV10_PGRAPH_RDI_DATA , nv_rd32(dev, NV04_PFB_CFG1));
643 nv_wr32(dev, 0x400820, 0);
644 nv_wr32(dev, 0x400824, 0);
645 nv_wr32(dev, 0x400864, vramsz - 1);
646 nv_wr32(dev, 0x400868, vramsz - 1);
647
648 /* interesting.. the below overwrites some of the tile setup above.. */
649 nv_wr32(dev, 0x400B20, 0x00000000);
650 nv_wr32(dev, 0x400B04, 0xFFFFFFFF);
651
652 nv_wr32(dev, NV03_PGRAPH_ABS_UCLIP_XMIN, 0);
653 nv_wr32(dev, NV03_PGRAPH_ABS_UCLIP_YMIN, 0);
654 nv_wr32(dev, NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff);
655 nv_wr32(dev, NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff);
656
657 return 0;
658 }
659
660 void
661 nv20_graph_takedown(struct drm_device *dev)
662 {
663 struct drm_nouveau_private *dev_priv = dev->dev_private;
664 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
665
666 nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0x00000000);
667 nouveau_irq_unregister(dev, 12);
668
669 nouveau_gpuobj_ref(NULL, &pgraph->ctx_table);
670 }
671
672 int
673 nv30_graph_init(struct drm_device *dev)
674 {
675 struct drm_nouveau_private *dev_priv = dev->dev_private;
676 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
677 int ret, i;
678
679 switch (dev_priv->chipset) {
680 case 0x30:
681 case 0x31:
682 pgraph->grctx_size = NV30_31_GRCTX_SIZE;
683 break;
684 case 0x34:
685 pgraph->grctx_size = NV34_GRCTX_SIZE;
686 break;
687 case 0x35:
688 case 0x36:
689 pgraph->grctx_size = NV35_36_GRCTX_SIZE;
690 break;
691 default:
692 NV_ERROR(dev, "unknown chipset, disabling acceleration\n");
693 pgraph->accel_blocked = true;
694 return 0;
695 }
696
697 nv_wr32(dev, NV03_PMC_ENABLE,
698 nv_rd32(dev, NV03_PMC_ENABLE) & ~NV_PMC_ENABLE_PGRAPH);
699 nv_wr32(dev, NV03_PMC_ENABLE,
700 nv_rd32(dev, NV03_PMC_ENABLE) | NV_PMC_ENABLE_PGRAPH);
701
702 if (!pgraph->ctx_table) {
703 /* Create Context Pointer Table */
704 ret = nouveau_gpuobj_new(dev, NULL, 32 * 4, 16,
705 NVOBJ_FLAG_ZERO_ALLOC,
706 &pgraph->ctx_table);
707 if (ret)
708 return ret;
709 }
710
711 ret = nv30_graph_register(dev);
712 if (ret) {
713 nouveau_gpuobj_ref(NULL, &pgraph->ctx_table);
714 return ret;
715 }
716
717 nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_TABLE,
718 pgraph->ctx_table->pinst >> 4);
719
720 nouveau_irq_register(dev, 12, nv20_graph_isr);
721 nv_wr32(dev, NV03_PGRAPH_INTR , 0xFFFFFFFF);
722 nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
723
724 nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
725 nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0x00000000);
726 nv_wr32(dev, NV04_PGRAPH_DEBUG_1, 0x401287c0);
727 nv_wr32(dev, 0x400890, 0x01b463ff);
728 nv_wr32(dev, NV04_PGRAPH_DEBUG_3, 0xf2de0475);
729 nv_wr32(dev, NV10_PGRAPH_DEBUG_4, 0x00008000);
730 nv_wr32(dev, NV04_PGRAPH_LIMIT_VIOL_PIX, 0xf04bdff6);
731 nv_wr32(dev, 0x400B80, 0x1003d888);
732 nv_wr32(dev, 0x400B84, 0x0c000000);
733 nv_wr32(dev, 0x400098, 0x00000000);
734 nv_wr32(dev, 0x40009C, 0x0005ad00);
735 nv_wr32(dev, 0x400B88, 0x62ff00ff); /* suspiciously like PGRAPH_DEBUG_2 */
736 nv_wr32(dev, 0x4000a0, 0x00000000);
737 nv_wr32(dev, 0x4000a4, 0x00000008);
738 nv_wr32(dev, 0x4008a8, 0xb784a400);
739 nv_wr32(dev, 0x400ba0, 0x002f8685);
740 nv_wr32(dev, 0x400ba4, 0x00231f3f);
741 nv_wr32(dev, 0x4008a4, 0x40000020);
742
743 if (dev_priv->chipset == 0x34) {
744 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0004);
745 nv_wr32(dev, NV10_PGRAPH_RDI_DATA , 0x00200201);
746 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0008);
747 nv_wr32(dev, NV10_PGRAPH_RDI_DATA , 0x00000008);
748 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0000);
749 nv_wr32(dev, NV10_PGRAPH_RDI_DATA , 0x00000032);
750 nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00E00004);
751 nv_wr32(dev, NV10_PGRAPH_RDI_DATA , 0x00000002);
752 }
753
754 nv_wr32(dev, 0x4000c0, 0x00000016);
755
756 /* Turn all the tiling regions off. */
757 for (i = 0; i < NV10_PFB_TILE__SIZE; i++)
758 nv20_graph_set_tile_region(dev, i);
759
760 nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10000100);
761 nv_wr32(dev, NV10_PGRAPH_STATE , 0xFFFFFFFF);
762 nv_wr32(dev, 0x0040075c , 0x00000001);
763
764 /* begin RAM config */
765 /* vramsz = pci_resource_len(dev->pdev, 0) - 1; */
766 nv_wr32(dev, 0x4009A4, nv_rd32(dev, NV04_PFB_CFG0));
767 nv_wr32(dev, 0x4009A8, nv_rd32(dev, NV04_PFB_CFG1));
768 if (dev_priv->chipset != 0x34) {
769 nv_wr32(dev, 0x400750, 0x00EA0000);
770 nv_wr32(dev, 0x400754, nv_rd32(dev, NV04_PFB_CFG0));
771 nv_wr32(dev, 0x400750, 0x00EA0004);
772 nv_wr32(dev, 0x400754, nv_rd32(dev, NV04_PFB_CFG1));
773 }
774
775 return 0;
776 }
777
778 static int
779 nv20_graph_register(struct drm_device *dev)
780 {
781 struct drm_nouveau_private *dev_priv = dev->dev_private;
782
783 if (dev_priv->engine.graph.registered)
784 return 0;
785
786 NVOBJ_CLASS(dev, 0x506e, SW); /* nvsw */
787 NVOBJ_CLASS(dev, 0x0030, GR); /* null */
788 NVOBJ_CLASS(dev, 0x0039, GR); /* m2mf */
789 NVOBJ_CLASS(dev, 0x004a, GR); /* gdirect */
790 NVOBJ_CLASS(dev, 0x009f, GR); /* imageblit (nv12) */
791 NVOBJ_CLASS(dev, 0x008a, GR); /* ifc */
792 NVOBJ_CLASS(dev, 0x0089, GR); /* sifm */
793 NVOBJ_CLASS(dev, 0x0062, GR); /* surf2d */
794 NVOBJ_CLASS(dev, 0x0043, GR); /* rop */
795 NVOBJ_CLASS(dev, 0x0012, GR); /* beta1 */
796 NVOBJ_CLASS(dev, 0x0072, GR); /* beta4 */
797 NVOBJ_CLASS(dev, 0x0019, GR); /* cliprect */
798 NVOBJ_CLASS(dev, 0x0044, GR); /* pattern */
799 NVOBJ_CLASS(dev, 0x009e, GR); /* swzsurf */
800 NVOBJ_CLASS(dev, 0x0096, GR); /* celcius */
801
802 /* kelvin */
803 if (dev_priv->chipset < 0x25)
804 NVOBJ_CLASS(dev, 0x0097, GR);
805 else
806 NVOBJ_CLASS(dev, 0x0597, GR);
807
808 /* nvsw */
809 NVOBJ_CLASS(dev, 0x506e, SW);
810 NVOBJ_MTHD (dev, 0x506e, 0x0500, nv04_graph_mthd_page_flip);
811
812 dev_priv->engine.graph.registered = true;
813 return 0;
814 }
815
816 static int
817 nv30_graph_register(struct drm_device *dev)
818 {
819 struct drm_nouveau_private *dev_priv = dev->dev_private;
820
821 if (dev_priv->engine.graph.registered)
822 return 0;
823
824 NVOBJ_CLASS(dev, 0x506e, SW); /* nvsw */
825 NVOBJ_CLASS(dev, 0x0030, GR); /* null */
826 NVOBJ_CLASS(dev, 0x0039, GR); /* m2mf */
827 NVOBJ_CLASS(dev, 0x004a, GR); /* gdirect */
828 NVOBJ_CLASS(dev, 0x009f, GR); /* imageblit (nv12) */
829 NVOBJ_CLASS(dev, 0x008a, GR); /* ifc */
830 NVOBJ_CLASS(dev, 0x038a, GR); /* ifc (nv30) */
831 NVOBJ_CLASS(dev, 0x0089, GR); /* sifm */
832 NVOBJ_CLASS(dev, 0x0389, GR); /* sifm (nv30) */
833 NVOBJ_CLASS(dev, 0x0062, GR); /* surf2d */
834 NVOBJ_CLASS(dev, 0x0362, GR); /* surf2d (nv30) */
835 NVOBJ_CLASS(dev, 0x0043, GR); /* rop */
836 NVOBJ_CLASS(dev, 0x0012, GR); /* beta1 */
837 NVOBJ_CLASS(dev, 0x0072, GR); /* beta4 */
838 NVOBJ_CLASS(dev, 0x0019, GR); /* cliprect */
839 NVOBJ_CLASS(dev, 0x0044, GR); /* pattern */
840 NVOBJ_CLASS(dev, 0x039e, GR); /* swzsurf */
841
842 /* rankine */
843 if (0x00000003 & (1 << (dev_priv->chipset & 0x0f)))
844 NVOBJ_CLASS(dev, 0x0397, GR);
845 else
846 if (0x00000010 & (1 << (dev_priv->chipset & 0x0f)))
847 NVOBJ_CLASS(dev, 0x0697, GR);
848 else
849 if (0x000001e0 & (1 << (dev_priv->chipset & 0x0f)))
850 NVOBJ_CLASS(dev, 0x0497, GR);
851
852 /* nvsw */
853 NVOBJ_CLASS(dev, 0x506e, SW);
854 NVOBJ_MTHD (dev, 0x506e, 0x0500, nv04_graph_mthd_page_flip);
855
856 dev_priv->engine.graph.registered = true;
857 return 0;
858 }
859
860 static void
861 nv20_graph_isr(struct drm_device *dev)
862 {
863 u32 stat;
864
865 while ((stat = nv_rd32(dev, NV03_PGRAPH_INTR))) {
866 u32 nsource = nv_rd32(dev, NV03_PGRAPH_NSOURCE);
867 u32 nstatus = nv_rd32(dev, NV03_PGRAPH_NSTATUS);
868 u32 addr = nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR);
869 u32 chid = (addr & 0x01f00000) >> 20;
870 u32 subc = (addr & 0x00070000) >> 16;
871 u32 mthd = (addr & 0x00001ffc);
872 u32 data = nv_rd32(dev, NV04_PGRAPH_TRAPPED_DATA);
873 u32 class = nv_rd32(dev, 0x400160 + subc * 4) & 0xfff;
874 u32 show = stat;
875
876 if (stat & NV_PGRAPH_INTR_ERROR) {
877 if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
878 if (!nouveau_gpuobj_mthd_call2(dev, chid, class, mthd, data))
879 show &= ~NV_PGRAPH_INTR_ERROR;
880 }
881 }
882
883 nv_wr32(dev, NV03_PGRAPH_INTR, stat);
884 nv_wr32(dev, NV04_PGRAPH_FIFO, 0x00000001);
885
886 if (show && nouveau_ratelimit()) {
887 NV_INFO(dev, "PGRAPH -");
888 nouveau_bitfield_print(nv10_graph_intr, show);
889 printk(" nsource:");
890 nouveau_bitfield_print(nv04_graph_nsource, nsource);
891 printk(" nstatus:");
892 nouveau_bitfield_print(nv10_graph_nstatus, nstatus);
893 printk("\n");
894 NV_INFO(dev, "PGRAPH - ch %d/%d class 0x%04x "
895 "mthd 0x%04x data 0x%08x\n",
896 chid, subc, class, mthd, data);
897 }
898 }
899 }
CRIS linux kernel tree