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FRV: Use generic show_interrupts()
[cris-mirror.git] / drivers / gpu / drm / nouveau / nv50_graph.c
blob8675b00caf1890b37b81a3245c6ebcb3a636df28
1 /*
2 * Copyright (C) 2007 Ben Skeggs.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
25 */
26
27 #include "drmP.h"
28 #include "drm.h"
29 #include "nouveau_drv.h"
30 #include "nouveau_ramht.h"
31 #include "nouveau_grctx.h"
32 #include "nouveau_dma.h"
33 #include "nouveau_vm.h"
34 #include "nv50_evo.h"
35
36 static int nv50_graph_register(struct drm_device *);
37 static void nv50_graph_isr(struct drm_device *);
38
39 static void
40 nv50_graph_init_reset(struct drm_device *dev)
41 {
42 uint32_t pmc_e = NV_PMC_ENABLE_PGRAPH | (1 << 21);
43
44 NV_DEBUG(dev, "\n");
45
46 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) & ~pmc_e);
47 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) | pmc_e);
48 }
49
50 static void
51 nv50_graph_init_intr(struct drm_device *dev)
52 {
53 NV_DEBUG(dev, "\n");
54
55 nouveau_irq_register(dev, 12, nv50_graph_isr);
56 nv_wr32(dev, NV03_PGRAPH_INTR, 0xffffffff);
57 nv_wr32(dev, 0x400138, 0xffffffff);
58 nv_wr32(dev, NV40_PGRAPH_INTR_EN, 0xffffffff);
59 }
60
61 static void
62 nv50_graph_init_regs__nv(struct drm_device *dev)
63 {
64 struct drm_nouveau_private *dev_priv = dev->dev_private;
65 uint32_t units = nv_rd32(dev, 0x1540);
66 int i;
67
68 NV_DEBUG(dev, "\n");
69
70 nv_wr32(dev, 0x400804, 0xc0000000);
71 nv_wr32(dev, 0x406800, 0xc0000000);
72 nv_wr32(dev, 0x400c04, 0xc0000000);
73 nv_wr32(dev, 0x401800, 0xc0000000);
74 nv_wr32(dev, 0x405018, 0xc0000000);
75 nv_wr32(dev, 0x402000, 0xc0000000);
76
77 for (i = 0; i < 16; i++) {
78 if (units & 1 << i) {
79 if (dev_priv->chipset < 0xa0) {
80 nv_wr32(dev, 0x408900 + (i << 12), 0xc0000000);
81 nv_wr32(dev, 0x408e08 + (i << 12), 0xc0000000);
82 nv_wr32(dev, 0x408314 + (i << 12), 0xc0000000);
83 } else {
84 nv_wr32(dev, 0x408600 + (i << 11), 0xc0000000);
85 nv_wr32(dev, 0x408708 + (i << 11), 0xc0000000);
86 nv_wr32(dev, 0x40831c + (i << 11), 0xc0000000);
87 }
88 }
89 }
90
91 nv_wr32(dev, 0x400108, 0xffffffff);
92
93 nv_wr32(dev, 0x400824, 0x00004000);
94 nv_wr32(dev, 0x400500, 0x00010001);
95 }
96
97 static void
98 nv50_graph_init_zcull(struct drm_device *dev)
99 {
100 struct drm_nouveau_private *dev_priv = dev->dev_private;
101 int i;
102
103 NV_DEBUG(dev, "\n");
104
105 switch (dev_priv->chipset & 0xf0) {
106 case 0x50:
107 case 0x80:
108 case 0x90:
109 nv_wr32(dev, 0x402ca8, 0x00000800);
110 break;
111 case 0xa0:
112 default:
113 nv_wr32(dev, 0x402cc0, 0x00000000);
114 if (dev_priv->chipset == 0xa0 ||
115 dev_priv->chipset == 0xaa ||
116 dev_priv->chipset == 0xac) {
117 nv_wr32(dev, 0x402ca8, 0x00000802);
118 } else {
119 nv_wr32(dev, 0x402cc0, 0x00000000);
120 nv_wr32(dev, 0x402ca8, 0x00000002);
121 }
122
123 break;
124 }
125
126 /* zero out zcull regions */
127 for (i = 0; i < 8; i++) {
128 nv_wr32(dev, 0x402c20 + (i * 8), 0x00000000);
129 nv_wr32(dev, 0x402c24 + (i * 8), 0x00000000);
130 nv_wr32(dev, 0x402c28 + (i * 8), 0x00000000);
131 nv_wr32(dev, 0x402c2c + (i * 8), 0x00000000);
132 }
133 }
134
135 static int
136 nv50_graph_init_ctxctl(struct drm_device *dev)
137 {
138 struct drm_nouveau_private *dev_priv = dev->dev_private;
139 struct nouveau_grctx ctx = {};
140 uint32_t *cp;
141 int i;
142
143 NV_DEBUG(dev, "\n");
144
145 cp = kmalloc(512 * 4, GFP_KERNEL);
146 if (!cp) {
147 NV_ERROR(dev, "failed to allocate ctxprog\n");
148 dev_priv->engine.graph.accel_blocked = true;
149 return 0;
150 }
151
152 ctx.dev = dev;
153 ctx.mode = NOUVEAU_GRCTX_PROG;
154 ctx.data = cp;
155 ctx.ctxprog_max = 512;
156 if (!nv50_grctx_init(&ctx)) {
157 dev_priv->engine.graph.grctx_size = ctx.ctxvals_pos * 4;
158
159 nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
160 for (i = 0; i < ctx.ctxprog_len; i++)
161 nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, cp[i]);
162 } else {
163 dev_priv->engine.graph.accel_blocked = true;
164 }
165 kfree(cp);
166
167 nv_wr32(dev, 0x40008c, 0x00000004); /* HW_CTX_SWITCH_ENABLED */
168 nv_wr32(dev, 0x400320, 4);
169 nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0);
170 nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, 0);
171 return 0;
172 }
173
174 int
175 nv50_graph_init(struct drm_device *dev)
176 {
177 int ret;
178
179 NV_DEBUG(dev, "\n");
180
181 nv50_graph_init_reset(dev);
182 nv50_graph_init_regs__nv(dev);
183 nv50_graph_init_zcull(dev);
184
185 ret = nv50_graph_init_ctxctl(dev);
186 if (ret)
187 return ret;
188
189 ret = nv50_graph_register(dev);
190 if (ret)
191 return ret;
192 nv50_graph_init_intr(dev);
193 return 0;
194 }
195
196 void
197 nv50_graph_takedown(struct drm_device *dev)
198 {
199 NV_DEBUG(dev, "\n");
200 nv_wr32(dev, 0x40013c, 0x00000000);
201 nouveau_irq_unregister(dev, 12);
202 }
203
204 void
205 nv50_graph_fifo_access(struct drm_device *dev, bool enabled)
206 {
207 const uint32_t mask = 0x00010001;
208
209 if (enabled)
210 nv_wr32(dev, 0x400500, nv_rd32(dev, 0x400500) | mask);
211 else
212 nv_wr32(dev, 0x400500, nv_rd32(dev, 0x400500) & ~mask);
213 }
214
215 struct nouveau_channel *
216 nv50_graph_channel(struct drm_device *dev)
217 {
218 struct drm_nouveau_private *dev_priv = dev->dev_private;
219 uint32_t inst;
220 int i;
221
222 /* Be sure we're not in the middle of a context switch or bad things
223 * will happen, such as unloading the wrong pgraph context.
224 */
225 if (!nv_wait(dev, 0x400300, 0x00000001, 0x00000000))
226 NV_ERROR(dev, "Ctxprog is still running\n");
227
228 inst = nv_rd32(dev, NV50_PGRAPH_CTXCTL_CUR);
229 if (!(inst & NV50_PGRAPH_CTXCTL_CUR_LOADED))
230 return NULL;
231 inst = (inst & NV50_PGRAPH_CTXCTL_CUR_INSTANCE) << 12;
232
233 for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
234 struct nouveau_channel *chan = dev_priv->channels.ptr[i];
235
236 if (chan && chan->ramin && chan->ramin->vinst == inst)
237 return chan;
238 }
239
240 return NULL;
241 }
242
243 int
244 nv50_graph_create_context(struct nouveau_channel *chan)
245 {
246 struct drm_device *dev = chan->dev;
247 struct drm_nouveau_private *dev_priv = dev->dev_private;
248 struct nouveau_gpuobj *ramin = chan->ramin;
249 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
250 struct nouveau_grctx ctx = {};
251 int hdr, ret;
252
253 NV_DEBUG(dev, "ch%d\n", chan->id);
254
255 ret = nouveau_gpuobj_new(dev, chan, pgraph->grctx_size, 0,
256 NVOBJ_FLAG_ZERO_ALLOC |
257 NVOBJ_FLAG_ZERO_FREE, &chan->ramin_grctx);
258 if (ret)
259 return ret;
260
261 hdr = (dev_priv->chipset == 0x50) ? 0x200 : 0x20;
262 nv_wo32(ramin, hdr + 0x00, 0x00190002);
263 nv_wo32(ramin, hdr + 0x04, chan->ramin_grctx->vinst +
264 pgraph->grctx_size - 1);
265 nv_wo32(ramin, hdr + 0x08, chan->ramin_grctx->vinst);
266 nv_wo32(ramin, hdr + 0x0c, 0);
267 nv_wo32(ramin, hdr + 0x10, 0);
268 nv_wo32(ramin, hdr + 0x14, 0x00010000);
269
270 ctx.dev = chan->dev;
271 ctx.mode = NOUVEAU_GRCTX_VALS;
272 ctx.data = chan->ramin_grctx;
273 nv50_grctx_init(&ctx);
274
275 nv_wo32(chan->ramin_grctx, 0x00000, chan->ramin->vinst >> 12);
276
277 dev_priv->engine.instmem.flush(dev);
278 atomic_inc(&chan->vm->pgraph_refs);
279 return 0;
280 }
281
282 void
283 nv50_graph_destroy_context(struct nouveau_channel *chan)
284 {
285 struct drm_device *dev = chan->dev;
286 struct drm_nouveau_private *dev_priv = dev->dev_private;
287 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
288 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
289 int i, hdr = (dev_priv->chipset == 0x50) ? 0x200 : 0x20;
290 unsigned long flags;
291
292 NV_DEBUG(dev, "ch%d\n", chan->id);
293
294 if (!chan->ramin)
295 return;
296
297 spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
298 pfifo->reassign(dev, false);
299 pgraph->fifo_access(dev, false);
300
301 if (pgraph->channel(dev) == chan)
302 pgraph->unload_context(dev);
303
304 for (i = hdr; i < hdr + 24; i += 4)
305 nv_wo32(chan->ramin, i, 0);
306 dev_priv->engine.instmem.flush(dev);
307
308 pgraph->fifo_access(dev, true);
309 pfifo->reassign(dev, true);
310 spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
311
312 nouveau_gpuobj_ref(NULL, &chan->ramin_grctx);
313
314 atomic_dec(&chan->vm->pgraph_refs);
315 }
316
317 static int
318 nv50_graph_do_load_context(struct drm_device *dev, uint32_t inst)
319 {
320 uint32_t fifo = nv_rd32(dev, 0x400500);
321
322 nv_wr32(dev, 0x400500, fifo & ~1);
323 nv_wr32(dev, 0x400784, inst);
324 nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) | 0x40);
325 nv_wr32(dev, 0x400320, nv_rd32(dev, 0x400320) | 0x11);
326 nv_wr32(dev, 0x400040, 0xffffffff);
327 (void)nv_rd32(dev, 0x400040);
328 nv_wr32(dev, 0x400040, 0x00000000);
329 nv_wr32(dev, 0x400304, nv_rd32(dev, 0x400304) | 1);
330
331 if (nouveau_wait_for_idle(dev))
332 nv_wr32(dev, 0x40032c, inst | (1<<31));
333 nv_wr32(dev, 0x400500, fifo);
334
335 return 0;
336 }
337
338 int
339 nv50_graph_load_context(struct nouveau_channel *chan)
340 {
341 uint32_t inst = chan->ramin->vinst >> 12;
342
343 NV_DEBUG(chan->dev, "ch%d\n", chan->id);
344 return nv50_graph_do_load_context(chan->dev, inst);
345 }
346
347 int
348 nv50_graph_unload_context(struct drm_device *dev)
349 {
350 uint32_t inst;
351
352 inst = nv_rd32(dev, NV50_PGRAPH_CTXCTL_CUR);
353 if (!(inst & NV50_PGRAPH_CTXCTL_CUR_LOADED))
354 return 0;
355 inst &= NV50_PGRAPH_CTXCTL_CUR_INSTANCE;
356
357 nouveau_wait_for_idle(dev);
358 nv_wr32(dev, 0x400784, inst);
359 nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) | 0x20);
360 nv_wr32(dev, 0x400304, nv_rd32(dev, 0x400304) | 0x01);
361 nouveau_wait_for_idle(dev);
362
363 nv_wr32(dev, NV50_PGRAPH_CTXCTL_CUR, inst);
364 return 0;
365 }
366
367 static void
368 nv50_graph_context_switch(struct drm_device *dev)
369 {
370 uint32_t inst;
371
372 nv50_graph_unload_context(dev);
373
374 inst = nv_rd32(dev, NV50_PGRAPH_CTXCTL_NEXT);
375 inst &= NV50_PGRAPH_CTXCTL_NEXT_INSTANCE;
376 nv50_graph_do_load_context(dev, inst);
377
378 nv_wr32(dev, NV40_PGRAPH_INTR_EN, nv_rd32(dev,
379 NV40_PGRAPH_INTR_EN) | NV_PGRAPH_INTR_CONTEXT_SWITCH);
380 }
381
382 static int
383 nv50_graph_nvsw_dma_vblsem(struct nouveau_channel *chan,
384 u32 class, u32 mthd, u32 data)
385 {
386 struct nouveau_gpuobj *gpuobj;
387
388 gpuobj = nouveau_ramht_find(chan, data);
389 if (!gpuobj)
390 return -ENOENT;
391
392 if (nouveau_notifier_offset(gpuobj, NULL))
393 return -EINVAL;
394
395 chan->nvsw.vblsem = gpuobj;
396 chan->nvsw.vblsem_offset = ~0;
397 return 0;
398 }
399
400 static int
401 nv50_graph_nvsw_vblsem_offset(struct nouveau_channel *chan,
402 u32 class, u32 mthd, u32 data)
403 {
404 if (nouveau_notifier_offset(chan->nvsw.vblsem, &data))
405 return -ERANGE;
406
407 chan->nvsw.vblsem_offset = data >> 2;
408 return 0;
409 }
410
411 static int
412 nv50_graph_nvsw_vblsem_release_val(struct nouveau_channel *chan,
413 u32 class, u32 mthd, u32 data)
414 {
415 chan->nvsw.vblsem_rval = data;
416 return 0;
417 }
418
419 static int
420 nv50_graph_nvsw_vblsem_release(struct nouveau_channel *chan,
421 u32 class, u32 mthd, u32 data)
422 {
423 struct drm_device *dev = chan->dev;
424 struct drm_nouveau_private *dev_priv = dev->dev_private;
425
426 if (!chan->nvsw.vblsem || chan->nvsw.vblsem_offset == ~0 || data > 1)
427 return -EINVAL;
428
429 drm_vblank_get(dev, data);
430
431 chan->nvsw.vblsem_head = data;
432 list_add(&chan->nvsw.vbl_wait, &dev_priv->vbl_waiting);
433
434 return 0;
435 }
436
437 static int
438 nv50_graph_nvsw_mthd_page_flip(struct nouveau_channel *chan,
439 u32 class, u32 mthd, u32 data)
440 {
441 nouveau_finish_page_flip(chan, NULL);
442 return 0;
443 }
444
445 static int
446 nv50_graph_register(struct drm_device *dev)
447 {
448 struct drm_nouveau_private *dev_priv = dev->dev_private;
449
450 if (dev_priv->engine.graph.registered)
451 return 0;
452
453 NVOBJ_CLASS(dev, 0x506e, SW); /* nvsw */
454 NVOBJ_MTHD (dev, 0x506e, 0x018c, nv50_graph_nvsw_dma_vblsem);
455 NVOBJ_MTHD (dev, 0x506e, 0x0400, nv50_graph_nvsw_vblsem_offset);
456 NVOBJ_MTHD (dev, 0x506e, 0x0404, nv50_graph_nvsw_vblsem_release_val);
457 NVOBJ_MTHD (dev, 0x506e, 0x0408, nv50_graph_nvsw_vblsem_release);
458 NVOBJ_MTHD (dev, 0x506e, 0x0500, nv50_graph_nvsw_mthd_page_flip);
459
460 NVOBJ_CLASS(dev, 0x0030, GR); /* null */
461 NVOBJ_CLASS(dev, 0x5039, GR); /* m2mf */
462 NVOBJ_CLASS(dev, 0x502d, GR); /* 2d */
463
464 /* tesla */
465 if (dev_priv->chipset == 0x50)
466 NVOBJ_CLASS(dev, 0x5097, GR); /* tesla (nv50) */
467 else
468 if (dev_priv->chipset < 0xa0)
469 NVOBJ_CLASS(dev, 0x8297, GR); /* tesla (nv8x/nv9x) */
470 else {
471 switch (dev_priv->chipset) {
472 case 0xa0:
473 case 0xaa:
474 case 0xac:
475 NVOBJ_CLASS(dev, 0x8397, GR);
476 break;
477 case 0xa3:
478 case 0xa5:
479 case 0xa8:
480 NVOBJ_CLASS(dev, 0x8597, GR);
481 break;
482 case 0xaf:
483 NVOBJ_CLASS(dev, 0x8697, GR);
484 break;
485 }
486 }
487
488 /* compute */
489 NVOBJ_CLASS(dev, 0x50c0, GR);
490 if (dev_priv->chipset > 0xa0 &&
491 dev_priv->chipset != 0xaa &&
492 dev_priv->chipset != 0xac)
493 NVOBJ_CLASS(dev, 0x85c0, GR);
494
495 dev_priv->engine.graph.registered = true;
496 return 0;
497 }
498
499 void
500 nv50_graph_tlb_flush(struct drm_device *dev)
501 {
502 nv50_vm_flush_engine(dev, 0);
503 }
504
505 void
506 nv86_graph_tlb_flush(struct drm_device *dev)
507 {
508 struct drm_nouveau_private *dev_priv = dev->dev_private;
509 struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
510 bool idle, timeout = false;
511 unsigned long flags;
512 u64 start;
513 u32 tmp;
514
515 spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
516 nv_mask(dev, 0x400500, 0x00000001, 0x00000000);
517
518 start = ptimer->read(dev);
519 do {
520 idle = true;
521
522 for (tmp = nv_rd32(dev, 0x400380); tmp && idle; tmp >>= 3) {
523 if ((tmp & 7) == 1)
524 idle = false;
525 }
526
527 for (tmp = nv_rd32(dev, 0x400384); tmp && idle; tmp >>= 3) {
528 if ((tmp & 7) == 1)
529 idle = false;
530 }
531
532 for (tmp = nv_rd32(dev, 0x400388); tmp && idle; tmp >>= 3) {
533 if ((tmp & 7) == 1)
534 idle = false;
535 }
536 } while (!idle && !(timeout = ptimer->read(dev) - start > 2000000000));
537
538 if (timeout) {
539 NV_ERROR(dev, "PGRAPH TLB flush idle timeout fail: "
540 "0x%08x 0x%08x 0x%08x 0x%08x\n",
541 nv_rd32(dev, 0x400700), nv_rd32(dev, 0x400380),
542 nv_rd32(dev, 0x400384), nv_rd32(dev, 0x400388));
543 }
544
545 nv50_vm_flush_engine(dev, 0);
546
547 nv_mask(dev, 0x400500, 0x00000001, 0x00000001);
548 spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
549 }
550
551 static struct nouveau_enum nv50_mp_exec_error_names[] =
552 {
553 { 3, "STACK_UNDERFLOW", NULL },
554 { 4, "QUADON_ACTIVE", NULL },
555 { 8, "TIMEOUT", NULL },
556 { 0x10, "INVALID_OPCODE", NULL },
557 { 0x40, "BREAKPOINT", NULL },
558 {}
559 };
560
561 static struct nouveau_bitfield nv50_graph_trap_m2mf[] = {
562 { 0x00000001, "NOTIFY" },
563 { 0x00000002, "IN" },
564 { 0x00000004, "OUT" },
565 {}
566 };
567
568 static struct nouveau_bitfield nv50_graph_trap_vfetch[] = {
569 { 0x00000001, "FAULT" },
570 {}
571 };
572
573 static struct nouveau_bitfield nv50_graph_trap_strmout[] = {
574 { 0x00000001, "FAULT" },
575 {}
576 };
577
578 static struct nouveau_bitfield nv50_graph_trap_ccache[] = {
579 { 0x00000001, "FAULT" },
580 {}
581 };
582
583 /* There must be a *lot* of these. Will take some time to gather them up. */
584 struct nouveau_enum nv50_data_error_names[] = {
585 { 0x00000003, "INVALID_QUERY_OR_TEXTURE", NULL },
586 { 0x00000004, "INVALID_VALUE", NULL },
587 { 0x00000005, "INVALID_ENUM", NULL },
588 { 0x00000008, "INVALID_OBJECT", NULL },
589 { 0x00000009, "READ_ONLY_OBJECT", NULL },
590 { 0x0000000a, "SUPERVISOR_OBJECT", NULL },
591 { 0x0000000b, "INVALID_ADDRESS_ALIGNMENT", NULL },
592 { 0x0000000c, "INVALID_BITFIELD", NULL },
593 { 0x0000000d, "BEGIN_END_ACTIVE", NULL },
594 { 0x0000000e, "SEMANTIC_COLOR_BACK_OVER_LIMIT", NULL },
595 { 0x0000000f, "VIEWPORT_ID_NEEDS_GP", NULL },
596 { 0x00000010, "RT_DOUBLE_BIND", NULL },
597 { 0x00000011, "RT_TYPES_MISMATCH", NULL },
598 { 0x00000012, "RT_LINEAR_WITH_ZETA", NULL },
599 { 0x00000015, "FP_TOO_FEW_REGS", NULL },
600 { 0x00000016, "ZETA_FORMAT_CSAA_MISMATCH", NULL },
601 { 0x00000017, "RT_LINEAR_WITH_MSAA", NULL },
602 { 0x00000018, "FP_INTERPOLANT_START_OVER_LIMIT", NULL },
603 { 0x00000019, "SEMANTIC_LAYER_OVER_LIMIT", NULL },
604 { 0x0000001a, "RT_INVALID_ALIGNMENT", NULL },
605 { 0x0000001b, "SAMPLER_OVER_LIMIT", NULL },
606 { 0x0000001c, "TEXTURE_OVER_LIMIT", NULL },
607 { 0x0000001e, "GP_TOO_MANY_OUTPUTS", NULL },
608 { 0x0000001f, "RT_BPP128_WITH_MS8", NULL },
609 { 0x00000021, "Z_OUT_OF_BOUNDS", NULL },
610 { 0x00000023, "XY_OUT_OF_BOUNDS", NULL },
611 { 0x00000027, "CP_MORE_PARAMS_THAN_SHARED", NULL },
612 { 0x00000028, "CP_NO_REG_SPACE_STRIPED", NULL },
613 { 0x00000029, "CP_NO_REG_SPACE_PACKED", NULL },
614 { 0x0000002a, "CP_NOT_ENOUGH_WARPS", NULL },
615 { 0x0000002b, "CP_BLOCK_SIZE_MISMATCH", NULL },
616 { 0x0000002c, "CP_NOT_ENOUGH_LOCAL_WARPS", NULL },
617 { 0x0000002d, "CP_NOT_ENOUGH_STACK_WARPS", NULL },
618 { 0x0000002e, "CP_NO_BLOCKDIM_LATCH", NULL },
619 { 0x00000031, "ENG2D_FORMAT_MISMATCH", NULL },
620 { 0x0000003f, "PRIMITIVE_ID_NEEDS_GP", NULL },
621 { 0x00000044, "SEMANTIC_VIEWPORT_OVER_LIMIT", NULL },
622 { 0x00000045, "SEMANTIC_COLOR_FRONT_OVER_LIMIT", NULL },
623 { 0x00000046, "LAYER_ID_NEEDS_GP", NULL },
624 { 0x00000047, "SEMANTIC_CLIP_OVER_LIMIT", NULL },
625 { 0x00000048, "SEMANTIC_PTSZ_OVER_LIMIT", NULL },
626 {}
627 };
628
629 static struct nouveau_bitfield nv50_graph_intr[] = {
630 { 0x00000001, "NOTIFY" },
631 { 0x00000002, "COMPUTE_QUERY" },
632 { 0x00000010, "ILLEGAL_MTHD" },
633 { 0x00000020, "ILLEGAL_CLASS" },
634 { 0x00000040, "DOUBLE_NOTIFY" },
635 { 0x00001000, "CONTEXT_SWITCH" },
636 { 0x00010000, "BUFFER_NOTIFY" },
637 { 0x00100000, "DATA_ERROR" },
638 { 0x00200000, "TRAP" },
639 { 0x01000000, "SINGLE_STEP" },
640 {}
641 };
642
643 static void
644 nv50_pgraph_mp_trap(struct drm_device *dev, int tpid, int display)
645 {
646 struct drm_nouveau_private *dev_priv = dev->dev_private;
647 uint32_t units = nv_rd32(dev, 0x1540);
648 uint32_t addr, mp10, status, pc, oplow, ophigh;
649 int i;
650 int mps = 0;
651 for (i = 0; i < 4; i++) {
652 if (!(units & 1 << (i+24)))
653 continue;
654 if (dev_priv->chipset < 0xa0)
655 addr = 0x408200 + (tpid << 12) + (i << 7);
656 else
657 addr = 0x408100 + (tpid << 11) + (i << 7);
658 mp10 = nv_rd32(dev, addr + 0x10);
659 status = nv_rd32(dev, addr + 0x14);
660 if (!status)
661 continue;
662 if (display) {
663 nv_rd32(dev, addr + 0x20);
664 pc = nv_rd32(dev, addr + 0x24);
665 oplow = nv_rd32(dev, addr + 0x70);
666 ophigh= nv_rd32(dev, addr + 0x74);
667 NV_INFO(dev, "PGRAPH_TRAP_MP_EXEC - "
668 "TP %d MP %d: ", tpid, i);
669 nouveau_enum_print(nv50_mp_exec_error_names, status);
670 printk(" at %06x warp %d, opcode %08x %08x\n",
671 pc&0xffffff, pc >> 24,
672 oplow, ophigh);
673 }
674 nv_wr32(dev, addr + 0x10, mp10);
675 nv_wr32(dev, addr + 0x14, 0);
676 mps++;
677 }
678 if (!mps && display)
679 NV_INFO(dev, "PGRAPH_TRAP_MP_EXEC - TP %d: "
680 "No MPs claiming errors?\n", tpid);
681 }
682
683 static void
684 nv50_pgraph_tp_trap(struct drm_device *dev, int type, uint32_t ustatus_old,
685 uint32_t ustatus_new, int display, const char *name)
686 {
687 struct drm_nouveau_private *dev_priv = dev->dev_private;
688 int tps = 0;
689 uint32_t units = nv_rd32(dev, 0x1540);
690 int i, r;
691 uint32_t ustatus_addr, ustatus;
692 for (i = 0; i < 16; i++) {
693 if (!(units & (1 << i)))
694 continue;
695 if (dev_priv->chipset < 0xa0)
696 ustatus_addr = ustatus_old + (i << 12);
697 else
698 ustatus_addr = ustatus_new + (i << 11);
699 ustatus = nv_rd32(dev, ustatus_addr) & 0x7fffffff;
700 if (!ustatus)
701 continue;
702 tps++;
703 switch (type) {
704 case 6: /* texture error... unknown for now */
705 if (display) {
706 NV_ERROR(dev, "magic set %d:\n", i);
707 for (r = ustatus_addr + 4; r <= ustatus_addr + 0x10; r += 4)
708 NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r,
709 nv_rd32(dev, r));
710 }
711 break;
712 case 7: /* MP error */
713 if (ustatus & 0x00010000) {
714 nv50_pgraph_mp_trap(dev, i, display);
715 ustatus &= ~0x00010000;
716 }
717 break;
718 case 8: /* TPDMA error */
719 {
720 uint32_t e0c = nv_rd32(dev, ustatus_addr + 4);
721 uint32_t e10 = nv_rd32(dev, ustatus_addr + 8);
722 uint32_t e14 = nv_rd32(dev, ustatus_addr + 0xc);
723 uint32_t e18 = nv_rd32(dev, ustatus_addr + 0x10);
724 uint32_t e1c = nv_rd32(dev, ustatus_addr + 0x14);
725 uint32_t e20 = nv_rd32(dev, ustatus_addr + 0x18);
726 uint32_t e24 = nv_rd32(dev, ustatus_addr + 0x1c);
727 /* 2d engine destination */
728 if (ustatus & 0x00000010) {
729 if (display) {
730 NV_INFO(dev, "PGRAPH_TRAP_TPDMA_2D - TP %d - Unknown fault at address %02x%08x\n",
731 i, e14, e10);
732 NV_INFO(dev, "PGRAPH_TRAP_TPDMA_2D - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
733 i, e0c, e18, e1c, e20, e24);
734 }
735 ustatus &= ~0x00000010;
736 }
737 /* Render target */
738 if (ustatus & 0x00000040) {
739 if (display) {
740 NV_INFO(dev, "PGRAPH_TRAP_TPDMA_RT - TP %d - Unknown fault at address %02x%08x\n",
741 i, e14, e10);
742 NV_INFO(dev, "PGRAPH_TRAP_TPDMA_RT - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
743 i, e0c, e18, e1c, e20, e24);
744 }
745 ustatus &= ~0x00000040;
746 }
747 /* CUDA memory: l[], g[] or stack. */
748 if (ustatus & 0x00000080) {
749 if (display) {
750 if (e18 & 0x80000000) {
751 /* g[] read fault? */
752 NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Global read fault at address %02x%08x\n",
753 i, e14, e10 | ((e18 >> 24) & 0x1f));
754 e18 &= ~0x1f000000;
755 } else if (e18 & 0xc) {
756 /* g[] write fault? */
757 NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Global write fault at address %02x%08x\n",
758 i, e14, e10 | ((e18 >> 7) & 0x1f));
759 e18 &= ~0x00000f80;
760 } else {
761 NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Unknown CUDA fault at address %02x%08x\n",
762 i, e14, e10);
763 }
764 NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
765 i, e0c, e18, e1c, e20, e24);
766 }
767 ustatus &= ~0x00000080;
768 }
769 }
770 break;
771 }
772 if (ustatus) {
773 if (display)
774 NV_INFO(dev, "%s - TP%d: Unhandled ustatus 0x%08x\n", name, i, ustatus);
775 }
776 nv_wr32(dev, ustatus_addr, 0xc0000000);
777 }
778
779 if (!tps && display)
780 NV_INFO(dev, "%s - No TPs claiming errors?\n", name);
781 }
782
783 static int
784 nv50_pgraph_trap_handler(struct drm_device *dev, u32 display, u64 inst, u32 chid)
785 {
786 u32 status = nv_rd32(dev, 0x400108);
787 u32 ustatus;
788
789 if (!status && display) {
790 NV_INFO(dev, "PGRAPH - TRAP: no units reporting traps?\n");
791 return 1;
792 }
793
794 /* DISPATCH: Relays commands to other units and handles NOTIFY,
795 * COND, QUERY. If you get a trap from it, the command is still stuck
796 * in DISPATCH and you need to do something about it. */
797 if (status & 0x001) {
798 ustatus = nv_rd32(dev, 0x400804) & 0x7fffffff;
799 if (!ustatus && display) {
800 NV_INFO(dev, "PGRAPH_TRAP_DISPATCH - no ustatus?\n");
801 }
802
803 nv_wr32(dev, 0x400500, 0x00000000);
804
805 /* Known to be triggered by screwed up NOTIFY and COND... */
806 if (ustatus & 0x00000001) {
807 u32 addr = nv_rd32(dev, 0x400808);
808 u32 subc = (addr & 0x00070000) >> 16;
809 u32 mthd = (addr & 0x00001ffc);
810 u32 datal = nv_rd32(dev, 0x40080c);
811 u32 datah = nv_rd32(dev, 0x400810);
812 u32 class = nv_rd32(dev, 0x400814);
813 u32 r848 = nv_rd32(dev, 0x400848);
814
815 NV_INFO(dev, "PGRAPH - TRAP DISPATCH_FAULT\n");
816 if (display && (addr & 0x80000000)) {
817 NV_INFO(dev, "PGRAPH - ch %d (0x%010llx) "
818 "subc %d class 0x%04x mthd 0x%04x "
819 "data 0x%08x%08x "
820 "400808 0x%08x 400848 0x%08x\n",
821 chid, inst, subc, class, mthd, datah,
822 datal, addr, r848);
823 } else
824 if (display) {
825 NV_INFO(dev, "PGRAPH - no stuck command?\n");
826 }
827
828 nv_wr32(dev, 0x400808, 0);
829 nv_wr32(dev, 0x4008e8, nv_rd32(dev, 0x4008e8) & 3);
830 nv_wr32(dev, 0x400848, 0);
831 ustatus &= ~0x00000001;
832 }
833
834 if (ustatus & 0x00000002) {
835 u32 addr = nv_rd32(dev, 0x40084c);
836 u32 subc = (addr & 0x00070000) >> 16;
837 u32 mthd = (addr & 0x00001ffc);
838 u32 data = nv_rd32(dev, 0x40085c);
839 u32 class = nv_rd32(dev, 0x400814);
840
841 NV_INFO(dev, "PGRAPH - TRAP DISPATCH_QUERY\n");
842 if (display && (addr & 0x80000000)) {
843 NV_INFO(dev, "PGRAPH - ch %d (0x%010llx) "
844 "subc %d class 0x%04x mthd 0x%04x "
845 "data 0x%08x 40084c 0x%08x\n",
846 chid, inst, subc, class, mthd,
847 data, addr);
848 } else
849 if (display) {
850 NV_INFO(dev, "PGRAPH - no stuck command?\n");
851 }
852
853 nv_wr32(dev, 0x40084c, 0);
854 ustatus &= ~0x00000002;
855 }
856
857 if (ustatus && display) {
858 NV_INFO(dev, "PGRAPH - TRAP_DISPATCH (unknown "
859 "0x%08x)\n", ustatus);
860 }
861
862 nv_wr32(dev, 0x400804, 0xc0000000);
863 nv_wr32(dev, 0x400108, 0x001);
864 status &= ~0x001;
865 if (!status)
866 return 0;
867 }
868
869 /* M2MF: Memory to memory copy engine. */
870 if (status & 0x002) {
871 u32 ustatus = nv_rd32(dev, 0x406800) & 0x7fffffff;
872 if (display) {
873 NV_INFO(dev, "PGRAPH - TRAP_M2MF");
874 nouveau_bitfield_print(nv50_graph_trap_m2mf, ustatus);
875 printk("\n");
876 NV_INFO(dev, "PGRAPH - TRAP_M2MF %08x %08x %08x %08x\n",
877 nv_rd32(dev, 0x406804), nv_rd32(dev, 0x406808),
878 nv_rd32(dev, 0x40680c), nv_rd32(dev, 0x406810));
879
880 }
881
882 /* No sane way found yet -- just reset the bugger. */
883 nv_wr32(dev, 0x400040, 2);
884 nv_wr32(dev, 0x400040, 0);
885 nv_wr32(dev, 0x406800, 0xc0000000);
886 nv_wr32(dev, 0x400108, 0x002);
887 status &= ~0x002;
888 }
889
890 /* VFETCH: Fetches data from vertex buffers. */
891 if (status & 0x004) {
892 u32 ustatus = nv_rd32(dev, 0x400c04) & 0x7fffffff;
893 if (display) {
894 NV_INFO(dev, "PGRAPH - TRAP_VFETCH");
895 nouveau_bitfield_print(nv50_graph_trap_vfetch, ustatus);
896 printk("\n");
897 NV_INFO(dev, "PGRAPH - TRAP_VFETCH %08x %08x %08x %08x\n",
898 nv_rd32(dev, 0x400c00), nv_rd32(dev, 0x400c08),
899 nv_rd32(dev, 0x400c0c), nv_rd32(dev, 0x400c10));
900 }
901
902 nv_wr32(dev, 0x400c04, 0xc0000000);
903 nv_wr32(dev, 0x400108, 0x004);
904 status &= ~0x004;
905 }
906
907 /* STRMOUT: DirectX streamout / OpenGL transform feedback. */
908 if (status & 0x008) {
909 ustatus = nv_rd32(dev, 0x401800) & 0x7fffffff;
910 if (display) {
911 NV_INFO(dev, "PGRAPH - TRAP_STRMOUT");
912 nouveau_bitfield_print(nv50_graph_trap_strmout, ustatus);
913 printk("\n");
914 NV_INFO(dev, "PGRAPH - TRAP_STRMOUT %08x %08x %08x %08x\n",
915 nv_rd32(dev, 0x401804), nv_rd32(dev, 0x401808),
916 nv_rd32(dev, 0x40180c), nv_rd32(dev, 0x401810));
917
918 }
919
920 /* No sane way found yet -- just reset the bugger. */
921 nv_wr32(dev, 0x400040, 0x80);
922 nv_wr32(dev, 0x400040, 0);
923 nv_wr32(dev, 0x401800, 0xc0000000);
924 nv_wr32(dev, 0x400108, 0x008);
925 status &= ~0x008;
926 }
927
928 /* CCACHE: Handles code and c[] caches and fills them. */
929 if (status & 0x010) {
930 ustatus = nv_rd32(dev, 0x405018) & 0x7fffffff;
931 if (display) {
932 NV_INFO(dev, "PGRAPH - TRAP_CCACHE");
933 nouveau_bitfield_print(nv50_graph_trap_ccache, ustatus);
934 printk("\n");
935 NV_INFO(dev, "PGRAPH - TRAP_CCACHE %08x %08x %08x %08x"
936 " %08x %08x %08x\n",
937 nv_rd32(dev, 0x405000), nv_rd32(dev, 0x405004),
938 nv_rd32(dev, 0x405008), nv_rd32(dev, 0x40500c),
939 nv_rd32(dev, 0x405010), nv_rd32(dev, 0x405014),
940 nv_rd32(dev, 0x40501c));
941
942 }
943
944 nv_wr32(dev, 0x405018, 0xc0000000);
945 nv_wr32(dev, 0x400108, 0x010);
946 status &= ~0x010;
947 }
948
949 /* Unknown, not seen yet... 0x402000 is the only trap status reg
950 * remaining, so try to handle it anyway. Perhaps related to that
951 * unknown DMA slot on tesla? */
952 if (status & 0x20) {
953 ustatus = nv_rd32(dev, 0x402000) & 0x7fffffff;
954 if (display)
955 NV_INFO(dev, "PGRAPH - TRAP_UNKC04 0x%08x\n", ustatus);
956 nv_wr32(dev, 0x402000, 0xc0000000);
957 /* no status modifiction on purpose */
958 }
959
960 /* TEXTURE: CUDA texturing units */
961 if (status & 0x040) {
962 nv50_pgraph_tp_trap(dev, 6, 0x408900, 0x408600, display,
963 "PGRAPH - TRAP_TEXTURE");
964 nv_wr32(dev, 0x400108, 0x040);
965 status &= ~0x040;
966 }
967
968 /* MP: CUDA execution engines. */
969 if (status & 0x080) {
970 nv50_pgraph_tp_trap(dev, 7, 0x408314, 0x40831c, display,
971 "PGRAPH - TRAP_MP");
972 nv_wr32(dev, 0x400108, 0x080);
973 status &= ~0x080;
974 }
975
976 /* TPDMA: Handles TP-initiated uncached memory accesses:
977 * l[], g[], stack, 2d surfaces, render targets. */
978 if (status & 0x100) {
979 nv50_pgraph_tp_trap(dev, 8, 0x408e08, 0x408708, display,
980 "PGRAPH - TRAP_TPDMA");
981 nv_wr32(dev, 0x400108, 0x100);
982 status &= ~0x100;
983 }
984
985 if (status) {
986 if (display)
987 NV_INFO(dev, "PGRAPH - TRAP: unknown 0x%08x\n", status);
988 nv_wr32(dev, 0x400108, status);
989 }
990
991 return 1;
992 }
993
994 static int
995 nv50_graph_isr_chid(struct drm_device *dev, u64 inst)
996 {
997 struct drm_nouveau_private *dev_priv = dev->dev_private;
998 struct nouveau_channel *chan;
999 unsigned long flags;
1000 int i;
1001
1002 spin_lock_irqsave(&dev_priv->channels.lock, flags);
1003 for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
1004 chan = dev_priv->channels.ptr[i];
1005 if (!chan || !chan->ramin)
1006 continue;
1007
1008 if (inst == chan->ramin->vinst)
1009 break;
1010 }
1011 spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
1012 return i;
1013 }
1014
1015 static void
1016 nv50_graph_isr(struct drm_device *dev)
1017 {
1018 u32 stat;
1019
1020 while ((stat = nv_rd32(dev, 0x400100))) {
1021 u64 inst = (u64)(nv_rd32(dev, 0x40032c) & 0x0fffffff) << 12;
1022 u32 chid = nv50_graph_isr_chid(dev, inst);
1023 u32 addr = nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR);
1024 u32 subc = (addr & 0x00070000) >> 16;
1025 u32 mthd = (addr & 0x00001ffc);
1026 u32 data = nv_rd32(dev, NV04_PGRAPH_TRAPPED_DATA);
1027 u32 class = nv_rd32(dev, 0x400814);
1028 u32 show = stat;
1029
1030 if (stat & 0x00000010) {
1031 if (!nouveau_gpuobj_mthd_call2(dev, chid, class,
1032 mthd, data))
1033 show &= ~0x00000010;
1034 }
1035
1036 if (stat & 0x00001000) {
1037 nv_wr32(dev, 0x400500, 0x00000000);
1038 nv_wr32(dev, 0x400100, 0x00001000);
1039 nv_mask(dev, 0x40013c, 0x00001000, 0x00000000);
1040 nv50_graph_context_switch(dev);
1041 stat &= ~0x00001000;
1042 show &= ~0x00001000;
1043 }
1044
1045 show = (show && nouveau_ratelimit()) ? show : 0;
1046
1047 if (show & 0x00100000) {
1048 u32 ecode = nv_rd32(dev, 0x400110);
1049 NV_INFO(dev, "PGRAPH - DATA_ERROR ");
1050 nouveau_enum_print(nv50_data_error_names, ecode);
1051 printk("\n");
1052 }
1053
1054 if (stat & 0x00200000) {
1055 if (!nv50_pgraph_trap_handler(dev, show, inst, chid))
1056 show &= ~0x00200000;
1057 }
1058
1059 nv_wr32(dev, 0x400100, stat);
1060 nv_wr32(dev, 0x400500, 0x00010001);
1061
1062 if (show) {
1063 NV_INFO(dev, "PGRAPH -");
1064 nouveau_bitfield_print(nv50_graph_intr, show);
1065 printk("\n");
1066 NV_INFO(dev, "PGRAPH - ch %d (0x%010llx) subc %d "
1067 "class 0x%04x mthd 0x%04x data 0x%08x\n",
1068 chid, inst, subc, class, mthd, data);
1069 nv50_fb_vm_trap(dev, 1);
1070 }
1071 }
1072
1073 if (nv_rd32(dev, 0x400824) & (1 << 31))
1074 nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) & ~(1 << 31));
1075 }
CRIS linux kernel tree