drivers/gpu/drm/nouveau/nv84_crypt.c

   1 /*
   2  * Copyright 2010 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include "drmP.h"
  26 #include "nouveau_drv.h"
  27 #include "nouveau_util.h"
  28 #include "nouveau_vm.h"
  29
  30 static void nv84_crypt_isr(struct drm_device *);
  31
  32 int
  33 nv84_crypt_create_context(struct nouveau_channel *chan)
  34 {
  35         struct drm_device *dev = chan->dev;
  36         struct drm_nouveau_private *dev_priv = dev->dev_private;
  37         struct nouveau_gpuobj *ramin = chan->ramin;
  38         int ret;
  39
  40         NV_DEBUG(dev, "ch%d\n", chan->id);
  41
  42         ret = nouveau_gpuobj_new(dev, chan, 256, 0,
  43                                  NVOBJ_FLAG_ZERO_ALLOC | NVOBJ_FLAG_ZERO_FREE,
  44                                  &chan->crypt_ctx);
  45         if (ret)
  46                 return ret;
  47
  48         nv_wo32(ramin, 0xa0, 0x00190000);
  49         nv_wo32(ramin, 0xa4, chan->crypt_ctx->vinst + 0xff);
  50         nv_wo32(ramin, 0xa8, chan->crypt_ctx->vinst);
  51         nv_wo32(ramin, 0xac, 0);
  52         nv_wo32(ramin, 0xb0, 0);
  53         nv_wo32(ramin, 0xb4, 0);
  54
  55         dev_priv->engine.instmem.flush(dev);
  56         atomic_inc(&chan->vm->pcrypt_refs);
  57         return 0;
  58 }
  59
  60 void
  61 nv84_crypt_destroy_context(struct nouveau_channel *chan)
  62 {
  63         struct drm_device *dev = chan->dev;
  64         u32 inst;
  65
  66         if (!chan->crypt_ctx)
  67                 return;
  68
  69         inst  = (chan->ramin->vinst >> 12);
  70         inst |= 0x80000000;
  71
  72         /* mark context as invalid if still on the hardware, not
  73          * doing this causes issues the next time PCRYPT is used,
  74          * unsurprisingly :)
  75          */
  76         nv_wr32(dev, 0x10200c, 0x00000000);
  77         if (nv_rd32(dev, 0x102188) == inst)
  78                 nv_mask(dev, 0x102188, 0x80000000, 0x00000000);
  79         if (nv_rd32(dev, 0x10218c) == inst)
  80                 nv_mask(dev, 0x10218c, 0x80000000, 0x00000000);
  81         nv_wr32(dev, 0x10200c, 0x00000010);
  82
  83         nouveau_gpuobj_ref(NULL, &chan->crypt_ctx);
  84         atomic_dec(&chan->vm->pcrypt_refs);
  85 }
  86
  87 void
  88 nv84_crypt_tlb_flush(struct drm_device *dev)
  89 {
  90         nv50_vm_flush_engine(dev, 0x0a);
  91 }
  92
  93 int
  94 nv84_crypt_init(struct drm_device *dev)
  95 {
  96         struct drm_nouveau_private *dev_priv = dev->dev_private;
  97         struct nouveau_crypt_engine *pcrypt = &dev_priv->engine.crypt;
  98
  99         if (!pcrypt->registered) {
 100                 NVOBJ_CLASS(dev, 0x74c1, CRYPT);
 101                 pcrypt->registered = true;
 102         }
 103
 104         nv_mask(dev, 0x000200, 0x00004000, 0x00000000);
 105         nv_mask(dev, 0x000200, 0x00004000, 0x00004000);
 106
 107         nouveau_irq_register(dev, 14, nv84_crypt_isr);
 108         nv_wr32(dev, 0x102130, 0xffffffff);
 109         nv_wr32(dev, 0x102140, 0xffffffbf);
 110
 111         nv_wr32(dev, 0x10200c, 0x00000010);
 112         return 0;
 113 }
 114
 115 void
 116 nv84_crypt_fini(struct drm_device *dev)
 117 {
 118         nv_wr32(dev, 0x102140, 0x00000000);
 119         nouveau_irq_unregister(dev, 14);
 120 }
 121
 122 static void
 123 nv84_crypt_isr(struct drm_device *dev)
 124 {
 125         u32 stat = nv_rd32(dev, 0x102130);
 126         u32 mthd = nv_rd32(dev, 0x102190);
 127         u32 data = nv_rd32(dev, 0x102194);
 128         u32 inst = nv_rd32(dev, 0x102188) & 0x7fffffff;
 129         int show = nouveau_ratelimit();
 130
 131         if (show) {
 132                 NV_INFO(dev, "PCRYPT_INTR: 0x%08x 0x%08x 0x%08x 0x%08x\n",
 133                              stat, mthd, data, inst);
 134         }
 135
 136         nv_wr32(dev, 0x102130, stat);
 137         nv_wr32(dev, 0x10200c, 0x10);
 138
 139         nv50_fb_vm_trap(dev, show);
 140 }