drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c

   1 /**************************************************************************
   2  *
   3  * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  21  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  22  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  23  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  24  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #include "vmwgfx_drv.h"
  29 #include "drmP.h"
  30 #include "ttm/ttm_placement.h"
  31
  32 bool vmw_fifo_have_3d(struct vmw_private *dev_priv)
  33 {
  34         __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
  35         uint32_t fifo_min, hwversion;
  36
  37         if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO))
  38                 return false;
  39
  40         fifo_min = ioread32(fifo_mem  + SVGA_FIFO_MIN);
  41         if (fifo_min <= SVGA_FIFO_3D_HWVERSION * sizeof(unsigned int))
  42                 return false;
  43
  44         hwversion = ioread32(fifo_mem + SVGA_FIFO_3D_HWVERSION);
  45         if (hwversion == 0)
  46                 return false;
  47
  48         if (hwversion < SVGA3D_HWVERSION_WS65_B1)
  49                 return false;
  50
  51         return true;
  52 }
  53
  54 bool vmw_fifo_have_pitchlock(struct vmw_private *dev_priv)
  55 {
  56         __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
  57         uint32_t caps;
  58
  59         if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO))
  60                 return false;
  61
  62         caps = ioread32(fifo_mem + SVGA_FIFO_CAPABILITIES);
  63         if (caps & SVGA_FIFO_CAP_PITCHLOCK)
  64                 return true;
  65
  66         return false;
  67 }
  68
  69 int vmw_fifo_init(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo)
  70 {
  71         __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
  72         uint32_t max;
  73         uint32_t min;
  74         uint32_t dummy;
  75         int ret;
  76
  77         fifo->static_buffer_size = VMWGFX_FIFO_STATIC_SIZE;
  78         fifo->static_buffer = vmalloc(fifo->static_buffer_size);
  79         if (unlikely(fifo->static_buffer == NULL))
  80                 return -ENOMEM;
  81
  82         fifo->last_buffer_size = VMWGFX_FIFO_STATIC_SIZE;
  83         fifo->last_data_size = 0;
  84         fifo->last_buffer_add = false;
  85         fifo->last_buffer = vmalloc(fifo->last_buffer_size);
  86         if (unlikely(fifo->last_buffer == NULL)) {
  87                 ret = -ENOMEM;
  88                 goto out_err;
  89         }
  90
  91         fifo->dynamic_buffer = NULL;
  92         fifo->reserved_size = 0;
  93         fifo->using_bounce_buffer = false;
  94
  95         mutex_init(&fifo->fifo_mutex);
  96         init_rwsem(&fifo->rwsem);
  97
  98         /*
  99          * Allow mapping the first page read-only to user-space.
 100          */
 101
 102         DRM_INFO("width %d\n", vmw_read(dev_priv, SVGA_REG_WIDTH));
 103         DRM_INFO("height %d\n", vmw_read(dev_priv, SVGA_REG_HEIGHT));
 104         DRM_INFO("bpp %d\n", vmw_read(dev_priv, SVGA_REG_BITS_PER_PIXEL));
 105
 106         mutex_lock(&dev_priv->hw_mutex);
 107         dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE);
 108         dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE);
 109         dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES);
 110         vmw_write(dev_priv, SVGA_REG_ENABLE, 1);
 111
 112         min = 4;
 113         if (dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO)
 114                 min = vmw_read(dev_priv, SVGA_REG_MEM_REGS);
 115         min <<= 2;
 116
 117         if (min < PAGE_SIZE)
 118                 min = PAGE_SIZE;
 119
 120         iowrite32(min, fifo_mem + SVGA_FIFO_MIN);
 121         iowrite32(dev_priv->mmio_size, fifo_mem + SVGA_FIFO_MAX);
 122         wmb();
 123         iowrite32(min,  fifo_mem + SVGA_FIFO_NEXT_CMD);
 124         iowrite32(min,  fifo_mem + SVGA_FIFO_STOP);
 125         iowrite32(0, fifo_mem + SVGA_FIFO_BUSY);
 126         mb();
 127
 128         vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, 1);
 129         mutex_unlock(&dev_priv->hw_mutex);
 130
 131         max = ioread32(fifo_mem + SVGA_FIFO_MAX);
 132         min = ioread32(fifo_mem  + SVGA_FIFO_MIN);
 133         fifo->capabilities = ioread32(fifo_mem + SVGA_FIFO_CAPABILITIES);
 134
 135         DRM_INFO("Fifo max 0x%08x min 0x%08x cap 0x%08x\n",
 136                  (unsigned int) max,
 137                  (unsigned int) min,
 138                  (unsigned int) fifo->capabilities);
 139
 140         atomic_set(&dev_priv->fence_seq, dev_priv->last_read_sequence);
 141         iowrite32(dev_priv->last_read_sequence, fifo_mem + SVGA_FIFO_FENCE);
 142         vmw_fence_queue_init(&fifo->fence_queue);
 143         return vmw_fifo_send_fence(dev_priv, &dummy);
 144 out_err:
 145         vfree(fifo->static_buffer);
 146         fifo->static_buffer = NULL;
 147         return ret;
 148 }
 149
 150 void vmw_fifo_ping_host(struct vmw_private *dev_priv, uint32_t reason)
 151 {
 152         __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
 153
 154         mutex_lock(&dev_priv->hw_mutex);
 155
 156         if (unlikely(ioread32(fifo_mem + SVGA_FIFO_BUSY) == 0)) {
 157                 iowrite32(1, fifo_mem + SVGA_FIFO_BUSY);
 158                 vmw_write(dev_priv, SVGA_REG_SYNC, reason);
 159         }
 160
 161         mutex_unlock(&dev_priv->hw_mutex);
 162 }
 163
 164 void vmw_fifo_release(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo)
 165 {
 166         __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
 167
 168         mutex_lock(&dev_priv->hw_mutex);
 169
 170         while (vmw_read(dev_priv, SVGA_REG_BUSY) != 0)
 171                 vmw_write(dev_priv, SVGA_REG_SYNC, SVGA_SYNC_GENERIC);
 172
 173         dev_priv->last_read_sequence = ioread32(fifo_mem + SVGA_FIFO_FENCE);
 174
 175         vmw_write(dev_priv, SVGA_REG_CONFIG_DONE,
 176                   dev_priv->config_done_state);
 177         vmw_write(dev_priv, SVGA_REG_ENABLE,
 178                   dev_priv->enable_state);
 179         vmw_write(dev_priv, SVGA_REG_TRACES,
 180                   dev_priv->traces_state);
 181
 182         mutex_unlock(&dev_priv->hw_mutex);
 183         vmw_fence_queue_takedown(&fifo->fence_queue);
 184
 185         if (likely(fifo->last_buffer != NULL)) {
 186                 vfree(fifo->last_buffer);
 187                 fifo->last_buffer = NULL;
 188         }
 189
 190         if (likely(fifo->static_buffer != NULL)) {
 191                 vfree(fifo->static_buffer);
 192                 fifo->static_buffer = NULL;
 193         }
 194
 195         if (likely(fifo->dynamic_buffer != NULL)) {
 196                 vfree(fifo->dynamic_buffer);
 197                 fifo->dynamic_buffer = NULL;
 198         }
 199 }
 200
 201 static bool vmw_fifo_is_full(struct vmw_private *dev_priv, uint32_t bytes)
 202 {
 203         __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
 204         uint32_t max = ioread32(fifo_mem + SVGA_FIFO_MAX);
 205         uint32_t next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD);
 206         uint32_t min = ioread32(fifo_mem + SVGA_FIFO_MIN);
 207         uint32_t stop = ioread32(fifo_mem + SVGA_FIFO_STOP);
 208
 209         return ((max - next_cmd) + (stop - min) <= bytes);
 210 }
 211
 212 static int vmw_fifo_wait_noirq(struct vmw_private *dev_priv,
 213                                uint32_t bytes, bool interruptible,
 214                                unsigned long timeout)
 215 {
 216         int ret = 0;
 217         unsigned long end_jiffies = jiffies + timeout;
 218         DEFINE_WAIT(__wait);
 219
 220         DRM_INFO("Fifo wait noirq.\n");
 221
 222         for (;;) {
 223                 prepare_to_wait(&dev_priv->fifo_queue, &__wait,
 224                                 (interruptible) ?
 225                                 TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
 226                 if (!vmw_fifo_is_full(dev_priv, bytes))
 227                         break;
 228                 if (time_after_eq(jiffies, end_jiffies)) {
 229                         ret = -EBUSY;
 230                         DRM_ERROR("SVGA device lockup.\n");
 231                         break;
 232                 }
 233                 schedule_timeout(1);
 234                 if (interruptible && signal_pending(current)) {
 235                         ret = -ERESTARTSYS;
 236                         break;
 237                 }
 238         }
 239         finish_wait(&dev_priv->fifo_queue, &__wait);
 240         wake_up_all(&dev_priv->fifo_queue);
 241         DRM_INFO("Fifo noirq exit.\n");
 242         return ret;
 243 }
 244
 245 static int vmw_fifo_wait(struct vmw_private *dev_priv,
 246                          uint32_t bytes, bool interruptible,
 247                          unsigned long timeout)
 248 {
 249         long ret = 1L;
 250         unsigned long irq_flags;
 251
 252         if (likely(!vmw_fifo_is_full(dev_priv, bytes)))
 253                 return 0;
 254
 255         vmw_fifo_ping_host(dev_priv, SVGA_SYNC_FIFOFULL);
 256         if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK))
 257                 return vmw_fifo_wait_noirq(dev_priv, bytes,
 258                                            interruptible, timeout);
 259
 260         mutex_lock(&dev_priv->hw_mutex);
 261         if (atomic_add_return(1, &dev_priv->fifo_queue_waiters) > 0) {
 262                 spin_lock_irqsave(&dev_priv->irq_lock, irq_flags);
 263                 outl(SVGA_IRQFLAG_FIFO_PROGRESS,
 264                      dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
 265                 vmw_write(dev_priv, SVGA_REG_IRQMASK,
 266                           vmw_read(dev_priv, SVGA_REG_IRQMASK) |
 267                           SVGA_IRQFLAG_FIFO_PROGRESS);
 268                 spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags);
 269         }
 270         mutex_unlock(&dev_priv->hw_mutex);
 271
 272         if (interruptible)
 273                 ret = wait_event_interruptible_timeout
 274                     (dev_priv->fifo_queue,
 275                      !vmw_fifo_is_full(dev_priv, bytes), timeout);
 276         else
 277                 ret = wait_event_timeout
 278                     (dev_priv->fifo_queue,
 279                      !vmw_fifo_is_full(dev_priv, bytes), timeout);
 280
 281         if (unlikely(ret == 0))
 282                 ret = -EBUSY;
 283         else if (likely(ret > 0))
 284                 ret = 0;
 285
 286         mutex_lock(&dev_priv->hw_mutex);
 287         if (atomic_dec_and_test(&dev_priv->fifo_queue_waiters)) {
 288                 spin_lock_irqsave(&dev_priv->irq_lock, irq_flags);
 289                 vmw_write(dev_priv, SVGA_REG_IRQMASK,
 290                           vmw_read(dev_priv, SVGA_REG_IRQMASK) &
 291                           ~SVGA_IRQFLAG_FIFO_PROGRESS);
 292                 spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags);
 293         }
 294         mutex_unlock(&dev_priv->hw_mutex);
 295
 296         return ret;
 297 }
 298
 299 void *vmw_fifo_reserve(struct vmw_private *dev_priv, uint32_t bytes)
 300 {
 301         struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
 302         __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
 303         uint32_t max;
 304         uint32_t min;
 305         uint32_t next_cmd;
 306         uint32_t reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE;
 307         int ret;
 308
 309         mutex_lock(&fifo_state->fifo_mutex);
 310         max = ioread32(fifo_mem + SVGA_FIFO_MAX);
 311         min = ioread32(fifo_mem + SVGA_FIFO_MIN);
 312         next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD);
 313
 314         if (unlikely(bytes >= (max - min)))
 315                 goto out_err;
 316
 317         BUG_ON(fifo_state->reserved_size != 0);
 318         BUG_ON(fifo_state->dynamic_buffer != NULL);
 319
 320         fifo_state->reserved_size = bytes;
 321
 322         while (1) {
 323                 uint32_t stop = ioread32(fifo_mem + SVGA_FIFO_STOP);
 324                 bool need_bounce = false;
 325                 bool reserve_in_place = false;
 326
 327                 if (next_cmd >= stop) {
 328                         if (likely((next_cmd + bytes < max ||
 329                                     (next_cmd + bytes == max && stop > min))))
 330                                 reserve_in_place = true;
 331
 332                         else if (vmw_fifo_is_full(dev_priv, bytes)) {
 333                                 ret = vmw_fifo_wait(dev_priv, bytes,
 334                                                     false, 3 * HZ);
 335                                 if (unlikely(ret != 0))
 336                                         goto out_err;
 337                         } else
 338                                 need_bounce = true;
 339
 340                 } else {
 341
 342                         if (likely((next_cmd + bytes < stop)))
 343                                 reserve_in_place = true;
 344                         else {
 345                                 ret = vmw_fifo_wait(dev_priv, bytes,
 346                                                     false, 3 * HZ);
 347                                 if (unlikely(ret != 0))
 348                                         goto out_err;
 349                         }
 350                 }
 351
 352                 if (reserve_in_place) {
 353                         if (reserveable || bytes <= sizeof(uint32_t)) {
 354                                 fifo_state->using_bounce_buffer = false;
 355
 356                                 if (reserveable)
 357                                         iowrite32(bytes, fifo_mem +
 358                                                   SVGA_FIFO_RESERVED);
 359                                 return fifo_mem + (next_cmd >> 2);
 360                         } else {
 361                                 need_bounce = true;
 362                         }
 363                 }
 364
 365                 if (need_bounce) {
 366                         fifo_state->using_bounce_buffer = true;
 367                         if (bytes < fifo_state->static_buffer_size)
 368                                 return fifo_state->static_buffer;
 369                         else {
 370                                 fifo_state->dynamic_buffer = vmalloc(bytes);
 371                                 return fifo_state->dynamic_buffer;
 372                         }
 373                 }
 374         }
 375 out_err:
 376         fifo_state->reserved_size = 0;
 377         mutex_unlock(&fifo_state->fifo_mutex);
 378         return NULL;
 379 }
 380
 381 static void vmw_fifo_res_copy(struct vmw_fifo_state *fifo_state,
 382                               __le32 __iomem *fifo_mem,
 383                               uint32_t next_cmd,
 384                               uint32_t max, uint32_t min, uint32_t bytes)
 385 {
 386         uint32_t chunk_size = max - next_cmd;
 387         uint32_t rest;
 388         uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ?
 389             fifo_state->dynamic_buffer : fifo_state->static_buffer;
 390
 391         if (bytes < chunk_size)
 392                 chunk_size = bytes;
 393
 394         iowrite32(bytes, fifo_mem + SVGA_FIFO_RESERVED);
 395         mb();
 396         memcpy_toio(fifo_mem + (next_cmd >> 2), buffer, chunk_size);
 397         rest = bytes - chunk_size;
 398         if (rest)
 399                 memcpy_toio(fifo_mem + (min >> 2), buffer + (chunk_size >> 2),
 400                             rest);
 401 }
 402
 403 static void vmw_fifo_slow_copy(struct vmw_fifo_state *fifo_state,
 404                                __le32 __iomem *fifo_mem,
 405                                uint32_t next_cmd,
 406                                uint32_t max, uint32_t min, uint32_t bytes)
 407 {
 408         uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ?
 409             fifo_state->dynamic_buffer : fifo_state->static_buffer;
 410
 411         while (bytes > 0) {
 412                 iowrite32(*buffer++, fifo_mem + (next_cmd >> 2));
 413                 next_cmd += sizeof(uint32_t);
 414                 if (unlikely(next_cmd == max))
 415                         next_cmd = min;
 416                 mb();
 417                 iowrite32(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD);
 418                 mb();
 419                 bytes -= sizeof(uint32_t);
 420         }
 421 }
 422
 423 void vmw_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes)
 424 {
 425         struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
 426         __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
 427         uint32_t next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD);
 428         uint32_t max = ioread32(fifo_mem + SVGA_FIFO_MAX);
 429         uint32_t min = ioread32(fifo_mem + SVGA_FIFO_MIN);
 430         bool reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE;
 431
 432         BUG_ON((bytes & 3) != 0);
 433         BUG_ON(bytes > fifo_state->reserved_size);
 434
 435         fifo_state->reserved_size = 0;
 436
 437         if (fifo_state->using_bounce_buffer) {
 438                 if (reserveable)
 439                         vmw_fifo_res_copy(fifo_state, fifo_mem,
 440                                           next_cmd, max, min, bytes);
 441                 else
 442                         vmw_fifo_slow_copy(fifo_state, fifo_mem,
 443                                            next_cmd, max, min, bytes);
 444
 445                 if (fifo_state->dynamic_buffer) {
 446                         vfree(fifo_state->dynamic_buffer);
 447                         fifo_state->dynamic_buffer = NULL;
 448                 }
 449
 450         }
 451
 452         down_write(&fifo_state->rwsem);
 453         if (fifo_state->using_bounce_buffer || reserveable) {
 454                 next_cmd += bytes;
 455                 if (next_cmd >= max)
 456                         next_cmd -= max - min;
 457                 mb();
 458                 iowrite32(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD);
 459         }
 460
 461         if (reserveable)
 462                 iowrite32(0, fifo_mem + SVGA_FIFO_RESERVED);
 463         mb();
 464         up_write(&fifo_state->rwsem);
 465         vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC);
 466         mutex_unlock(&fifo_state->fifo_mutex);
 467 }
 468
 469 int vmw_fifo_send_fence(struct vmw_private *dev_priv, uint32_t *sequence)
 470 {
 471         struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
 472         struct svga_fifo_cmd_fence *cmd_fence;
 473         void *fm;
 474         int ret = 0;
 475         uint32_t bytes = sizeof(__le32) + sizeof(*cmd_fence);
 476
 477         fm = vmw_fifo_reserve(dev_priv, bytes);
 478         if (unlikely(fm == NULL)) {
 479                 *sequence = atomic_read(&dev_priv->fence_seq);
 480                 ret = -ENOMEM;
 481                 (void)vmw_fallback_wait(dev_priv, false, true, *sequence,
 482                                         false, 3*HZ);
 483                 goto out_err;
 484         }
 485
 486         do {
 487                 *sequence = atomic_add_return(1, &dev_priv->fence_seq);
 488         } while (*sequence == 0);
 489
 490         if (!(fifo_state->capabilities & SVGA_FIFO_CAP_FENCE)) {
 491
 492                 /*
 493                  * Don't request hardware to send a fence. The
 494                  * waiting code in vmwgfx_irq.c will emulate this.
 495                  */
 496
 497                 vmw_fifo_commit(dev_priv, 0);
 498                 return 0;
 499         }
 500
 501         *(__le32 *) fm = cpu_to_le32(SVGA_CMD_FENCE);
 502         cmd_fence = (struct svga_fifo_cmd_fence *)
 503             ((unsigned long)fm + sizeof(__le32));
 504
 505         iowrite32(*sequence, &cmd_fence->fence);
 506         fifo_state->last_buffer_add = true;
 507         vmw_fifo_commit(dev_priv, bytes);
 508         fifo_state->last_buffer_add = false;
 509         (void) vmw_fence_push(&fifo_state->fence_queue, *sequence);
 510         vmw_update_sequence(dev_priv, fifo_state);
 511
 512 out_err:
 513         return ret;
 514 }
 515
 516 /**
 517  * Map the first page of the FIFO read-only to user-space.
 518  */
 519
 520 static int vmw_fifo_vm_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
 521 {
 522         int ret;
 523         unsigned long address = (unsigned long)vmf->virtual_address;
 524
 525         if (address != vma->vm_start)
 526                 return VM_FAULT_SIGBUS;
 527
 528         ret = vm_insert_pfn(vma, address, vma->vm_pgoff);
 529         if (likely(ret == -EBUSY || ret == 0))
 530                 return VM_FAULT_NOPAGE;
 531         else if (ret == -ENOMEM)
 532                 return VM_FAULT_OOM;
 533
 534         return VM_FAULT_SIGBUS;
 535 }
 536
 537 static struct vm_operations_struct vmw_fifo_vm_ops = {
 538         .fault = vmw_fifo_vm_fault,
 539         .open = NULL,
 540         .close = NULL
 541 };
 542
 543 int vmw_fifo_mmap(struct file *filp, struct vm_area_struct *vma)
 544 {
 545         struct drm_file *file_priv;
 546         struct vmw_private *dev_priv;
 547
 548         file_priv = filp->private_data;
 549         dev_priv = vmw_priv(file_priv->minor->dev);
 550
 551         if (vma->vm_pgoff != (dev_priv->mmio_start >> PAGE_SHIFT) ||
 552             (vma->vm_end - vma->vm_start) != PAGE_SIZE)
 553                 return -EINVAL;
 554
 555         vma->vm_flags &= ~(VM_WRITE | VM_MAYWRITE);
 556         vma->vm_flags |= VM_IO | VM_PFNMAP | VM_DONTEXPAND | VM_SHARED;
 557         vma->vm_page_prot = vm_get_page_prot(vma->vm_flags);
 558         vma->vm_page_prot = ttm_io_prot(TTM_PL_FLAG_UNCACHED,
 559                                         vma->vm_page_prot);
 560         vma->vm_ops = &vmw_fifo_vm_ops;
 561         return 0;
 562 }