FRV: Use generic show_interrupts()
[cris-mirror.git] / drivers / i2c / busses / i2c-s3c2410.c
blob6c00c107ebf30af4360bd3fef78fac03b62a4683
1 /* linux/drivers/i2c/busses/i2c-s3c2410.c
3 * Copyright (C) 2004,2005,2009 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * S3C2410 I2C Controller
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #include <linux/kernel.h>
24 #include <linux/module.h>
26 #include <linux/i2c.h>
27 #include <linux/init.h>
28 #include <linux/time.h>
29 #include <linux/interrupt.h>
30 #include <linux/delay.h>
31 #include <linux/errno.h>
32 #include <linux/err.h>
33 #include <linux/platform_device.h>
34 #include <linux/clk.h>
35 #include <linux/cpufreq.h>
36 #include <linux/slab.h>
37 #include <linux/io.h>
39 #include <asm/irq.h>
41 #include <plat/regs-iic.h>
42 #include <plat/iic.h>
44 /* i2c controller state */
46 enum s3c24xx_i2c_state {
47 STATE_IDLE,
48 STATE_START,
49 STATE_READ,
50 STATE_WRITE,
51 STATE_STOP
54 enum s3c24xx_i2c_type {
55 TYPE_S3C2410,
56 TYPE_S3C2440,
59 struct s3c24xx_i2c {
60 spinlock_t lock;
61 wait_queue_head_t wait;
62 unsigned int suspended:1;
64 struct i2c_msg *msg;
65 unsigned int msg_num;
66 unsigned int msg_idx;
67 unsigned int msg_ptr;
69 unsigned int tx_setup;
70 unsigned int irq;
72 enum s3c24xx_i2c_state state;
73 unsigned long clkrate;
75 void __iomem *regs;
76 struct clk *clk;
77 struct device *dev;
78 struct resource *ioarea;
79 struct i2c_adapter adap;
81 #ifdef CONFIG_CPU_FREQ
82 struct notifier_block freq_transition;
83 #endif
86 /* default platform data removed, dev should always carry data. */
88 /* s3c24xx_i2c_is2440()
90 * return true is this is an s3c2440
93 static inline int s3c24xx_i2c_is2440(struct s3c24xx_i2c *i2c)
95 struct platform_device *pdev = to_platform_device(i2c->dev);
96 enum s3c24xx_i2c_type type;
98 type = platform_get_device_id(pdev)->driver_data;
99 return type == TYPE_S3C2440;
102 /* s3c24xx_i2c_master_complete
104 * complete the message and wake up the caller, using the given return code,
105 * or zero to mean ok.
108 static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret)
110 dev_dbg(i2c->dev, "master_complete %d\n", ret);
112 i2c->msg_ptr = 0;
113 i2c->msg = NULL;
114 i2c->msg_idx++;
115 i2c->msg_num = 0;
116 if (ret)
117 i2c->msg_idx = ret;
119 wake_up(&i2c->wait);
122 static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c)
124 unsigned long tmp;
126 tmp = readl(i2c->regs + S3C2410_IICCON);
127 writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
130 static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c)
132 unsigned long tmp;
134 tmp = readl(i2c->regs + S3C2410_IICCON);
135 writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
138 /* irq enable/disable functions */
140 static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c)
142 unsigned long tmp;
144 tmp = readl(i2c->regs + S3C2410_IICCON);
145 writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
148 static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c)
150 unsigned long tmp;
152 tmp = readl(i2c->regs + S3C2410_IICCON);
153 writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
157 /* s3c24xx_i2c_message_start
159 * put the start of a message onto the bus
162 static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c,
163 struct i2c_msg *msg)
165 unsigned int addr = (msg->addr & 0x7f) << 1;
166 unsigned long stat;
167 unsigned long iiccon;
169 stat = 0;
170 stat |= S3C2410_IICSTAT_TXRXEN;
172 if (msg->flags & I2C_M_RD) {
173 stat |= S3C2410_IICSTAT_MASTER_RX;
174 addr |= 1;
175 } else
176 stat |= S3C2410_IICSTAT_MASTER_TX;
178 if (msg->flags & I2C_M_REV_DIR_ADDR)
179 addr ^= 1;
181 /* todo - check for wether ack wanted or not */
182 s3c24xx_i2c_enable_ack(i2c);
184 iiccon = readl(i2c->regs + S3C2410_IICCON);
185 writel(stat, i2c->regs + S3C2410_IICSTAT);
187 dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr);
188 writeb(addr, i2c->regs + S3C2410_IICDS);
190 /* delay here to ensure the data byte has gotten onto the bus
191 * before the transaction is started */
193 ndelay(i2c->tx_setup);
195 dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon);
196 writel(iiccon, i2c->regs + S3C2410_IICCON);
198 stat |= S3C2410_IICSTAT_START;
199 writel(stat, i2c->regs + S3C2410_IICSTAT);
202 static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret)
204 unsigned long iicstat = readl(i2c->regs + S3C2410_IICSTAT);
206 dev_dbg(i2c->dev, "STOP\n");
208 /* stop the transfer */
209 iicstat &= ~S3C2410_IICSTAT_START;
210 writel(iicstat, i2c->regs + S3C2410_IICSTAT);
212 i2c->state = STATE_STOP;
214 s3c24xx_i2c_master_complete(i2c, ret);
215 s3c24xx_i2c_disable_irq(i2c);
218 /* helper functions to determine the current state in the set of
219 * messages we are sending */
221 /* is_lastmsg()
223 * returns TRUE if the current message is the last in the set
226 static inline int is_lastmsg(struct s3c24xx_i2c *i2c)
228 return i2c->msg_idx >= (i2c->msg_num - 1);
231 /* is_msglast
233 * returns TRUE if we this is the last byte in the current message
236 static inline int is_msglast(struct s3c24xx_i2c *i2c)
238 return i2c->msg_ptr == i2c->msg->len-1;
241 /* is_msgend
243 * returns TRUE if we reached the end of the current message
246 static inline int is_msgend(struct s3c24xx_i2c *i2c)
248 return i2c->msg_ptr >= i2c->msg->len;
251 /* i2s_s3c_irq_nextbyte
253 * process an interrupt and work out what to do
256 static int i2s_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat)
258 unsigned long tmp;
259 unsigned char byte;
260 int ret = 0;
262 switch (i2c->state) {
264 case STATE_IDLE:
265 dev_err(i2c->dev, "%s: called in STATE_IDLE\n", __func__);
266 goto out;
267 break;
269 case STATE_STOP:
270 dev_err(i2c->dev, "%s: called in STATE_STOP\n", __func__);
271 s3c24xx_i2c_disable_irq(i2c);
272 goto out_ack;
274 case STATE_START:
275 /* last thing we did was send a start condition on the
276 * bus, or started a new i2c message
279 if (iicstat & S3C2410_IICSTAT_LASTBIT &&
280 !(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
281 /* ack was not received... */
283 dev_dbg(i2c->dev, "ack was not received\n");
284 s3c24xx_i2c_stop(i2c, -ENXIO);
285 goto out_ack;
288 if (i2c->msg->flags & I2C_M_RD)
289 i2c->state = STATE_READ;
290 else
291 i2c->state = STATE_WRITE;
293 /* terminate the transfer if there is nothing to do
294 * as this is used by the i2c probe to find devices. */
296 if (is_lastmsg(i2c) && i2c->msg->len == 0) {
297 s3c24xx_i2c_stop(i2c, 0);
298 goto out_ack;
301 if (i2c->state == STATE_READ)
302 goto prepare_read;
304 /* fall through to the write state, as we will need to
305 * send a byte as well */
307 case STATE_WRITE:
308 /* we are writing data to the device... check for the
309 * end of the message, and if so, work out what to do
312 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
313 if (iicstat & S3C2410_IICSTAT_LASTBIT) {
314 dev_dbg(i2c->dev, "WRITE: No Ack\n");
316 s3c24xx_i2c_stop(i2c, -ECONNREFUSED);
317 goto out_ack;
321 retry_write:
323 if (!is_msgend(i2c)) {
324 byte = i2c->msg->buf[i2c->msg_ptr++];
325 writeb(byte, i2c->regs + S3C2410_IICDS);
327 /* delay after writing the byte to allow the
328 * data setup time on the bus, as writing the
329 * data to the register causes the first bit
330 * to appear on SDA, and SCL will change as
331 * soon as the interrupt is acknowledged */
333 ndelay(i2c->tx_setup);
335 } else if (!is_lastmsg(i2c)) {
336 /* we need to go to the next i2c message */
338 dev_dbg(i2c->dev, "WRITE: Next Message\n");
340 i2c->msg_ptr = 0;
341 i2c->msg_idx++;
342 i2c->msg++;
344 /* check to see if we need to do another message */
345 if (i2c->msg->flags & I2C_M_NOSTART) {
347 if (i2c->msg->flags & I2C_M_RD) {
348 /* cannot do this, the controller
349 * forces us to send a new START
350 * when we change direction */
352 s3c24xx_i2c_stop(i2c, -EINVAL);
355 goto retry_write;
356 } else {
357 /* send the new start */
358 s3c24xx_i2c_message_start(i2c, i2c->msg);
359 i2c->state = STATE_START;
362 } else {
363 /* send stop */
365 s3c24xx_i2c_stop(i2c, 0);
367 break;
369 case STATE_READ:
370 /* we have a byte of data in the data register, do
371 * something with it, and then work out wether we are
372 * going to do any more read/write
375 byte = readb(i2c->regs + S3C2410_IICDS);
376 i2c->msg->buf[i2c->msg_ptr++] = byte;
378 prepare_read:
379 if (is_msglast(i2c)) {
380 /* last byte of buffer */
382 if (is_lastmsg(i2c))
383 s3c24xx_i2c_disable_ack(i2c);
385 } else if (is_msgend(i2c)) {
386 /* ok, we've read the entire buffer, see if there
387 * is anything else we need to do */
389 if (is_lastmsg(i2c)) {
390 /* last message, send stop and complete */
391 dev_dbg(i2c->dev, "READ: Send Stop\n");
393 s3c24xx_i2c_stop(i2c, 0);
394 } else {
395 /* go to the next transfer */
396 dev_dbg(i2c->dev, "READ: Next Transfer\n");
398 i2c->msg_ptr = 0;
399 i2c->msg_idx++;
400 i2c->msg++;
404 break;
407 /* acknowlegde the IRQ and get back on with the work */
409 out_ack:
410 tmp = readl(i2c->regs + S3C2410_IICCON);
411 tmp &= ~S3C2410_IICCON_IRQPEND;
412 writel(tmp, i2c->regs + S3C2410_IICCON);
413 out:
414 return ret;
417 /* s3c24xx_i2c_irq
419 * top level IRQ servicing routine
422 static irqreturn_t s3c24xx_i2c_irq(int irqno, void *dev_id)
424 struct s3c24xx_i2c *i2c = dev_id;
425 unsigned long status;
426 unsigned long tmp;
428 status = readl(i2c->regs + S3C2410_IICSTAT);
430 if (status & S3C2410_IICSTAT_ARBITR) {
431 /* deal with arbitration loss */
432 dev_err(i2c->dev, "deal with arbitration loss\n");
435 if (i2c->state == STATE_IDLE) {
436 dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n");
438 tmp = readl(i2c->regs + S3C2410_IICCON);
439 tmp &= ~S3C2410_IICCON_IRQPEND;
440 writel(tmp, i2c->regs + S3C2410_IICCON);
441 goto out;
444 /* pretty much this leaves us with the fact that we've
445 * transmitted or received whatever byte we last sent */
447 i2s_s3c_irq_nextbyte(i2c, status);
449 out:
450 return IRQ_HANDLED;
454 /* s3c24xx_i2c_set_master
456 * get the i2c bus for a master transaction
459 static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c)
461 unsigned long iicstat;
462 int timeout = 400;
464 while (timeout-- > 0) {
465 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
467 if (!(iicstat & S3C2410_IICSTAT_BUSBUSY))
468 return 0;
470 msleep(1);
473 return -ETIMEDOUT;
476 /* s3c24xx_i2c_doxfer
478 * this starts an i2c transfer
481 static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c,
482 struct i2c_msg *msgs, int num)
484 unsigned long iicstat, timeout;
485 int spins = 20;
486 int ret;
488 if (i2c->suspended)
489 return -EIO;
491 ret = s3c24xx_i2c_set_master(i2c);
492 if (ret != 0) {
493 dev_err(i2c->dev, "cannot get bus (error %d)\n", ret);
494 ret = -EAGAIN;
495 goto out;
498 spin_lock_irq(&i2c->lock);
500 i2c->msg = msgs;
501 i2c->msg_num = num;
502 i2c->msg_ptr = 0;
503 i2c->msg_idx = 0;
504 i2c->state = STATE_START;
506 s3c24xx_i2c_enable_irq(i2c);
507 s3c24xx_i2c_message_start(i2c, msgs);
508 spin_unlock_irq(&i2c->lock);
510 timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
512 ret = i2c->msg_idx;
514 /* having these next two as dev_err() makes life very
515 * noisy when doing an i2cdetect */
517 if (timeout == 0)
518 dev_dbg(i2c->dev, "timeout\n");
519 else if (ret != num)
520 dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
522 /* ensure the stop has been through the bus */
524 dev_dbg(i2c->dev, "waiting for bus idle\n");
526 /* first, try busy waiting briefly */
527 do {
528 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
529 } while ((iicstat & S3C2410_IICSTAT_START) && --spins);
531 /* if that timed out sleep */
532 if (!spins) {
533 msleep(1);
534 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
537 if (iicstat & S3C2410_IICSTAT_START)
538 dev_warn(i2c->dev, "timeout waiting for bus idle\n");
540 out:
541 return ret;
544 /* s3c24xx_i2c_xfer
546 * first port of call from the i2c bus code when an message needs
547 * transferring across the i2c bus.
550 static int s3c24xx_i2c_xfer(struct i2c_adapter *adap,
551 struct i2c_msg *msgs, int num)
553 struct s3c24xx_i2c *i2c = (struct s3c24xx_i2c *)adap->algo_data;
554 int retry;
555 int ret;
557 clk_enable(i2c->clk);
559 for (retry = 0; retry < adap->retries; retry++) {
561 ret = s3c24xx_i2c_doxfer(i2c, msgs, num);
563 if (ret != -EAGAIN) {
564 clk_disable(i2c->clk);
565 return ret;
568 dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry);
570 udelay(100);
573 clk_disable(i2c->clk);
574 return -EREMOTEIO;
577 /* declare our i2c functionality */
578 static u32 s3c24xx_i2c_func(struct i2c_adapter *adap)
580 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
583 /* i2c bus registration info */
585 static const struct i2c_algorithm s3c24xx_i2c_algorithm = {
586 .master_xfer = s3c24xx_i2c_xfer,
587 .functionality = s3c24xx_i2c_func,
590 /* s3c24xx_i2c_calcdivisor
592 * return the divisor settings for a given frequency
595 static int s3c24xx_i2c_calcdivisor(unsigned long clkin, unsigned int wanted,
596 unsigned int *div1, unsigned int *divs)
598 unsigned int calc_divs = clkin / wanted;
599 unsigned int calc_div1;
601 if (calc_divs > (16*16))
602 calc_div1 = 512;
603 else
604 calc_div1 = 16;
606 calc_divs += calc_div1-1;
607 calc_divs /= calc_div1;
609 if (calc_divs == 0)
610 calc_divs = 1;
611 if (calc_divs > 17)
612 calc_divs = 17;
614 *divs = calc_divs;
615 *div1 = calc_div1;
617 return clkin / (calc_divs * calc_div1);
620 /* s3c24xx_i2c_clockrate
622 * work out a divisor for the user requested frequency setting,
623 * either by the requested frequency, or scanning the acceptable
624 * range of frequencies until something is found
627 static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got)
629 struct s3c2410_platform_i2c *pdata = i2c->dev->platform_data;
630 unsigned long clkin = clk_get_rate(i2c->clk);
631 unsigned int divs, div1;
632 unsigned long target_frequency;
633 u32 iiccon;
634 int freq;
636 i2c->clkrate = clkin;
637 clkin /= 1000; /* clkin now in KHz */
639 dev_dbg(i2c->dev, "pdata desired frequency %lu\n", pdata->frequency);
641 target_frequency = pdata->frequency ? pdata->frequency : 100000;
643 target_frequency /= 1000; /* Target frequency now in KHz */
645 freq = s3c24xx_i2c_calcdivisor(clkin, target_frequency, &div1, &divs);
647 if (freq > target_frequency) {
648 dev_err(i2c->dev,
649 "Unable to achieve desired frequency %luKHz." \
650 " Lowest achievable %dKHz\n", target_frequency, freq);
651 return -EINVAL;
654 *got = freq;
656 iiccon = readl(i2c->regs + S3C2410_IICCON);
657 iiccon &= ~(S3C2410_IICCON_SCALEMASK | S3C2410_IICCON_TXDIV_512);
658 iiccon |= (divs-1);
660 if (div1 == 512)
661 iiccon |= S3C2410_IICCON_TXDIV_512;
663 writel(iiccon, i2c->regs + S3C2410_IICCON);
665 if (s3c24xx_i2c_is2440(i2c)) {
666 unsigned long sda_delay;
668 if (pdata->sda_delay) {
669 sda_delay = clkin * pdata->sda_delay;
670 sda_delay = DIV_ROUND_UP(sda_delay, 1000000);
671 sda_delay = DIV_ROUND_UP(sda_delay, 5);
672 if (sda_delay > 3)
673 sda_delay = 3;
674 sda_delay |= S3C2410_IICLC_FILTER_ON;
675 } else
676 sda_delay = 0;
678 dev_dbg(i2c->dev, "IICLC=%08lx\n", sda_delay);
679 writel(sda_delay, i2c->regs + S3C2440_IICLC);
682 return 0;
685 #ifdef CONFIG_CPU_FREQ
687 #define freq_to_i2c(_n) container_of(_n, struct s3c24xx_i2c, freq_transition)
689 static int s3c24xx_i2c_cpufreq_transition(struct notifier_block *nb,
690 unsigned long val, void *data)
692 struct s3c24xx_i2c *i2c = freq_to_i2c(nb);
693 unsigned long flags;
694 unsigned int got;
695 int delta_f;
696 int ret;
698 delta_f = clk_get_rate(i2c->clk) - i2c->clkrate;
700 /* if we're post-change and the input clock has slowed down
701 * or at pre-change and the clock is about to speed up, then
702 * adjust our clock rate. <0 is slow, >0 speedup.
705 if ((val == CPUFREQ_POSTCHANGE && delta_f < 0) ||
706 (val == CPUFREQ_PRECHANGE && delta_f > 0)) {
707 spin_lock_irqsave(&i2c->lock, flags);
708 ret = s3c24xx_i2c_clockrate(i2c, &got);
709 spin_unlock_irqrestore(&i2c->lock, flags);
711 if (ret < 0)
712 dev_err(i2c->dev, "cannot find frequency\n");
713 else
714 dev_info(i2c->dev, "setting freq %d\n", got);
717 return 0;
720 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c)
722 i2c->freq_transition.notifier_call = s3c24xx_i2c_cpufreq_transition;
724 return cpufreq_register_notifier(&i2c->freq_transition,
725 CPUFREQ_TRANSITION_NOTIFIER);
728 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c)
730 cpufreq_unregister_notifier(&i2c->freq_transition,
731 CPUFREQ_TRANSITION_NOTIFIER);
734 #else
735 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c)
737 return 0;
740 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c)
743 #endif
745 /* s3c24xx_i2c_init
747 * initialise the controller, set the IO lines and frequency
750 static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c)
752 unsigned long iicon = S3C2410_IICCON_IRQEN | S3C2410_IICCON_ACKEN;
753 struct s3c2410_platform_i2c *pdata;
754 unsigned int freq;
756 /* get the plafrom data */
758 pdata = i2c->dev->platform_data;
760 /* inititalise the gpio */
762 if (pdata->cfg_gpio)
763 pdata->cfg_gpio(to_platform_device(i2c->dev));
765 /* write slave address */
767 writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD);
769 dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr);
771 writel(iicon, i2c->regs + S3C2410_IICCON);
773 /* we need to work out the divisors for the clock... */
775 if (s3c24xx_i2c_clockrate(i2c, &freq) != 0) {
776 writel(0, i2c->regs + S3C2410_IICCON);
777 dev_err(i2c->dev, "cannot meet bus frequency required\n");
778 return -EINVAL;
781 /* todo - check that the i2c lines aren't being dragged anywhere */
783 dev_info(i2c->dev, "bus frequency set to %d KHz\n", freq);
784 dev_dbg(i2c->dev, "S3C2410_IICCON=0x%02lx\n", iicon);
786 return 0;
789 /* s3c24xx_i2c_probe
791 * called by the bus driver when a suitable device is found
794 static int s3c24xx_i2c_probe(struct platform_device *pdev)
796 struct s3c24xx_i2c *i2c;
797 struct s3c2410_platform_i2c *pdata;
798 struct resource *res;
799 int ret;
801 pdata = pdev->dev.platform_data;
802 if (!pdata) {
803 dev_err(&pdev->dev, "no platform data\n");
804 return -EINVAL;
807 i2c = kzalloc(sizeof(struct s3c24xx_i2c), GFP_KERNEL);
808 if (!i2c) {
809 dev_err(&pdev->dev, "no memory for state\n");
810 return -ENOMEM;
813 strlcpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name));
814 i2c->adap.owner = THIS_MODULE;
815 i2c->adap.algo = &s3c24xx_i2c_algorithm;
816 i2c->adap.retries = 2;
817 i2c->adap.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
818 i2c->tx_setup = 50;
820 spin_lock_init(&i2c->lock);
821 init_waitqueue_head(&i2c->wait);
823 /* find the clock and enable it */
825 i2c->dev = &pdev->dev;
826 i2c->clk = clk_get(&pdev->dev, "i2c");
827 if (IS_ERR(i2c->clk)) {
828 dev_err(&pdev->dev, "cannot get clock\n");
829 ret = -ENOENT;
830 goto err_noclk;
833 dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk);
835 clk_enable(i2c->clk);
837 /* map the registers */
839 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
840 if (res == NULL) {
841 dev_err(&pdev->dev, "cannot find IO resource\n");
842 ret = -ENOENT;
843 goto err_clk;
846 i2c->ioarea = request_mem_region(res->start, resource_size(res),
847 pdev->name);
849 if (i2c->ioarea == NULL) {
850 dev_err(&pdev->dev, "cannot request IO\n");
851 ret = -ENXIO;
852 goto err_clk;
855 i2c->regs = ioremap(res->start, resource_size(res));
857 if (i2c->regs == NULL) {
858 dev_err(&pdev->dev, "cannot map IO\n");
859 ret = -ENXIO;
860 goto err_ioarea;
863 dev_dbg(&pdev->dev, "registers %p (%p, %p)\n",
864 i2c->regs, i2c->ioarea, res);
866 /* setup info block for the i2c core */
868 i2c->adap.algo_data = i2c;
869 i2c->adap.dev.parent = &pdev->dev;
871 /* initialise the i2c controller */
873 ret = s3c24xx_i2c_init(i2c);
874 if (ret != 0)
875 goto err_iomap;
877 /* find the IRQ for this unit (note, this relies on the init call to
878 * ensure no current IRQs pending
881 i2c->irq = ret = platform_get_irq(pdev, 0);
882 if (ret <= 0) {
883 dev_err(&pdev->dev, "cannot find IRQ\n");
884 goto err_iomap;
887 ret = request_irq(i2c->irq, s3c24xx_i2c_irq, IRQF_DISABLED,
888 dev_name(&pdev->dev), i2c);
890 if (ret != 0) {
891 dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq);
892 goto err_iomap;
895 ret = s3c24xx_i2c_register_cpufreq(i2c);
896 if (ret < 0) {
897 dev_err(&pdev->dev, "failed to register cpufreq notifier\n");
898 goto err_irq;
901 /* Note, previous versions of the driver used i2c_add_adapter()
902 * to add the bus at any number. We now pass the bus number via
903 * the platform data, so if unset it will now default to always
904 * being bus 0.
907 i2c->adap.nr = pdata->bus_num;
909 ret = i2c_add_numbered_adapter(&i2c->adap);
910 if (ret < 0) {
911 dev_err(&pdev->dev, "failed to add bus to i2c core\n");
912 goto err_cpufreq;
915 platform_set_drvdata(pdev, i2c);
917 dev_info(&pdev->dev, "%s: S3C I2C adapter\n", dev_name(&i2c->adap.dev));
918 clk_disable(i2c->clk);
919 return 0;
921 err_cpufreq:
922 s3c24xx_i2c_deregister_cpufreq(i2c);
924 err_irq:
925 free_irq(i2c->irq, i2c);
927 err_iomap:
928 iounmap(i2c->regs);
930 err_ioarea:
931 release_resource(i2c->ioarea);
932 kfree(i2c->ioarea);
934 err_clk:
935 clk_disable(i2c->clk);
936 clk_put(i2c->clk);
938 err_noclk:
939 kfree(i2c);
940 return ret;
943 /* s3c24xx_i2c_remove
945 * called when device is removed from the bus
948 static int s3c24xx_i2c_remove(struct platform_device *pdev)
950 struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
952 s3c24xx_i2c_deregister_cpufreq(i2c);
954 i2c_del_adapter(&i2c->adap);
955 free_irq(i2c->irq, i2c);
957 clk_disable(i2c->clk);
958 clk_put(i2c->clk);
960 iounmap(i2c->regs);
962 release_resource(i2c->ioarea);
963 kfree(i2c->ioarea);
964 kfree(i2c);
966 return 0;
969 #ifdef CONFIG_PM
970 static int s3c24xx_i2c_suspend_noirq(struct device *dev)
972 struct platform_device *pdev = to_platform_device(dev);
973 struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
975 i2c->suspended = 1;
977 return 0;
980 static int s3c24xx_i2c_resume(struct device *dev)
982 struct platform_device *pdev = to_platform_device(dev);
983 struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
985 i2c->suspended = 0;
986 clk_enable(i2c->clk);
987 s3c24xx_i2c_init(i2c);
988 clk_disable(i2c->clk);
990 return 0;
993 static const struct dev_pm_ops s3c24xx_i2c_dev_pm_ops = {
994 .suspend_noirq = s3c24xx_i2c_suspend_noirq,
995 .resume = s3c24xx_i2c_resume,
998 #define S3C24XX_DEV_PM_OPS (&s3c24xx_i2c_dev_pm_ops)
999 #else
1000 #define S3C24XX_DEV_PM_OPS NULL
1001 #endif
1003 /* device driver for platform bus bits */
1005 static struct platform_device_id s3c24xx_driver_ids[] = {
1007 .name = "s3c2410-i2c",
1008 .driver_data = TYPE_S3C2410,
1009 }, {
1010 .name = "s3c2440-i2c",
1011 .driver_data = TYPE_S3C2440,
1012 }, { },
1014 MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids);
1016 static struct platform_driver s3c24xx_i2c_driver = {
1017 .probe = s3c24xx_i2c_probe,
1018 .remove = s3c24xx_i2c_remove,
1019 .id_table = s3c24xx_driver_ids,
1020 .driver = {
1021 .owner = THIS_MODULE,
1022 .name = "s3c-i2c",
1023 .pm = S3C24XX_DEV_PM_OPS,
1027 static int __init i2c_adap_s3c_init(void)
1029 return platform_driver_register(&s3c24xx_i2c_driver);
1031 subsys_initcall(i2c_adap_s3c_init);
1033 static void __exit i2c_adap_s3c_exit(void)
1035 platform_driver_unregister(&s3c24xx_i2c_driver);
1037 module_exit(i2c_adap_s3c_exit);
1039 MODULE_DESCRIPTION("S3C24XX I2C Bus driver");
1040 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
1041 MODULE_LICENSE("GPL");