?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
FRV: Use generic show_interrupts()
[cris-mirror.git] / drivers / input / keyboard / tegra-kbc.c
blob99ce9032d08cd61f437fb5e3256db537cfa751e8
1 /*
2 * Keyboard class input driver for the NVIDIA Tegra SoC internal matrix
3 * keyboard controller
4 *
5 * Copyright (c) 2009-2011, NVIDIA Corporation.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
20 */
21
22 #include <linux/module.h>
23 #include <linux/input.h>
24 #include <linux/platform_device.h>
25 #include <linux/delay.h>
26 #include <linux/io.h>
27 #include <linux/interrupt.h>
28 #include <linux/clk.h>
29 #include <linux/slab.h>
30 #include <mach/clk.h>
31 #include <mach/kbc.h>
32
33 #define KBC_MAX_DEBOUNCE_CNT 0x3ffu
34
35 /* KBC row scan time and delay for beginning the row scan. */
36 #define KBC_ROW_SCAN_TIME 16
37 #define KBC_ROW_SCAN_DLY 5
38
39 /* KBC uses a 32KHz clock so a cycle = 1/32Khz */
40 #define KBC_CYCLE_USEC 32
41
42 /* KBC Registers */
43
44 /* KBC Control Register */
45 #define KBC_CONTROL_0 0x0
46 #define KBC_FIFO_TH_CNT_SHIFT(cnt) (cnt << 14)
47 #define KBC_DEBOUNCE_CNT_SHIFT(cnt) (cnt << 4)
48 #define KBC_CONTROL_FIFO_CNT_INT_EN (1 << 3)
49 #define KBC_CONTROL_KBC_EN (1 << 0)
50
51 /* KBC Interrupt Register */
52 #define KBC_INT_0 0x4
53 #define KBC_INT_FIFO_CNT_INT_STATUS (1 << 2)
54
55 #define KBC_ROW_CFG0_0 0x8
56 #define KBC_COL_CFG0_0 0x18
57 #define KBC_INIT_DLY_0 0x28
58 #define KBC_RPT_DLY_0 0x2c
59 #define KBC_KP_ENT0_0 0x30
60 #define KBC_KP_ENT1_0 0x34
61 #define KBC_ROW0_MASK_0 0x38
62
63 #define KBC_ROW_SHIFT 3
64
65 struct tegra_kbc {
66 void __iomem *mmio;
67 struct input_dev *idev;
68 unsigned int irq;
69 unsigned int wake_enable_rows;
70 unsigned int wake_enable_cols;
71 spinlock_t lock;
72 unsigned int repoll_dly;
73 unsigned long cp_dly_jiffies;
74 bool use_fn_map;
75 const struct tegra_kbc_platform_data *pdata;
76 unsigned short keycode[KBC_MAX_KEY * 2];
77 unsigned short current_keys[KBC_MAX_KPENT];
78 unsigned int num_pressed_keys;
79 struct timer_list timer;
80 struct clk *clk;
81 };
82
83 static const u32 tegra_kbc_default_keymap[] = {
84 KEY(0, 2, KEY_W),
85 KEY(0, 3, KEY_S),
86 KEY(0, 4, KEY_A),
87 KEY(0, 5, KEY_Z),
88 KEY(0, 7, KEY_FN),
89
90 KEY(1, 7, KEY_LEFTMETA),
91
92 KEY(2, 6, KEY_RIGHTALT),
93 KEY(2, 7, KEY_LEFTALT),
94
95 KEY(3, 0, KEY_5),
96 KEY(3, 1, KEY_4),
97 KEY(3, 2, KEY_R),
98 KEY(3, 3, KEY_E),
99 KEY(3, 4, KEY_F),
100 KEY(3, 5, KEY_D),
101 KEY(3, 6, KEY_X),
102
103 KEY(4, 0, KEY_7),
104 KEY(4, 1, KEY_6),
105 KEY(4, 2, KEY_T),
106 KEY(4, 3, KEY_H),
107 KEY(4, 4, KEY_G),
108 KEY(4, 5, KEY_V),
109 KEY(4, 6, KEY_C),
110 KEY(4, 7, KEY_SPACE),
111
112 KEY(5, 0, KEY_9),
113 KEY(5, 1, KEY_8),
114 KEY(5, 2, KEY_U),
115 KEY(5, 3, KEY_Y),
116 KEY(5, 4, KEY_J),
117 KEY(5, 5, KEY_N),
118 KEY(5, 6, KEY_B),
119 KEY(5, 7, KEY_BACKSLASH),
120
121 KEY(6, 0, KEY_MINUS),
122 KEY(6, 1, KEY_0),
123 KEY(6, 2, KEY_O),
124 KEY(6, 3, KEY_I),
125 KEY(6, 4, KEY_L),
126 KEY(6, 5, KEY_K),
127 KEY(6, 6, KEY_COMMA),
128 KEY(6, 7, KEY_M),
129
130 KEY(7, 1, KEY_EQUAL),
131 KEY(7, 2, KEY_RIGHTBRACE),
132 KEY(7, 3, KEY_ENTER),
133 KEY(7, 7, KEY_MENU),
134
135 KEY(8, 4, KEY_RIGHTSHIFT),
136 KEY(8, 5, KEY_LEFTSHIFT),
137
138 KEY(9, 5, KEY_RIGHTCTRL),
139 KEY(9, 7, KEY_LEFTCTRL),
140
141 KEY(11, 0, KEY_LEFTBRACE),
142 KEY(11, 1, KEY_P),
143 KEY(11, 2, KEY_APOSTROPHE),
144 KEY(11, 3, KEY_SEMICOLON),
145 KEY(11, 4, KEY_SLASH),
146 KEY(11, 5, KEY_DOT),
147
148 KEY(12, 0, KEY_F10),
149 KEY(12, 1, KEY_F9),
150 KEY(12, 2, KEY_BACKSPACE),
151 KEY(12, 3, KEY_3),
152 KEY(12, 4, KEY_2),
153 KEY(12, 5, KEY_UP),
154 KEY(12, 6, KEY_PRINT),
155 KEY(12, 7, KEY_PAUSE),
156
157 KEY(13, 0, KEY_INSERT),
158 KEY(13, 1, KEY_DELETE),
159 KEY(13, 3, KEY_PAGEUP),
160 KEY(13, 4, KEY_PAGEDOWN),
161 KEY(13, 5, KEY_RIGHT),
162 KEY(13, 6, KEY_DOWN),
163 KEY(13, 7, KEY_LEFT),
164
165 KEY(14, 0, KEY_F11),
166 KEY(14, 1, KEY_F12),
167 KEY(14, 2, KEY_F8),
168 KEY(14, 3, KEY_Q),
169 KEY(14, 4, KEY_F4),
170 KEY(14, 5, KEY_F3),
171 KEY(14, 6, KEY_1),
172 KEY(14, 7, KEY_F7),
173
174 KEY(15, 0, KEY_ESC),
175 KEY(15, 1, KEY_GRAVE),
176 KEY(15, 2, KEY_F5),
177 KEY(15, 3, KEY_TAB),
178 KEY(15, 4, KEY_F1),
179 KEY(15, 5, KEY_F2),
180 KEY(15, 6, KEY_CAPSLOCK),
181 KEY(15, 7, KEY_F6),
182
183 /* Software Handled Function Keys */
184 KEY(20, 0, KEY_KP7),
185
186 KEY(21, 0, KEY_KP9),
187 KEY(21, 1, KEY_KP8),
188 KEY(21, 2, KEY_KP4),
189 KEY(21, 4, KEY_KP1),
190
191 KEY(22, 1, KEY_KPSLASH),
192 KEY(22, 2, KEY_KP6),
193 KEY(22, 3, KEY_KP5),
194 KEY(22, 4, KEY_KP3),
195 KEY(22, 5, KEY_KP2),
196 KEY(22, 7, KEY_KP0),
197
198 KEY(27, 1, KEY_KPASTERISK),
199 KEY(27, 3, KEY_KPMINUS),
200 KEY(27, 4, KEY_KPPLUS),
201 KEY(27, 5, KEY_KPDOT),
202
203 KEY(28, 5, KEY_VOLUMEUP),
204
205 KEY(29, 3, KEY_HOME),
206 KEY(29, 4, KEY_END),
207 KEY(29, 5, KEY_BRIGHTNESSDOWN),
208 KEY(29, 6, KEY_VOLUMEDOWN),
209 KEY(29, 7, KEY_BRIGHTNESSUP),
210
211 KEY(30, 0, KEY_NUMLOCK),
212 KEY(30, 1, KEY_SCROLLLOCK),
213 KEY(30, 2, KEY_MUTE),
214
215 KEY(31, 4, KEY_HELP),
216 };
217
218 static const struct matrix_keymap_data tegra_kbc_default_keymap_data = {
219 .keymap = tegra_kbc_default_keymap,
220 .keymap_size = ARRAY_SIZE(tegra_kbc_default_keymap),
221 };
222
223 static void tegra_kbc_report_released_keys(struct input_dev *input,
224 unsigned short old_keycodes[],
225 unsigned int old_num_keys,
226 unsigned short new_keycodes[],
227 unsigned int new_num_keys)
228 {
229 unsigned int i, j;
230
231 for (i = 0; i < old_num_keys; i++) {
232 for (j = 0; j < new_num_keys; j++)
233 if (old_keycodes[i] == new_keycodes[j])
234 break;
235
236 if (j == new_num_keys)
237 input_report_key(input, old_keycodes[i], 0);
238 }
239 }
240
241 static void tegra_kbc_report_pressed_keys(struct input_dev *input,
242 unsigned char scancodes[],
243 unsigned short keycodes[],
244 unsigned int num_pressed_keys)
245 {
246 unsigned int i;
247
248 for (i = 0; i < num_pressed_keys; i++) {
249 input_event(input, EV_MSC, MSC_SCAN, scancodes[i]);
250 input_report_key(input, keycodes[i], 1);
251 }
252 }
253
254 static void tegra_kbc_report_keys(struct tegra_kbc *kbc)
255 {
256 unsigned char scancodes[KBC_MAX_KPENT];
257 unsigned short keycodes[KBC_MAX_KPENT];
258 u32 val = 0;
259 unsigned int i;
260 unsigned int num_down = 0;
261 unsigned long flags;
262 bool fn_keypress = false;
263
264 spin_lock_irqsave(&kbc->lock, flags);
265 for (i = 0; i < KBC_MAX_KPENT; i++) {
266 if ((i % 4) == 0)
267 val = readl(kbc->mmio + KBC_KP_ENT0_0 + i);
268
269 if (val & 0x80) {
270 unsigned int col = val & 0x07;
271 unsigned int row = (val >> 3) & 0x0f;
272 unsigned char scancode =
273 MATRIX_SCAN_CODE(row, col, KBC_ROW_SHIFT);
274
275 scancodes[num_down] = scancode;
276 keycodes[num_down] = kbc->keycode[scancode];
277 /* If driver uses Fn map, do not report the Fn key. */
278 if ((keycodes[num_down] == KEY_FN) && kbc->use_fn_map)
279 fn_keypress = true;
280 else
281 num_down++;
282 }
283
284 val >>= 8;
285 }
286
287 /*
288 * If the platform uses Fn keymaps, translate keys on a Fn keypress.
289 * Function keycodes are KBC_MAX_KEY apart from the plain keycodes.
290 */
291 if (fn_keypress) {
292 for (i = 0; i < num_down; i++) {
293 scancodes[i] += KBC_MAX_KEY;
294 keycodes[i] = kbc->keycode[scancodes[i]];
295 }
296 }
297
298 spin_unlock_irqrestore(&kbc->lock, flags);
299
300 tegra_kbc_report_released_keys(kbc->idev,
301 kbc->current_keys, kbc->num_pressed_keys,
302 keycodes, num_down);
303 tegra_kbc_report_pressed_keys(kbc->idev, scancodes, keycodes, num_down);
304 input_sync(kbc->idev);
305
306 memcpy(kbc->current_keys, keycodes, sizeof(kbc->current_keys));
307 kbc->num_pressed_keys = num_down;
308 }
309
310 static void tegra_kbc_keypress_timer(unsigned long data)
311 {
312 struct tegra_kbc *kbc = (struct tegra_kbc *)data;
313 unsigned long flags;
314 u32 val;
315 unsigned int i;
316
317 val = (readl(kbc->mmio + KBC_INT_0) >> 4) & 0xf;
318 if (val) {
319 unsigned long dly;
320
321 tegra_kbc_report_keys(kbc);
322
323 /*
324 * If more than one keys are pressed we need not wait
325 * for the repoll delay.
326 */
327 dly = (val == 1) ? kbc->repoll_dly : 1;
328 mod_timer(&kbc->timer, jiffies + msecs_to_jiffies(dly));
329 } else {
330 /* Release any pressed keys and exit the polling loop */
331 for (i = 0; i < kbc->num_pressed_keys; i++)
332 input_report_key(kbc->idev, kbc->current_keys[i], 0);
333 input_sync(kbc->idev);
334
335 kbc->num_pressed_keys = 0;
336
337 /* All keys are released so enable the keypress interrupt */
338 spin_lock_irqsave(&kbc->lock, flags);
339 val = readl(kbc->mmio + KBC_CONTROL_0);
340 val |= KBC_CONTROL_FIFO_CNT_INT_EN;
341 writel(val, kbc->mmio + KBC_CONTROL_0);
342 spin_unlock_irqrestore(&kbc->lock, flags);
343 }
344 }
345
346 static irqreturn_t tegra_kbc_isr(int irq, void *args)
347 {
348 struct tegra_kbc *kbc = args;
349 u32 val, ctl;
350
351 /*
352 * Until all keys are released, defer further processing to
353 * the polling loop in tegra_kbc_keypress_timer
354 */
355 ctl = readl(kbc->mmio + KBC_CONTROL_0);
356 ctl &= ~KBC_CONTROL_FIFO_CNT_INT_EN;
357 writel(ctl, kbc->mmio + KBC_CONTROL_0);
358
359 /*
360 * Quickly bail out & reenable interrupts if the fifo threshold
361 * count interrupt wasn't the interrupt source
362 */
363 val = readl(kbc->mmio + KBC_INT_0);
364 writel(val, kbc->mmio + KBC_INT_0);
365
366 if (val & KBC_INT_FIFO_CNT_INT_STATUS) {
367 /*
368 * Schedule timer to run when hardware is in continuous
369 * polling mode.
370 */
371 mod_timer(&kbc->timer, jiffies + kbc->cp_dly_jiffies);
372 } else {
373 ctl |= KBC_CONTROL_FIFO_CNT_INT_EN;
374 writel(ctl, kbc->mmio + KBC_CONTROL_0);
375 }
376
377 return IRQ_HANDLED;
378 }
379
380 static void tegra_kbc_setup_wakekeys(struct tegra_kbc *kbc, bool filter)
381 {
382 const struct tegra_kbc_platform_data *pdata = kbc->pdata;
383 int i;
384 unsigned int rst_val;
385
386 BUG_ON(pdata->wake_cnt > KBC_MAX_KEY);
387 rst_val = (filter && pdata->wake_cnt) ? ~0 : 0;
388
389 for (i = 0; i < KBC_MAX_ROW; i++)
390 writel(rst_val, kbc->mmio + KBC_ROW0_MASK_0 + i * 4);
391
392 if (filter) {
393 for (i = 0; i < pdata->wake_cnt; i++) {
394 u32 val, addr;
395 addr = pdata->wake_cfg[i].row * 4 + KBC_ROW0_MASK_0;
396 val = readl(kbc->mmio + addr);
397 val &= ~(1 << pdata->wake_cfg[i].col);
398 writel(val, kbc->mmio + addr);
399 }
400 }
401 }
402
403 static void tegra_kbc_config_pins(struct tegra_kbc *kbc)
404 {
405 const struct tegra_kbc_platform_data *pdata = kbc->pdata;
406 int i;
407
408 for (i = 0; i < KBC_MAX_GPIO; i++) {
409 u32 r_shft = 5 * (i % 6);
410 u32 c_shft = 4 * (i % 8);
411 u32 r_mask = 0x1f << r_shft;
412 u32 c_mask = 0x0f << c_shft;
413 u32 r_offs = (i / 6) * 4 + KBC_ROW_CFG0_0;
414 u32 c_offs = (i / 8) * 4 + KBC_COL_CFG0_0;
415 u32 row_cfg = readl(kbc->mmio + r_offs);
416 u32 col_cfg = readl(kbc->mmio + c_offs);
417
418 row_cfg &= ~r_mask;
419 col_cfg &= ~c_mask;
420
421 if (pdata->pin_cfg[i].is_row)
422 row_cfg |= ((pdata->pin_cfg[i].num << 1) | 1) << r_shft;
423 else
424 col_cfg |= ((pdata->pin_cfg[i].num << 1) | 1) << c_shft;
425
426 writel(row_cfg, kbc->mmio + r_offs);
427 writel(col_cfg, kbc->mmio + c_offs);
428 }
429 }
430
431 static int tegra_kbc_start(struct tegra_kbc *kbc)
432 {
433 const struct tegra_kbc_platform_data *pdata = kbc->pdata;
434 unsigned long flags;
435 unsigned int debounce_cnt;
436 u32 val = 0;
437
438 clk_enable(kbc->clk);
439
440 /* Reset the KBC controller to clear all previous status.*/
441 tegra_periph_reset_assert(kbc->clk);
442 udelay(100);
443 tegra_periph_reset_deassert(kbc->clk);
444 udelay(100);
445
446 tegra_kbc_config_pins(kbc);
447 tegra_kbc_setup_wakekeys(kbc, false);
448
449 writel(pdata->repeat_cnt, kbc->mmio + KBC_RPT_DLY_0);
450
451 /* Keyboard debounce count is maximum of 12 bits. */
452 debounce_cnt = min(pdata->debounce_cnt, KBC_MAX_DEBOUNCE_CNT);
453 val = KBC_DEBOUNCE_CNT_SHIFT(debounce_cnt);
454 val |= KBC_FIFO_TH_CNT_SHIFT(1); /* set fifo interrupt threshold to 1 */
455 val |= KBC_CONTROL_FIFO_CNT_INT_EN; /* interrupt on FIFO threshold */
456 val |= KBC_CONTROL_KBC_EN; /* enable */
457 writel(val, kbc->mmio + KBC_CONTROL_0);
458
459 /*
460 * Compute the delay(ns) from interrupt mode to continuous polling
461 * mode so the timer routine is scheduled appropriately.
462 */
463 val = readl(kbc->mmio + KBC_INIT_DLY_0);
464 kbc->cp_dly_jiffies = usecs_to_jiffies((val & 0xfffff) * 32);
465
466 kbc->num_pressed_keys = 0;
467
468 /*
469 * Atomically clear out any remaining entries in the key FIFO
470 * and enable keyboard interrupts.
471 */
472 spin_lock_irqsave(&kbc->lock, flags);
473 while (1) {
474 val = readl(kbc->mmio + KBC_INT_0);
475 val >>= 4;
476 if (!val)
477 break;
478
479 val = readl(kbc->mmio + KBC_KP_ENT0_0);
480 val = readl(kbc->mmio + KBC_KP_ENT1_0);
481 }
482 writel(0x7, kbc->mmio + KBC_INT_0);
483 spin_unlock_irqrestore(&kbc->lock, flags);
484
485 enable_irq(kbc->irq);
486
487 return 0;
488 }
489
490 static void tegra_kbc_stop(struct tegra_kbc *kbc)
491 {
492 unsigned long flags;
493 u32 val;
494
495 spin_lock_irqsave(&kbc->lock, flags);
496 val = readl(kbc->mmio + KBC_CONTROL_0);
497 val &= ~1;
498 writel(val, kbc->mmio + KBC_CONTROL_0);
499 spin_unlock_irqrestore(&kbc->lock, flags);
500
501 disable_irq(kbc->irq);
502 del_timer_sync(&kbc->timer);
503
504 clk_disable(kbc->clk);
505 }
506
507 static int tegra_kbc_open(struct input_dev *dev)
508 {
509 struct tegra_kbc *kbc = input_get_drvdata(dev);
510
511 return tegra_kbc_start(kbc);
512 }
513
514 static void tegra_kbc_close(struct input_dev *dev)
515 {
516 struct tegra_kbc *kbc = input_get_drvdata(dev);
517
518 return tegra_kbc_stop(kbc);
519 }
520
521 static bool __devinit
522 tegra_kbc_check_pin_cfg(const struct tegra_kbc_platform_data *pdata,
523 struct device *dev, unsigned int *num_rows)
524 {
525 int i;
526
527 *num_rows = 0;
528
529 for (i = 0; i < KBC_MAX_GPIO; i++) {
530 const struct tegra_kbc_pin_cfg *pin_cfg = &pdata->pin_cfg[i];
531
532 if (pin_cfg->is_row) {
533 if (pin_cfg->num >= KBC_MAX_ROW) {
534 dev_err(dev,
535 "pin_cfg[%d]: invalid row number %d\n",
536 i, pin_cfg->num);
537 return false;
538 }
539 (*num_rows)++;
540 } else {
541 if (pin_cfg->num >= KBC_MAX_COL) {
542 dev_err(dev,
543 "pin_cfg[%d]: invalid column number %d\n",
544 i, pin_cfg->num);
545 return false;
546 }
547 }
548 }
549
550 return true;
551 }
552
553 static int __devinit tegra_kbc_probe(struct platform_device *pdev)
554 {
555 const struct tegra_kbc_platform_data *pdata = pdev->dev.platform_data;
556 const struct matrix_keymap_data *keymap_data;
557 struct tegra_kbc *kbc;
558 struct input_dev *input_dev;
559 struct resource *res;
560 int irq;
561 int err;
562 int i;
563 int num_rows = 0;
564 unsigned int debounce_cnt;
565 unsigned int scan_time_rows;
566
567 if (!pdata)
568 return -EINVAL;
569
570 if (!tegra_kbc_check_pin_cfg(pdata, &pdev->dev, &num_rows))
571 return -EINVAL;
572
573 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
574 if (!res) {
575 dev_err(&pdev->dev, "failed to get I/O memory\n");
576 return -ENXIO;
577 }
578
579 irq = platform_get_irq(pdev, 0);
580 if (irq < 0) {
581 dev_err(&pdev->dev, "failed to get keyboard IRQ\n");
582 return -ENXIO;
583 }
584
585 kbc = kzalloc(sizeof(*kbc), GFP_KERNEL);
586 input_dev = input_allocate_device();
587 if (!kbc || !input_dev) {
588 err = -ENOMEM;
589 goto err_free_mem;
590 }
591
592 kbc->pdata = pdata;
593 kbc->idev = input_dev;
594 kbc->irq = irq;
595 spin_lock_init(&kbc->lock);
596 setup_timer(&kbc->timer, tegra_kbc_keypress_timer, (unsigned long)kbc);
597
598 res = request_mem_region(res->start, resource_size(res), pdev->name);
599 if (!res) {
600 dev_err(&pdev->dev, "failed to request I/O memory\n");
601 err = -EBUSY;
602 goto err_free_mem;
603 }
604
605 kbc->mmio = ioremap(res->start, resource_size(res));
606 if (!kbc->mmio) {
607 dev_err(&pdev->dev, "failed to remap I/O memory\n");
608 err = -ENXIO;
609 goto err_free_mem_region;
610 }
611
612 kbc->clk = clk_get(&pdev->dev, NULL);
613 if (IS_ERR(kbc->clk)) {
614 dev_err(&pdev->dev, "failed to get keyboard clock\n");
615 err = PTR_ERR(kbc->clk);
616 goto err_iounmap;
617 }
618
619 kbc->wake_enable_rows = 0;
620 kbc->wake_enable_cols = 0;
621 for (i = 0; i < pdata->wake_cnt; i++) {
622 kbc->wake_enable_rows |= (1 << pdata->wake_cfg[i].row);
623 kbc->wake_enable_cols |= (1 << pdata->wake_cfg[i].col);
624 }
625
626 /*
627 * The time delay between two consecutive reads of the FIFO is
628 * the sum of the repeat time and the time taken for scanning
629 * the rows. There is an additional delay before the row scanning
630 * starts. The repoll delay is computed in milliseconds.
631 */
632 debounce_cnt = min(pdata->debounce_cnt, KBC_MAX_DEBOUNCE_CNT);
633 scan_time_rows = (KBC_ROW_SCAN_TIME + debounce_cnt) * num_rows;
634 kbc->repoll_dly = KBC_ROW_SCAN_DLY + scan_time_rows + pdata->repeat_cnt;
635 kbc->repoll_dly = ((kbc->repoll_dly * KBC_CYCLE_USEC) + 999) / 1000;
636
637 input_dev->name = pdev->name;
638 input_dev->id.bustype = BUS_HOST;
639 input_dev->dev.parent = &pdev->dev;
640 input_dev->open = tegra_kbc_open;
641 input_dev->close = tegra_kbc_close;
642
643 input_set_drvdata(input_dev, kbc);
644
645 input_dev->evbit[0] = BIT_MASK(EV_KEY);
646 input_set_capability(input_dev, EV_MSC, MSC_SCAN);
647
648 input_dev->keycode = kbc->keycode;
649 input_dev->keycodesize = sizeof(kbc->keycode[0]);
650 input_dev->keycodemax = KBC_MAX_KEY;
651 if (pdata->use_fn_map)
652 input_dev->keycodemax *= 2;
653
654 kbc->use_fn_map = pdata->use_fn_map;
655 keymap_data = pdata->keymap_data ?: &tegra_kbc_default_keymap_data;
656 matrix_keypad_build_keymap(keymap_data, KBC_ROW_SHIFT,
657 input_dev->keycode, input_dev->keybit);
658
659 err = request_irq(kbc->irq, tegra_kbc_isr, IRQF_TRIGGER_HIGH,
660 pdev->name, kbc);
661 if (err) {
662 dev_err(&pdev->dev, "failed to request keyboard IRQ\n");
663 goto err_put_clk;
664 }
665
666 disable_irq(kbc->irq);
667
668 err = input_register_device(kbc->idev);
669 if (err) {
670 dev_err(&pdev->dev, "failed to register input device\n");
671 goto err_free_irq;
672 }
673
674 platform_set_drvdata(pdev, kbc);
675 device_init_wakeup(&pdev->dev, pdata->wakeup);
676
677 return 0;
678
679 err_free_irq:
680 free_irq(kbc->irq, pdev);
681 err_put_clk:
682 clk_put(kbc->clk);
683 err_iounmap:
684 iounmap(kbc->mmio);
685 err_free_mem_region:
686 release_mem_region(res->start, resource_size(res));
687 err_free_mem:
688 input_free_device(kbc->idev);
689 kfree(kbc);
690
691 return err;
692 }
693
694 static int __devexit tegra_kbc_remove(struct platform_device *pdev)
695 {
696 struct tegra_kbc *kbc = platform_get_drvdata(pdev);
697 struct resource *res;
698
699 free_irq(kbc->irq, pdev);
700 clk_put(kbc->clk);
701
702 input_unregister_device(kbc->idev);
703 iounmap(kbc->mmio);
704 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
705 release_mem_region(res->start, resource_size(res));
706
707 kfree(kbc);
708
709 platform_set_drvdata(pdev, NULL);
710
711 return 0;
712 }
713
714 #ifdef CONFIG_PM_SLEEP
715 static int tegra_kbc_suspend(struct device *dev)
716 {
717 struct platform_device *pdev = to_platform_device(dev);
718 struct tegra_kbc *kbc = platform_get_drvdata(pdev);
719
720 if (device_may_wakeup(&pdev->dev)) {
721 tegra_kbc_setup_wakekeys(kbc, true);
722 enable_irq_wake(kbc->irq);
723 /* Forcefully clear the interrupt status */
724 writel(0x7, kbc->mmio + KBC_INT_0);
725 msleep(30);
726 } else {
727 mutex_lock(&kbc->idev->mutex);
728 if (kbc->idev->users)
729 tegra_kbc_stop(kbc);
730 mutex_unlock(&kbc->idev->mutex);
731 }
732
733 return 0;
734 }
735
736 static int tegra_kbc_resume(struct device *dev)
737 {
738 struct platform_device *pdev = to_platform_device(dev);
739 struct tegra_kbc *kbc = platform_get_drvdata(pdev);
740 int err = 0;
741
742 if (device_may_wakeup(&pdev->dev)) {
743 disable_irq_wake(kbc->irq);
744 tegra_kbc_setup_wakekeys(kbc, false);
745 } else {
746 mutex_lock(&kbc->idev->mutex);
747 if (kbc->idev->users)
748 err = tegra_kbc_start(kbc);
749 mutex_unlock(&kbc->idev->mutex);
750 }
751
752 return err;
753 }
754 #endif
755
756 static SIMPLE_DEV_PM_OPS(tegra_kbc_pm_ops, tegra_kbc_suspend, tegra_kbc_resume);
757
758 static struct platform_driver tegra_kbc_driver = {
759 .probe = tegra_kbc_probe,
760 .remove = __devexit_p(tegra_kbc_remove),
761 .driver = {
762 .name = "tegra-kbc",
763 .owner = THIS_MODULE,
764 .pm = &tegra_kbc_pm_ops,
765 },
766 };
767
768 static void __exit tegra_kbc_exit(void)
769 {
770 platform_driver_unregister(&tegra_kbc_driver);
771 }
772 module_exit(tegra_kbc_exit);
773
774 static int __init tegra_kbc_init(void)
775 {
776 return platform_driver_register(&tegra_kbc_driver);
777 }
778 module_init(tegra_kbc_init);
779
780 MODULE_LICENSE("GPL");
781 MODULE_AUTHOR("Rakesh Iyer <riyer@nvidia.com>");
782 MODULE_DESCRIPTION("Tegra matrix keyboard controller driver");
783 MODULE_ALIAS("platform:tegra-kbc");
CRIS linux kernel tree