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FRV: Use generic show_interrupts()
[cris-mirror.git] / drivers / media / video / em28xx / em28xx-core.c
blob44c63cbd6dda8da1dcdc1375c94db856e934b4d4
1 /*
2 em28xx-core.c - driver for Empia EM2800/EM2820/2840 USB video capture devices
3
4 Copyright (C) 2005 Ludovico Cavedon <cavedon@sssup.it>
5 Markus Rechberger <mrechberger@gmail.com>
6 Mauro Carvalho Chehab <mchehab@infradead.org>
7 Sascha Sommer <saschasommer@freenet.de>
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
23
24 #include <linux/init.h>
25 #include <linux/list.h>
26 #include <linux/module.h>
27 #include <linux/slab.h>
28 #include <linux/usb.h>
29 #include <linux/vmalloc.h>
30 #include <media/v4l2-common.h>
31
32 #include "em28xx.h"
33
34 /* #define ENABLE_DEBUG_ISOC_FRAMES */
35
36 static unsigned int core_debug;
37 module_param(core_debug, int, 0644);
38 MODULE_PARM_DESC(core_debug, "enable debug messages [core]");
39
40 #define em28xx_coredbg(fmt, arg...) do {\
41 if (core_debug) \
42 printk(KERN_INFO "%s %s :"fmt, \
43 dev->name, __func__ , ##arg); } while (0)
44
45 static unsigned int reg_debug;
46 module_param(reg_debug, int, 0644);
47 MODULE_PARM_DESC(reg_debug, "enable debug messages [URB reg]");
48
49 #define em28xx_regdbg(fmt, arg...) do {\
50 if (reg_debug) \
51 printk(KERN_INFO "%s %s :"fmt, \
52 dev->name, __func__ , ##arg); } while (0)
53
54 static int alt;
55 module_param(alt, int, 0644);
56 MODULE_PARM_DESC(alt, "alternate setting to use for video endpoint");
57
58 static unsigned int disable_vbi;
59 module_param(disable_vbi, int, 0644);
60 MODULE_PARM_DESC(disable_vbi, "disable vbi support");
61
62 /* FIXME */
63 #define em28xx_isocdbg(fmt, arg...) do {\
64 if (core_debug) \
65 printk(KERN_INFO "%s %s :"fmt, \
66 dev->name, __func__ , ##arg); } while (0)
67
68 /*
69 * em28xx_read_reg_req()
70 * reads data from the usb device specifying bRequest
71 */
72 int em28xx_read_reg_req_len(struct em28xx *dev, u8 req, u16 reg,
73 char *buf, int len)
74 {
75 int ret;
76 int pipe = usb_rcvctrlpipe(dev->udev, 0);
77
78 if (dev->state & DEV_DISCONNECTED)
79 return -ENODEV;
80
81 if (len > URB_MAX_CTRL_SIZE)
82 return -EINVAL;
83
84 if (reg_debug) {
85 printk(KERN_DEBUG "(pipe 0x%08x): "
86 "IN: %02x %02x %02x %02x %02x %02x %02x %02x ",
87 pipe,
88 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
89 req, 0, 0,
90 reg & 0xff, reg >> 8,
91 len & 0xff, len >> 8);
92 }
93
94 mutex_lock(&dev->ctrl_urb_lock);
95 ret = usb_control_msg(dev->udev, pipe, req,
96 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
97 0x0000, reg, dev->urb_buf, len, HZ);
98 if (ret < 0) {
99 if (reg_debug)
100 printk(" failed!\n");
101 mutex_unlock(&dev->ctrl_urb_lock);
102 return ret;
103 }
104
105 if (len)
106 memcpy(buf, dev->urb_buf, len);
107
108 mutex_unlock(&dev->ctrl_urb_lock);
109
110 if (reg_debug) {
111 int byte;
112
113 printk("<<<");
114 for (byte = 0; byte < len; byte++)
115 printk(" %02x", (unsigned char)buf[byte]);
116 printk("\n");
117 }
118
119 return ret;
120 }
121
122 /*
123 * em28xx_read_reg_req()
124 * reads data from the usb device specifying bRequest
125 */
126 int em28xx_read_reg_req(struct em28xx *dev, u8 req, u16 reg)
127 {
128 int ret;
129 u8 val;
130
131 ret = em28xx_read_reg_req_len(dev, req, reg, &val, 1);
132 if (ret < 0)
133 return ret;
134
135 return val;
136 }
137
138 int em28xx_read_reg(struct em28xx *dev, u16 reg)
139 {
140 return em28xx_read_reg_req(dev, USB_REQ_GET_STATUS, reg);
141 }
142
143 /*
144 * em28xx_write_regs_req()
145 * sends data to the usb device, specifying bRequest
146 */
147 int em28xx_write_regs_req(struct em28xx *dev, u8 req, u16 reg, char *buf,
148 int len)
149 {
150 int ret;
151 int pipe = usb_sndctrlpipe(dev->udev, 0);
152
153 if (dev->state & DEV_DISCONNECTED)
154 return -ENODEV;
155
156 if ((len < 1) || (len > URB_MAX_CTRL_SIZE))
157 return -EINVAL;
158
159 if (reg_debug) {
160 int byte;
161
162 printk(KERN_DEBUG "(pipe 0x%08x): "
163 "OUT: %02x %02x %02x %02x %02x %02x %02x %02x >>>",
164 pipe,
165 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
166 req, 0, 0,
167 reg & 0xff, reg >> 8,
168 len & 0xff, len >> 8);
169
170 for (byte = 0; byte < len; byte++)
171 printk(" %02x", (unsigned char)buf[byte]);
172 printk("\n");
173 }
174
175 mutex_lock(&dev->ctrl_urb_lock);
176 memcpy(dev->urb_buf, buf, len);
177 ret = usb_control_msg(dev->udev, pipe, req,
178 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
179 0x0000, reg, dev->urb_buf, len, HZ);
180 mutex_unlock(&dev->ctrl_urb_lock);
181
182 if (dev->wait_after_write)
183 msleep(dev->wait_after_write);
184
185 return ret;
186 }
187
188 int em28xx_write_regs(struct em28xx *dev, u16 reg, char *buf, int len)
189 {
190 int rc;
191
192 rc = em28xx_write_regs_req(dev, USB_REQ_GET_STATUS, reg, buf, len);
193
194 /* Stores GPO/GPIO values at the cache, if changed
195 Only write values should be stored, since input on a GPIO
196 register will return the input bits.
197 Not sure what happens on reading GPO register.
198 */
199 if (rc >= 0) {
200 if (reg == dev->reg_gpo_num)
201 dev->reg_gpo = buf[0];
202 else if (reg == dev->reg_gpio_num)
203 dev->reg_gpio = buf[0];
204 }
205
206 return rc;
207 }
208
209 /* Write a single register */
210 int em28xx_write_reg(struct em28xx *dev, u16 reg, u8 val)
211 {
212 return em28xx_write_regs(dev, reg, &val, 1);
213 }
214
215 /*
216 * em28xx_write_reg_bits()
217 * sets only some bits (specified by bitmask) of a register, by first reading
218 * the actual value
219 */
220 int em28xx_write_reg_bits(struct em28xx *dev, u16 reg, u8 val,
221 u8 bitmask)
222 {
223 int oldval;
224 u8 newval;
225
226 /* Uses cache for gpo/gpio registers */
227 if (reg == dev->reg_gpo_num)
228 oldval = dev->reg_gpo;
229 else if (reg == dev->reg_gpio_num)
230 oldval = dev->reg_gpio;
231 else
232 oldval = em28xx_read_reg(dev, reg);
233
234 if (oldval < 0)
235 return oldval;
236
237 newval = (((u8) oldval) & ~bitmask) | (val & bitmask);
238
239 return em28xx_write_regs(dev, reg, &newval, 1);
240 }
241
242 /*
243 * em28xx_is_ac97_ready()
244 * Checks if ac97 is ready
245 */
246 static int em28xx_is_ac97_ready(struct em28xx *dev)
247 {
248 int ret, i;
249
250 /* Wait up to 50 ms for AC97 command to complete */
251 for (i = 0; i < 10; i++, msleep(5)) {
252 ret = em28xx_read_reg(dev, EM28XX_R43_AC97BUSY);
253 if (ret < 0)
254 return ret;
255
256 if (!(ret & 0x01))
257 return 0;
258 }
259
260 em28xx_warn("AC97 command still being executed: not handled properly!\n");
261 return -EBUSY;
262 }
263
264 /*
265 * em28xx_read_ac97()
266 * write a 16 bit value to the specified AC97 address (LSB first!)
267 */
268 int em28xx_read_ac97(struct em28xx *dev, u8 reg)
269 {
270 int ret;
271 u8 addr = (reg & 0x7f) | 0x80;
272 u16 val;
273
274 ret = em28xx_is_ac97_ready(dev);
275 if (ret < 0)
276 return ret;
277
278 ret = em28xx_write_regs(dev, EM28XX_R42_AC97ADDR, &addr, 1);
279 if (ret < 0)
280 return ret;
281
282 ret = dev->em28xx_read_reg_req_len(dev, 0, EM28XX_R40_AC97LSB,
283 (u8 *)&val, sizeof(val));
284
285 if (ret < 0)
286 return ret;
287 return le16_to_cpu(val);
288 }
289
290 /*
291 * em28xx_write_ac97()
292 * write a 16 bit value to the specified AC97 address (LSB first!)
293 */
294 int em28xx_write_ac97(struct em28xx *dev, u8 reg, u16 val)
295 {
296 int ret;
297 u8 addr = reg & 0x7f;
298 __le16 value;
299
300 value = cpu_to_le16(val);
301
302 ret = em28xx_is_ac97_ready(dev);
303 if (ret < 0)
304 return ret;
305
306 ret = em28xx_write_regs(dev, EM28XX_R40_AC97LSB, (u8 *) &value, 2);
307 if (ret < 0)
308 return ret;
309
310 ret = em28xx_write_regs(dev, EM28XX_R42_AC97ADDR, &addr, 1);
311 if (ret < 0)
312 return ret;
313
314 return 0;
315 }
316
317 struct em28xx_vol_table {
318 enum em28xx_amux mux;
319 u8 reg;
320 };
321
322 static struct em28xx_vol_table inputs[] = {
323 { EM28XX_AMUX_VIDEO, AC97_VIDEO_VOL },
324 { EM28XX_AMUX_LINE_IN, AC97_LINEIN_VOL },
325 { EM28XX_AMUX_PHONE, AC97_PHONE_VOL },
326 { EM28XX_AMUX_MIC, AC97_MIC_VOL },
327 { EM28XX_AMUX_CD, AC97_CD_VOL },
328 { EM28XX_AMUX_AUX, AC97_AUX_VOL },
329 { EM28XX_AMUX_PCM_OUT, AC97_PCM_OUT_VOL },
330 };
331
332 static int set_ac97_input(struct em28xx *dev)
333 {
334 int ret, i;
335 enum em28xx_amux amux = dev->ctl_ainput;
336
337 /* EM28XX_AMUX_VIDEO2 is a special case used to indicate that
338 em28xx should point to LINE IN, while AC97 should use VIDEO
339 */
340 if (amux == EM28XX_AMUX_VIDEO2)
341 amux = EM28XX_AMUX_VIDEO;
342
343 /* Mute all entres but the one that were selected */
344 for (i = 0; i < ARRAY_SIZE(inputs); i++) {
345 if (amux == inputs[i].mux)
346 ret = em28xx_write_ac97(dev, inputs[i].reg, 0x0808);
347 else
348 ret = em28xx_write_ac97(dev, inputs[i].reg, 0x8000);
349
350 if (ret < 0)
351 em28xx_warn("couldn't setup AC97 register %d\n",
352 inputs[i].reg);
353 }
354 return 0;
355 }
356
357 static int em28xx_set_audio_source(struct em28xx *dev)
358 {
359 int ret;
360 u8 input;
361
362 if (dev->board.is_em2800) {
363 if (dev->ctl_ainput == EM28XX_AMUX_VIDEO)
364 input = EM2800_AUDIO_SRC_TUNER;
365 else
366 input = EM2800_AUDIO_SRC_LINE;
367
368 ret = em28xx_write_regs(dev, EM2800_R08_AUDIOSRC, &input, 1);
369 if (ret < 0)
370 return ret;
371 }
372
373 if (dev->board.has_msp34xx)
374 input = EM28XX_AUDIO_SRC_TUNER;
375 else {
376 switch (dev->ctl_ainput) {
377 case EM28XX_AMUX_VIDEO:
378 input = EM28XX_AUDIO_SRC_TUNER;
379 break;
380 default:
381 input = EM28XX_AUDIO_SRC_LINE;
382 break;
383 }
384 }
385
386 if (dev->board.mute_gpio && dev->mute)
387 em28xx_gpio_set(dev, dev->board.mute_gpio);
388 else
389 em28xx_gpio_set(dev, INPUT(dev->ctl_input)->gpio);
390
391 ret = em28xx_write_reg_bits(dev, EM28XX_R0E_AUDIOSRC, input, 0xc0);
392 if (ret < 0)
393 return ret;
394 msleep(5);
395
396 switch (dev->audio_mode.ac97) {
397 case EM28XX_NO_AC97:
398 break;
399 default:
400 ret = set_ac97_input(dev);
401 }
402
403 return ret;
404 }
405
406 static const struct em28xx_vol_table outputs[] = {
407 { EM28XX_AOUT_MASTER, AC97_MASTER_VOL },
408 { EM28XX_AOUT_LINE, AC97_LINE_LEVEL_VOL },
409 { EM28XX_AOUT_MONO, AC97_MASTER_MONO_VOL },
410 { EM28XX_AOUT_LFE, AC97_LFE_MASTER_VOL },
411 { EM28XX_AOUT_SURR, AC97_SURR_MASTER_VOL },
412 };
413
414 int em28xx_audio_analog_set(struct em28xx *dev)
415 {
416 int ret, i;
417 u8 xclk;
418
419 if (!dev->audio_mode.has_audio)
420 return 0;
421
422 /* It is assumed that all devices use master volume for output.
423 It would be possible to use also line output.
424 */
425 if (dev->audio_mode.ac97 != EM28XX_NO_AC97) {
426 /* Mute all outputs */
427 for (i = 0; i < ARRAY_SIZE(outputs); i++) {
428 ret = em28xx_write_ac97(dev, outputs[i].reg, 0x8000);
429 if (ret < 0)
430 em28xx_warn("couldn't setup AC97 register %d\n",
431 outputs[i].reg);
432 }
433 }
434
435 xclk = dev->board.xclk & 0x7f;
436 if (!dev->mute)
437 xclk |= EM28XX_XCLK_AUDIO_UNMUTE;
438
439 ret = em28xx_write_reg(dev, EM28XX_R0F_XCLK, xclk);
440 if (ret < 0)
441 return ret;
442 msleep(10);
443
444 /* Selects the proper audio input */
445 ret = em28xx_set_audio_source(dev);
446
447 /* Sets volume */
448 if (dev->audio_mode.ac97 != EM28XX_NO_AC97) {
449 int vol;
450
451 em28xx_write_ac97(dev, AC97_POWER_DOWN_CTRL, 0x4200);
452 em28xx_write_ac97(dev, AC97_EXT_AUD_CTRL, 0x0031);
453 em28xx_write_ac97(dev, AC97_PCM_IN_SRATE, 0xbb80);
454
455 /* LSB: left channel - both channels with the same level */
456 vol = (0x1f - dev->volume) | ((0x1f - dev->volume) << 8);
457
458 /* Mute device, if needed */
459 if (dev->mute)
460 vol |= 0x8000;
461
462 /* Sets volume */
463 for (i = 0; i < ARRAY_SIZE(outputs); i++) {
464 if (dev->ctl_aoutput & outputs[i].mux)
465 ret = em28xx_write_ac97(dev, outputs[i].reg,
466 vol);
467 if (ret < 0)
468 em28xx_warn("couldn't setup AC97 register %d\n",
469 outputs[i].reg);
470 }
471
472 if (dev->ctl_aoutput & EM28XX_AOUT_PCM_IN) {
473 int sel = ac97_return_record_select(dev->ctl_aoutput);
474
475 /* Use the same input for both left and right
476 channels */
477 sel |= (sel << 8);
478
479 em28xx_write_ac97(dev, AC97_RECORD_SELECT, sel);
480 }
481 }
482
483 return ret;
484 }
485 EXPORT_SYMBOL_GPL(em28xx_audio_analog_set);
486
487 int em28xx_audio_setup(struct em28xx *dev)
488 {
489 int vid1, vid2, feat, cfg;
490 u32 vid;
491
492 if (dev->chip_id == CHIP_ID_EM2870 || dev->chip_id == CHIP_ID_EM2874) {
493 /* Digital only device - don't load any alsa module */
494 dev->audio_mode.has_audio = 0;
495 dev->has_audio_class = 0;
496 dev->has_alsa_audio = 0;
497 return 0;
498 }
499
500 /* If device doesn't support Usb Audio Class, use vendor class */
501 if (!dev->has_audio_class)
502 dev->has_alsa_audio = 1;
503
504 dev->audio_mode.has_audio = 1;
505
506 /* See how this device is configured */
507 cfg = em28xx_read_reg(dev, EM28XX_R00_CHIPCFG);
508 em28xx_info("Config register raw data: 0x%02x\n", cfg);
509 if (cfg < 0) {
510 /* Register read error? */
511 cfg = EM28XX_CHIPCFG_AC97; /* Be conservative */
512 } else if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) == 0x00) {
513 /* The device doesn't have vendor audio at all */
514 dev->has_alsa_audio = 0;
515 dev->audio_mode.has_audio = 0;
516 return 0;
517 } else if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) ==
518 EM28XX_CHIPCFG_I2S_3_SAMPRATES) {
519 em28xx_info("I2S Audio (3 sample rates)\n");
520 dev->audio_mode.i2s_3rates = 1;
521 } else if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) ==
522 EM28XX_CHIPCFG_I2S_5_SAMPRATES) {
523 em28xx_info("I2S Audio (5 sample rates)\n");
524 dev->audio_mode.i2s_5rates = 1;
525 }
526
527 if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) != EM28XX_CHIPCFG_AC97) {
528 /* Skip the code that does AC97 vendor detection */
529 dev->audio_mode.ac97 = EM28XX_NO_AC97;
530 goto init_audio;
531 }
532
533 dev->audio_mode.ac97 = EM28XX_AC97_OTHER;
534
535 vid1 = em28xx_read_ac97(dev, AC97_VENDOR_ID1);
536 if (vid1 < 0) {
537 /*
538 * Device likely doesn't support AC97
539 * Note: (some) em2800 devices without eeprom reports 0x91 on
540 * CHIPCFG register, even not having an AC97 chip
541 */
542 em28xx_warn("AC97 chip type couldn't be determined\n");
543 dev->audio_mode.ac97 = EM28XX_NO_AC97;
544 dev->has_alsa_audio = 0;
545 dev->audio_mode.has_audio = 0;
546 goto init_audio;
547 }
548
549 vid2 = em28xx_read_ac97(dev, AC97_VENDOR_ID2);
550 if (vid2 < 0)
551 goto init_audio;
552
553 vid = vid1 << 16 | vid2;
554
555 dev->audio_mode.ac97_vendor_id = vid;
556 em28xx_warn("AC97 vendor ID = 0x%08x\n", vid);
557
558 feat = em28xx_read_ac97(dev, AC97_RESET);
559 if (feat < 0)
560 goto init_audio;
561
562 dev->audio_mode.ac97_feat = feat;
563 em28xx_warn("AC97 features = 0x%04x\n", feat);
564
565 /* Try to identify what audio processor we have */
566 if ((vid == 0xffffffff) && (feat == 0x6a90))
567 dev->audio_mode.ac97 = EM28XX_AC97_EM202;
568 else if ((vid >> 8) == 0x838476)
569 dev->audio_mode.ac97 = EM28XX_AC97_SIGMATEL;
570
571 init_audio:
572 /* Reports detected AC97 processor */
573 switch (dev->audio_mode.ac97) {
574 case EM28XX_NO_AC97:
575 em28xx_info("No AC97 audio processor\n");
576 break;
577 case EM28XX_AC97_EM202:
578 em28xx_info("Empia 202 AC97 audio processor detected\n");
579 break;
580 case EM28XX_AC97_SIGMATEL:
581 em28xx_info("Sigmatel audio processor detected(stac 97%02x)\n",
582 dev->audio_mode.ac97_vendor_id & 0xff);
583 break;
584 case EM28XX_AC97_OTHER:
585 em28xx_warn("Unknown AC97 audio processor detected!\n");
586 break;
587 default:
588 break;
589 }
590
591 return em28xx_audio_analog_set(dev);
592 }
593 EXPORT_SYMBOL_GPL(em28xx_audio_setup);
594
595 int em28xx_colorlevels_set_default(struct em28xx *dev)
596 {
597 em28xx_write_reg(dev, EM28XX_R20_YGAIN, 0x10); /* contrast */
598 em28xx_write_reg(dev, EM28XX_R21_YOFFSET, 0x00); /* brightness */
599 em28xx_write_reg(dev, EM28XX_R22_UVGAIN, 0x10); /* saturation */
600 em28xx_write_reg(dev, EM28XX_R23_UOFFSET, 0x00);
601 em28xx_write_reg(dev, EM28XX_R24_VOFFSET, 0x00);
602 em28xx_write_reg(dev, EM28XX_R25_SHARPNESS, 0x00);
603
604 em28xx_write_reg(dev, EM28XX_R14_GAMMA, 0x20);
605 em28xx_write_reg(dev, EM28XX_R15_RGAIN, 0x20);
606 em28xx_write_reg(dev, EM28XX_R16_GGAIN, 0x20);
607 em28xx_write_reg(dev, EM28XX_R17_BGAIN, 0x20);
608 em28xx_write_reg(dev, EM28XX_R18_ROFFSET, 0x00);
609 em28xx_write_reg(dev, EM28XX_R19_GOFFSET, 0x00);
610 return em28xx_write_reg(dev, EM28XX_R1A_BOFFSET, 0x00);
611 }
612
613 int em28xx_capture_start(struct em28xx *dev, int start)
614 {
615 int rc;
616
617 if (dev->chip_id == CHIP_ID_EM2874) {
618 /* The Transport Stream Enable Register moved in em2874 */
619 if (!start) {
620 rc = em28xx_write_reg_bits(dev, EM2874_R5F_TS_ENABLE,
621 0x00,
622 EM2874_TS1_CAPTURE_ENABLE);
623 return rc;
624 }
625
626 /* Enable Transport Stream */
627 rc = em28xx_write_reg_bits(dev, EM2874_R5F_TS_ENABLE,
628 EM2874_TS1_CAPTURE_ENABLE,
629 EM2874_TS1_CAPTURE_ENABLE);
630 return rc;
631 }
632
633
634 /* FIXME: which is the best order? */
635 /* video registers are sampled by VREF */
636 rc = em28xx_write_reg_bits(dev, EM28XX_R0C_USBSUSP,
637 start ? 0x10 : 0x00, 0x10);
638 if (rc < 0)
639 return rc;
640
641 if (!start) {
642 /* disable video capture */
643 rc = em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x27);
644 return rc;
645 }
646
647 if (dev->board.is_webcam)
648 rc = em28xx_write_reg(dev, 0x13, 0x0c);
649
650 /* enable video capture */
651 rc = em28xx_write_reg(dev, 0x48, 0x00);
652
653 if (dev->mode == EM28XX_ANALOG_MODE)
654 rc = em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x67);
655 else
656 rc = em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x37);
657
658 msleep(6);
659
660 return rc;
661 }
662
663 int em28xx_vbi_supported(struct em28xx *dev)
664 {
665 /* Modprobe option to manually disable */
666 if (disable_vbi == 1)
667 return 0;
668
669 if (dev->chip_id == CHIP_ID_EM2860 ||
670 dev->chip_id == CHIP_ID_EM2883)
671 return 1;
672
673 /* Version of em28xx that does not support VBI */
674 return 0;
675 }
676
677 int em28xx_set_outfmt(struct em28xx *dev)
678 {
679 int ret;
680 u8 vinctrl;
681
682 ret = em28xx_write_reg_bits(dev, EM28XX_R27_OUTFMT,
683 dev->format->reg | 0x20, 0xff);
684 if (ret < 0)
685 return ret;
686
687 ret = em28xx_write_reg(dev, EM28XX_R10_VINMODE, dev->vinmode);
688 if (ret < 0)
689 return ret;
690
691 vinctrl = dev->vinctl;
692 if (em28xx_vbi_supported(dev) == 1) {
693 vinctrl |= EM28XX_VINCTRL_VBI_RAW;
694 em28xx_write_reg(dev, EM28XX_R34_VBI_START_H, 0x00);
695 em28xx_write_reg(dev, EM28XX_R36_VBI_WIDTH, dev->vbi_width/4);
696 em28xx_write_reg(dev, EM28XX_R37_VBI_HEIGHT, dev->vbi_height);
697 if (dev->norm & V4L2_STD_525_60) {
698 /* NTSC */
699 em28xx_write_reg(dev, EM28XX_R35_VBI_START_V, 0x09);
700 } else if (dev->norm & V4L2_STD_625_50) {
701 /* PAL */
702 em28xx_write_reg(dev, EM28XX_R35_VBI_START_V, 0x07);
703 }
704 }
705
706 return em28xx_write_reg(dev, EM28XX_R11_VINCTRL, vinctrl);
707 }
708
709 static int em28xx_accumulator_set(struct em28xx *dev, u8 xmin, u8 xmax,
710 u8 ymin, u8 ymax)
711 {
712 em28xx_coredbg("em28xx Scale: (%d,%d)-(%d,%d)\n",
713 xmin, ymin, xmax, ymax);
714
715 em28xx_write_regs(dev, EM28XX_R28_XMIN, &xmin, 1);
716 em28xx_write_regs(dev, EM28XX_R29_XMAX, &xmax, 1);
717 em28xx_write_regs(dev, EM28XX_R2A_YMIN, &ymin, 1);
718 return em28xx_write_regs(dev, EM28XX_R2B_YMAX, &ymax, 1);
719 }
720
721 static int em28xx_capture_area_set(struct em28xx *dev, u8 hstart, u8 vstart,
722 u16 width, u16 height)
723 {
724 u8 cwidth = width;
725 u8 cheight = height;
726 u8 overflow = (height >> 7 & 0x02) | (width >> 8 & 0x01);
727
728 em28xx_coredbg("em28xx Area Set: (%d,%d)\n",
729 (width | (overflow & 2) << 7),
730 (height | (overflow & 1) << 8));
731
732 em28xx_write_regs(dev, EM28XX_R1C_HSTART, &hstart, 1);
733 em28xx_write_regs(dev, EM28XX_R1D_VSTART, &vstart, 1);
734 em28xx_write_regs(dev, EM28XX_R1E_CWIDTH, &cwidth, 1);
735 em28xx_write_regs(dev, EM28XX_R1F_CHEIGHT, &cheight, 1);
736 return em28xx_write_regs(dev, EM28XX_R1B_OFLOW, &overflow, 1);
737 }
738
739 static int em28xx_scaler_set(struct em28xx *dev, u16 h, u16 v)
740 {
741 u8 mode;
742 /* the em2800 scaler only supports scaling down to 50% */
743
744 if (dev->board.is_em2800) {
745 mode = (v ? 0x20 : 0x00) | (h ? 0x10 : 0x00);
746 } else {
747 u8 buf[2];
748
749 buf[0] = h;
750 buf[1] = h >> 8;
751 em28xx_write_regs(dev, EM28XX_R30_HSCALELOW, (char *)buf, 2);
752
753 buf[0] = v;
754 buf[1] = v >> 8;
755 em28xx_write_regs(dev, EM28XX_R32_VSCALELOW, (char *)buf, 2);
756 /* it seems that both H and V scalers must be active
757 to work correctly */
758 mode = (h || v) ? 0x30 : 0x00;
759 }
760 return em28xx_write_reg_bits(dev, EM28XX_R26_COMPR, mode, 0x30);
761 }
762
763 /* FIXME: this only function read values from dev */
764 int em28xx_resolution_set(struct em28xx *dev)
765 {
766 int width, height;
767 width = norm_maxw(dev);
768 height = norm_maxh(dev);
769
770 /* Properly setup VBI */
771 dev->vbi_width = 720;
772 if (dev->norm & V4L2_STD_525_60)
773 dev->vbi_height = 12;
774 else
775 dev->vbi_height = 18;
776
777 if (!dev->progressive)
778 height >>= norm_maxh(dev);
779
780 em28xx_set_outfmt(dev);
781
782
783 em28xx_accumulator_set(dev, 1, (width - 4) >> 2, 1, (height - 4) >> 2);
784
785 /* If we don't set the start position to 2 in VBI mode, we end up
786 with line 20/21 being YUYV encoded instead of being in 8-bit
787 greyscale. The core of the issue is that line 21 (and line 23 for
788 PAL WSS) are inside of active video region, and as a result they
789 get the pixelformatting associated with that area. So by cropping
790 it out, we end up with the same format as the rest of the VBI
791 region */
792 if (em28xx_vbi_supported(dev) == 1)
793 em28xx_capture_area_set(dev, 0, 2, width >> 2, height >> 2);
794 else
795 em28xx_capture_area_set(dev, 0, 0, width >> 2, height >> 2);
796
797 return em28xx_scaler_set(dev, dev->hscale, dev->vscale);
798 }
799
800 int em28xx_set_alternate(struct em28xx *dev)
801 {
802 int errCode, prev_alt = dev->alt;
803 int i;
804 unsigned int min_pkt_size = dev->width * 2 + 4;
805
806 /*
807 * alt = 0 is used only for control messages, so, only values
808 * greater than 0 can be used for streaming.
809 */
810 if (alt && alt < dev->num_alt) {
811 em28xx_coredbg("alternate forced to %d\n", dev->alt);
812 dev->alt = alt;
813 goto set_alt;
814 }
815
816 /* When image size is bigger than a certain value,
817 the frame size should be increased, otherwise, only
818 green screen will be received.
819 */
820 if (dev->width * 2 * dev->height > 720 * 240 * 2)
821 min_pkt_size *= 2;
822
823 for (i = 0; i < dev->num_alt; i++) {
824 /* stop when the selected alt setting offers enough bandwidth */
825 if (dev->alt_max_pkt_size[i] >= min_pkt_size) {
826 dev->alt = i;
827 break;
828 /* otherwise make sure that we end up with the maximum bandwidth
829 because the min_pkt_size equation might be wrong...
830 */
831 } else if (dev->alt_max_pkt_size[i] >
832 dev->alt_max_pkt_size[dev->alt])
833 dev->alt = i;
834 }
835
836 set_alt:
837 if (dev->alt != prev_alt) {
838 em28xx_coredbg("minimum isoc packet size: %u (alt=%d)\n",
839 min_pkt_size, dev->alt);
840 dev->max_pkt_size = dev->alt_max_pkt_size[dev->alt];
841 em28xx_coredbg("setting alternate %d with wMaxPacketSize=%u\n",
842 dev->alt, dev->max_pkt_size);
843 errCode = usb_set_interface(dev->udev, 0, dev->alt);
844 if (errCode < 0) {
845 em28xx_errdev("cannot change alternate number to %d (error=%i)\n",
846 dev->alt, errCode);
847 return errCode;
848 }
849 }
850 return 0;
851 }
852
853 int em28xx_gpio_set(struct em28xx *dev, struct em28xx_reg_seq *gpio)
854 {
855 int rc = 0;
856
857 if (!gpio)
858 return rc;
859
860 if (dev->mode != EM28XX_SUSPEND) {
861 em28xx_write_reg(dev, 0x48, 0x00);
862 if (dev->mode == EM28XX_ANALOG_MODE)
863 em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x67);
864 else
865 em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x37);
866 msleep(6);
867 }
868
869 /* Send GPIO reset sequences specified at board entry */
870 while (gpio->sleep >= 0) {
871 if (gpio->reg >= 0) {
872 rc = em28xx_write_reg_bits(dev,
873 gpio->reg,
874 gpio->val,
875 gpio->mask);
876 if (rc < 0)
877 return rc;
878 }
879 if (gpio->sleep > 0)
880 msleep(gpio->sleep);
881
882 gpio++;
883 }
884 return rc;
885 }
886
887 int em28xx_set_mode(struct em28xx *dev, enum em28xx_mode set_mode)
888 {
889 if (dev->mode == set_mode)
890 return 0;
891
892 if (set_mode == EM28XX_SUSPEND) {
893 dev->mode = set_mode;
894
895 /* FIXME: add suspend support for ac97 */
896
897 return em28xx_gpio_set(dev, dev->board.suspend_gpio);
898 }
899
900 dev->mode = set_mode;
901
902 if (dev->mode == EM28XX_DIGITAL_MODE)
903 return em28xx_gpio_set(dev, dev->board.dvb_gpio);
904 else
905 return em28xx_gpio_set(dev, INPUT(dev->ctl_input)->gpio);
906 }
907 EXPORT_SYMBOL_GPL(em28xx_set_mode);
908
909 /* ------------------------------------------------------------------
910 URB control
911 ------------------------------------------------------------------*/
912
913 /*
914 * IRQ callback, called by URB callback
915 */
916 static void em28xx_irq_callback(struct urb *urb)
917 {
918 struct em28xx *dev = urb->context;
919 int rc, i;
920
921 switch (urb->status) {
922 case 0: /* success */
923 case -ETIMEDOUT: /* NAK */
924 break;
925 case -ECONNRESET: /* kill */
926 case -ENOENT:
927 case -ESHUTDOWN:
928 return;
929 default: /* error */
930 em28xx_isocdbg("urb completition error %d.\n", urb->status);
931 break;
932 }
933
934 /* Copy data from URB */
935 spin_lock(&dev->slock);
936 rc = dev->isoc_ctl.isoc_copy(dev, urb);
937 spin_unlock(&dev->slock);
938
939 /* Reset urb buffers */
940 for (i = 0; i < urb->number_of_packets; i++) {
941 urb->iso_frame_desc[i].status = 0;
942 urb->iso_frame_desc[i].actual_length = 0;
943 }
944 urb->status = 0;
945
946 urb->status = usb_submit_urb(urb, GFP_ATOMIC);
947 if (urb->status) {
948 em28xx_isocdbg("urb resubmit failed (error=%i)\n",
949 urb->status);
950 }
951 }
952
953 /*
954 * Stop and Deallocate URBs
955 */
956 void em28xx_uninit_isoc(struct em28xx *dev)
957 {
958 struct urb *urb;
959 int i;
960
961 em28xx_isocdbg("em28xx: called em28xx_uninit_isoc\n");
962
963 dev->isoc_ctl.nfields = -1;
964 for (i = 0; i < dev->isoc_ctl.num_bufs; i++) {
965 urb = dev->isoc_ctl.urb[i];
966 if (urb) {
967 if (!irqs_disabled())
968 usb_kill_urb(urb);
969 else
970 usb_unlink_urb(urb);
971
972 if (dev->isoc_ctl.transfer_buffer[i]) {
973 usb_free_coherent(dev->udev,
974 urb->transfer_buffer_length,
975 dev->isoc_ctl.transfer_buffer[i],
976 urb->transfer_dma);
977 }
978 usb_free_urb(urb);
979 dev->isoc_ctl.urb[i] = NULL;
980 }
981 dev->isoc_ctl.transfer_buffer[i] = NULL;
982 }
983
984 kfree(dev->isoc_ctl.urb);
985 kfree(dev->isoc_ctl.transfer_buffer);
986
987 dev->isoc_ctl.urb = NULL;
988 dev->isoc_ctl.transfer_buffer = NULL;
989 dev->isoc_ctl.num_bufs = 0;
990
991 em28xx_capture_start(dev, 0);
992 }
993 EXPORT_SYMBOL_GPL(em28xx_uninit_isoc);
994
995 /*
996 * Allocate URBs and start IRQ
997 */
998 int em28xx_init_isoc(struct em28xx *dev, int max_packets,
999 int num_bufs, int max_pkt_size,
1000 int (*isoc_copy) (struct em28xx *dev, struct urb *urb))
1001 {
1002 struct em28xx_dmaqueue *dma_q = &dev->vidq;
1003 struct em28xx_dmaqueue *vbi_dma_q = &dev->vbiq;
1004 int i;
1005 int sb_size, pipe;
1006 struct urb *urb;
1007 int j, k;
1008 int rc;
1009
1010 em28xx_isocdbg("em28xx: called em28xx_prepare_isoc\n");
1011
1012 /* De-allocates all pending stuff */
1013 em28xx_uninit_isoc(dev);
1014
1015 dev->isoc_ctl.isoc_copy = isoc_copy;
1016 dev->isoc_ctl.num_bufs = num_bufs;
1017
1018 dev->isoc_ctl.urb = kzalloc(sizeof(void *)*num_bufs, GFP_KERNEL);
1019 if (!dev->isoc_ctl.urb) {
1020 em28xx_errdev("cannot alloc memory for usb buffers\n");
1021 return -ENOMEM;
1022 }
1023
1024 dev->isoc_ctl.transfer_buffer = kzalloc(sizeof(void *)*num_bufs,
1025 GFP_KERNEL);
1026 if (!dev->isoc_ctl.transfer_buffer) {
1027 em28xx_errdev("cannot allocate memory for usb transfer\n");
1028 kfree(dev->isoc_ctl.urb);
1029 return -ENOMEM;
1030 }
1031
1032 dev->isoc_ctl.max_pkt_size = max_pkt_size;
1033 dev->isoc_ctl.vid_buf = NULL;
1034 dev->isoc_ctl.vbi_buf = NULL;
1035
1036 sb_size = max_packets * dev->isoc_ctl.max_pkt_size;
1037
1038 /* allocate urbs and transfer buffers */
1039 for (i = 0; i < dev->isoc_ctl.num_bufs; i++) {
1040 urb = usb_alloc_urb(max_packets, GFP_KERNEL);
1041 if (!urb) {
1042 em28xx_err("cannot alloc isoc_ctl.urb %i\n", i);
1043 em28xx_uninit_isoc(dev);
1044 return -ENOMEM;
1045 }
1046 dev->isoc_ctl.urb[i] = urb;
1047
1048 dev->isoc_ctl.transfer_buffer[i] = usb_alloc_coherent(dev->udev,
1049 sb_size, GFP_KERNEL, &urb->transfer_dma);
1050 if (!dev->isoc_ctl.transfer_buffer[i]) {
1051 em28xx_err("unable to allocate %i bytes for transfer"
1052 " buffer %i%s\n",
1053 sb_size, i,
1054 in_interrupt() ? " while in int" : "");
1055 em28xx_uninit_isoc(dev);
1056 return -ENOMEM;
1057 }
1058 memset(dev->isoc_ctl.transfer_buffer[i], 0, sb_size);
1059
1060 /* FIXME: this is a hack - should be
1061 'desc.bEndpointAddress & USB_ENDPOINT_NUMBER_MASK'
1062 should also be using 'desc.bInterval'
1063 */
1064 pipe = usb_rcvisocpipe(dev->udev,
1065 dev->mode == EM28XX_ANALOG_MODE ? 0x82 : 0x84);
1066
1067 usb_fill_int_urb(urb, dev->udev, pipe,
1068 dev->isoc_ctl.transfer_buffer[i], sb_size,
1069 em28xx_irq_callback, dev, 1);
1070
1071 urb->number_of_packets = max_packets;
1072 urb->transfer_flags = URB_ISO_ASAP | URB_NO_TRANSFER_DMA_MAP;
1073
1074 k = 0;
1075 for (j = 0; j < max_packets; j++) {
1076 urb->iso_frame_desc[j].offset = k;
1077 urb->iso_frame_desc[j].length =
1078 dev->isoc_ctl.max_pkt_size;
1079 k += dev->isoc_ctl.max_pkt_size;
1080 }
1081 }
1082
1083 init_waitqueue_head(&dma_q->wq);
1084 init_waitqueue_head(&vbi_dma_q->wq);
1085
1086 em28xx_capture_start(dev, 1);
1087
1088 /* submit urbs and enables IRQ */
1089 for (i = 0; i < dev->isoc_ctl.num_bufs; i++) {
1090 rc = usb_submit_urb(dev->isoc_ctl.urb[i], GFP_ATOMIC);
1091 if (rc) {
1092 em28xx_err("submit of urb %i failed (error=%i)\n", i,
1093 rc);
1094 em28xx_uninit_isoc(dev);
1095 return rc;
1096 }
1097 }
1098
1099 return 0;
1100 }
1101 EXPORT_SYMBOL_GPL(em28xx_init_isoc);
1102
1103 /* Determine the packet size for the DVB stream for the given device
1104 (underlying value programmed into the eeprom) */
1105 int em28xx_isoc_dvb_max_packetsize(struct em28xx *dev)
1106 {
1107 unsigned int chip_cfg2;
1108 unsigned int packet_size = 564;
1109
1110 if (dev->chip_id == CHIP_ID_EM2874) {
1111 /* FIXME - for now assume 564 like it was before, but the
1112 em2874 code should be added to return the proper value... */
1113 packet_size = 564;
1114 } else {
1115 /* TS max packet size stored in bits 1-0 of R01 */
1116 chip_cfg2 = em28xx_read_reg(dev, EM28XX_R01_CHIPCFG2);
1117 switch (chip_cfg2 & EM28XX_CHIPCFG2_TS_PACKETSIZE_MASK) {
1118 case EM28XX_CHIPCFG2_TS_PACKETSIZE_188:
1119 packet_size = 188;
1120 break;
1121 case EM28XX_CHIPCFG2_TS_PACKETSIZE_376:
1122 packet_size = 376;
1123 break;
1124 case EM28XX_CHIPCFG2_TS_PACKETSIZE_564:
1125 packet_size = 564;
1126 break;
1127 case EM28XX_CHIPCFG2_TS_PACKETSIZE_752:
1128 packet_size = 752;
1129 break;
1130 }
1131 }
1132
1133 em28xx_coredbg("dvb max packet size=%d\n", packet_size);
1134 return packet_size;
1135 }
1136 EXPORT_SYMBOL_GPL(em28xx_isoc_dvb_max_packetsize);
1137
1138 /*
1139 * em28xx_wake_i2c()
1140 * configure i2c attached devices
1141 */
1142 void em28xx_wake_i2c(struct em28xx *dev)
1143 {
1144 v4l2_device_call_all(&dev->v4l2_dev, 0, core, reset, 0);
1145 v4l2_device_call_all(&dev->v4l2_dev, 0, video, s_routing,
1146 INPUT(dev->ctl_input)->vmux, 0, 0);
1147 v4l2_device_call_all(&dev->v4l2_dev, 0, video, s_stream, 0);
1148 }
1149
1150 /*
1151 * Device control list
1152 */
1153
1154 static LIST_HEAD(em28xx_devlist);
1155 static DEFINE_MUTEX(em28xx_devlist_mutex);
1156
1157 /*
1158 * em28xx_realease_resources()
1159 * unregisters the v4l2,i2c and usb devices
1160 * called when the device gets disconected or at module unload
1161 */
1162 void em28xx_remove_from_devlist(struct em28xx *dev)
1163 {
1164 mutex_lock(&em28xx_devlist_mutex);
1165 list_del(&dev->devlist);
1166 mutex_unlock(&em28xx_devlist_mutex);
1167 };
1168
1169 void em28xx_add_into_devlist(struct em28xx *dev)
1170 {
1171 mutex_lock(&em28xx_devlist_mutex);
1172 list_add_tail(&dev->devlist, &em28xx_devlist);
1173 mutex_unlock(&em28xx_devlist_mutex);
1174 };
1175
1176 /*
1177 * Extension interface
1178 */
1179
1180 static LIST_HEAD(em28xx_extension_devlist);
1181
1182 int em28xx_register_extension(struct em28xx_ops *ops)
1183 {
1184 struct em28xx *dev = NULL;
1185
1186 mutex_lock(&em28xx_devlist_mutex);
1187 list_add_tail(&ops->next, &em28xx_extension_devlist);
1188 list_for_each_entry(dev, &em28xx_devlist, devlist) {
1189 ops->init(dev);
1190 }
1191 printk(KERN_INFO "Em28xx: Initialized (%s) extension\n", ops->name);
1192 mutex_unlock(&em28xx_devlist_mutex);
1193 return 0;
1194 }
1195 EXPORT_SYMBOL(em28xx_register_extension);
1196
1197 void em28xx_unregister_extension(struct em28xx_ops *ops)
1198 {
1199 struct em28xx *dev = NULL;
1200
1201 mutex_lock(&em28xx_devlist_mutex);
1202 list_for_each_entry(dev, &em28xx_devlist, devlist) {
1203 ops->fini(dev);
1204 }
1205 printk(KERN_INFO "Em28xx: Removed (%s) extension\n", ops->name);
1206 list_del(&ops->next);
1207 mutex_unlock(&em28xx_devlist_mutex);
1208 }
1209 EXPORT_SYMBOL(em28xx_unregister_extension);
1210
1211 void em28xx_init_extension(struct em28xx *dev)
1212 {
1213 struct em28xx_ops *ops = NULL;
1214
1215 mutex_lock(&em28xx_devlist_mutex);
1216 if (!list_empty(&em28xx_extension_devlist)) {
1217 list_for_each_entry(ops, &em28xx_extension_devlist, next) {
1218 if (ops->init)
1219 ops->init(dev);
1220 }
1221 }
1222 mutex_unlock(&em28xx_devlist_mutex);
1223 }
1224
1225 void em28xx_close_extension(struct em28xx *dev)
1226 {
1227 struct em28xx_ops *ops = NULL;
1228
1229 mutex_lock(&em28xx_devlist_mutex);
1230 if (!list_empty(&em28xx_extension_devlist)) {
1231 list_for_each_entry(ops, &em28xx_extension_devlist, next) {
1232 if (ops->fini)
1233 ops->fini(dev);
1234 }
1235 }
1236 mutex_unlock(&em28xx_devlist_mutex);
1237 }
CRIS linux kernel tree