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FRV: Use generic show_interrupts()
[cris-mirror.git] / drivers / media / video / omap3isp / ispccp2.c
blob0efef2e78d93a2474aeb48989bd317d363d47340
1 /*
2 * ispccp2.c
3 *
4 * TI OMAP3 ISP - CCP2 module
5 *
6 * Copyright (C) 2010 Nokia Corporation
7 * Copyright (C) 2010 Texas Instruments, Inc.
8 *
9 * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
10 * Sakari Ailus <sakari.ailus@iki.fi>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
24 * 02110-1301 USA
25 */
26
27 #include <linux/delay.h>
28 #include <linux/device.h>
29 #include <linux/mm.h>
30 #include <linux/module.h>
31 #include <linux/mutex.h>
32 #include <linux/uaccess.h>
33
34 #include "isp.h"
35 #include "ispreg.h"
36 #include "ispccp2.h"
37
38 /* Number of LCX channels */
39 #define CCP2_LCx_CHANS_NUM 3
40 /* Max/Min size for CCP2 video port */
41 #define ISPCCP2_DAT_START_MIN 0
42 #define ISPCCP2_DAT_START_MAX 4095
43 #define ISPCCP2_DAT_SIZE_MIN 0
44 #define ISPCCP2_DAT_SIZE_MAX 4095
45 #define ISPCCP2_VPCLK_FRACDIV 65536
46 #define ISPCCP2_LCx_CTRL_FORMAT_RAW8_DPCM10_VP 0x12
47 #define ISPCCP2_LCx_CTRL_FORMAT_RAW10_VP 0x16
48 /* Max/Min size for CCP2 memory channel */
49 #define ISPCCP2_LCM_HSIZE_COUNT_MIN 16
50 #define ISPCCP2_LCM_HSIZE_COUNT_MAX 8191
51 #define ISPCCP2_LCM_HSIZE_SKIP_MIN 0
52 #define ISPCCP2_LCM_HSIZE_SKIP_MAX 8191
53 #define ISPCCP2_LCM_VSIZE_MIN 1
54 #define ISPCCP2_LCM_VSIZE_MAX 8191
55 #define ISPCCP2_LCM_HWORDS_MIN 1
56 #define ISPCCP2_LCM_HWORDS_MAX 4095
57 #define ISPCCP2_LCM_CTRL_BURST_SIZE_32X 5
58 #define ISPCCP2_LCM_CTRL_READ_THROTTLE_FULL 0
59 #define ISPCCP2_LCM_CTRL_SRC_DECOMPR_DPCM10 2
60 #define ISPCCP2_LCM_CTRL_SRC_FORMAT_RAW8 2
61 #define ISPCCP2_LCM_CTRL_SRC_FORMAT_RAW10 3
62 #define ISPCCP2_LCM_CTRL_DST_FORMAT_RAW10 3
63 #define ISPCCP2_LCM_CTRL_DST_PORT_VP 0
64 #define ISPCCP2_LCM_CTRL_DST_PORT_MEM 1
65
66 /* Set only the required bits */
67 #define BIT_SET(var, shift, mask, val) \
68 do { \
69 var = ((var) & ~((mask) << (shift))) \
70 | ((val) << (shift)); \
71 } while (0)
72
73 /*
74 * ccp2_print_status - Print current CCP2 module register values.
75 */
76 #define CCP2_PRINT_REGISTER(isp, name)\
77 dev_dbg(isp->dev, "###CCP2 " #name "=0x%08x\n", \
78 isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_##name))
79
80 static void ccp2_print_status(struct isp_ccp2_device *ccp2)
81 {
82 struct isp_device *isp = to_isp_device(ccp2);
83
84 dev_dbg(isp->dev, "-------------CCP2 Register dump-------------\n");
85
86 CCP2_PRINT_REGISTER(isp, SYSCONFIG);
87 CCP2_PRINT_REGISTER(isp, SYSSTATUS);
88 CCP2_PRINT_REGISTER(isp, LC01_IRQENABLE);
89 CCP2_PRINT_REGISTER(isp, LC01_IRQSTATUS);
90 CCP2_PRINT_REGISTER(isp, LC23_IRQENABLE);
91 CCP2_PRINT_REGISTER(isp, LC23_IRQSTATUS);
92 CCP2_PRINT_REGISTER(isp, LCM_IRQENABLE);
93 CCP2_PRINT_REGISTER(isp, LCM_IRQSTATUS);
94 CCP2_PRINT_REGISTER(isp, CTRL);
95 CCP2_PRINT_REGISTER(isp, LCx_CTRL(0));
96 CCP2_PRINT_REGISTER(isp, LCx_CODE(0));
97 CCP2_PRINT_REGISTER(isp, LCx_STAT_START(0));
98 CCP2_PRINT_REGISTER(isp, LCx_STAT_SIZE(0));
99 CCP2_PRINT_REGISTER(isp, LCx_SOF_ADDR(0));
100 CCP2_PRINT_REGISTER(isp, LCx_EOF_ADDR(0));
101 CCP2_PRINT_REGISTER(isp, LCx_DAT_START(0));
102 CCP2_PRINT_REGISTER(isp, LCx_DAT_SIZE(0));
103 CCP2_PRINT_REGISTER(isp, LCx_DAT_PING_ADDR(0));
104 CCP2_PRINT_REGISTER(isp, LCx_DAT_PONG_ADDR(0));
105 CCP2_PRINT_REGISTER(isp, LCx_DAT_OFST(0));
106 CCP2_PRINT_REGISTER(isp, LCM_CTRL);
107 CCP2_PRINT_REGISTER(isp, LCM_VSIZE);
108 CCP2_PRINT_REGISTER(isp, LCM_HSIZE);
109 CCP2_PRINT_REGISTER(isp, LCM_PREFETCH);
110 CCP2_PRINT_REGISTER(isp, LCM_SRC_ADDR);
111 CCP2_PRINT_REGISTER(isp, LCM_SRC_OFST);
112 CCP2_PRINT_REGISTER(isp, LCM_DST_ADDR);
113 CCP2_PRINT_REGISTER(isp, LCM_DST_OFST);
114
115 dev_dbg(isp->dev, "--------------------------------------------\n");
116 }
117
118 /*
119 * ccp2_reset - Reset the CCP2
120 * @ccp2: pointer to ISP CCP2 device
121 */
122 static void ccp2_reset(struct isp_ccp2_device *ccp2)
123 {
124 struct isp_device *isp = to_isp_device(ccp2);
125 int i = 0;
126
127 /* Reset the CSI1/CCP2B and wait for reset to complete */
128 isp_reg_set(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_SYSCONFIG,
129 ISPCCP2_SYSCONFIG_SOFT_RESET);
130 while (!(isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_SYSSTATUS) &
131 ISPCCP2_SYSSTATUS_RESET_DONE)) {
132 udelay(10);
133 if (i++ > 10) { /* try read 10 times */
134 dev_warn(isp->dev,
135 "omap3_isp: timeout waiting for ccp2 reset\n");
136 break;
137 }
138 }
139 }
140
141 /*
142 * ccp2_pwr_cfg - Configure the power mode settings
143 * @ccp2: pointer to ISP CCP2 device
144 */
145 static void ccp2_pwr_cfg(struct isp_ccp2_device *ccp2)
146 {
147 struct isp_device *isp = to_isp_device(ccp2);
148
149 isp_reg_writel(isp, ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SMART |
150 ((isp->revision == ISP_REVISION_15_0 && isp->autoidle) ?
151 ISPCCP2_SYSCONFIG_AUTO_IDLE : 0),
152 OMAP3_ISP_IOMEM_CCP2, ISPCCP2_SYSCONFIG);
153 }
154
155 /*
156 * ccp2_if_enable - Enable CCP2 interface.
157 * @ccp2: pointer to ISP CCP2 device
158 * @enable: enable/disable flag
159 */
160 static void ccp2_if_enable(struct isp_ccp2_device *ccp2, u8 enable)
161 {
162 struct isp_device *isp = to_isp_device(ccp2);
163 struct isp_pipeline *pipe = to_isp_pipeline(&ccp2->subdev.entity);
164 int i;
165
166 /* Enable/Disable all the LCx channels */
167 for (i = 0; i < CCP2_LCx_CHANS_NUM; i++)
168 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCx_CTRL(i),
169 ISPCCP2_LCx_CTRL_CHAN_EN,
170 enable ? ISPCCP2_LCx_CTRL_CHAN_EN : 0);
171
172 /* Enable/Disable ccp2 interface in ccp2 mode */
173 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL,
174 ISPCCP2_CTRL_MODE | ISPCCP2_CTRL_IF_EN,
175 enable ? (ISPCCP2_CTRL_MODE | ISPCCP2_CTRL_IF_EN) : 0);
176
177 /* For frame count propagation */
178 if (pipe->do_propagation) {
179 /* We may want the Frame Start IRQ from LC0 */
180 if (enable)
181 isp_reg_set(isp, OMAP3_ISP_IOMEM_CCP2,
182 ISPCCP2_LC01_IRQENABLE,
183 ISPCCP2_LC01_IRQSTATUS_LC0_FS_IRQ);
184 else
185 isp_reg_clr(isp, OMAP3_ISP_IOMEM_CCP2,
186 ISPCCP2_LC01_IRQENABLE,
187 ISPCCP2_LC01_IRQSTATUS_LC0_FS_IRQ);
188 }
189 }
190
191 /*
192 * ccp2_mem_enable - Enable CCP2 memory interface.
193 * @ccp2: pointer to ISP CCP2 device
194 * @enable: enable/disable flag
195 */
196 static void ccp2_mem_enable(struct isp_ccp2_device *ccp2, u8 enable)
197 {
198 struct isp_device *isp = to_isp_device(ccp2);
199
200 if (enable)
201 ccp2_if_enable(ccp2, 0);
202
203 /* Enable/Disable ccp2 interface in ccp2 mode */
204 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL,
205 ISPCCP2_CTRL_MODE, enable ? ISPCCP2_CTRL_MODE : 0);
206
207 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCM_CTRL,
208 ISPCCP2_LCM_CTRL_CHAN_EN,
209 enable ? ISPCCP2_LCM_CTRL_CHAN_EN : 0);
210 }
211
212 /*
213 * ccp2_phyif_config - Initialize CCP2 phy interface config
214 * @ccp2: Pointer to ISP CCP2 device
215 * @config: CCP2 platform data
216 *
217 * Configure the CCP2 physical interface module from platform data.
218 *
219 * Returns -EIO if strobe is chosen in CSI1 mode, or 0 on success.
220 */
221 static int ccp2_phyif_config(struct isp_ccp2_device *ccp2,
222 const struct isp_ccp2_platform_data *pdata)
223 {
224 struct isp_device *isp = to_isp_device(ccp2);
225 u32 val;
226
227 /* CCP2B mode */
228 val = isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL) |
229 ISPCCP2_CTRL_IO_OUT_SEL | ISPCCP2_CTRL_MODE;
230 /* Data/strobe physical layer */
231 BIT_SET(val, ISPCCP2_CTRL_PHY_SEL_SHIFT, ISPCCP2_CTRL_PHY_SEL_MASK,
232 pdata->phy_layer);
233 BIT_SET(val, ISPCCP2_CTRL_INV_SHIFT, ISPCCP2_CTRL_INV_MASK,
234 pdata->strobe_clk_pol);
235 isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL);
236
237 val = isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL);
238 if (!(val & ISPCCP2_CTRL_MODE)) {
239 if (pdata->ccp2_mode)
240 dev_warn(isp->dev, "OMAP3 CCP2 bus not available\n");
241 if (pdata->phy_layer == ISPCCP2_CTRL_PHY_SEL_STROBE)
242 /* Strobe mode requires CCP2 */
243 return -EIO;
244 }
245
246 return 0;
247 }
248
249 /*
250 * ccp2_vp_config - Initialize CCP2 video port interface.
251 * @ccp2: Pointer to ISP CCP2 device
252 * @vpclk_div: Video port divisor
253 *
254 * Configure the CCP2 video port with the given clock divisor. The valid divisor
255 * values depend on the ISP revision:
256 *
257 * - revision 1.0 and 2.0 1 to 4
258 * - revision 15.0 1 to 65536
259 *
260 * The exact divisor value used might differ from the requested value, as ISP
261 * revision 15.0 represent the divisor by 65536 divided by an integer.
262 */
263 static void ccp2_vp_config(struct isp_ccp2_device *ccp2,
264 unsigned int vpclk_div)
265 {
266 struct isp_device *isp = to_isp_device(ccp2);
267 u32 val;
268
269 /* ISPCCP2_CTRL Video port */
270 val = isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL);
271 val |= ISPCCP2_CTRL_VP_ONLY_EN; /* Disable the memory write port */
272
273 if (isp->revision == ISP_REVISION_15_0) {
274 vpclk_div = clamp_t(unsigned int, vpclk_div, 1, 65536);
275 vpclk_div = min(ISPCCP2_VPCLK_FRACDIV / vpclk_div, 65535U);
276 BIT_SET(val, ISPCCP2_CTRL_VPCLK_DIV_SHIFT,
277 ISPCCP2_CTRL_VPCLK_DIV_MASK, vpclk_div);
278 } else {
279 vpclk_div = clamp_t(unsigned int, vpclk_div, 1, 4);
280 BIT_SET(val, ISPCCP2_CTRL_VP_OUT_CTRL_SHIFT,
281 ISPCCP2_CTRL_VP_OUT_CTRL_MASK, vpclk_div - 1);
282 }
283
284 isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL);
285 }
286
287 /*
288 * ccp2_lcx_config - Initialize CCP2 logical channel interface.
289 * @ccp2: Pointer to ISP CCP2 device
290 * @config: Pointer to ISP LCx config structure.
291 *
292 * This will analyze the parameters passed by the interface config
293 * and configure CSI1/CCP2 logical channel
294 *
295 */
296 static void ccp2_lcx_config(struct isp_ccp2_device *ccp2,
297 struct isp_interface_lcx_config *config)
298 {
299 struct isp_device *isp = to_isp_device(ccp2);
300 u32 val, format;
301
302 switch (config->format) {
303 case V4L2_MBUS_FMT_SGRBG10_DPCM8_1X8:
304 format = ISPCCP2_LCx_CTRL_FORMAT_RAW8_DPCM10_VP;
305 break;
306 case V4L2_MBUS_FMT_SGRBG10_1X10:
307 default:
308 format = ISPCCP2_LCx_CTRL_FORMAT_RAW10_VP; /* RAW10+VP */
309 break;
310 }
311 /* ISPCCP2_LCx_CTRL logical channel #0 */
312 val = isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCx_CTRL(0))
313 | (ISPCCP2_LCx_CTRL_REGION_EN); /* Region */
314
315 if (isp->revision == ISP_REVISION_15_0) {
316 /* CRC */
317 BIT_SET(val, ISPCCP2_LCx_CTRL_CRC_SHIFT_15_0,
318 ISPCCP2_LCx_CTRL_CRC_MASK,
319 config->crc);
320 /* Format = RAW10+VP or RAW8+DPCM10+VP*/
321 BIT_SET(val, ISPCCP2_LCx_CTRL_FORMAT_SHIFT_15_0,
322 ISPCCP2_LCx_CTRL_FORMAT_MASK_15_0, format);
323 } else {
324 BIT_SET(val, ISPCCP2_LCx_CTRL_CRC_SHIFT,
325 ISPCCP2_LCx_CTRL_CRC_MASK,
326 config->crc);
327
328 BIT_SET(val, ISPCCP2_LCx_CTRL_FORMAT_SHIFT,
329 ISPCCP2_LCx_CTRL_FORMAT_MASK, format);
330 }
331 isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCx_CTRL(0));
332
333 /* ISPCCP2_DAT_START for logical channel #0 */
334 isp_reg_writel(isp, config->data_start << ISPCCP2_LCx_DAT_SHIFT,
335 OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCx_DAT_START(0));
336
337 /* ISPCCP2_DAT_SIZE for logical channel #0 */
338 isp_reg_writel(isp, config->data_size << ISPCCP2_LCx_DAT_SHIFT,
339 OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCx_DAT_SIZE(0));
340
341 /* Enable error IRQs for logical channel #0 */
342 val = ISPCCP2_LC01_IRQSTATUS_LC0_FIFO_OVF_IRQ |
343 ISPCCP2_LC01_IRQSTATUS_LC0_CRC_IRQ |
344 ISPCCP2_LC01_IRQSTATUS_LC0_FSP_IRQ |
345 ISPCCP2_LC01_IRQSTATUS_LC0_FW_IRQ |
346 ISPCCP2_LC01_IRQSTATUS_LC0_FS_IRQ |
347 ISPCCP2_LC01_IRQSTATUS_LC0_FSC_IRQ |
348 ISPCCP2_LC01_IRQSTATUS_LC0_SSC_IRQ;
349
350 isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LC01_IRQSTATUS);
351 isp_reg_set(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LC01_IRQENABLE, val);
352 }
353
354 /*
355 * ccp2_if_configure - Configure ccp2 with data from sensor
356 * @ccp2: Pointer to ISP CCP2 device
357 *
358 * Return 0 on success or a negative error code
359 */
360 static int ccp2_if_configure(struct isp_ccp2_device *ccp2)
361 {
362 const struct isp_v4l2_subdevs_group *pdata;
363 struct v4l2_mbus_framefmt *format;
364 struct media_pad *pad;
365 struct v4l2_subdev *sensor;
366 u32 lines = 0;
367 int ret;
368
369 ccp2_pwr_cfg(ccp2);
370
371 pad = media_entity_remote_source(&ccp2->pads[CCP2_PAD_SINK]);
372 sensor = media_entity_to_v4l2_subdev(pad->entity);
373 pdata = sensor->host_priv;
374
375 ret = ccp2_phyif_config(ccp2, &pdata->bus.ccp2);
376 if (ret < 0)
377 return ret;
378
379 ccp2_vp_config(ccp2, pdata->bus.ccp2.vpclk_div + 1);
380
381 v4l2_subdev_call(sensor, sensor, g_skip_top_lines, &lines);
382
383 format = &ccp2->formats[CCP2_PAD_SINK];
384
385 ccp2->if_cfg.data_start = lines;
386 ccp2->if_cfg.crc = pdata->bus.ccp2.crc;
387 ccp2->if_cfg.format = format->code;
388 ccp2->if_cfg.data_size = format->height;
389
390 ccp2_lcx_config(ccp2, &ccp2->if_cfg);
391
392 return 0;
393 }
394
395 static int ccp2_adjust_bandwidth(struct isp_ccp2_device *ccp2)
396 {
397 struct isp_pipeline *pipe = to_isp_pipeline(&ccp2->subdev.entity);
398 struct isp_device *isp = to_isp_device(ccp2);
399 const struct v4l2_mbus_framefmt *ofmt = &ccp2->formats[CCP2_PAD_SOURCE];
400 unsigned long l3_ick = pipe->l3_ick;
401 struct v4l2_fract *timeperframe;
402 unsigned int vpclk_div = 2;
403 unsigned int value;
404 u64 bound;
405 u64 area;
406
407 /* Compute the minimum clock divisor, based on the pipeline maximum
408 * data rate. This is an absolute lower bound if we don't want SBL
409 * overflows, so round the value up.
410 */
411 vpclk_div = max_t(unsigned int, DIV_ROUND_UP(l3_ick, pipe->max_rate),
412 vpclk_div);
413
414 /* Compute the maximum clock divisor, based on the requested frame rate.
415 * This is a soft lower bound to achieve a frame rate equal or higher
416 * than the requested value, so round the value down.
417 */
418 timeperframe = &pipe->max_timeperframe;
419
420 if (timeperframe->numerator) {
421 area = ofmt->width * ofmt->height;
422 bound = div_u64(area * timeperframe->denominator,
423 timeperframe->numerator);
424 value = min_t(u64, bound, l3_ick);
425 vpclk_div = max_t(unsigned int, l3_ick / value, vpclk_div);
426 }
427
428 dev_dbg(isp->dev, "%s: minimum clock divisor = %u\n", __func__,
429 vpclk_div);
430
431 return vpclk_div;
432 }
433
434 /*
435 * ccp2_mem_configure - Initialize CCP2 memory input/output interface
436 * @ccp2: Pointer to ISP CCP2 device
437 * @config: Pointer to ISP mem interface config structure
438 *
439 * This will analyze the parameters passed by the interface config
440 * structure, and configure the respective registers for proper
441 * CSI1/CCP2 memory input.
442 */
443 static void ccp2_mem_configure(struct isp_ccp2_device *ccp2,
444 struct isp_interface_mem_config *config)
445 {
446 struct isp_device *isp = to_isp_device(ccp2);
447 u32 sink_pixcode = ccp2->formats[CCP2_PAD_SINK].code;
448 u32 source_pixcode = ccp2->formats[CCP2_PAD_SOURCE].code;
449 unsigned int dpcm_decompress = 0;
450 u32 val, hwords;
451
452 if (sink_pixcode != source_pixcode &&
453 sink_pixcode == V4L2_MBUS_FMT_SGRBG10_DPCM8_1X8)
454 dpcm_decompress = 1;
455
456 ccp2_pwr_cfg(ccp2);
457
458 /* Hsize, Skip */
459 isp_reg_writel(isp, ISPCCP2_LCM_HSIZE_SKIP_MIN |
460 (config->hsize_count << ISPCCP2_LCM_HSIZE_SHIFT),
461 OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCM_HSIZE);
462
463 /* Vsize, no. of lines */
464 isp_reg_writel(isp, config->vsize_count << ISPCCP2_LCM_VSIZE_SHIFT,
465 OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCM_VSIZE);
466
467 if (ccp2->video_in.bpl_padding == 0)
468 config->src_ofst = 0;
469 else
470 config->src_ofst = ccp2->video_in.bpl_value;
471
472 isp_reg_writel(isp, config->src_ofst, OMAP3_ISP_IOMEM_CCP2,
473 ISPCCP2_LCM_SRC_OFST);
474
475 /* Source and Destination formats */
476 val = ISPCCP2_LCM_CTRL_DST_FORMAT_RAW10 <<
477 ISPCCP2_LCM_CTRL_DST_FORMAT_SHIFT;
478
479 if (dpcm_decompress) {
480 /* source format is RAW8 */
481 val |= ISPCCP2_LCM_CTRL_SRC_FORMAT_RAW8 <<
482 ISPCCP2_LCM_CTRL_SRC_FORMAT_SHIFT;
483
484 /* RAW8 + DPCM10 - simple predictor */
485 val |= ISPCCP2_LCM_CTRL_SRC_DPCM_PRED;
486
487 /* enable source DPCM decompression */
488 val |= ISPCCP2_LCM_CTRL_SRC_DECOMPR_DPCM10 <<
489 ISPCCP2_LCM_CTRL_SRC_DECOMPR_SHIFT;
490 } else {
491 /* source format is RAW10 */
492 val |= ISPCCP2_LCM_CTRL_SRC_FORMAT_RAW10 <<
493 ISPCCP2_LCM_CTRL_SRC_FORMAT_SHIFT;
494 }
495
496 /* Burst size to 32x64 */
497 val |= ISPCCP2_LCM_CTRL_BURST_SIZE_32X <<
498 ISPCCP2_LCM_CTRL_BURST_SIZE_SHIFT;
499
500 isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCM_CTRL);
501
502 /* Prefetch setup */
503 if (dpcm_decompress)
504 hwords = (ISPCCP2_LCM_HSIZE_SKIP_MIN +
505 config->hsize_count) >> 3;
506 else
507 hwords = (ISPCCP2_LCM_HSIZE_SKIP_MIN +
508 config->hsize_count) >> 2;
509
510 isp_reg_writel(isp, hwords << ISPCCP2_LCM_PREFETCH_SHIFT,
511 OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCM_PREFETCH);
512
513 /* Video port */
514 isp_reg_set(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL,
515 ISPCCP2_CTRL_IO_OUT_SEL | ISPCCP2_CTRL_MODE);
516 ccp2_vp_config(ccp2, ccp2_adjust_bandwidth(ccp2));
517
518 /* Clear LCM interrupts */
519 isp_reg_writel(isp, ISPCCP2_LCM_IRQSTATUS_OCPERROR_IRQ |
520 ISPCCP2_LCM_IRQSTATUS_EOF_IRQ,
521 OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCM_IRQSTATUS);
522
523 /* Enable LCM interupts */
524 isp_reg_set(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCM_IRQENABLE,
525 ISPCCP2_LCM_IRQSTATUS_EOF_IRQ |
526 ISPCCP2_LCM_IRQSTATUS_OCPERROR_IRQ);
527 }
528
529 /*
530 * ccp2_set_inaddr - Sets memory address of input frame.
531 * @ccp2: Pointer to ISP CCP2 device
532 * @addr: 32bit memory address aligned on 32byte boundary.
533 *
534 * Configures the memory address from which the input frame is to be read.
535 */
536 static void ccp2_set_inaddr(struct isp_ccp2_device *ccp2, u32 addr)
537 {
538 struct isp_device *isp = to_isp_device(ccp2);
539
540 isp_reg_writel(isp, addr, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCM_SRC_ADDR);
541 }
542
543 /* -----------------------------------------------------------------------------
544 * Interrupt handling
545 */
546
547 static void ccp2_isr_buffer(struct isp_ccp2_device *ccp2)
548 {
549 struct isp_pipeline *pipe = to_isp_pipeline(&ccp2->subdev.entity);
550 struct isp_buffer *buffer;
551
552 buffer = omap3isp_video_buffer_next(&ccp2->video_in, ccp2->error);
553 if (buffer != NULL)
554 ccp2_set_inaddr(ccp2, buffer->isp_addr);
555
556 pipe->state |= ISP_PIPELINE_IDLE_INPUT;
557
558 if (ccp2->state == ISP_PIPELINE_STREAM_SINGLESHOT) {
559 if (isp_pipeline_ready(pipe))
560 omap3isp_pipeline_set_stream(pipe,
561 ISP_PIPELINE_STREAM_SINGLESHOT);
562 }
563
564 ccp2->error = 0;
565 }
566
567 /*
568 * omap3isp_ccp2_isr - Handle ISP CCP2 interrupts
569 * @ccp2: Pointer to ISP CCP2 device
570 *
571 * This will handle the CCP2 interrupts
572 *
573 * Returns -EIO in case of error, or 0 on success.
574 */
575 int omap3isp_ccp2_isr(struct isp_ccp2_device *ccp2)
576 {
577 struct isp_device *isp = to_isp_device(ccp2);
578 int ret = 0;
579 static const u32 ISPCCP2_LC01_ERROR =
580 ISPCCP2_LC01_IRQSTATUS_LC0_FIFO_OVF_IRQ |
581 ISPCCP2_LC01_IRQSTATUS_LC0_CRC_IRQ |
582 ISPCCP2_LC01_IRQSTATUS_LC0_FSP_IRQ |
583 ISPCCP2_LC01_IRQSTATUS_LC0_FW_IRQ |
584 ISPCCP2_LC01_IRQSTATUS_LC0_FSC_IRQ |
585 ISPCCP2_LC01_IRQSTATUS_LC0_SSC_IRQ;
586 u32 lcx_irqstatus, lcm_irqstatus;
587
588 /* First clear the interrupts */
589 lcx_irqstatus = isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2,
590 ISPCCP2_LC01_IRQSTATUS);
591 isp_reg_writel(isp, lcx_irqstatus, OMAP3_ISP_IOMEM_CCP2,
592 ISPCCP2_LC01_IRQSTATUS);
593
594 lcm_irqstatus = isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2,
595 ISPCCP2_LCM_IRQSTATUS);
596 isp_reg_writel(isp, lcm_irqstatus, OMAP3_ISP_IOMEM_CCP2,
597 ISPCCP2_LCM_IRQSTATUS);
598 /* Errors */
599 if (lcx_irqstatus & ISPCCP2_LC01_ERROR) {
600 ccp2->error = 1;
601 dev_dbg(isp->dev, "CCP2 err:%x\n", lcx_irqstatus);
602 return -EIO;
603 }
604
605 if (lcm_irqstatus & ISPCCP2_LCM_IRQSTATUS_OCPERROR_IRQ) {
606 ccp2->error = 1;
607 dev_dbg(isp->dev, "CCP2 OCP err:%x\n", lcm_irqstatus);
608 ret = -EIO;
609 }
610
611 if (omap3isp_module_sync_is_stopping(&ccp2->wait, &ccp2->stopping))
612 return 0;
613
614 /* Frame number propagation */
615 if (lcx_irqstatus & ISPCCP2_LC01_IRQSTATUS_LC0_FS_IRQ) {
616 struct isp_pipeline *pipe =
617 to_isp_pipeline(&ccp2->subdev.entity);
618 if (pipe->do_propagation)
619 atomic_inc(&pipe->frame_number);
620 }
621
622 /* Handle queued buffers on frame end interrupts */
623 if (lcm_irqstatus & ISPCCP2_LCM_IRQSTATUS_EOF_IRQ)
624 ccp2_isr_buffer(ccp2);
625
626 return ret;
627 }
628
629 /* -----------------------------------------------------------------------------
630 * V4L2 subdev operations
631 */
632
633 static const unsigned int ccp2_fmts[] = {
634 V4L2_MBUS_FMT_SGRBG10_1X10,
635 V4L2_MBUS_FMT_SGRBG10_DPCM8_1X8,
636 };
637
638 /*
639 * __ccp2_get_format - helper function for getting ccp2 format
640 * @ccp2 : Pointer to ISP CCP2 device
641 * @fh : V4L2 subdev file handle
642 * @pad : pad number
643 * @which : wanted subdev format
644 * return format structure or NULL on error
645 */
646 static struct v4l2_mbus_framefmt *
647 __ccp2_get_format(struct isp_ccp2_device *ccp2, struct v4l2_subdev_fh *fh,
648 unsigned int pad, enum v4l2_subdev_format_whence which)
649 {
650 if (which == V4L2_SUBDEV_FORMAT_TRY)
651 return v4l2_subdev_get_try_format(fh, pad);
652 else
653 return &ccp2->formats[pad];
654 }
655
656 /*
657 * ccp2_try_format - Handle try format by pad subdev method
658 * @ccp2 : Pointer to ISP CCP2 device
659 * @fh : V4L2 subdev file handle
660 * @pad : pad num
661 * @fmt : pointer to v4l2 mbus format structure
662 * @which : wanted subdev format
663 */
664 static void ccp2_try_format(struct isp_ccp2_device *ccp2,
665 struct v4l2_subdev_fh *fh, unsigned int pad,
666 struct v4l2_mbus_framefmt *fmt,
667 enum v4l2_subdev_format_whence which)
668 {
669 struct v4l2_mbus_framefmt *format;
670
671 switch (pad) {
672 case CCP2_PAD_SINK:
673 if (fmt->code != V4L2_MBUS_FMT_SGRBG10_DPCM8_1X8)
674 fmt->code = V4L2_MBUS_FMT_SGRBG10_1X10;
675
676 if (ccp2->input == CCP2_INPUT_SENSOR) {
677 fmt->width = clamp_t(u32, fmt->width,
678 ISPCCP2_DAT_START_MIN,
679 ISPCCP2_DAT_START_MAX);
680 fmt->height = clamp_t(u32, fmt->height,
681 ISPCCP2_DAT_SIZE_MIN,
682 ISPCCP2_DAT_SIZE_MAX);
683 } else if (ccp2->input == CCP2_INPUT_MEMORY) {
684 fmt->width = clamp_t(u32, fmt->width,
685 ISPCCP2_LCM_HSIZE_COUNT_MIN,
686 ISPCCP2_LCM_HSIZE_COUNT_MAX);
687 fmt->height = clamp_t(u32, fmt->height,
688 ISPCCP2_LCM_VSIZE_MIN,
689 ISPCCP2_LCM_VSIZE_MAX);
690 }
691 break;
692
693 case CCP2_PAD_SOURCE:
694 /* Source format - copy sink format and change pixel code
695 * to SGRBG10_1X10 as we don't support CCP2 write to memory.
696 * When CCP2 write to memory feature will be added this
697 * should be changed properly.
698 */
699 format = __ccp2_get_format(ccp2, fh, CCP2_PAD_SINK, which);
700 memcpy(fmt, format, sizeof(*fmt));
701 fmt->code = V4L2_MBUS_FMT_SGRBG10_1X10;
702 break;
703 }
704
705 fmt->field = V4L2_FIELD_NONE;
706 fmt->colorspace = V4L2_COLORSPACE_SRGB;
707 }
708
709 /*
710 * ccp2_enum_mbus_code - Handle pixel format enumeration
711 * @sd : pointer to v4l2 subdev structure
712 * @fh : V4L2 subdev file handle
713 * @code : pointer to v4l2_subdev_mbus_code_enum structure
714 * return -EINVAL or zero on success
715 */
716 static int ccp2_enum_mbus_code(struct v4l2_subdev *sd,
717 struct v4l2_subdev_fh *fh,
718 struct v4l2_subdev_mbus_code_enum *code)
719 {
720 struct isp_ccp2_device *ccp2 = v4l2_get_subdevdata(sd);
721 struct v4l2_mbus_framefmt *format;
722
723 if (code->pad == CCP2_PAD_SINK) {
724 if (code->index >= ARRAY_SIZE(ccp2_fmts))
725 return -EINVAL;
726
727 code->code = ccp2_fmts[code->index];
728 } else {
729 if (code->index != 0)
730 return -EINVAL;
731
732 format = __ccp2_get_format(ccp2, fh, CCP2_PAD_SINK,
733 V4L2_SUBDEV_FORMAT_TRY);
734 code->code = format->code;
735 }
736
737 return 0;
738 }
739
740 static int ccp2_enum_frame_size(struct v4l2_subdev *sd,
741 struct v4l2_subdev_fh *fh,
742 struct v4l2_subdev_frame_size_enum *fse)
743 {
744 struct isp_ccp2_device *ccp2 = v4l2_get_subdevdata(sd);
745 struct v4l2_mbus_framefmt format;
746
747 if (fse->index != 0)
748 return -EINVAL;
749
750 format.code = fse->code;
751 format.width = 1;
752 format.height = 1;
753 ccp2_try_format(ccp2, fh, fse->pad, &format, V4L2_SUBDEV_FORMAT_TRY);
754 fse->min_width = format.width;
755 fse->min_height = format.height;
756
757 if (format.code != fse->code)
758 return -EINVAL;
759
760 format.code = fse->code;
761 format.width = -1;
762 format.height = -1;
763 ccp2_try_format(ccp2, fh, fse->pad, &format, V4L2_SUBDEV_FORMAT_TRY);
764 fse->max_width = format.width;
765 fse->max_height = format.height;
766
767 return 0;
768 }
769
770 /*
771 * ccp2_get_format - Handle get format by pads subdev method
772 * @sd : pointer to v4l2 subdev structure
773 * @fh : V4L2 subdev file handle
774 * @fmt : pointer to v4l2 subdev format structure
775 * return -EINVAL or zero on sucess
776 */
777 static int ccp2_get_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
778 struct v4l2_subdev_format *fmt)
779 {
780 struct isp_ccp2_device *ccp2 = v4l2_get_subdevdata(sd);
781 struct v4l2_mbus_framefmt *format;
782
783 format = __ccp2_get_format(ccp2, fh, fmt->pad, fmt->which);
784 if (format == NULL)
785 return -EINVAL;
786
787 fmt->format = *format;
788 return 0;
789 }
790
791 /*
792 * ccp2_set_format - Handle set format by pads subdev method
793 * @sd : pointer to v4l2 subdev structure
794 * @fh : V4L2 subdev file handle
795 * @fmt : pointer to v4l2 subdev format structure
796 * returns zero
797 */
798 static int ccp2_set_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
799 struct v4l2_subdev_format *fmt)
800 {
801 struct isp_ccp2_device *ccp2 = v4l2_get_subdevdata(sd);
802 struct v4l2_mbus_framefmt *format;
803
804 format = __ccp2_get_format(ccp2, fh, fmt->pad, fmt->which);
805 if (format == NULL)
806 return -EINVAL;
807
808 ccp2_try_format(ccp2, fh, fmt->pad, &fmt->format, fmt->which);
809 *format = fmt->format;
810
811 /* Propagate the format from sink to source */
812 if (fmt->pad == CCP2_PAD_SINK) {
813 format = __ccp2_get_format(ccp2, fh, CCP2_PAD_SOURCE,
814 fmt->which);
815 *format = fmt->format;
816 ccp2_try_format(ccp2, fh, CCP2_PAD_SOURCE, format, fmt->which);
817 }
818
819 return 0;
820 }
821
822 /*
823 * ccp2_init_formats - Initialize formats on all pads
824 * @sd: ISP CCP2 V4L2 subdevice
825 * @fh: V4L2 subdev file handle
826 *
827 * Initialize all pad formats with default values. If fh is not NULL, try
828 * formats are initialized on the file handle. Otherwise active formats are
829 * initialized on the device.
830 */
831 static int ccp2_init_formats(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
832 {
833 struct v4l2_subdev_format format;
834
835 memset(&format, 0, sizeof(format));
836 format.pad = CCP2_PAD_SINK;
837 format.which = fh ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE;
838 format.format.code = V4L2_MBUS_FMT_SGRBG10_1X10;
839 format.format.width = 4096;
840 format.format.height = 4096;
841 ccp2_set_format(sd, fh, &format);
842
843 return 0;
844 }
845
846 /*
847 * ccp2_s_stream - Enable/Disable streaming on ccp2 subdev
848 * @sd : pointer to v4l2 subdev structure
849 * @enable: 1 == Enable, 0 == Disable
850 * return zero
851 */
852 static int ccp2_s_stream(struct v4l2_subdev *sd, int enable)
853 {
854 struct isp_ccp2_device *ccp2 = v4l2_get_subdevdata(sd);
855 struct isp_device *isp = to_isp_device(ccp2);
856 struct device *dev = to_device(ccp2);
857 int ret;
858
859 if (ccp2->state == ISP_PIPELINE_STREAM_STOPPED) {
860 if (enable == ISP_PIPELINE_STREAM_STOPPED)
861 return 0;
862 atomic_set(&ccp2->stopping, 0);
863 ccp2->error = 0;
864 }
865
866 switch (enable) {
867 case ISP_PIPELINE_STREAM_CONTINUOUS:
868 if (ccp2->phy) {
869 ret = omap3isp_csiphy_acquire(ccp2->phy);
870 if (ret < 0)
871 return ret;
872 }
873
874 ccp2_if_configure(ccp2);
875 ccp2_print_status(ccp2);
876
877 /* Enable CSI1/CCP2 interface */
878 ccp2_if_enable(ccp2, 1);
879 break;
880
881 case ISP_PIPELINE_STREAM_SINGLESHOT:
882 if (ccp2->state != ISP_PIPELINE_STREAM_SINGLESHOT) {
883 struct v4l2_mbus_framefmt *format;
884
885 format = &ccp2->formats[CCP2_PAD_SINK];
886
887 ccp2->mem_cfg.hsize_count = format->width;
888 ccp2->mem_cfg.vsize_count = format->height;
889 ccp2->mem_cfg.src_ofst = 0;
890
891 ccp2_mem_configure(ccp2, &ccp2->mem_cfg);
892 omap3isp_sbl_enable(isp, OMAP3_ISP_SBL_CSI1_READ);
893 ccp2_print_status(ccp2);
894 }
895 ccp2_mem_enable(ccp2, 1);
896 break;
897
898 case ISP_PIPELINE_STREAM_STOPPED:
899 if (omap3isp_module_sync_idle(&sd->entity, &ccp2->wait,
900 &ccp2->stopping))
901 dev_dbg(dev, "%s: module stop timeout.\n", sd->name);
902 if (ccp2->input == CCP2_INPUT_MEMORY) {
903 ccp2_mem_enable(ccp2, 0);
904 omap3isp_sbl_disable(isp, OMAP3_ISP_SBL_CSI1_READ);
905 } else if (ccp2->input == CCP2_INPUT_SENSOR) {
906 /* Disable CSI1/CCP2 interface */
907 ccp2_if_enable(ccp2, 0);
908 if (ccp2->phy)
909 omap3isp_csiphy_release(ccp2->phy);
910 }
911 break;
912 }
913
914 ccp2->state = enable;
915 return 0;
916 }
917
918 /* subdev video operations */
919 static const struct v4l2_subdev_video_ops ccp2_sd_video_ops = {
920 .s_stream = ccp2_s_stream,
921 };
922
923 /* subdev pad operations */
924 static const struct v4l2_subdev_pad_ops ccp2_sd_pad_ops = {
925 .enum_mbus_code = ccp2_enum_mbus_code,
926 .enum_frame_size = ccp2_enum_frame_size,
927 .get_fmt = ccp2_get_format,
928 .set_fmt = ccp2_set_format,
929 };
930
931 /* subdev operations */
932 static const struct v4l2_subdev_ops ccp2_sd_ops = {
933 .video = &ccp2_sd_video_ops,
934 .pad = &ccp2_sd_pad_ops,
935 };
936
937 /* subdev internal operations */
938 static const struct v4l2_subdev_internal_ops ccp2_sd_internal_ops = {
939 .open = ccp2_init_formats,
940 };
941
942 /* --------------------------------------------------------------------------
943 * ISP ccp2 video device node
944 */
945
946 /*
947 * ccp2_video_queue - Queue video buffer.
948 * @video : Pointer to isp video structure
949 * @buffer: Pointer to isp_buffer structure
950 * return -EIO or zero on success
951 */
952 static int ccp2_video_queue(struct isp_video *video, struct isp_buffer *buffer)
953 {
954 struct isp_ccp2_device *ccp2 = &video->isp->isp_ccp2;
955
956 ccp2_set_inaddr(ccp2, buffer->isp_addr);
957 return 0;
958 }
959
960 static const struct isp_video_operations ccp2_video_ops = {
961 .queue = ccp2_video_queue,
962 };
963
964 /* -----------------------------------------------------------------------------
965 * Media entity operations
966 */
967
968 /*
969 * ccp2_link_setup - Setup ccp2 connections.
970 * @entity : Pointer to media entity structure
971 * @local : Pointer to local pad array
972 * @remote : Pointer to remote pad array
973 * @flags : Link flags
974 * return -EINVAL on error or zero on success
975 */
976 static int ccp2_link_setup(struct media_entity *entity,
977 const struct media_pad *local,
978 const struct media_pad *remote, u32 flags)
979 {
980 struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
981 struct isp_ccp2_device *ccp2 = v4l2_get_subdevdata(sd);
982
983 switch (local->index | media_entity_type(remote->entity)) {
984 case CCP2_PAD_SINK | MEDIA_ENT_T_DEVNODE:
985 /* read from memory */
986 if (flags & MEDIA_LNK_FL_ENABLED) {
987 if (ccp2->input == CCP2_INPUT_SENSOR)
988 return -EBUSY;
989 ccp2->input = CCP2_INPUT_MEMORY;
990 } else {
991 if (ccp2->input == CCP2_INPUT_MEMORY)
992 ccp2->input = CCP2_INPUT_NONE;
993 }
994 break;
995
996 case CCP2_PAD_SINK | MEDIA_ENT_T_V4L2_SUBDEV:
997 /* read from sensor/phy */
998 if (flags & MEDIA_LNK_FL_ENABLED) {
999 if (ccp2->input == CCP2_INPUT_MEMORY)
1000 return -EBUSY;
1001 ccp2->input = CCP2_INPUT_SENSOR;
1002 } else {
1003 if (ccp2->input == CCP2_INPUT_SENSOR)
1004 ccp2->input = CCP2_INPUT_NONE;
1005 } break;
1006
1007 case CCP2_PAD_SOURCE | MEDIA_ENT_T_V4L2_SUBDEV:
1008 /* write to video port/ccdc */
1009 if (flags & MEDIA_LNK_FL_ENABLED)
1010 ccp2->output = CCP2_OUTPUT_CCDC;
1011 else
1012 ccp2->output = CCP2_OUTPUT_NONE;
1013 break;
1014
1015 default:
1016 return -EINVAL;
1017 }
1018
1019 return 0;
1020 }
1021
1022 /* media operations */
1023 static const struct media_entity_operations ccp2_media_ops = {
1024 .link_setup = ccp2_link_setup,
1025 };
1026
1027 /*
1028 * ccp2_init_entities - Initialize ccp2 subdev and media entity.
1029 * @ccp2: Pointer to ISP CCP2 device
1030 * return negative error code or zero on success
1031 */
1032 static int ccp2_init_entities(struct isp_ccp2_device *ccp2)
1033 {
1034 struct v4l2_subdev *sd = &ccp2->subdev;
1035 struct media_pad *pads = ccp2->pads;
1036 struct media_entity *me = &sd->entity;
1037 int ret;
1038
1039 ccp2->input = CCP2_INPUT_NONE;
1040 ccp2->output = CCP2_OUTPUT_NONE;
1041
1042 v4l2_subdev_init(sd, &ccp2_sd_ops);
1043 sd->internal_ops = &ccp2_sd_internal_ops;
1044 strlcpy(sd->name, "OMAP3 ISP CCP2", sizeof(sd->name));
1045 sd->grp_id = 1 << 16; /* group ID for isp subdevs */
1046 v4l2_set_subdevdata(sd, ccp2);
1047 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1048
1049 pads[CCP2_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
1050 pads[CCP2_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
1051
1052 me->ops = &ccp2_media_ops;
1053 ret = media_entity_init(me, CCP2_PADS_NUM, pads, 0);
1054 if (ret < 0)
1055 return ret;
1056
1057 ccp2_init_formats(sd, NULL);
1058
1059 /*
1060 * The CCP2 has weird line alignment requirements, possibly caused by
1061 * DPCM8 decompression. Line length for data read from memory must be a
1062 * multiple of 128 bits (16 bytes) in continuous mode (when no padding
1063 * is present at end of lines). Additionally, if padding is used, the
1064 * padded line length must be a multiple of 32 bytes. To simplify the
1065 * implementation we use a fixed 32 bytes alignment regardless of the
1066 * input format and width. If strict 128 bits alignment support is
1067 * required ispvideo will need to be made aware of this special dual
1068 * alignement requirements.
1069 */
1070 ccp2->video_in.type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
1071 ccp2->video_in.bpl_alignment = 32;
1072 ccp2->video_in.bpl_max = 0xffffffe0;
1073 ccp2->video_in.isp = to_isp_device(ccp2);
1074 ccp2->video_in.ops = &ccp2_video_ops;
1075 ccp2->video_in.capture_mem = PAGE_ALIGN(4096 * 4096) * 3;
1076
1077 ret = omap3isp_video_init(&ccp2->video_in, "CCP2");
1078 if (ret < 0)
1079 return ret;
1080
1081 /* Connect the video node to the ccp2 subdev. */
1082 ret = media_entity_create_link(&ccp2->video_in.video.entity, 0,
1083 &ccp2->subdev.entity, CCP2_PAD_SINK, 0);
1084 if (ret < 0)
1085 return ret;
1086
1087 return 0;
1088 }
1089
1090 /*
1091 * omap3isp_ccp2_unregister_entities - Unregister media entities: subdev
1092 * @ccp2: Pointer to ISP CCP2 device
1093 */
1094 void omap3isp_ccp2_unregister_entities(struct isp_ccp2_device *ccp2)
1095 {
1096 media_entity_cleanup(&ccp2->subdev.entity);
1097
1098 v4l2_device_unregister_subdev(&ccp2->subdev);
1099 omap3isp_video_unregister(&ccp2->video_in);
1100 }
1101
1102 /*
1103 * omap3isp_ccp2_register_entities - Register the subdev media entity
1104 * @ccp2: Pointer to ISP CCP2 device
1105 * @vdev: Pointer to v4l device
1106 * return negative error code or zero on success
1107 */
1108
1109 int omap3isp_ccp2_register_entities(struct isp_ccp2_device *ccp2,
1110 struct v4l2_device *vdev)
1111 {
1112 int ret;
1113
1114 /* Register the subdev and video nodes. */
1115 ret = v4l2_device_register_subdev(vdev, &ccp2->subdev);
1116 if (ret < 0)
1117 goto error;
1118
1119 ret = omap3isp_video_register(&ccp2->video_in, vdev);
1120 if (ret < 0)
1121 goto error;
1122
1123 return 0;
1124
1125 error:
1126 omap3isp_ccp2_unregister_entities(ccp2);
1127 return ret;
1128 }
1129
1130 /* -----------------------------------------------------------------------------
1131 * ISP ccp2 initialisation and cleanup
1132 */
1133
1134 /*
1135 * omap3isp_ccp2_cleanup - CCP2 un-initialization
1136 * @isp : Pointer to ISP device
1137 */
1138 void omap3isp_ccp2_cleanup(struct isp_device *isp)
1139 {
1140 }
1141
1142 /*
1143 * omap3isp_ccp2_init - CCP2 initialization.
1144 * @isp : Pointer to ISP device
1145 * return negative error code or zero on success
1146 */
1147 int omap3isp_ccp2_init(struct isp_device *isp)
1148 {
1149 struct isp_ccp2_device *ccp2 = &isp->isp_ccp2;
1150 int ret;
1151
1152 init_waitqueue_head(&ccp2->wait);
1153
1154 /* On the OMAP36xx, the CCP2 uses the CSI PHY1 or PHY2, shared with
1155 * the CSI2c or CSI2a receivers. The PHY then needs to be explicitly
1156 * configured.
1157 *
1158 * TODO: Don't hardcode the usage of PHY1 (shared with CSI2c).
1159 */
1160 if (isp->revision == ISP_REVISION_15_0)
1161 ccp2->phy = &isp->isp_csiphy1;
1162
1163 ret = ccp2_init_entities(ccp2);
1164 if (ret < 0)
1165 goto out;
1166
1167 ccp2_reset(ccp2);
1168 out:
1169 if (ret)
1170 omap3isp_ccp2_cleanup(isp);
1171
1172 return ret;
1173 }
CRIS linux kernel tree