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FRV: Use generic show_interrupts()
[cris-mirror.git] / drivers / media / video / s5p-fimc / fimc-core.c
blob6c919b38a3d89c17c33d4cd5d4beee2252f23929
1 /*
2 * S5P camera interface (video postprocessor) driver
3 *
4 * Copyright (c) 2010 Samsung Electronics Co., Ltd
5 *
6 * Sylwester Nawrocki, <s.nawrocki@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published
10 * by the Free Software Foundation, either version 2 of the License,
11 * or (at your option) any later version.
12 */
13
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/version.h>
17 #include <linux/types.h>
18 #include <linux/errno.h>
19 #include <linux/bug.h>
20 #include <linux/interrupt.h>
21 #include <linux/device.h>
22 #include <linux/platform_device.h>
23 #include <linux/list.h>
24 #include <linux/io.h>
25 #include <linux/slab.h>
26 #include <linux/clk.h>
27 #include <media/v4l2-ioctl.h>
28 #include <media/videobuf2-core.h>
29 #include <media/videobuf2-dma-contig.h>
30
31 #include "fimc-core.h"
32
33 static char *fimc_clocks[MAX_FIMC_CLOCKS] = {
34 "sclk_fimc", "fimc", "sclk_cam"
35 };
36
37 static struct fimc_fmt fimc_formats[] = {
38 {
39 .name = "RGB565",
40 .fourcc = V4L2_PIX_FMT_RGB565X,
41 .depth = { 16 },
42 .color = S5P_FIMC_RGB565,
43 .memplanes = 1,
44 .colplanes = 1,
45 .mbus_code = V4L2_MBUS_FMT_RGB565_2X8_BE,
46 .flags = FMT_FLAGS_M2M,
47 }, {
48 .name = "BGR666",
49 .fourcc = V4L2_PIX_FMT_BGR666,
50 .depth = { 32 },
51 .color = S5P_FIMC_RGB666,
52 .memplanes = 1,
53 .colplanes = 1,
54 .flags = FMT_FLAGS_M2M,
55 }, {
56 .name = "XRGB-8-8-8-8, 32 bpp",
57 .fourcc = V4L2_PIX_FMT_RGB32,
58 .depth = { 32 },
59 .color = S5P_FIMC_RGB888,
60 .memplanes = 1,
61 .colplanes = 1,
62 .flags = FMT_FLAGS_M2M,
63 }, {
64 .name = "YUV 4:2:2 packed, YCbYCr",
65 .fourcc = V4L2_PIX_FMT_YUYV,
66 .depth = { 16 },
67 .color = S5P_FIMC_YCBYCR422,
68 .memplanes = 1,
69 .colplanes = 1,
70 .mbus_code = V4L2_MBUS_FMT_YUYV8_2X8,
71 .flags = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
72 }, {
73 .name = "YUV 4:2:2 packed, CbYCrY",
74 .fourcc = V4L2_PIX_FMT_UYVY,
75 .depth = { 16 },
76 .color = S5P_FIMC_CBYCRY422,
77 .memplanes = 1,
78 .colplanes = 1,
79 .mbus_code = V4L2_MBUS_FMT_UYVY8_2X8,
80 .flags = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
81 }, {
82 .name = "YUV 4:2:2 packed, CrYCbY",
83 .fourcc = V4L2_PIX_FMT_VYUY,
84 .depth = { 16 },
85 .color = S5P_FIMC_CRYCBY422,
86 .memplanes = 1,
87 .colplanes = 1,
88 .mbus_code = V4L2_MBUS_FMT_VYUY8_2X8,
89 .flags = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
90 }, {
91 .name = "YUV 4:2:2 packed, YCrYCb",
92 .fourcc = V4L2_PIX_FMT_YVYU,
93 .depth = { 16 },
94 .color = S5P_FIMC_YCRYCB422,
95 .memplanes = 1,
96 .colplanes = 1,
97 .mbus_code = V4L2_MBUS_FMT_YVYU8_2X8,
98 .flags = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
99 }, {
100 .name = "YUV 4:2:2 planar, Y/Cb/Cr",
101 .fourcc = V4L2_PIX_FMT_YUV422P,
102 .depth = { 12 },
103 .color = S5P_FIMC_YCBYCR422,
104 .memplanes = 1,
105 .colplanes = 3,
106 .flags = FMT_FLAGS_M2M,
107 }, {
108 .name = "YUV 4:2:2 planar, Y/CbCr",
109 .fourcc = V4L2_PIX_FMT_NV16,
110 .depth = { 16 },
111 .color = S5P_FIMC_YCBYCR422,
112 .memplanes = 1,
113 .colplanes = 2,
114 .flags = FMT_FLAGS_M2M,
115 }, {
116 .name = "YUV 4:2:2 planar, Y/CrCb",
117 .fourcc = V4L2_PIX_FMT_NV61,
118 .depth = { 16 },
119 .color = S5P_FIMC_YCRYCB422,
120 .memplanes = 1,
121 .colplanes = 2,
122 .flags = FMT_FLAGS_M2M,
123 }, {
124 .name = "YUV 4:2:0 planar, YCbCr",
125 .fourcc = V4L2_PIX_FMT_YUV420,
126 .depth = { 12 },
127 .color = S5P_FIMC_YCBCR420,
128 .memplanes = 1,
129 .colplanes = 3,
130 .flags = FMT_FLAGS_M2M,
131 }, {
132 .name = "YUV 4:2:0 planar, Y/CbCr",
133 .fourcc = V4L2_PIX_FMT_NV12,
134 .depth = { 12 },
135 .color = S5P_FIMC_YCBCR420,
136 .memplanes = 1,
137 .colplanes = 2,
138 .flags = FMT_FLAGS_M2M,
139 }, {
140 .name = "YUV 4:2:0 non-contiguous 2-planar, Y/CbCr",
141 .fourcc = V4L2_PIX_FMT_NV12M,
142 .color = S5P_FIMC_YCBCR420,
143 .depth = { 8, 4 },
144 .memplanes = 2,
145 .colplanes = 2,
146 .flags = FMT_FLAGS_M2M,
147 }, {
148 .name = "YUV 4:2:0 non-contiguous 3-planar, Y/Cb/Cr",
149 .fourcc = V4L2_PIX_FMT_YUV420M,
150 .color = S5P_FIMC_YCBCR420,
151 .depth = { 8, 2, 2 },
152 .memplanes = 3,
153 .colplanes = 3,
154 .flags = FMT_FLAGS_M2M,
155 }, {
156 .name = "YUV 4:2:0 non-contiguous 2-planar, Y/CbCr, tiled",
157 .fourcc = V4L2_PIX_FMT_NV12MT,
158 .color = S5P_FIMC_YCBCR420,
159 .depth = { 8, 4 },
160 .memplanes = 2,
161 .colplanes = 2,
162 .flags = FMT_FLAGS_M2M,
163 },
164 };
165
166 static struct v4l2_queryctrl fimc_ctrls[] = {
167 {
168 .id = V4L2_CID_HFLIP,
169 .type = V4L2_CTRL_TYPE_BOOLEAN,
170 .name = "Horizontal flip",
171 .minimum = 0,
172 .maximum = 1,
173 .default_value = 0,
174 }, {
175 .id = V4L2_CID_VFLIP,
176 .type = V4L2_CTRL_TYPE_BOOLEAN,
177 .name = "Vertical flip",
178 .minimum = 0,
179 .maximum = 1,
180 .default_value = 0,
181 }, {
182 .id = V4L2_CID_ROTATE,
183 .type = V4L2_CTRL_TYPE_INTEGER,
184 .name = "Rotation (CCW)",
185 .minimum = 0,
186 .maximum = 270,
187 .step = 90,
188 .default_value = 0,
189 },
190 };
191
192
193 static struct v4l2_queryctrl *get_ctrl(int id)
194 {
195 int i;
196
197 for (i = 0; i < ARRAY_SIZE(fimc_ctrls); ++i)
198 if (id == fimc_ctrls[i].id)
199 return &fimc_ctrls[i];
200 return NULL;
201 }
202
203 int fimc_check_scaler_ratio(int sw, int sh, int dw, int dh, int rot)
204 {
205 int tx, ty;
206
207 if (rot == 90 || rot == 270) {
208 ty = dw;
209 tx = dh;
210 } else {
211 tx = dw;
212 ty = dh;
213 }
214
215 if ((sw >= SCALER_MAX_HRATIO * tx) || (sh >= SCALER_MAX_VRATIO * ty))
216 return -EINVAL;
217
218 return 0;
219 }
220
221 static int fimc_get_scaler_factor(u32 src, u32 tar, u32 *ratio, u32 *shift)
222 {
223 u32 sh = 6;
224
225 if (src >= 64 * tar)
226 return -EINVAL;
227
228 while (sh--) {
229 u32 tmp = 1 << sh;
230 if (src >= tar * tmp) {
231 *shift = sh, *ratio = tmp;
232 return 0;
233 }
234 }
235
236 *shift = 0, *ratio = 1;
237
238 dbg("s: %d, t: %d, shift: %d, ratio: %d",
239 src, tar, *shift, *ratio);
240 return 0;
241 }
242
243 int fimc_set_scaler_info(struct fimc_ctx *ctx)
244 {
245 struct fimc_scaler *sc = &ctx->scaler;
246 struct fimc_frame *s_frame = &ctx->s_frame;
247 struct fimc_frame *d_frame = &ctx->d_frame;
248 struct samsung_fimc_variant *variant = ctx->fimc_dev->variant;
249 int tx, ty, sx, sy;
250 int ret;
251
252 if (ctx->rotation == 90 || ctx->rotation == 270) {
253 ty = d_frame->width;
254 tx = d_frame->height;
255 } else {
256 tx = d_frame->width;
257 ty = d_frame->height;
258 }
259 if (tx <= 0 || ty <= 0) {
260 v4l2_err(&ctx->fimc_dev->m2m.v4l2_dev,
261 "invalid target size: %d x %d", tx, ty);
262 return -EINVAL;
263 }
264
265 sx = s_frame->width;
266 sy = s_frame->height;
267 if (sx <= 0 || sy <= 0) {
268 err("invalid source size: %d x %d", sx, sy);
269 return -EINVAL;
270 }
271
272 sc->real_width = sx;
273 sc->real_height = sy;
274 dbg("sx= %d, sy= %d, tx= %d, ty= %d", sx, sy, tx, ty);
275
276 ret = fimc_get_scaler_factor(sx, tx, &sc->pre_hratio, &sc->hfactor);
277 if (ret)
278 return ret;
279
280 ret = fimc_get_scaler_factor(sy, ty, &sc->pre_vratio, &sc->vfactor);
281 if (ret)
282 return ret;
283
284 sc->pre_dst_width = sx / sc->pre_hratio;
285 sc->pre_dst_height = sy / sc->pre_vratio;
286
287 if (variant->has_mainscaler_ext) {
288 sc->main_hratio = (sx << 14) / (tx << sc->hfactor);
289 sc->main_vratio = (sy << 14) / (ty << sc->vfactor);
290 } else {
291 sc->main_hratio = (sx << 8) / (tx << sc->hfactor);
292 sc->main_vratio = (sy << 8) / (ty << sc->vfactor);
293
294 }
295
296 sc->scaleup_h = (tx >= sx) ? 1 : 0;
297 sc->scaleup_v = (ty >= sy) ? 1 : 0;
298
299 /* check to see if input and output size/format differ */
300 if (s_frame->fmt->color == d_frame->fmt->color
301 && s_frame->width == d_frame->width
302 && s_frame->height == d_frame->height)
303 sc->copy_mode = 1;
304 else
305 sc->copy_mode = 0;
306
307 return 0;
308 }
309
310 static void fimc_m2m_job_finish(struct fimc_ctx *ctx, int vb_state)
311 {
312 struct vb2_buffer *src_vb, *dst_vb;
313 struct fimc_dev *fimc = ctx->fimc_dev;
314
315 if (!ctx || !ctx->m2m_ctx)
316 return;
317
318 src_vb = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
319 dst_vb = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx);
320
321 if (src_vb && dst_vb) {
322 v4l2_m2m_buf_done(src_vb, vb_state);
323 v4l2_m2m_buf_done(dst_vb, vb_state);
324 v4l2_m2m_job_finish(fimc->m2m.m2m_dev, ctx->m2m_ctx);
325 }
326 }
327
328 /* Complete the transaction which has been scheduled for execution. */
329 static void fimc_m2m_shutdown(struct fimc_ctx *ctx)
330 {
331 struct fimc_dev *fimc = ctx->fimc_dev;
332 int ret;
333
334 if (!fimc_m2m_pending(fimc))
335 return;
336
337 fimc_ctx_state_lock_set(FIMC_CTX_SHUT, ctx);
338
339 ret = wait_event_timeout(fimc->irq_queue,
340 !fimc_ctx_state_is_set(FIMC_CTX_SHUT, ctx),
341 FIMC_SHUTDOWN_TIMEOUT);
342 /*
343 * In case of a timeout the buffers are not released in the interrupt
344 * handler so return them here with the error flag set, if there are
345 * any on the queue.
346 */
347 if (ret == 0)
348 fimc_m2m_job_finish(ctx, VB2_BUF_STATE_ERROR);
349 }
350
351 static int stop_streaming(struct vb2_queue *q)
352 {
353 struct fimc_ctx *ctx = q->drv_priv;
354
355 fimc_m2m_shutdown(ctx);
356
357 return 0;
358 }
359
360 static void fimc_capture_irq_handler(struct fimc_dev *fimc)
361 {
362 struct fimc_vid_cap *cap = &fimc->vid_cap;
363 struct fimc_vid_buffer *v_buf;
364
365 if (!list_empty(&cap->active_buf_q) &&
366 test_bit(ST_CAPT_RUN, &fimc->state)) {
367 v_buf = active_queue_pop(cap);
368 vb2_buffer_done(&v_buf->vb, VB2_BUF_STATE_DONE);
369 }
370
371 if (test_and_clear_bit(ST_CAPT_SHUT, &fimc->state)) {
372 wake_up(&fimc->irq_queue);
373 return;
374 }
375
376 if (!list_empty(&cap->pending_buf_q)) {
377
378 v_buf = pending_queue_pop(cap);
379 fimc_hw_set_output_addr(fimc, &v_buf->paddr, cap->buf_index);
380 v_buf->index = cap->buf_index;
381
382 /* Move the buffer to the capture active queue */
383 active_queue_add(cap, v_buf);
384
385 dbg("next frame: %d, done frame: %d",
386 fimc_hw_get_frame_index(fimc), v_buf->index);
387
388 if (++cap->buf_index >= FIMC_MAX_OUT_BUFS)
389 cap->buf_index = 0;
390 }
391
392 if (cap->active_buf_cnt == 0) {
393 clear_bit(ST_CAPT_RUN, &fimc->state);
394
395 if (++cap->buf_index >= FIMC_MAX_OUT_BUFS)
396 cap->buf_index = 0;
397 } else {
398 set_bit(ST_CAPT_RUN, &fimc->state);
399 }
400
401 dbg("frame: %d, active_buf_cnt: %d",
402 fimc_hw_get_frame_index(fimc), cap->active_buf_cnt);
403 }
404
405 static irqreturn_t fimc_isr(int irq, void *priv)
406 {
407 struct fimc_dev *fimc = priv;
408 struct fimc_vid_cap *cap = &fimc->vid_cap;
409 struct fimc_ctx *ctx;
410
411 fimc_hw_clear_irq(fimc);
412
413 if (test_and_clear_bit(ST_M2M_PEND, &fimc->state)) {
414 ctx = v4l2_m2m_get_curr_priv(fimc->m2m.m2m_dev);
415 if (ctx != NULL) {
416 fimc_m2m_job_finish(ctx, VB2_BUF_STATE_DONE);
417
418 spin_lock(&ctx->slock);
419 if (ctx->state & FIMC_CTX_SHUT) {
420 ctx->state &= ~FIMC_CTX_SHUT;
421 wake_up(&fimc->irq_queue);
422 }
423 spin_unlock(&ctx->slock);
424 }
425
426 return IRQ_HANDLED;
427 }
428
429 spin_lock(&fimc->slock);
430
431 if (test_bit(ST_CAPT_PEND, &fimc->state)) {
432 fimc_capture_irq_handler(fimc);
433
434 if (cap->active_buf_cnt == 1) {
435 fimc_deactivate_capture(fimc);
436 clear_bit(ST_CAPT_STREAM, &fimc->state);
437 }
438 }
439
440 spin_unlock(&fimc->slock);
441 return IRQ_HANDLED;
442 }
443
444 /* The color format (colplanes, memplanes) must be already configured. */
445 int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb,
446 struct fimc_frame *frame, struct fimc_addr *paddr)
447 {
448 int ret = 0;
449 u32 pix_size;
450
451 if (vb == NULL || frame == NULL)
452 return -EINVAL;
453
454 pix_size = frame->width * frame->height;
455
456 dbg("memplanes= %d, colplanes= %d, pix_size= %d",
457 frame->fmt->memplanes, frame->fmt->colplanes, pix_size);
458
459 paddr->y = vb2_dma_contig_plane_paddr(vb, 0);
460
461 if (frame->fmt->memplanes == 1) {
462 switch (frame->fmt->colplanes) {
463 case 1:
464 paddr->cb = 0;
465 paddr->cr = 0;
466 break;
467 case 2:
468 /* decompose Y into Y/Cb */
469 paddr->cb = (u32)(paddr->y + pix_size);
470 paddr->cr = 0;
471 break;
472 case 3:
473 paddr->cb = (u32)(paddr->y + pix_size);
474 /* decompose Y into Y/Cb/Cr */
475 if (S5P_FIMC_YCBCR420 == frame->fmt->color)
476 paddr->cr = (u32)(paddr->cb
477 + (pix_size >> 2));
478 else /* 422 */
479 paddr->cr = (u32)(paddr->cb
480 + (pix_size >> 1));
481 break;
482 default:
483 return -EINVAL;
484 }
485 } else {
486 if (frame->fmt->memplanes >= 2)
487 paddr->cb = vb2_dma_contig_plane_paddr(vb, 1);
488
489 if (frame->fmt->memplanes == 3)
490 paddr->cr = vb2_dma_contig_plane_paddr(vb, 2);
491 }
492
493 dbg("PHYS_ADDR: y= 0x%X cb= 0x%X cr= 0x%X ret= %d",
494 paddr->y, paddr->cb, paddr->cr, ret);
495
496 return ret;
497 }
498
499 /* Set order for 1 and 2 plane YCBCR 4:2:2 formats. */
500 static void fimc_set_yuv_order(struct fimc_ctx *ctx)
501 {
502 /* The one only mode supported in SoC. */
503 ctx->in_order_2p = S5P_FIMC_LSB_CRCB;
504 ctx->out_order_2p = S5P_FIMC_LSB_CRCB;
505
506 /* Set order for 1 plane input formats. */
507 switch (ctx->s_frame.fmt->color) {
508 case S5P_FIMC_YCRYCB422:
509 ctx->in_order_1p = S5P_MSCTRL_ORDER422_CBYCRY;
510 break;
511 case S5P_FIMC_CBYCRY422:
512 ctx->in_order_1p = S5P_MSCTRL_ORDER422_YCRYCB;
513 break;
514 case S5P_FIMC_CRYCBY422:
515 ctx->in_order_1p = S5P_MSCTRL_ORDER422_YCBYCR;
516 break;
517 case S5P_FIMC_YCBYCR422:
518 default:
519 ctx->in_order_1p = S5P_MSCTRL_ORDER422_CRYCBY;
520 break;
521 }
522 dbg("ctx->in_order_1p= %d", ctx->in_order_1p);
523
524 switch (ctx->d_frame.fmt->color) {
525 case S5P_FIMC_YCRYCB422:
526 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_CBYCRY;
527 break;
528 case S5P_FIMC_CBYCRY422:
529 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_YCRYCB;
530 break;
531 case S5P_FIMC_CRYCBY422:
532 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_YCBYCR;
533 break;
534 case S5P_FIMC_YCBYCR422:
535 default:
536 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_CRYCBY;
537 break;
538 }
539 dbg("ctx->out_order_1p= %d", ctx->out_order_1p);
540 }
541
542 static void fimc_prepare_dma_offset(struct fimc_ctx *ctx, struct fimc_frame *f)
543 {
544 struct samsung_fimc_variant *variant = ctx->fimc_dev->variant;
545 u32 i, depth = 0;
546
547 for (i = 0; i < f->fmt->colplanes; i++)
548 depth += f->fmt->depth[i];
549
550 f->dma_offset.y_h = f->offs_h;
551 if (!variant->pix_hoff)
552 f->dma_offset.y_h *= (depth >> 3);
553
554 f->dma_offset.y_v = f->offs_v;
555
556 f->dma_offset.cb_h = f->offs_h;
557 f->dma_offset.cb_v = f->offs_v;
558
559 f->dma_offset.cr_h = f->offs_h;
560 f->dma_offset.cr_v = f->offs_v;
561
562 if (!variant->pix_hoff) {
563 if (f->fmt->colplanes == 3) {
564 f->dma_offset.cb_h >>= 1;
565 f->dma_offset.cr_h >>= 1;
566 }
567 if (f->fmt->color == S5P_FIMC_YCBCR420) {
568 f->dma_offset.cb_v >>= 1;
569 f->dma_offset.cr_v >>= 1;
570 }
571 }
572
573 dbg("in_offset: color= %d, y_h= %d, y_v= %d",
574 f->fmt->color, f->dma_offset.y_h, f->dma_offset.y_v);
575 }
576
577 /**
578 * fimc_prepare_config - check dimensions, operation and color mode
579 * and pre-calculate offset and the scaling coefficients.
580 *
581 * @ctx: hardware context information
582 * @flags: flags indicating which parameters to check/update
583 *
584 * Return: 0 if dimensions are valid or non zero otherwise.
585 */
586 int fimc_prepare_config(struct fimc_ctx *ctx, u32 flags)
587 {
588 struct fimc_frame *s_frame, *d_frame;
589 struct vb2_buffer *vb = NULL;
590 int ret = 0;
591
592 s_frame = &ctx->s_frame;
593 d_frame = &ctx->d_frame;
594
595 if (flags & FIMC_PARAMS) {
596 /* Prepare the DMA offset ratios for scaler. */
597 fimc_prepare_dma_offset(ctx, &ctx->s_frame);
598 fimc_prepare_dma_offset(ctx, &ctx->d_frame);
599
600 if (s_frame->height > (SCALER_MAX_VRATIO * d_frame->height) ||
601 s_frame->width > (SCALER_MAX_HRATIO * d_frame->width)) {
602 err("out of scaler range");
603 return -EINVAL;
604 }
605 fimc_set_yuv_order(ctx);
606 }
607
608 /* Input DMA mode is not allowed when the scaler is disabled. */
609 ctx->scaler.enabled = 1;
610
611 if (flags & FIMC_SRC_ADDR) {
612 vb = v4l2_m2m_next_src_buf(ctx->m2m_ctx);
613 ret = fimc_prepare_addr(ctx, vb, s_frame, &s_frame->paddr);
614 if (ret)
615 return ret;
616 }
617
618 if (flags & FIMC_DST_ADDR) {
619 vb = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
620 ret = fimc_prepare_addr(ctx, vb, d_frame, &d_frame->paddr);
621 }
622
623 return ret;
624 }
625
626 static void fimc_dma_run(void *priv)
627 {
628 struct fimc_ctx *ctx = priv;
629 struct fimc_dev *fimc;
630 unsigned long flags;
631 u32 ret;
632
633 if (WARN(!ctx, "null hardware context\n"))
634 return;
635
636 fimc = ctx->fimc_dev;
637
638 spin_lock_irqsave(&ctx->slock, flags);
639 set_bit(ST_M2M_PEND, &fimc->state);
640
641 ctx->state |= (FIMC_SRC_ADDR | FIMC_DST_ADDR);
642 ret = fimc_prepare_config(ctx, ctx->state);
643 if (ret)
644 goto dma_unlock;
645
646 /* Reconfigure hardware if the context has changed. */
647 if (fimc->m2m.ctx != ctx) {
648 ctx->state |= FIMC_PARAMS;
649 fimc->m2m.ctx = ctx;
650 }
651
652 spin_lock(&fimc->slock);
653 fimc_hw_set_input_addr(fimc, &ctx->s_frame.paddr);
654
655 if (ctx->state & FIMC_PARAMS) {
656 fimc_hw_set_input_path(ctx);
657 fimc_hw_set_in_dma(ctx);
658 ret = fimc_set_scaler_info(ctx);
659 if (ret) {
660 spin_unlock(&fimc->slock);
661 goto dma_unlock;
662 }
663 fimc_hw_set_prescaler(ctx);
664 fimc_hw_set_mainscaler(ctx);
665 fimc_hw_set_target_format(ctx);
666 fimc_hw_set_rotation(ctx);
667 fimc_hw_set_effect(ctx);
668 }
669
670 fimc_hw_set_output_path(ctx);
671 if (ctx->state & (FIMC_DST_ADDR | FIMC_PARAMS))
672 fimc_hw_set_output_addr(fimc, &ctx->d_frame.paddr, -1);
673
674 if (ctx->state & FIMC_PARAMS)
675 fimc_hw_set_out_dma(ctx);
676
677 fimc_activate_capture(ctx);
678
679 ctx->state &= (FIMC_CTX_M2M | FIMC_CTX_CAP |
680 FIMC_SRC_FMT | FIMC_DST_FMT);
681 fimc_hw_activate_input_dma(fimc, true);
682 spin_unlock(&fimc->slock);
683
684 dma_unlock:
685 spin_unlock_irqrestore(&ctx->slock, flags);
686 }
687
688 static void fimc_job_abort(void *priv)
689 {
690 fimc_m2m_shutdown(priv);
691 }
692
693 static int fimc_queue_setup(struct vb2_queue *vq, unsigned int *num_buffers,
694 unsigned int *num_planes, unsigned long sizes[],
695 void *allocators[])
696 {
697 struct fimc_ctx *ctx = vb2_get_drv_priv(vq);
698 struct fimc_frame *f;
699 int i;
700
701 f = ctx_get_frame(ctx, vq->type);
702 if (IS_ERR(f))
703 return PTR_ERR(f);
704
705 /*
706 * Return number of non-contigous planes (plane buffers)
707 * depending on the configured color format.
708 */
709 if (f->fmt)
710 *num_planes = f->fmt->memplanes;
711
712 for (i = 0; i < f->fmt->memplanes; i++) {
713 sizes[i] = (f->width * f->height * f->fmt->depth[i]) >> 3;
714 allocators[i] = ctx->fimc_dev->alloc_ctx;
715 }
716
717 if (*num_buffers == 0)
718 *num_buffers = 1;
719
720 return 0;
721 }
722
723 static int fimc_buf_prepare(struct vb2_buffer *vb)
724 {
725 struct fimc_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
726 struct fimc_frame *frame;
727 int i;
728
729 frame = ctx_get_frame(ctx, vb->vb2_queue->type);
730 if (IS_ERR(frame))
731 return PTR_ERR(frame);
732
733 for (i = 0; i < frame->fmt->memplanes; i++)
734 vb2_set_plane_payload(vb, i, frame->payload[i]);
735
736 return 0;
737 }
738
739 static void fimc_buf_queue(struct vb2_buffer *vb)
740 {
741 struct fimc_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
742
743 dbg("ctx: %p, ctx->state: 0x%x", ctx, ctx->state);
744
745 if (ctx->m2m_ctx)
746 v4l2_m2m_buf_queue(ctx->m2m_ctx, vb);
747 }
748
749 static void fimc_lock(struct vb2_queue *vq)
750 {
751 struct fimc_ctx *ctx = vb2_get_drv_priv(vq);
752 mutex_lock(&ctx->fimc_dev->lock);
753 }
754
755 static void fimc_unlock(struct vb2_queue *vq)
756 {
757 struct fimc_ctx *ctx = vb2_get_drv_priv(vq);
758 mutex_unlock(&ctx->fimc_dev->lock);
759 }
760
761 struct vb2_ops fimc_qops = {
762 .queue_setup = fimc_queue_setup,
763 .buf_prepare = fimc_buf_prepare,
764 .buf_queue = fimc_buf_queue,
765 .wait_prepare = fimc_unlock,
766 .wait_finish = fimc_lock,
767 .stop_streaming = stop_streaming,
768 };
769
770 static int fimc_m2m_querycap(struct file *file, void *priv,
771 struct v4l2_capability *cap)
772 {
773 struct fimc_ctx *ctx = file->private_data;
774 struct fimc_dev *fimc = ctx->fimc_dev;
775
776 strncpy(cap->driver, fimc->pdev->name, sizeof(cap->driver) - 1);
777 strncpy(cap->card, fimc->pdev->name, sizeof(cap->card) - 1);
778 cap->bus_info[0] = 0;
779 cap->version = KERNEL_VERSION(1, 0, 0);
780 cap->capabilities = V4L2_CAP_STREAMING |
781 V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_VIDEO_OUTPUT |
782 V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_VIDEO_OUTPUT_MPLANE;
783
784 return 0;
785 }
786
787 int fimc_vidioc_enum_fmt_mplane(struct file *file, void *priv,
788 struct v4l2_fmtdesc *f)
789 {
790 struct fimc_fmt *fmt;
791
792 if (f->index >= ARRAY_SIZE(fimc_formats))
793 return -EINVAL;
794
795 fmt = &fimc_formats[f->index];
796 strncpy(f->description, fmt->name, sizeof(f->description) - 1);
797 f->pixelformat = fmt->fourcc;
798
799 return 0;
800 }
801
802 int fimc_vidioc_g_fmt_mplane(struct file *file, void *priv,
803 struct v4l2_format *f)
804 {
805 struct fimc_ctx *ctx = priv;
806 struct fimc_frame *frame;
807 struct v4l2_pix_format_mplane *pixm;
808 int i;
809
810 frame = ctx_get_frame(ctx, f->type);
811 if (IS_ERR(frame))
812 return PTR_ERR(frame);
813
814 pixm = &f->fmt.pix_mp;
815
816 pixm->width = frame->width;
817 pixm->height = frame->height;
818 pixm->field = V4L2_FIELD_NONE;
819 pixm->pixelformat = frame->fmt->fourcc;
820 pixm->colorspace = V4L2_COLORSPACE_JPEG;
821 pixm->num_planes = frame->fmt->memplanes;
822
823 for (i = 0; i < pixm->num_planes; ++i) {
824 int bpl = frame->o_width;
825
826 if (frame->fmt->colplanes == 1) /* packed formats */
827 bpl = (bpl * frame->fmt->depth[0]) / 8;
828
829 pixm->plane_fmt[i].bytesperline = bpl;
830
831 pixm->plane_fmt[i].sizeimage = (frame->o_width *
832 frame->o_height * frame->fmt->depth[i]) / 8;
833 }
834
835 return 0;
836 }
837
838 struct fimc_fmt *find_format(struct v4l2_format *f, unsigned int mask)
839 {
840 struct fimc_fmt *fmt;
841 unsigned int i;
842
843 for (i = 0; i < ARRAY_SIZE(fimc_formats); ++i) {
844 fmt = &fimc_formats[i];
845 if (fmt->fourcc == f->fmt.pix.pixelformat &&
846 (fmt->flags & mask))
847 break;
848 }
849
850 return (i == ARRAY_SIZE(fimc_formats)) ? NULL : fmt;
851 }
852
853 struct fimc_fmt *find_mbus_format(struct v4l2_mbus_framefmt *f,
854 unsigned int mask)
855 {
856 struct fimc_fmt *fmt;
857 unsigned int i;
858
859 for (i = 0; i < ARRAY_SIZE(fimc_formats); ++i) {
860 fmt = &fimc_formats[i];
861 if (fmt->mbus_code == f->code && (fmt->flags & mask))
862 break;
863 }
864
865 return (i == ARRAY_SIZE(fimc_formats)) ? NULL : fmt;
866 }
867
868
869 int fimc_vidioc_try_fmt_mplane(struct file *file, void *priv,
870 struct v4l2_format *f)
871 {
872 struct fimc_ctx *ctx = priv;
873 struct fimc_dev *fimc = ctx->fimc_dev;
874 struct samsung_fimc_variant *variant = fimc->variant;
875 struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
876 struct fimc_fmt *fmt;
877 u32 max_width, mod_x, mod_y, mask;
878 int i, is_output = 0;
879
880
881 if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
882 if (fimc_ctx_state_is_set(FIMC_CTX_CAP, ctx))
883 return -EINVAL;
884 is_output = 1;
885 } else if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
886 return -EINVAL;
887 }
888
889 dbg("w: %d, h: %d", pix->width, pix->height);
890
891 mask = is_output ? FMT_FLAGS_M2M : FMT_FLAGS_M2M | FMT_FLAGS_CAM;
892 fmt = find_format(f, mask);
893 if (!fmt) {
894 v4l2_err(&fimc->m2m.v4l2_dev, "Fourcc format (0x%X) invalid.\n",
895 pix->pixelformat);
896 return -EINVAL;
897 }
898
899 if (pix->field == V4L2_FIELD_ANY)
900 pix->field = V4L2_FIELD_NONE;
901 else if (V4L2_FIELD_NONE != pix->field)
902 return -EINVAL;
903
904 if (is_output) {
905 max_width = variant->pix_limit->scaler_dis_w;
906 mod_x = ffs(variant->min_inp_pixsize) - 1;
907 } else {
908 max_width = variant->pix_limit->out_rot_dis_w;
909 mod_x = ffs(variant->min_out_pixsize) - 1;
910 }
911
912 if (tiled_fmt(fmt)) {
913 mod_x = 6; /* 64 x 32 pixels tile */
914 mod_y = 5;
915 } else {
916 if (fimc->id == 1 && variant->pix_hoff)
917 mod_y = fimc_fmt_is_rgb(fmt->color) ? 0 : 1;
918 else
919 mod_y = mod_x;
920 }
921
922 dbg("mod_x: %d, mod_y: %d, max_w: %d", mod_x, mod_y, max_width);
923
924 v4l_bound_align_image(&pix->width, 16, max_width, mod_x,
925 &pix->height, 8, variant->pix_limit->scaler_dis_w, mod_y, 0);
926
927 pix->num_planes = fmt->memplanes;
928 pix->colorspace = V4L2_COLORSPACE_JPEG;
929
930 for (i = 0; i < pix->num_planes; ++i) {
931 int bpl = pix->plane_fmt[i].bytesperline;
932
933 dbg("[%d] bpl: %d, depth: %d, w: %d, h: %d",
934 i, bpl, fmt->depth[i], pix->width, pix->height);
935
936 if (!bpl || (bpl * 8 / fmt->depth[i]) > pix->width)
937 bpl = (pix->width * fmt->depth[0]) >> 3;
938
939 if (!pix->plane_fmt[i].sizeimage)
940 pix->plane_fmt[i].sizeimage = pix->height * bpl;
941
942 pix->plane_fmt[i].bytesperline = bpl;
943
944 dbg("[%d]: bpl: %d, sizeimage: %d",
945 i, pix->plane_fmt[i].bytesperline,
946 pix->plane_fmt[i].sizeimage);
947 }
948
949 return 0;
950 }
951
952 static int fimc_m2m_s_fmt_mplane(struct file *file, void *priv,
953 struct v4l2_format *f)
954 {
955 struct fimc_ctx *ctx = priv;
956 struct fimc_dev *fimc = ctx->fimc_dev;
957 struct vb2_queue *vq;
958 struct fimc_frame *frame;
959 struct v4l2_pix_format_mplane *pix;
960 int i, ret = 0;
961
962 ret = fimc_vidioc_try_fmt_mplane(file, priv, f);
963 if (ret)
964 return ret;
965
966 vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
967
968 if (vb2_is_streaming(vq)) {
969 v4l2_err(&fimc->m2m.v4l2_dev, "queue (%d) busy\n", f->type);
970 return -EBUSY;
971 }
972
973 if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
974 frame = &ctx->s_frame;
975 } else if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
976 frame = &ctx->d_frame;
977 } else {
978 v4l2_err(&fimc->m2m.v4l2_dev,
979 "Wrong buffer/video queue type (%d)\n", f->type);
980 return -EINVAL;
981 }
982
983 pix = &f->fmt.pix_mp;
984 frame->fmt = find_format(f, FMT_FLAGS_M2M);
985 if (!frame->fmt)
986 return -EINVAL;
987
988 for (i = 0; i < frame->fmt->colplanes; i++)
989 frame->payload[i] = pix->plane_fmt[i].bytesperline * pix->height;
990
991 frame->f_width = pix->plane_fmt[0].bytesperline * 8 /
992 frame->fmt->depth[0];
993 frame->f_height = pix->height;
994 frame->width = pix->width;
995 frame->height = pix->height;
996 frame->o_width = pix->width;
997 frame->o_height = pix->height;
998 frame->offs_h = 0;
999 frame->offs_v = 0;
1000
1001 if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
1002 fimc_ctx_state_lock_set(FIMC_PARAMS | FIMC_DST_FMT, ctx);
1003 else
1004 fimc_ctx_state_lock_set(FIMC_PARAMS | FIMC_SRC_FMT, ctx);
1005
1006 dbg("f_w: %d, f_h: %d", frame->f_width, frame->f_height);
1007
1008 return 0;
1009 }
1010
1011 static int fimc_m2m_reqbufs(struct file *file, void *priv,
1012 struct v4l2_requestbuffers *reqbufs)
1013 {
1014 struct fimc_ctx *ctx = priv;
1015 return v4l2_m2m_reqbufs(file, ctx->m2m_ctx, reqbufs);
1016 }
1017
1018 static int fimc_m2m_querybuf(struct file *file, void *priv,
1019 struct v4l2_buffer *buf)
1020 {
1021 struct fimc_ctx *ctx = priv;
1022 return v4l2_m2m_querybuf(file, ctx->m2m_ctx, buf);
1023 }
1024
1025 static int fimc_m2m_qbuf(struct file *file, void *priv,
1026 struct v4l2_buffer *buf)
1027 {
1028 struct fimc_ctx *ctx = priv;
1029
1030 return v4l2_m2m_qbuf(file, ctx->m2m_ctx, buf);
1031 }
1032
1033 static int fimc_m2m_dqbuf(struct file *file, void *priv,
1034 struct v4l2_buffer *buf)
1035 {
1036 struct fimc_ctx *ctx = priv;
1037 return v4l2_m2m_dqbuf(file, ctx->m2m_ctx, buf);
1038 }
1039
1040 static int fimc_m2m_streamon(struct file *file, void *priv,
1041 enum v4l2_buf_type type)
1042 {
1043 struct fimc_ctx *ctx = priv;
1044
1045 /* The source and target color format need to be set */
1046 if (V4L2_TYPE_IS_OUTPUT(type)) {
1047 if (!fimc_ctx_state_is_set(FIMC_SRC_FMT, ctx))
1048 return -EINVAL;
1049 } else if (!fimc_ctx_state_is_set(FIMC_DST_FMT, ctx)) {
1050 return -EINVAL;
1051 }
1052
1053 return v4l2_m2m_streamon(file, ctx->m2m_ctx, type);
1054 }
1055
1056 static int fimc_m2m_streamoff(struct file *file, void *priv,
1057 enum v4l2_buf_type type)
1058 {
1059 struct fimc_ctx *ctx = priv;
1060 return v4l2_m2m_streamoff(file, ctx->m2m_ctx, type);
1061 }
1062
1063 int fimc_vidioc_queryctrl(struct file *file, void *priv,
1064 struct v4l2_queryctrl *qc)
1065 {
1066 struct fimc_ctx *ctx = priv;
1067 struct v4l2_queryctrl *c;
1068 int ret = -EINVAL;
1069
1070 c = get_ctrl(qc->id);
1071 if (c) {
1072 *qc = *c;
1073 return 0;
1074 }
1075
1076 if (fimc_ctx_state_is_set(FIMC_CTX_CAP, ctx)) {
1077 return v4l2_subdev_call(ctx->fimc_dev->vid_cap.sd,
1078 core, queryctrl, qc);
1079 }
1080 return ret;
1081 }
1082
1083 int fimc_vidioc_g_ctrl(struct file *file, void *priv,
1084 struct v4l2_control *ctrl)
1085 {
1086 struct fimc_ctx *ctx = priv;
1087 struct fimc_dev *fimc = ctx->fimc_dev;
1088
1089 switch (ctrl->id) {
1090 case V4L2_CID_HFLIP:
1091 ctrl->value = (FLIP_X_AXIS & ctx->flip) ? 1 : 0;
1092 break;
1093 case V4L2_CID_VFLIP:
1094 ctrl->value = (FLIP_Y_AXIS & ctx->flip) ? 1 : 0;
1095 break;
1096 case V4L2_CID_ROTATE:
1097 ctrl->value = ctx->rotation;
1098 break;
1099 default:
1100 if (fimc_ctx_state_is_set(FIMC_CTX_CAP, ctx)) {
1101 return v4l2_subdev_call(fimc->vid_cap.sd, core,
1102 g_ctrl, ctrl);
1103 } else {
1104 v4l2_err(&fimc->m2m.v4l2_dev, "Invalid control\n");
1105 return -EINVAL;
1106 }
1107 }
1108 dbg("ctrl->value= %d", ctrl->value);
1109
1110 return 0;
1111 }
1112
1113 int check_ctrl_val(struct fimc_ctx *ctx, struct v4l2_control *ctrl)
1114 {
1115 struct v4l2_queryctrl *c;
1116 c = get_ctrl(ctrl->id);
1117 if (!c)
1118 return -EINVAL;
1119
1120 if (ctrl->value < c->minimum || ctrl->value > c->maximum
1121 || (c->step != 0 && ctrl->value % c->step != 0)) {
1122 v4l2_err(&ctx->fimc_dev->m2m.v4l2_dev,
1123 "Invalid control value\n");
1124 return -ERANGE;
1125 }
1126
1127 return 0;
1128 }
1129
1130 int fimc_s_ctrl(struct fimc_ctx *ctx, struct v4l2_control *ctrl)
1131 {
1132 struct samsung_fimc_variant *variant = ctx->fimc_dev->variant;
1133 struct fimc_dev *fimc = ctx->fimc_dev;
1134 int ret = 0;
1135
1136 switch (ctrl->id) {
1137 case V4L2_CID_HFLIP:
1138 if (ctrl->value)
1139 ctx->flip |= FLIP_X_AXIS;
1140 else
1141 ctx->flip &= ~FLIP_X_AXIS;
1142 break;
1143
1144 case V4L2_CID_VFLIP:
1145 if (ctrl->value)
1146 ctx->flip |= FLIP_Y_AXIS;
1147 else
1148 ctx->flip &= ~FLIP_Y_AXIS;
1149 break;
1150
1151 case V4L2_CID_ROTATE:
1152 if (fimc_ctx_state_is_set(FIMC_DST_FMT | FIMC_SRC_FMT, ctx)) {
1153 ret = fimc_check_scaler_ratio(ctx->s_frame.width,
1154 ctx->s_frame.height, ctx->d_frame.width,
1155 ctx->d_frame.height, ctrl->value);
1156 }
1157
1158 if (ret) {
1159 v4l2_err(&fimc->m2m.v4l2_dev, "Out of scaler range\n");
1160 return -EINVAL;
1161 }
1162
1163 /* Check for the output rotator availability */
1164 if ((ctrl->value == 90 || ctrl->value == 270) &&
1165 (ctx->in_path == FIMC_DMA && !variant->has_out_rot))
1166 return -EINVAL;
1167 ctx->rotation = ctrl->value;
1168 break;
1169
1170 default:
1171 v4l2_err(&fimc->m2m.v4l2_dev, "Invalid control\n");
1172 return -EINVAL;
1173 }
1174
1175 fimc_ctx_state_lock_set(FIMC_PARAMS, ctx);
1176
1177 return 0;
1178 }
1179
1180 static int fimc_m2m_s_ctrl(struct file *file, void *priv,
1181 struct v4l2_control *ctrl)
1182 {
1183 struct fimc_ctx *ctx = priv;
1184 int ret = 0;
1185
1186 ret = check_ctrl_val(ctx, ctrl);
1187 if (ret)
1188 return ret;
1189
1190 ret = fimc_s_ctrl(ctx, ctrl);
1191 return 0;
1192 }
1193
1194 static int fimc_m2m_cropcap(struct file *file, void *fh,
1195 struct v4l2_cropcap *cr)
1196 {
1197 struct fimc_frame *frame;
1198 struct fimc_ctx *ctx = fh;
1199
1200 frame = ctx_get_frame(ctx, cr->type);
1201 if (IS_ERR(frame))
1202 return PTR_ERR(frame);
1203
1204 cr->bounds.left = 0;
1205 cr->bounds.top = 0;
1206 cr->bounds.width = frame->f_width;
1207 cr->bounds.height = frame->f_height;
1208 cr->defrect = cr->bounds;
1209
1210 return 0;
1211 }
1212
1213 static int fimc_m2m_g_crop(struct file *file, void *fh, struct v4l2_crop *cr)
1214 {
1215 struct fimc_frame *frame;
1216 struct fimc_ctx *ctx = file->private_data;
1217
1218 frame = ctx_get_frame(ctx, cr->type);
1219 if (IS_ERR(frame))
1220 return PTR_ERR(frame);
1221
1222 cr->c.left = frame->offs_h;
1223 cr->c.top = frame->offs_v;
1224 cr->c.width = frame->width;
1225 cr->c.height = frame->height;
1226
1227 return 0;
1228 }
1229
1230 int fimc_try_crop(struct fimc_ctx *ctx, struct v4l2_crop *cr)
1231 {
1232 struct fimc_dev *fimc = ctx->fimc_dev;
1233 struct fimc_frame *f;
1234 u32 min_size, halign, depth = 0;
1235 bool is_capture_ctx;
1236 int i;
1237
1238 if (cr->c.top < 0 || cr->c.left < 0) {
1239 v4l2_err(&fimc->m2m.v4l2_dev,
1240 "doesn't support negative values for top & left\n");
1241 return -EINVAL;
1242 }
1243
1244 is_capture_ctx = fimc_ctx_state_is_set(FIMC_CTX_CAP, ctx);
1245
1246 if (cr->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
1247 f = is_capture_ctx ? &ctx->s_frame : &ctx->d_frame;
1248 else if (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE &&
1249 !is_capture_ctx)
1250 f = &ctx->s_frame;
1251 else
1252 return -EINVAL;
1253
1254 min_size = (f == &ctx->s_frame) ?
1255 fimc->variant->min_inp_pixsize : fimc->variant->min_out_pixsize;
1256
1257 /* Get pixel alignment constraints. */
1258 if (is_capture_ctx) {
1259 min_size = 16;
1260 halign = 4;
1261 } else {
1262 if (fimc->id == 1 && fimc->variant->pix_hoff)
1263 halign = fimc_fmt_is_rgb(f->fmt->color) ? 0 : 1;
1264 else
1265 halign = ffs(min_size) - 1;
1266 }
1267
1268 for (i = 0; i < f->fmt->colplanes; i++)
1269 depth += f->fmt->depth[i];
1270
1271 v4l_bound_align_image(&cr->c.width, min_size, f->o_width,
1272 ffs(min_size) - 1,
1273 &cr->c.height, min_size, f->o_height,
1274 halign, 64/(ALIGN(depth, 8)));
1275
1276 /* adjust left/top if cropping rectangle is out of bounds */
1277 if (cr->c.left + cr->c.width > f->o_width)
1278 cr->c.left = f->o_width - cr->c.width;
1279 if (cr->c.top + cr->c.height > f->o_height)
1280 cr->c.top = f->o_height - cr->c.height;
1281
1282 cr->c.left = round_down(cr->c.left, min_size);
1283 cr->c.top = round_down(cr->c.top, is_capture_ctx ? 16 : 8);
1284
1285 dbg("l:%d, t:%d, w:%d, h:%d, f_w: %d, f_h: %d",
1286 cr->c.left, cr->c.top, cr->c.width, cr->c.height,
1287 f->f_width, f->f_height);
1288
1289 return 0;
1290 }
1291
1292 static int fimc_m2m_s_crop(struct file *file, void *fh, struct v4l2_crop *cr)
1293 {
1294 struct fimc_ctx *ctx = file->private_data;
1295 struct fimc_dev *fimc = ctx->fimc_dev;
1296 struct fimc_frame *f;
1297 int ret;
1298
1299 ret = fimc_try_crop(ctx, cr);
1300 if (ret)
1301 return ret;
1302
1303 f = (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) ?
1304 &ctx->s_frame : &ctx->d_frame;
1305
1306 /* Check to see if scaling ratio is within supported range */
1307 if (fimc_ctx_state_is_set(FIMC_DST_FMT | FIMC_SRC_FMT, ctx)) {
1308 if (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
1309 ret = fimc_check_scaler_ratio(cr->c.width, cr->c.height,
1310 ctx->d_frame.width,
1311 ctx->d_frame.height,
1312 ctx->rotation);
1313 } else {
1314 ret = fimc_check_scaler_ratio(ctx->s_frame.width,
1315 ctx->s_frame.height,
1316 cr->c.width, cr->c.height,
1317 ctx->rotation);
1318 }
1319 if (ret) {
1320 v4l2_err(&fimc->m2m.v4l2_dev, "Out of scaler range\n");
1321 return -EINVAL;
1322 }
1323 }
1324
1325 f->offs_h = cr->c.left;
1326 f->offs_v = cr->c.top;
1327 f->width = cr->c.width;
1328 f->height = cr->c.height;
1329
1330 fimc_ctx_state_lock_set(FIMC_PARAMS, ctx);
1331
1332 return 0;
1333 }
1334
1335 static const struct v4l2_ioctl_ops fimc_m2m_ioctl_ops = {
1336 .vidioc_querycap = fimc_m2m_querycap,
1337
1338 .vidioc_enum_fmt_vid_cap_mplane = fimc_vidioc_enum_fmt_mplane,
1339 .vidioc_enum_fmt_vid_out_mplane = fimc_vidioc_enum_fmt_mplane,
1340
1341 .vidioc_g_fmt_vid_cap_mplane = fimc_vidioc_g_fmt_mplane,
1342 .vidioc_g_fmt_vid_out_mplane = fimc_vidioc_g_fmt_mplane,
1343
1344 .vidioc_try_fmt_vid_cap_mplane = fimc_vidioc_try_fmt_mplane,
1345 .vidioc_try_fmt_vid_out_mplane = fimc_vidioc_try_fmt_mplane,
1346
1347 .vidioc_s_fmt_vid_cap_mplane = fimc_m2m_s_fmt_mplane,
1348 .vidioc_s_fmt_vid_out_mplane = fimc_m2m_s_fmt_mplane,
1349
1350 .vidioc_reqbufs = fimc_m2m_reqbufs,
1351 .vidioc_querybuf = fimc_m2m_querybuf,
1352
1353 .vidioc_qbuf = fimc_m2m_qbuf,
1354 .vidioc_dqbuf = fimc_m2m_dqbuf,
1355
1356 .vidioc_streamon = fimc_m2m_streamon,
1357 .vidioc_streamoff = fimc_m2m_streamoff,
1358
1359 .vidioc_queryctrl = fimc_vidioc_queryctrl,
1360 .vidioc_g_ctrl = fimc_vidioc_g_ctrl,
1361 .vidioc_s_ctrl = fimc_m2m_s_ctrl,
1362
1363 .vidioc_g_crop = fimc_m2m_g_crop,
1364 .vidioc_s_crop = fimc_m2m_s_crop,
1365 .vidioc_cropcap = fimc_m2m_cropcap
1366
1367 };
1368
1369 static int queue_init(void *priv, struct vb2_queue *src_vq,
1370 struct vb2_queue *dst_vq)
1371 {
1372 struct fimc_ctx *ctx = priv;
1373 int ret;
1374
1375 memset(src_vq, 0, sizeof(*src_vq));
1376 src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
1377 src_vq->io_modes = VB2_MMAP | VB2_USERPTR;
1378 src_vq->drv_priv = ctx;
1379 src_vq->ops = &fimc_qops;
1380 src_vq->mem_ops = &vb2_dma_contig_memops;
1381 src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
1382
1383 ret = vb2_queue_init(src_vq);
1384 if (ret)
1385 return ret;
1386
1387 memset(dst_vq, 0, sizeof(*dst_vq));
1388 dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
1389 dst_vq->io_modes = VB2_MMAP | VB2_USERPTR;
1390 dst_vq->drv_priv = ctx;
1391 dst_vq->ops = &fimc_qops;
1392 dst_vq->mem_ops = &vb2_dma_contig_memops;
1393 dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
1394
1395 return vb2_queue_init(dst_vq);
1396 }
1397
1398 static int fimc_m2m_open(struct file *file)
1399 {
1400 struct fimc_dev *fimc = video_drvdata(file);
1401 struct fimc_ctx *ctx = NULL;
1402
1403 dbg("pid: %d, state: 0x%lx, refcnt: %d",
1404 task_pid_nr(current), fimc->state, fimc->vid_cap.refcnt);
1405
1406 /*
1407 * Return if the corresponding video capture node
1408 * is already opened.
1409 */
1410 if (fimc->vid_cap.refcnt > 0)
1411 return -EBUSY;
1412
1413 fimc->m2m.refcnt++;
1414 set_bit(ST_OUTDMA_RUN, &fimc->state);
1415
1416 ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
1417 if (!ctx)
1418 return -ENOMEM;
1419
1420 file->private_data = ctx;
1421 ctx->fimc_dev = fimc;
1422 /* Default color format */
1423 ctx->s_frame.fmt = &fimc_formats[0];
1424 ctx->d_frame.fmt = &fimc_formats[0];
1425 /* Setup the device context for mem2mem mode. */
1426 ctx->state = FIMC_CTX_M2M;
1427 ctx->flags = 0;
1428 ctx->in_path = FIMC_DMA;
1429 ctx->out_path = FIMC_DMA;
1430 spin_lock_init(&ctx->slock);
1431
1432 ctx->m2m_ctx = v4l2_m2m_ctx_init(fimc->m2m.m2m_dev, ctx, queue_init);
1433 if (IS_ERR(ctx->m2m_ctx)) {
1434 int err = PTR_ERR(ctx->m2m_ctx);
1435 kfree(ctx);
1436 return err;
1437 }
1438
1439 return 0;
1440 }
1441
1442 static int fimc_m2m_release(struct file *file)
1443 {
1444 struct fimc_ctx *ctx = file->private_data;
1445 struct fimc_dev *fimc = ctx->fimc_dev;
1446
1447 dbg("pid: %d, state: 0x%lx, refcnt= %d",
1448 task_pid_nr(current), fimc->state, fimc->m2m.refcnt);
1449
1450 v4l2_m2m_ctx_release(ctx->m2m_ctx);
1451 kfree(ctx);
1452 if (--fimc->m2m.refcnt <= 0)
1453 clear_bit(ST_OUTDMA_RUN, &fimc->state);
1454
1455 return 0;
1456 }
1457
1458 static unsigned int fimc_m2m_poll(struct file *file,
1459 struct poll_table_struct *wait)
1460 {
1461 struct fimc_ctx *ctx = file->private_data;
1462
1463 return v4l2_m2m_poll(file, ctx->m2m_ctx, wait);
1464 }
1465
1466
1467 static int fimc_m2m_mmap(struct file *file, struct vm_area_struct *vma)
1468 {
1469 struct fimc_ctx *ctx = file->private_data;
1470
1471 return v4l2_m2m_mmap(file, ctx->m2m_ctx, vma);
1472 }
1473
1474 static const struct v4l2_file_operations fimc_m2m_fops = {
1475 .owner = THIS_MODULE,
1476 .open = fimc_m2m_open,
1477 .release = fimc_m2m_release,
1478 .poll = fimc_m2m_poll,
1479 .unlocked_ioctl = video_ioctl2,
1480 .mmap = fimc_m2m_mmap,
1481 };
1482
1483 static struct v4l2_m2m_ops m2m_ops = {
1484 .device_run = fimc_dma_run,
1485 .job_abort = fimc_job_abort,
1486 };
1487
1488 static int fimc_register_m2m_device(struct fimc_dev *fimc)
1489 {
1490 struct video_device *vfd;
1491 struct platform_device *pdev;
1492 struct v4l2_device *v4l2_dev;
1493 int ret = 0;
1494
1495 if (!fimc)
1496 return -ENODEV;
1497
1498 pdev = fimc->pdev;
1499 v4l2_dev = &fimc->m2m.v4l2_dev;
1500
1501 /* set name if it is empty */
1502 if (!v4l2_dev->name[0])
1503 snprintf(v4l2_dev->name, sizeof(v4l2_dev->name),
1504 "%s.m2m", dev_name(&pdev->dev));
1505
1506 ret = v4l2_device_register(&pdev->dev, v4l2_dev);
1507 if (ret)
1508 goto err_m2m_r1;
1509
1510 vfd = video_device_alloc();
1511 if (!vfd) {
1512 v4l2_err(v4l2_dev, "Failed to allocate video device\n");
1513 goto err_m2m_r1;
1514 }
1515
1516 vfd->fops = &fimc_m2m_fops;
1517 vfd->ioctl_ops = &fimc_m2m_ioctl_ops;
1518 vfd->minor = -1;
1519 vfd->release = video_device_release;
1520 vfd->lock = &fimc->lock;
1521
1522 snprintf(vfd->name, sizeof(vfd->name), "%s:m2m", dev_name(&pdev->dev));
1523
1524 video_set_drvdata(vfd, fimc);
1525 platform_set_drvdata(pdev, fimc);
1526
1527 fimc->m2m.vfd = vfd;
1528 fimc->m2m.m2m_dev = v4l2_m2m_init(&m2m_ops);
1529 if (IS_ERR(fimc->m2m.m2m_dev)) {
1530 v4l2_err(v4l2_dev, "failed to initialize v4l2-m2m device\n");
1531 ret = PTR_ERR(fimc->m2m.m2m_dev);
1532 goto err_m2m_r2;
1533 }
1534
1535 ret = video_register_device(vfd, VFL_TYPE_GRABBER, -1);
1536 if (ret) {
1537 v4l2_err(v4l2_dev,
1538 "%s(): failed to register video device\n", __func__);
1539 goto err_m2m_r3;
1540 }
1541 v4l2_info(v4l2_dev,
1542 "FIMC m2m driver registered as /dev/video%d\n", vfd->num);
1543
1544 return 0;
1545
1546 err_m2m_r3:
1547 v4l2_m2m_release(fimc->m2m.m2m_dev);
1548 err_m2m_r2:
1549 video_device_release(fimc->m2m.vfd);
1550 err_m2m_r1:
1551 v4l2_device_unregister(v4l2_dev);
1552
1553 return ret;
1554 }
1555
1556 static void fimc_unregister_m2m_device(struct fimc_dev *fimc)
1557 {
1558 if (fimc) {
1559 v4l2_m2m_release(fimc->m2m.m2m_dev);
1560 video_unregister_device(fimc->m2m.vfd);
1561
1562 v4l2_device_unregister(&fimc->m2m.v4l2_dev);
1563 }
1564 }
1565
1566 static void fimc_clk_release(struct fimc_dev *fimc)
1567 {
1568 int i;
1569 for (i = 0; i < fimc->num_clocks; i++) {
1570 if (fimc->clock[i]) {
1571 clk_disable(fimc->clock[i]);
1572 clk_put(fimc->clock[i]);
1573 }
1574 }
1575 }
1576
1577 static int fimc_clk_get(struct fimc_dev *fimc)
1578 {
1579 int i;
1580 for (i = 0; i < fimc->num_clocks; i++) {
1581 fimc->clock[i] = clk_get(&fimc->pdev->dev, fimc_clocks[i]);
1582
1583 if (!IS_ERR_OR_NULL(fimc->clock[i])) {
1584 clk_enable(fimc->clock[i]);
1585 continue;
1586 }
1587 dev_err(&fimc->pdev->dev, "failed to get fimc clock: %s\n",
1588 fimc_clocks[i]);
1589 return -ENXIO;
1590 }
1591 return 0;
1592 }
1593
1594 static int fimc_probe(struct platform_device *pdev)
1595 {
1596 struct fimc_dev *fimc;
1597 struct resource *res;
1598 struct samsung_fimc_driverdata *drv_data;
1599 struct s5p_platform_fimc *pdata;
1600 int ret = 0;
1601 int cap_input_index = -1;
1602
1603 dev_dbg(&pdev->dev, "%s():\n", __func__);
1604
1605 drv_data = (struct samsung_fimc_driverdata *)
1606 platform_get_device_id(pdev)->driver_data;
1607
1608 if (pdev->id >= drv_data->num_entities) {
1609 dev_err(&pdev->dev, "Invalid platform device id: %d\n",
1610 pdev->id);
1611 return -EINVAL;
1612 }
1613
1614 fimc = kzalloc(sizeof(struct fimc_dev), GFP_KERNEL);
1615 if (!fimc)
1616 return -ENOMEM;
1617
1618 fimc->id = pdev->id;
1619 fimc->variant = drv_data->variant[fimc->id];
1620 fimc->pdev = pdev;
1621 pdata = pdev->dev.platform_data;
1622 fimc->pdata = pdata;
1623 fimc->state = ST_IDLE;
1624
1625 init_waitqueue_head(&fimc->irq_queue);
1626 spin_lock_init(&fimc->slock);
1627
1628 mutex_init(&fimc->lock);
1629
1630 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1631 if (!res) {
1632 dev_err(&pdev->dev, "failed to find the registers\n");
1633 ret = -ENOENT;
1634 goto err_info;
1635 }
1636
1637 fimc->regs_res = request_mem_region(res->start, resource_size(res),
1638 dev_name(&pdev->dev));
1639 if (!fimc->regs_res) {
1640 dev_err(&pdev->dev, "failed to obtain register region\n");
1641 ret = -ENOENT;
1642 goto err_info;
1643 }
1644
1645 fimc->regs = ioremap(res->start, resource_size(res));
1646 if (!fimc->regs) {
1647 dev_err(&pdev->dev, "failed to map registers\n");
1648 ret = -ENXIO;
1649 goto err_req_region;
1650 }
1651
1652 fimc->num_clocks = MAX_FIMC_CLOCKS - 1;
1653
1654 /* Check if a video capture node needs to be registered. */
1655 if (pdata && pdata->num_clients > 0) {
1656 cap_input_index = 0;
1657 fimc->num_clocks++;
1658 }
1659
1660 ret = fimc_clk_get(fimc);
1661 if (ret)
1662 goto err_regs_unmap;
1663 clk_set_rate(fimc->clock[CLK_BUS], drv_data->lclk_frequency);
1664
1665 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1666 if (!res) {
1667 dev_err(&pdev->dev, "failed to get IRQ resource\n");
1668 ret = -ENXIO;
1669 goto err_clk;
1670 }
1671 fimc->irq = res->start;
1672
1673 fimc_hw_reset(fimc);
1674
1675 ret = request_irq(fimc->irq, fimc_isr, 0, pdev->name, fimc);
1676 if (ret) {
1677 dev_err(&pdev->dev, "failed to install irq (%d)\n", ret);
1678 goto err_clk;
1679 }
1680
1681 /* Initialize contiguous memory allocator */
1682 fimc->alloc_ctx = vb2_dma_contig_init_ctx(&fimc->pdev->dev);
1683 if (IS_ERR(fimc->alloc_ctx)) {
1684 ret = PTR_ERR(fimc->alloc_ctx);
1685 goto err_irq;
1686 }
1687
1688 ret = fimc_register_m2m_device(fimc);
1689 if (ret)
1690 goto err_irq;
1691
1692 /* At least one camera sensor is required to register capture node */
1693 if (cap_input_index >= 0) {
1694 ret = fimc_register_capture_device(fimc);
1695 if (ret)
1696 goto err_m2m;
1697 clk_disable(fimc->clock[CLK_CAM]);
1698 }
1699 /*
1700 * Exclude the additional output DMA address registers by masking
1701 * them out on HW revisions that provide extended capabilites.
1702 */
1703 if (fimc->variant->out_buf_count > 4)
1704 fimc_hw_set_dma_seq(fimc, 0xF);
1705
1706 dev_dbg(&pdev->dev, "%s(): fimc-%d registered successfully\n",
1707 __func__, fimc->id);
1708
1709 return 0;
1710
1711 err_m2m:
1712 fimc_unregister_m2m_device(fimc);
1713 err_irq:
1714 free_irq(fimc->irq, fimc);
1715 err_clk:
1716 fimc_clk_release(fimc);
1717 err_regs_unmap:
1718 iounmap(fimc->regs);
1719 err_req_region:
1720 release_resource(fimc->regs_res);
1721 kfree(fimc->regs_res);
1722 err_info:
1723 kfree(fimc);
1724
1725 return ret;
1726 }
1727
1728 static int __devexit fimc_remove(struct platform_device *pdev)
1729 {
1730 struct fimc_dev *fimc =
1731 (struct fimc_dev *)platform_get_drvdata(pdev);
1732
1733 free_irq(fimc->irq, fimc);
1734 fimc_hw_reset(fimc);
1735
1736 fimc_unregister_m2m_device(fimc);
1737 fimc_unregister_capture_device(fimc);
1738
1739 fimc_clk_release(fimc);
1740
1741 vb2_dma_contig_cleanup_ctx(fimc->alloc_ctx);
1742
1743 iounmap(fimc->regs);
1744 release_resource(fimc->regs_res);
1745 kfree(fimc->regs_res);
1746 kfree(fimc);
1747
1748 dev_info(&pdev->dev, "%s driver unloaded\n", pdev->name);
1749 return 0;
1750 }
1751
1752 /* Image pixel limits, similar across several FIMC HW revisions. */
1753 static struct fimc_pix_limit s5p_pix_limit[3] = {
1754 [0] = {
1755 .scaler_en_w = 3264,
1756 .scaler_dis_w = 8192,
1757 .in_rot_en_h = 1920,
1758 .in_rot_dis_w = 8192,
1759 .out_rot_en_w = 1920,
1760 .out_rot_dis_w = 4224,
1761 },
1762 [1] = {
1763 .scaler_en_w = 4224,
1764 .scaler_dis_w = 8192,
1765 .in_rot_en_h = 1920,
1766 .in_rot_dis_w = 8192,
1767 .out_rot_en_w = 1920,
1768 .out_rot_dis_w = 4224,
1769 },
1770 [2] = {
1771 .scaler_en_w = 1920,
1772 .scaler_dis_w = 8192,
1773 .in_rot_en_h = 1280,
1774 .in_rot_dis_w = 8192,
1775 .out_rot_en_w = 1280,
1776 .out_rot_dis_w = 1920,
1777 },
1778 };
1779
1780 static struct samsung_fimc_variant fimc0_variant_s5p = {
1781 .has_inp_rot = 1,
1782 .has_out_rot = 1,
1783 .min_inp_pixsize = 16,
1784 .min_out_pixsize = 16,
1785 .hor_offs_align = 8,
1786 .out_buf_count = 4,
1787 .pix_limit = &s5p_pix_limit[0],
1788 };
1789
1790 static struct samsung_fimc_variant fimc2_variant_s5p = {
1791 .min_inp_pixsize = 16,
1792 .min_out_pixsize = 16,
1793 .hor_offs_align = 8,
1794 .out_buf_count = 4,
1795 .pix_limit = &s5p_pix_limit[1],
1796 };
1797
1798 static struct samsung_fimc_variant fimc0_variant_s5pv210 = {
1799 .pix_hoff = 1,
1800 .has_inp_rot = 1,
1801 .has_out_rot = 1,
1802 .min_inp_pixsize = 16,
1803 .min_out_pixsize = 16,
1804 .hor_offs_align = 8,
1805 .out_buf_count = 4,
1806 .pix_limit = &s5p_pix_limit[1],
1807 };
1808
1809 static struct samsung_fimc_variant fimc1_variant_s5pv210 = {
1810 .pix_hoff = 1,
1811 .has_inp_rot = 1,
1812 .has_out_rot = 1,
1813 .has_mainscaler_ext = 1,
1814 .min_inp_pixsize = 16,
1815 .min_out_pixsize = 16,
1816 .hor_offs_align = 1,
1817 .out_buf_count = 4,
1818 .pix_limit = &s5p_pix_limit[2],
1819 };
1820
1821 static struct samsung_fimc_variant fimc2_variant_s5pv210 = {
1822 .pix_hoff = 1,
1823 .min_inp_pixsize = 16,
1824 .min_out_pixsize = 16,
1825 .hor_offs_align = 8,
1826 .out_buf_count = 4,
1827 .pix_limit = &s5p_pix_limit[2],
1828 };
1829
1830 static struct samsung_fimc_variant fimc0_variant_s5pv310 = {
1831 .pix_hoff = 1,
1832 .has_inp_rot = 1,
1833 .has_out_rot = 1,
1834 .has_cistatus2 = 1,
1835 .has_mainscaler_ext = 1,
1836 .min_inp_pixsize = 16,
1837 .min_out_pixsize = 16,
1838 .hor_offs_align = 1,
1839 .out_buf_count = 32,
1840 .pix_limit = &s5p_pix_limit[1],
1841 };
1842
1843 static struct samsung_fimc_variant fimc2_variant_s5pv310 = {
1844 .pix_hoff = 1,
1845 .has_cistatus2 = 1,
1846 .has_mainscaler_ext = 1,
1847 .min_inp_pixsize = 16,
1848 .min_out_pixsize = 16,
1849 .hor_offs_align = 1,
1850 .out_buf_count = 32,
1851 .pix_limit = &s5p_pix_limit[2],
1852 };
1853
1854 /* S5PC100 */
1855 static struct samsung_fimc_driverdata fimc_drvdata_s5p = {
1856 .variant = {
1857 [0] = &fimc0_variant_s5p,
1858 [1] = &fimc0_variant_s5p,
1859 [2] = &fimc2_variant_s5p,
1860 },
1861 .num_entities = 3,
1862 .lclk_frequency = 133000000UL,
1863 };
1864
1865 /* S5PV210, S5PC110 */
1866 static struct samsung_fimc_driverdata fimc_drvdata_s5pv210 = {
1867 .variant = {
1868 [0] = &fimc0_variant_s5pv210,
1869 [1] = &fimc1_variant_s5pv210,
1870 [2] = &fimc2_variant_s5pv210,
1871 },
1872 .num_entities = 3,
1873 .lclk_frequency = 166000000UL,
1874 };
1875
1876 /* S5PV310, S5PC210 */
1877 static struct samsung_fimc_driverdata fimc_drvdata_s5pv310 = {
1878 .variant = {
1879 [0] = &fimc0_variant_s5pv310,
1880 [1] = &fimc0_variant_s5pv310,
1881 [2] = &fimc0_variant_s5pv310,
1882 [3] = &fimc2_variant_s5pv310,
1883 },
1884 .num_entities = 4,
1885 .lclk_frequency = 166000000UL,
1886 };
1887
1888 static struct platform_device_id fimc_driver_ids[] = {
1889 {
1890 .name = "s5p-fimc",
1891 .driver_data = (unsigned long)&fimc_drvdata_s5p,
1892 }, {
1893 .name = "s5pv210-fimc",
1894 .driver_data = (unsigned long)&fimc_drvdata_s5pv210,
1895 }, {
1896 .name = "s5pv310-fimc",
1897 .driver_data = (unsigned long)&fimc_drvdata_s5pv310,
1898 },
1899 {},
1900 };
1901 MODULE_DEVICE_TABLE(platform, fimc_driver_ids);
1902
1903 static struct platform_driver fimc_driver = {
1904 .probe = fimc_probe,
1905 .remove = __devexit_p(fimc_remove),
1906 .id_table = fimc_driver_ids,
1907 .driver = {
1908 .name = MODULE_NAME,
1909 .owner = THIS_MODULE,
1910 }
1911 };
1912
1913 static int __init fimc_init(void)
1914 {
1915 int ret = platform_driver_register(&fimc_driver);
1916 if (ret)
1917 err("platform_driver_register failed: %d\n", ret);
1918 return ret;
1919 }
1920
1921 static void __exit fimc_exit(void)
1922 {
1923 platform_driver_unregister(&fimc_driver);
1924 }
1925
1926 module_init(fimc_init);
1927 module_exit(fimc_exit);
1928
1929 MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
1930 MODULE_DESCRIPTION("S5P FIMC camera host interface/video postprocessor driver");
1931 MODULE_LICENSE("GPL");
CRIS linux kernel tree