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FRV: Use generic show_interrupts()
[cris-mirror.git] / drivers / media / video / sn9c102 / sn9c102_ov7660.c
blob7977795d342b73b7d8d0f20773cf61e29ab0a934
1 /***************************************************************************
2 * Plug-in for OV7660 image sensor connected to the SN9C1xx PC Camera *
3 * Controllers *
4 * *
5 * Copyright (C) 2007 by Luca Risolia <luca.risolia@studio.unibo.it> *
6 * *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
11 * *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
16 * *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the Free Software *
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. *
20 ***************************************************************************/
21
22 #include "sn9c102_sensor.h"
23 #include "sn9c102_devtable.h"
24
25
26 static int ov7660_init(struct sn9c102_device* cam)
27 {
28 int err = 0;
29
30 err = sn9c102_write_const_regs(cam, {0x40, 0x02}, {0x00, 0x03},
31 {0x1a, 0x04}, {0x03, 0x10},
32 {0x08, 0x14}, {0x20, 0x17},
33 {0x8b, 0x18}, {0x00, 0x19},
34 {0x1d, 0x1a}, {0x10, 0x1b},
35 {0x02, 0x1c}, {0x03, 0x1d},
36 {0x0f, 0x1e}, {0x0c, 0x1f},
37 {0x00, 0x20}, {0x29, 0x21},
38 {0x40, 0x22}, {0x54, 0x23},
39 {0x66, 0x24}, {0x76, 0x25},
40 {0x85, 0x26}, {0x94, 0x27},
41 {0xa1, 0x28}, {0xae, 0x29},
42 {0xbb, 0x2a}, {0xc7, 0x2b},
43 {0xd3, 0x2c}, {0xde, 0x2d},
44 {0xea, 0x2e}, {0xf4, 0x2f},
45 {0xff, 0x30}, {0x00, 0x3f},
46 {0xc7, 0x40}, {0x01, 0x41},
47 {0x44, 0x42}, {0x00, 0x43},
48 {0x44, 0x44}, {0x00, 0x45},
49 {0x44, 0x46}, {0x00, 0x47},
50 {0xc7, 0x48}, {0x01, 0x49},
51 {0xc7, 0x4a}, {0x01, 0x4b},
52 {0xc7, 0x4c}, {0x01, 0x4d},
53 {0x44, 0x4e}, {0x00, 0x4f},
54 {0x44, 0x50}, {0x00, 0x51},
55 {0x44, 0x52}, {0x00, 0x53},
56 {0xc7, 0x54}, {0x01, 0x55},
57 {0xc7, 0x56}, {0x01, 0x57},
58 {0xc7, 0x58}, {0x01, 0x59},
59 {0x44, 0x5a}, {0x00, 0x5b},
60 {0x44, 0x5c}, {0x00, 0x5d},
61 {0x44, 0x5e}, {0x00, 0x5f},
62 {0xc7, 0x60}, {0x01, 0x61},
63 {0xc7, 0x62}, {0x01, 0x63},
64 {0xc7, 0x64}, {0x01, 0x65},
65 {0x44, 0x66}, {0x00, 0x67},
66 {0x44, 0x68}, {0x00, 0x69},
67 {0x44, 0x6a}, {0x00, 0x6b},
68 {0xc7, 0x6c}, {0x01, 0x6d},
69 {0xc7, 0x6e}, {0x01, 0x6f},
70 {0xc7, 0x70}, {0x01, 0x71},
71 {0x44, 0x72}, {0x00, 0x73},
72 {0x44, 0x74}, {0x00, 0x75},
73 {0x44, 0x76}, {0x00, 0x77},
74 {0xc7, 0x78}, {0x01, 0x79},
75 {0xc7, 0x7a}, {0x01, 0x7b},
76 {0xc7, 0x7c}, {0x01, 0x7d},
77 {0x44, 0x7e}, {0x00, 0x7f},
78 {0x14, 0x84}, {0x00, 0x85},
79 {0x27, 0x86}, {0x00, 0x87},
80 {0x07, 0x88}, {0x00, 0x89},
81 {0xec, 0x8a}, {0x0f, 0x8b},
82 {0xd8, 0x8c}, {0x0f, 0x8d},
83 {0x3d, 0x8e}, {0x00, 0x8f},
84 {0x3d, 0x90}, {0x00, 0x91},
85 {0xcd, 0x92}, {0x0f, 0x93},
86 {0xf7, 0x94}, {0x0f, 0x95},
87 {0x0c, 0x96}, {0x00, 0x97},
88 {0x00, 0x98}, {0x66, 0x99},
89 {0x05, 0x9a}, {0x00, 0x9b},
90 {0x04, 0x9c}, {0x00, 0x9d},
91 {0x08, 0x9e}, {0x00, 0x9f},
92 {0x2d, 0xc0}, {0x2d, 0xc1},
93 {0x3a, 0xc2}, {0x05, 0xc3},
94 {0x04, 0xc4}, {0x3f, 0xc5},
95 {0x00, 0xc6}, {0x00, 0xc7},
96 {0x50, 0xc8}, {0x3C, 0xc9},
97 {0x28, 0xca}, {0xd8, 0xcb},
98 {0x14, 0xcc}, {0xec, 0xcd},
99 {0x32, 0xce}, {0xdd, 0xcf},
100 {0x32, 0xd0}, {0xdd, 0xd1},
101 {0x6a, 0xd2}, {0x50, 0xd3},
102 {0x00, 0xd4}, {0x00, 0xd5},
103 {0x00, 0xd6});
104
105 err += sn9c102_i2c_write(cam, 0x12, 0x80);
106 err += sn9c102_i2c_write(cam, 0x11, 0x09);
107 err += sn9c102_i2c_write(cam, 0x00, 0x0A);
108 err += sn9c102_i2c_write(cam, 0x01, 0x80);
109 err += sn9c102_i2c_write(cam, 0x02, 0x80);
110 err += sn9c102_i2c_write(cam, 0x03, 0x00);
111 err += sn9c102_i2c_write(cam, 0x04, 0x00);
112 err += sn9c102_i2c_write(cam, 0x05, 0x08);
113 err += sn9c102_i2c_write(cam, 0x06, 0x0B);
114 err += sn9c102_i2c_write(cam, 0x07, 0x00);
115 err += sn9c102_i2c_write(cam, 0x08, 0x1C);
116 err += sn9c102_i2c_write(cam, 0x09, 0x01);
117 err += sn9c102_i2c_write(cam, 0x0A, 0x76);
118 err += sn9c102_i2c_write(cam, 0x0B, 0x60);
119 err += sn9c102_i2c_write(cam, 0x0C, 0x00);
120 err += sn9c102_i2c_write(cam, 0x0D, 0x08);
121 err += sn9c102_i2c_write(cam, 0x0E, 0x04);
122 err += sn9c102_i2c_write(cam, 0x0F, 0x6F);
123 err += sn9c102_i2c_write(cam, 0x10, 0x20);
124 err += sn9c102_i2c_write(cam, 0x11, 0x03);
125 err += sn9c102_i2c_write(cam, 0x12, 0x05);
126 err += sn9c102_i2c_write(cam, 0x13, 0xC7);
127 err += sn9c102_i2c_write(cam, 0x14, 0x2C);
128 err += sn9c102_i2c_write(cam, 0x15, 0x00);
129 err += sn9c102_i2c_write(cam, 0x16, 0x02);
130 err += sn9c102_i2c_write(cam, 0x17, 0x10);
131 err += sn9c102_i2c_write(cam, 0x18, 0x60);
132 err += sn9c102_i2c_write(cam, 0x19, 0x02);
133 err += sn9c102_i2c_write(cam, 0x1A, 0x7B);
134 err += sn9c102_i2c_write(cam, 0x1B, 0x02);
135 err += sn9c102_i2c_write(cam, 0x1C, 0x7F);
136 err += sn9c102_i2c_write(cam, 0x1D, 0xA2);
137 err += sn9c102_i2c_write(cam, 0x1E, 0x01);
138 err += sn9c102_i2c_write(cam, 0x1F, 0x0E);
139 err += sn9c102_i2c_write(cam, 0x20, 0x05);
140 err += sn9c102_i2c_write(cam, 0x21, 0x05);
141 err += sn9c102_i2c_write(cam, 0x22, 0x05);
142 err += sn9c102_i2c_write(cam, 0x23, 0x05);
143 err += sn9c102_i2c_write(cam, 0x24, 0x68);
144 err += sn9c102_i2c_write(cam, 0x25, 0x58);
145 err += sn9c102_i2c_write(cam, 0x26, 0xD4);
146 err += sn9c102_i2c_write(cam, 0x27, 0x80);
147 err += sn9c102_i2c_write(cam, 0x28, 0x80);
148 err += sn9c102_i2c_write(cam, 0x29, 0x30);
149 err += sn9c102_i2c_write(cam, 0x2A, 0x00);
150 err += sn9c102_i2c_write(cam, 0x2B, 0x00);
151 err += sn9c102_i2c_write(cam, 0x2C, 0x80);
152 err += sn9c102_i2c_write(cam, 0x2D, 0x00);
153 err += sn9c102_i2c_write(cam, 0x2E, 0x00);
154 err += sn9c102_i2c_write(cam, 0x2F, 0x0E);
155 err += sn9c102_i2c_write(cam, 0x30, 0x08);
156 err += sn9c102_i2c_write(cam, 0x31, 0x30);
157 err += sn9c102_i2c_write(cam, 0x32, 0xB4);
158 err += sn9c102_i2c_write(cam, 0x33, 0x00);
159 err += sn9c102_i2c_write(cam, 0x34, 0x07);
160 err += sn9c102_i2c_write(cam, 0x35, 0x84);
161 err += sn9c102_i2c_write(cam, 0x36, 0x00);
162 err += sn9c102_i2c_write(cam, 0x37, 0x0C);
163 err += sn9c102_i2c_write(cam, 0x38, 0x02);
164 err += sn9c102_i2c_write(cam, 0x39, 0x43);
165 err += sn9c102_i2c_write(cam, 0x3A, 0x00);
166 err += sn9c102_i2c_write(cam, 0x3B, 0x0A);
167 err += sn9c102_i2c_write(cam, 0x3C, 0x6C);
168 err += sn9c102_i2c_write(cam, 0x3D, 0x99);
169 err += sn9c102_i2c_write(cam, 0x3E, 0x0E);
170 err += sn9c102_i2c_write(cam, 0x3F, 0x41);
171 err += sn9c102_i2c_write(cam, 0x40, 0xC1);
172 err += sn9c102_i2c_write(cam, 0x41, 0x22);
173 err += sn9c102_i2c_write(cam, 0x42, 0x08);
174 err += sn9c102_i2c_write(cam, 0x43, 0xF0);
175 err += sn9c102_i2c_write(cam, 0x44, 0x10);
176 err += sn9c102_i2c_write(cam, 0x45, 0x78);
177 err += sn9c102_i2c_write(cam, 0x46, 0xA8);
178 err += sn9c102_i2c_write(cam, 0x47, 0x60);
179 err += sn9c102_i2c_write(cam, 0x48, 0x80);
180 err += sn9c102_i2c_write(cam, 0x49, 0x00);
181 err += sn9c102_i2c_write(cam, 0x4A, 0x00);
182 err += sn9c102_i2c_write(cam, 0x4B, 0x00);
183 err += sn9c102_i2c_write(cam, 0x4C, 0x00);
184 err += sn9c102_i2c_write(cam, 0x4D, 0x00);
185 err += sn9c102_i2c_write(cam, 0x4E, 0x00);
186 err += sn9c102_i2c_write(cam, 0x4F, 0x46);
187 err += sn9c102_i2c_write(cam, 0x50, 0x36);
188 err += sn9c102_i2c_write(cam, 0x51, 0x0F);
189 err += sn9c102_i2c_write(cam, 0x52, 0x17);
190 err += sn9c102_i2c_write(cam, 0x53, 0x7F);
191 err += sn9c102_i2c_write(cam, 0x54, 0x96);
192 err += sn9c102_i2c_write(cam, 0x55, 0x40);
193 err += sn9c102_i2c_write(cam, 0x56, 0x40);
194 err += sn9c102_i2c_write(cam, 0x57, 0x40);
195 err += sn9c102_i2c_write(cam, 0x58, 0x0F);
196 err += sn9c102_i2c_write(cam, 0x59, 0xBA);
197 err += sn9c102_i2c_write(cam, 0x5A, 0x9A);
198 err += sn9c102_i2c_write(cam, 0x5B, 0x22);
199 err += sn9c102_i2c_write(cam, 0x5C, 0xB9);
200 err += sn9c102_i2c_write(cam, 0x5D, 0x9B);
201 err += sn9c102_i2c_write(cam, 0x5E, 0x10);
202 err += sn9c102_i2c_write(cam, 0x5F, 0xF0);
203 err += sn9c102_i2c_write(cam, 0x60, 0x05);
204 err += sn9c102_i2c_write(cam, 0x61, 0x60);
205 err += sn9c102_i2c_write(cam, 0x62, 0x00);
206 err += sn9c102_i2c_write(cam, 0x63, 0x00);
207 err += sn9c102_i2c_write(cam, 0x64, 0x50);
208 err += sn9c102_i2c_write(cam, 0x65, 0x30);
209 err += sn9c102_i2c_write(cam, 0x66, 0x00);
210 err += sn9c102_i2c_write(cam, 0x67, 0x80);
211 err += sn9c102_i2c_write(cam, 0x68, 0x7A);
212 err += sn9c102_i2c_write(cam, 0x69, 0x90);
213 err += sn9c102_i2c_write(cam, 0x6A, 0x80);
214 err += sn9c102_i2c_write(cam, 0x6B, 0x0A);
215 err += sn9c102_i2c_write(cam, 0x6C, 0x30);
216 err += sn9c102_i2c_write(cam, 0x6D, 0x48);
217 err += sn9c102_i2c_write(cam, 0x6E, 0x80);
218 err += sn9c102_i2c_write(cam, 0x6F, 0x74);
219 err += sn9c102_i2c_write(cam, 0x70, 0x64);
220 err += sn9c102_i2c_write(cam, 0x71, 0x60);
221 err += sn9c102_i2c_write(cam, 0x72, 0x5C);
222 err += sn9c102_i2c_write(cam, 0x73, 0x58);
223 err += sn9c102_i2c_write(cam, 0x74, 0x54);
224 err += sn9c102_i2c_write(cam, 0x75, 0x4C);
225 err += sn9c102_i2c_write(cam, 0x76, 0x40);
226 err += sn9c102_i2c_write(cam, 0x77, 0x38);
227 err += sn9c102_i2c_write(cam, 0x78, 0x34);
228 err += sn9c102_i2c_write(cam, 0x79, 0x30);
229 err += sn9c102_i2c_write(cam, 0x7A, 0x2F);
230 err += sn9c102_i2c_write(cam, 0x7B, 0x2B);
231 err += sn9c102_i2c_write(cam, 0x7C, 0x03);
232 err += sn9c102_i2c_write(cam, 0x7D, 0x07);
233 err += sn9c102_i2c_write(cam, 0x7E, 0x17);
234 err += sn9c102_i2c_write(cam, 0x7F, 0x34);
235 err += sn9c102_i2c_write(cam, 0x80, 0x41);
236 err += sn9c102_i2c_write(cam, 0x81, 0x4D);
237 err += sn9c102_i2c_write(cam, 0x82, 0x58);
238 err += sn9c102_i2c_write(cam, 0x83, 0x63);
239 err += sn9c102_i2c_write(cam, 0x84, 0x6E);
240 err += sn9c102_i2c_write(cam, 0x85, 0x77);
241 err += sn9c102_i2c_write(cam, 0x86, 0x87);
242 err += sn9c102_i2c_write(cam, 0x87, 0x95);
243 err += sn9c102_i2c_write(cam, 0x88, 0xAF);
244 err += sn9c102_i2c_write(cam, 0x89, 0xC7);
245 err += sn9c102_i2c_write(cam, 0x8A, 0xDF);
246 err += sn9c102_i2c_write(cam, 0x8B, 0x99);
247 err += sn9c102_i2c_write(cam, 0x8C, 0x99);
248 err += sn9c102_i2c_write(cam, 0x8D, 0xCF);
249 err += sn9c102_i2c_write(cam, 0x8E, 0x20);
250 err += sn9c102_i2c_write(cam, 0x8F, 0x26);
251 err += sn9c102_i2c_write(cam, 0x90, 0x10);
252 err += sn9c102_i2c_write(cam, 0x91, 0x0C);
253 err += sn9c102_i2c_write(cam, 0x92, 0x25);
254 err += sn9c102_i2c_write(cam, 0x93, 0x00);
255 err += sn9c102_i2c_write(cam, 0x94, 0x50);
256 err += sn9c102_i2c_write(cam, 0x95, 0x50);
257 err += sn9c102_i2c_write(cam, 0x96, 0x00);
258 err += sn9c102_i2c_write(cam, 0x97, 0x01);
259 err += sn9c102_i2c_write(cam, 0x98, 0x10);
260 err += sn9c102_i2c_write(cam, 0x99, 0x40);
261 err += sn9c102_i2c_write(cam, 0x9A, 0x40);
262 err += sn9c102_i2c_write(cam, 0x9B, 0x20);
263 err += sn9c102_i2c_write(cam, 0x9C, 0x00);
264 err += sn9c102_i2c_write(cam, 0x9D, 0x99);
265 err += sn9c102_i2c_write(cam, 0x9E, 0x7F);
266 err += sn9c102_i2c_write(cam, 0x9F, 0x00);
267 err += sn9c102_i2c_write(cam, 0xA0, 0x00);
268 err += sn9c102_i2c_write(cam, 0xA1, 0x00);
269
270 return err;
271 }
272
273
274 static int ov7660_get_ctrl(struct sn9c102_device* cam,
275 struct v4l2_control* ctrl)
276 {
277 int err = 0;
278
279 switch (ctrl->id) {
280 case V4L2_CID_EXPOSURE:
281 if ((ctrl->value = sn9c102_i2c_read(cam, 0x10)) < 0)
282 return -EIO;
283 break;
284 case V4L2_CID_DO_WHITE_BALANCE:
285 if ((ctrl->value = sn9c102_read_reg(cam, 0x02)) < 0)
286 return -EIO;
287 ctrl->value = (ctrl->value & 0x04) ? 1 : 0;
288 break;
289 case V4L2_CID_RED_BALANCE:
290 if ((ctrl->value = sn9c102_read_reg(cam, 0x05)) < 0)
291 return -EIO;
292 ctrl->value &= 0x7f;
293 break;
294 case V4L2_CID_BLUE_BALANCE:
295 if ((ctrl->value = sn9c102_read_reg(cam, 0x06)) < 0)
296 return -EIO;
297 ctrl->value &= 0x7f;
298 break;
299 case SN9C102_V4L2_CID_GREEN_BALANCE:
300 if ((ctrl->value = sn9c102_read_reg(cam, 0x07)) < 0)
301 return -EIO;
302 ctrl->value &= 0x7f;
303 break;
304 case SN9C102_V4L2_CID_BAND_FILTER:
305 if ((ctrl->value = sn9c102_i2c_read(cam, 0x3b)) < 0)
306 return -EIO;
307 ctrl->value &= 0x08;
308 break;
309 case V4L2_CID_GAIN:
310 if ((ctrl->value = sn9c102_i2c_read(cam, 0x00)) < 0)
311 return -EIO;
312 ctrl->value &= 0x1f;
313 break;
314 case V4L2_CID_AUTOGAIN:
315 if ((ctrl->value = sn9c102_i2c_read(cam, 0x13)) < 0)
316 return -EIO;
317 ctrl->value &= 0x01;
318 break;
319 default:
320 return -EINVAL;
321 }
322
323 return err ? -EIO : 0;
324 }
325
326
327 static int ov7660_set_ctrl(struct sn9c102_device* cam,
328 const struct v4l2_control* ctrl)
329 {
330 int err = 0;
331
332 switch (ctrl->id) {
333 case V4L2_CID_EXPOSURE:
334 err += sn9c102_i2c_write(cam, 0x10, ctrl->value);
335 break;
336 case V4L2_CID_DO_WHITE_BALANCE:
337 err += sn9c102_write_reg(cam, 0x43 | (ctrl->value << 2), 0x02);
338 break;
339 case V4L2_CID_RED_BALANCE:
340 err += sn9c102_write_reg(cam, ctrl->value, 0x05);
341 break;
342 case V4L2_CID_BLUE_BALANCE:
343 err += sn9c102_write_reg(cam, ctrl->value, 0x06);
344 break;
345 case SN9C102_V4L2_CID_GREEN_BALANCE:
346 err += sn9c102_write_reg(cam, ctrl->value, 0x07);
347 break;
348 case SN9C102_V4L2_CID_BAND_FILTER:
349 err += sn9c102_i2c_write(cam, ctrl->value << 3, 0x3b);
350 break;
351 case V4L2_CID_GAIN:
352 err += sn9c102_i2c_write(cam, 0x00, 0x60 + ctrl->value);
353 break;
354 case V4L2_CID_AUTOGAIN:
355 err += sn9c102_i2c_write(cam, 0x13, 0xc0 |
356 (ctrl->value * 0x07));
357 break;
358 default:
359 return -EINVAL;
360 }
361
362 return err ? -EIO : 0;
363 }
364
365
366 static int ov7660_set_crop(struct sn9c102_device* cam,
367 const struct v4l2_rect* rect)
368 {
369 struct sn9c102_sensor* s = sn9c102_get_sensor(cam);
370 int err = 0;
371 u8 h_start = (u8)(rect->left - s->cropcap.bounds.left) + 1,
372 v_start = (u8)(rect->top - s->cropcap.bounds.top) + 1;
373
374 err += sn9c102_write_reg(cam, h_start, 0x12);
375 err += sn9c102_write_reg(cam, v_start, 0x13);
376
377 return err;
378 }
379
380
381 static int ov7660_set_pix_format(struct sn9c102_device* cam,
382 const struct v4l2_pix_format* pix)
383 {
384 int r0, err = 0;
385
386 r0 = sn9c102_pread_reg(cam, 0x01);
387
388 if (pix->pixelformat == V4L2_PIX_FMT_JPEG) {
389 err += sn9c102_write_reg(cam, r0 | 0x40, 0x01);
390 err += sn9c102_write_reg(cam, 0xa2, 0x17);
391 err += sn9c102_i2c_write(cam, 0x11, 0x00);
392 } else {
393 err += sn9c102_write_reg(cam, r0 | 0x40, 0x01);
394 err += sn9c102_write_reg(cam, 0xa2, 0x17);
395 err += sn9c102_i2c_write(cam, 0x11, 0x0d);
396 }
397
398 return err;
399 }
400
401
402 static const struct sn9c102_sensor ov7660 = {
403 .name = "OV7660",
404 .maintainer = "Luca Risolia <luca.risolia@studio.unibo.it>",
405 .supported_bridge = BRIDGE_SN9C105 | BRIDGE_SN9C120,
406 .sysfs_ops = SN9C102_I2C_READ | SN9C102_I2C_WRITE,
407 .frequency = SN9C102_I2C_100KHZ,
408 .interface = SN9C102_I2C_2WIRES,
409 .i2c_slave_id = 0x21,
410 .init = &ov7660_init,
411 .qctrl = {
412 {
413 .id = V4L2_CID_GAIN,
414 .type = V4L2_CTRL_TYPE_INTEGER,
415 .name = "global gain",
416 .minimum = 0x00,
417 .maximum = 0x1f,
418 .step = 0x01,
419 .default_value = 0x09,
420 .flags = 0,
421 },
422 {
423 .id = V4L2_CID_EXPOSURE,
424 .type = V4L2_CTRL_TYPE_INTEGER,
425 .name = "exposure",
426 .minimum = 0x00,
427 .maximum = 0xff,
428 .step = 0x01,
429 .default_value = 0x27,
430 .flags = 0,
431 },
432 {
433 .id = V4L2_CID_DO_WHITE_BALANCE,
434 .type = V4L2_CTRL_TYPE_BOOLEAN,
435 .name = "night mode",
436 .minimum = 0x00,
437 .maximum = 0x01,
438 .step = 0x01,
439 .default_value = 0x00,
440 .flags = 0,
441 },
442 {
443 .id = V4L2_CID_RED_BALANCE,
444 .type = V4L2_CTRL_TYPE_INTEGER,
445 .name = "red balance",
446 .minimum = 0x00,
447 .maximum = 0x7f,
448 .step = 0x01,
449 .default_value = 0x14,
450 .flags = 0,
451 },
452 {
453 .id = V4L2_CID_BLUE_BALANCE,
454 .type = V4L2_CTRL_TYPE_INTEGER,
455 .name = "blue balance",
456 .minimum = 0x00,
457 .maximum = 0x7f,
458 .step = 0x01,
459 .default_value = 0x14,
460 .flags = 0,
461 },
462 {
463 .id = V4L2_CID_AUTOGAIN,
464 .type = V4L2_CTRL_TYPE_BOOLEAN,
465 .name = "auto adjust",
466 .minimum = 0x00,
467 .maximum = 0x01,
468 .step = 0x01,
469 .default_value = 0x01,
470 .flags = 0,
471 },
472 {
473 .id = SN9C102_V4L2_CID_GREEN_BALANCE,
474 .type = V4L2_CTRL_TYPE_INTEGER,
475 .name = "green balance",
476 .minimum = 0x00,
477 .maximum = 0x7f,
478 .step = 0x01,
479 .default_value = 0x14,
480 .flags = 0,
481 },
482 {
483 .id = SN9C102_V4L2_CID_BAND_FILTER,
484 .type = V4L2_CTRL_TYPE_BOOLEAN,
485 .name = "band filter",
486 .minimum = 0x00,
487 .maximum = 0x01,
488 .step = 0x01,
489 .default_value = 0x00,
490 .flags = 0,
491 },
492 },
493 .get_ctrl = &ov7660_get_ctrl,
494 .set_ctrl = &ov7660_set_ctrl,
495 .cropcap = {
496 .bounds = {
497 .left = 0,
498 .top = 0,
499 .width = 640,
500 .height = 480,
501 },
502 .defrect = {
503 .left = 0,
504 .top = 0,
505 .width = 640,
506 .height = 480,
507 },
508 },
509 .set_crop = &ov7660_set_crop,
510 .pix_format = {
511 .width = 640,
512 .height = 480,
513 .pixelformat = V4L2_PIX_FMT_JPEG,
514 .priv = 8,
515 },
516 .set_pix_format = &ov7660_set_pix_format
517 };
518
519
520 int sn9c102_probe_ov7660(struct sn9c102_device* cam)
521 {
522 int pid, ver, err;
523
524 err = sn9c102_write_const_regs(cam, {0x01, 0xf1}, {0x00, 0xf1},
525 {0x01, 0x01}, {0x00, 0x01},
526 {0x28, 0x17});
527
528 pid = sn9c102_i2c_try_read(cam, &ov7660, 0x0a);
529 ver = sn9c102_i2c_try_read(cam, &ov7660, 0x0b);
530 if (err || pid < 0 || ver < 0)
531 return -EIO;
532 if (pid != 0x76 || ver != 0x60)
533 return -ENODEV;
534
535 sn9c102_attach_sensor(cam, &ov7660);
536
537 return 0;
538 }
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