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Linux 3.11-rc3
[cris-mirror.git] / arch / arm / mach-davinci / da850.c
bloba0d4f6038b608f187eedc4a0cf89b0b97ce6a49c
1 /*
2 * TI DA850/OMAP-L138 chip specific setup
3 *
4 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * Derived from: arch/arm/mach-davinci/da830.c
7 * Original Copyrights follow:
8 *
9 * 2009 (c) MontaVista Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 */
14 #include <linux/gpio.h>
15 #include <linux/init.h>
16 #include <linux/clk.h>
17 #include <linux/platform_device.h>
18 #include <linux/cpufreq.h>
19 #include <linux/regulator/consumer.h>
20
21 #include <asm/mach/map.h>
22
23 #include <mach/psc.h>
24 #include <mach/irqs.h>
25 #include <mach/cputype.h>
26 #include <mach/common.h>
27 #include <mach/time.h>
28 #include <mach/da8xx.h>
29 #include <mach/cpufreq.h>
30 #include <mach/pm.h>
31 #include <mach/gpio-davinci.h>
32
33 #include "clock.h"
34 #include "mux.h"
35
36 /* SoC specific clock flags */
37 #define DA850_CLK_ASYNC3 BIT(16)
38
39 #define DA850_PLL1_BASE 0x01e1a000
40 #define DA850_TIMER64P2_BASE 0x01f0c000
41 #define DA850_TIMER64P3_BASE 0x01f0d000
42
43 #define DA850_REF_FREQ 24000000
44
45 #define CFGCHIP3_ASYNC3_CLKSRC BIT(4)
46 #define CFGCHIP3_PLL1_MASTER_LOCK BIT(5)
47 #define CFGCHIP0_PLL_MASTER_LOCK BIT(4)
48
49 static int da850_set_armrate(struct clk *clk, unsigned long rate);
50 static int da850_round_armrate(struct clk *clk, unsigned long rate);
51 static int da850_set_pll0rate(struct clk *clk, unsigned long armrate);
52
53 static struct pll_data pll0_data = {
54 .num = 1,
55 .phys_base = DA8XX_PLL0_BASE,
56 .flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
57 };
58
59 static struct clk ref_clk = {
60 .name = "ref_clk",
61 .rate = DA850_REF_FREQ,
62 .set_rate = davinci_simple_set_rate,
63 };
64
65 static struct clk pll0_clk = {
66 .name = "pll0",
67 .parent = &ref_clk,
68 .pll_data = &pll0_data,
69 .flags = CLK_PLL,
70 .set_rate = da850_set_pll0rate,
71 };
72
73 static struct clk pll0_aux_clk = {
74 .name = "pll0_aux_clk",
75 .parent = &pll0_clk,
76 .flags = CLK_PLL | PRE_PLL,
77 };
78
79 static struct clk pll0_sysclk1 = {
80 .name = "pll0_sysclk1",
81 .parent = &pll0_clk,
82 .flags = CLK_PLL,
83 .div_reg = PLLDIV1,
84 };
85
86 static struct clk pll0_sysclk2 = {
87 .name = "pll0_sysclk2",
88 .parent = &pll0_clk,
89 .flags = CLK_PLL,
90 .div_reg = PLLDIV2,
91 };
92
93 static struct clk pll0_sysclk3 = {
94 .name = "pll0_sysclk3",
95 .parent = &pll0_clk,
96 .flags = CLK_PLL,
97 .div_reg = PLLDIV3,
98 .set_rate = davinci_set_sysclk_rate,
99 .maxrate = 100000000,
100 };
101
102 static struct clk pll0_sysclk4 = {
103 .name = "pll0_sysclk4",
104 .parent = &pll0_clk,
105 .flags = CLK_PLL,
106 .div_reg = PLLDIV4,
107 };
108
109 static struct clk pll0_sysclk5 = {
110 .name = "pll0_sysclk5",
111 .parent = &pll0_clk,
112 .flags = CLK_PLL,
113 .div_reg = PLLDIV5,
114 };
115
116 static struct clk pll0_sysclk6 = {
117 .name = "pll0_sysclk6",
118 .parent = &pll0_clk,
119 .flags = CLK_PLL,
120 .div_reg = PLLDIV6,
121 };
122
123 static struct clk pll0_sysclk7 = {
124 .name = "pll0_sysclk7",
125 .parent = &pll0_clk,
126 .flags = CLK_PLL,
127 .div_reg = PLLDIV7,
128 };
129
130 static struct pll_data pll1_data = {
131 .num = 2,
132 .phys_base = DA850_PLL1_BASE,
133 .flags = PLL_HAS_POSTDIV,
134 };
135
136 static struct clk pll1_clk = {
137 .name = "pll1",
138 .parent = &ref_clk,
139 .pll_data = &pll1_data,
140 .flags = CLK_PLL,
141 };
142
143 static struct clk pll1_aux_clk = {
144 .name = "pll1_aux_clk",
145 .parent = &pll1_clk,
146 .flags = CLK_PLL | PRE_PLL,
147 };
148
149 static struct clk pll1_sysclk2 = {
150 .name = "pll1_sysclk2",
151 .parent = &pll1_clk,
152 .flags = CLK_PLL,
153 .div_reg = PLLDIV2,
154 };
155
156 static struct clk pll1_sysclk3 = {
157 .name = "pll1_sysclk3",
158 .parent = &pll1_clk,
159 .flags = CLK_PLL,
160 .div_reg = PLLDIV3,
161 };
162
163 static struct clk i2c0_clk = {
164 .name = "i2c0",
165 .parent = &pll0_aux_clk,
166 };
167
168 static struct clk timerp64_0_clk = {
169 .name = "timer0",
170 .parent = &pll0_aux_clk,
171 };
172
173 static struct clk timerp64_1_clk = {
174 .name = "timer1",
175 .parent = &pll0_aux_clk,
176 };
177
178 static struct clk arm_rom_clk = {
179 .name = "arm_rom",
180 .parent = &pll0_sysclk2,
181 .lpsc = DA8XX_LPSC0_ARM_RAM_ROM,
182 .flags = ALWAYS_ENABLED,
183 };
184
185 static struct clk tpcc0_clk = {
186 .name = "tpcc0",
187 .parent = &pll0_sysclk2,
188 .lpsc = DA8XX_LPSC0_TPCC,
189 .flags = ALWAYS_ENABLED | CLK_PSC,
190 };
191
192 static struct clk tptc0_clk = {
193 .name = "tptc0",
194 .parent = &pll0_sysclk2,
195 .lpsc = DA8XX_LPSC0_TPTC0,
196 .flags = ALWAYS_ENABLED,
197 };
198
199 static struct clk tptc1_clk = {
200 .name = "tptc1",
201 .parent = &pll0_sysclk2,
202 .lpsc = DA8XX_LPSC0_TPTC1,
203 .flags = ALWAYS_ENABLED,
204 };
205
206 static struct clk tpcc1_clk = {
207 .name = "tpcc1",
208 .parent = &pll0_sysclk2,
209 .lpsc = DA850_LPSC1_TPCC1,
210 .gpsc = 1,
211 .flags = CLK_PSC | ALWAYS_ENABLED,
212 };
213
214 static struct clk tptc2_clk = {
215 .name = "tptc2",
216 .parent = &pll0_sysclk2,
217 .lpsc = DA850_LPSC1_TPTC2,
218 .gpsc = 1,
219 .flags = ALWAYS_ENABLED,
220 };
221
222 static struct clk pruss_clk = {
223 .name = "pruss",
224 .parent = &pll0_sysclk2,
225 .lpsc = DA8XX_LPSC0_PRUSS,
226 };
227
228 static struct clk uart0_clk = {
229 .name = "uart0",
230 .parent = &pll0_sysclk2,
231 .lpsc = DA8XX_LPSC0_UART0,
232 };
233
234 static struct clk uart1_clk = {
235 .name = "uart1",
236 .parent = &pll0_sysclk2,
237 .lpsc = DA8XX_LPSC1_UART1,
238 .gpsc = 1,
239 .flags = DA850_CLK_ASYNC3,
240 };
241
242 static struct clk uart2_clk = {
243 .name = "uart2",
244 .parent = &pll0_sysclk2,
245 .lpsc = DA8XX_LPSC1_UART2,
246 .gpsc = 1,
247 .flags = DA850_CLK_ASYNC3,
248 };
249
250 static struct clk aintc_clk = {
251 .name = "aintc",
252 .parent = &pll0_sysclk4,
253 .lpsc = DA8XX_LPSC0_AINTC,
254 .flags = ALWAYS_ENABLED,
255 };
256
257 static struct clk gpio_clk = {
258 .name = "gpio",
259 .parent = &pll0_sysclk4,
260 .lpsc = DA8XX_LPSC1_GPIO,
261 .gpsc = 1,
262 };
263
264 static struct clk i2c1_clk = {
265 .name = "i2c1",
266 .parent = &pll0_sysclk4,
267 .lpsc = DA8XX_LPSC1_I2C,
268 .gpsc = 1,
269 };
270
271 static struct clk emif3_clk = {
272 .name = "emif3",
273 .parent = &pll0_sysclk5,
274 .lpsc = DA8XX_LPSC1_EMIF3C,
275 .gpsc = 1,
276 .flags = ALWAYS_ENABLED,
277 };
278
279 static struct clk arm_clk = {
280 .name = "arm",
281 .parent = &pll0_sysclk6,
282 .lpsc = DA8XX_LPSC0_ARM,
283 .flags = ALWAYS_ENABLED,
284 .set_rate = da850_set_armrate,
285 .round_rate = da850_round_armrate,
286 };
287
288 static struct clk rmii_clk = {
289 .name = "rmii",
290 .parent = &pll0_sysclk7,
291 };
292
293 static struct clk emac_clk = {
294 .name = "emac",
295 .parent = &pll0_sysclk4,
296 .lpsc = DA8XX_LPSC1_CPGMAC,
297 .gpsc = 1,
298 };
299
300 static struct clk mcasp_clk = {
301 .name = "mcasp",
302 .parent = &pll0_sysclk2,
303 .lpsc = DA8XX_LPSC1_McASP0,
304 .gpsc = 1,
305 .flags = DA850_CLK_ASYNC3,
306 };
307
308 static struct clk lcdc_clk = {
309 .name = "lcdc",
310 .parent = &pll0_sysclk2,
311 .lpsc = DA8XX_LPSC1_LCDC,
312 .gpsc = 1,
313 };
314
315 static struct clk mmcsd0_clk = {
316 .name = "mmcsd0",
317 .parent = &pll0_sysclk2,
318 .lpsc = DA8XX_LPSC0_MMC_SD,
319 };
320
321 static struct clk mmcsd1_clk = {
322 .name = "mmcsd1",
323 .parent = &pll0_sysclk2,
324 .lpsc = DA850_LPSC1_MMC_SD1,
325 .gpsc = 1,
326 };
327
328 static struct clk aemif_clk = {
329 .name = "aemif",
330 .parent = &pll0_sysclk3,
331 .lpsc = DA8XX_LPSC0_EMIF25,
332 .flags = ALWAYS_ENABLED,
333 };
334
335 static struct clk usb11_clk = {
336 .name = "usb11",
337 .parent = &pll0_sysclk4,
338 .lpsc = DA8XX_LPSC1_USB11,
339 .gpsc = 1,
340 };
341
342 static struct clk usb20_clk = {
343 .name = "usb20",
344 .parent = &pll0_sysclk2,
345 .lpsc = DA8XX_LPSC1_USB20,
346 .gpsc = 1,
347 };
348
349 static struct clk spi0_clk = {
350 .name = "spi0",
351 .parent = &pll0_sysclk2,
352 .lpsc = DA8XX_LPSC0_SPI0,
353 };
354
355 static struct clk spi1_clk = {
356 .name = "spi1",
357 .parent = &pll0_sysclk2,
358 .lpsc = DA8XX_LPSC1_SPI1,
359 .gpsc = 1,
360 .flags = DA850_CLK_ASYNC3,
361 };
362
363 static struct clk vpif_clk = {
364 .name = "vpif",
365 .parent = &pll0_sysclk2,
366 .lpsc = DA850_LPSC1_VPIF,
367 .gpsc = 1,
368 };
369
370 static struct clk sata_clk = {
371 .name = "sata",
372 .parent = &pll0_sysclk2,
373 .lpsc = DA850_LPSC1_SATA,
374 .gpsc = 1,
375 .flags = PSC_FORCE,
376 };
377
378 static struct clk dsp_clk = {
379 .name = "dsp",
380 .parent = &pll0_sysclk1,
381 .domain = DAVINCI_GPSC_DSPDOMAIN,
382 .lpsc = DA8XX_LPSC0_GEM,
383 .flags = PSC_LRST | PSC_FORCE,
384 };
385
386 static struct clk ehrpwm_clk = {
387 .name = "ehrpwm",
388 .parent = &pll0_sysclk2,
389 .lpsc = DA8XX_LPSC1_PWM,
390 .gpsc = 1,
391 .flags = DA850_CLK_ASYNC3,
392 };
393
394 #define DA8XX_EHRPWM_TBCLKSYNC BIT(12)
395
396 static void ehrpwm_tblck_enable(struct clk *clk)
397 {
398 u32 val;
399
400 val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG));
401 val |= DA8XX_EHRPWM_TBCLKSYNC;
402 writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG));
403 }
404
405 static void ehrpwm_tblck_disable(struct clk *clk)
406 {
407 u32 val;
408
409 val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG));
410 val &= ~DA8XX_EHRPWM_TBCLKSYNC;
411 writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG));
412 }
413
414 static struct clk ehrpwm_tbclk = {
415 .name = "ehrpwm_tbclk",
416 .parent = &ehrpwm_clk,
417 .clk_enable = ehrpwm_tblck_enable,
418 .clk_disable = ehrpwm_tblck_disable,
419 };
420
421 static struct clk ecap_clk = {
422 .name = "ecap",
423 .parent = &pll0_sysclk2,
424 .lpsc = DA8XX_LPSC1_ECAP,
425 .gpsc = 1,
426 .flags = DA850_CLK_ASYNC3,
427 };
428
429 static struct clk_lookup da850_clks[] = {
430 CLK(NULL, "ref", &ref_clk),
431 CLK(NULL, "pll0", &pll0_clk),
432 CLK(NULL, "pll0_aux", &pll0_aux_clk),
433 CLK(NULL, "pll0_sysclk1", &pll0_sysclk1),
434 CLK(NULL, "pll0_sysclk2", &pll0_sysclk2),
435 CLK(NULL, "pll0_sysclk3", &pll0_sysclk3),
436 CLK(NULL, "pll0_sysclk4", &pll0_sysclk4),
437 CLK(NULL, "pll0_sysclk5", &pll0_sysclk5),
438 CLK(NULL, "pll0_sysclk6", &pll0_sysclk6),
439 CLK(NULL, "pll0_sysclk7", &pll0_sysclk7),
440 CLK(NULL, "pll1", &pll1_clk),
441 CLK(NULL, "pll1_aux", &pll1_aux_clk),
442 CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
443 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
444 CLK("i2c_davinci.1", NULL, &i2c0_clk),
445 CLK(NULL, "timer0", &timerp64_0_clk),
446 CLK("watchdog", NULL, &timerp64_1_clk),
447 CLK(NULL, "arm_rom", &arm_rom_clk),
448 CLK(NULL, "tpcc0", &tpcc0_clk),
449 CLK(NULL, "tptc0", &tptc0_clk),
450 CLK(NULL, "tptc1", &tptc1_clk),
451 CLK(NULL, "tpcc1", &tpcc1_clk),
452 CLK(NULL, "tptc2", &tptc2_clk),
453 CLK("pruss_uio", "pruss", &pruss_clk),
454 CLK(NULL, "uart0", &uart0_clk),
455 CLK(NULL, "uart1", &uart1_clk),
456 CLK(NULL, "uart2", &uart2_clk),
457 CLK(NULL, "aintc", &aintc_clk),
458 CLK(NULL, "gpio", &gpio_clk),
459 CLK("i2c_davinci.2", NULL, &i2c1_clk),
460 CLK(NULL, "emif3", &emif3_clk),
461 CLK(NULL, "arm", &arm_clk),
462 CLK(NULL, "rmii", &rmii_clk),
463 CLK("davinci_emac.1", NULL, &emac_clk),
464 CLK("davinci-mcasp.0", NULL, &mcasp_clk),
465 CLK("da8xx_lcdc.0", "fck", &lcdc_clk),
466 CLK("da830-mmc.0", NULL, &mmcsd0_clk),
467 CLK("da830-mmc.1", NULL, &mmcsd1_clk),
468 CLK(NULL, "aemif", &aemif_clk),
469 CLK(NULL, "usb11", &usb11_clk),
470 CLK(NULL, "usb20", &usb20_clk),
471 CLK("spi_davinci.0", NULL, &spi0_clk),
472 CLK("spi_davinci.1", NULL, &spi1_clk),
473 CLK("vpif", NULL, &vpif_clk),
474 CLK("ahci", NULL, &sata_clk),
475 CLK("davinci-rproc.0", NULL, &dsp_clk),
476 CLK("ehrpwm", "fck", &ehrpwm_clk),
477 CLK("ehrpwm", "tbclk", &ehrpwm_tbclk),
478 CLK("ecap", "fck", &ecap_clk),
479 CLK(NULL, NULL, NULL),
480 };
481
482 /*
483 * Device specific mux setup
484 *
485 * soc description mux mode mode mux dbg
486 * reg offset mask mode
487 */
488 static const struct mux_config da850_pins[] = {
489 #ifdef CONFIG_DAVINCI_MUX
490 /* UART0 function */
491 MUX_CFG(DA850, NUART0_CTS, 3, 24, 15, 2, false)
492 MUX_CFG(DA850, NUART0_RTS, 3, 28, 15, 2, false)
493 MUX_CFG(DA850, UART0_RXD, 3, 16, 15, 2, false)
494 MUX_CFG(DA850, UART0_TXD, 3, 20, 15, 2, false)
495 /* UART1 function */
496 MUX_CFG(DA850, UART1_RXD, 4, 24, 15, 2, false)
497 MUX_CFG(DA850, UART1_TXD, 4, 28, 15, 2, false)
498 /* UART2 function */
499 MUX_CFG(DA850, UART2_RXD, 4, 16, 15, 2, false)
500 MUX_CFG(DA850, UART2_TXD, 4, 20, 15, 2, false)
501 /* I2C1 function */
502 MUX_CFG(DA850, I2C1_SCL, 4, 16, 15, 4, false)
503 MUX_CFG(DA850, I2C1_SDA, 4, 20, 15, 4, false)
504 /* I2C0 function */
505 MUX_CFG(DA850, I2C0_SDA, 4, 12, 15, 2, false)
506 MUX_CFG(DA850, I2C0_SCL, 4, 8, 15, 2, false)
507 /* EMAC function */
508 MUX_CFG(DA850, MII_TXEN, 2, 4, 15, 8, false)
509 MUX_CFG(DA850, MII_TXCLK, 2, 8, 15, 8, false)
510 MUX_CFG(DA850, MII_COL, 2, 12, 15, 8, false)
511 MUX_CFG(DA850, MII_TXD_3, 2, 16, 15, 8, false)
512 MUX_CFG(DA850, MII_TXD_2, 2, 20, 15, 8, false)
513 MUX_CFG(DA850, MII_TXD_1, 2, 24, 15, 8, false)
514 MUX_CFG(DA850, MII_TXD_0, 2, 28, 15, 8, false)
515 MUX_CFG(DA850, MII_RXCLK, 3, 0, 15, 8, false)
516 MUX_CFG(DA850, MII_RXDV, 3, 4, 15, 8, false)
517 MUX_CFG(DA850, MII_RXER, 3, 8, 15, 8, false)
518 MUX_CFG(DA850, MII_CRS, 3, 12, 15, 8, false)
519 MUX_CFG(DA850, MII_RXD_3, 3, 16, 15, 8, false)
520 MUX_CFG(DA850, MII_RXD_2, 3, 20, 15, 8, false)
521 MUX_CFG(DA850, MII_RXD_1, 3, 24, 15, 8, false)
522 MUX_CFG(DA850, MII_RXD_0, 3, 28, 15, 8, false)
523 MUX_CFG(DA850, MDIO_CLK, 4, 0, 15, 8, false)
524 MUX_CFG(DA850, MDIO_D, 4, 4, 15, 8, false)
525 MUX_CFG(DA850, RMII_TXD_0, 14, 12, 15, 8, false)
526 MUX_CFG(DA850, RMII_TXD_1, 14, 8, 15, 8, false)
527 MUX_CFG(DA850, RMII_TXEN, 14, 16, 15, 8, false)
528 MUX_CFG(DA850, RMII_CRS_DV, 15, 4, 15, 8, false)
529 MUX_CFG(DA850, RMII_RXD_0, 14, 24, 15, 8, false)
530 MUX_CFG(DA850, RMII_RXD_1, 14, 20, 15, 8, false)
531 MUX_CFG(DA850, RMII_RXER, 14, 28, 15, 8, false)
532 MUX_CFG(DA850, RMII_MHZ_50_CLK, 15, 0, 15, 0, false)
533 /* McASP function */
534 MUX_CFG(DA850, ACLKR, 0, 0, 15, 1, false)
535 MUX_CFG(DA850, ACLKX, 0, 4, 15, 1, false)
536 MUX_CFG(DA850, AFSR, 0, 8, 15, 1, false)
537 MUX_CFG(DA850, AFSX, 0, 12, 15, 1, false)
538 MUX_CFG(DA850, AHCLKR, 0, 16, 15, 1, false)
539 MUX_CFG(DA850, AHCLKX, 0, 20, 15, 1, false)
540 MUX_CFG(DA850, AMUTE, 0, 24, 15, 1, false)
541 MUX_CFG(DA850, AXR_15, 1, 0, 15, 1, false)
542 MUX_CFG(DA850, AXR_14, 1, 4, 15, 1, false)
543 MUX_CFG(DA850, AXR_13, 1, 8, 15, 1, false)
544 MUX_CFG(DA850, AXR_12, 1, 12, 15, 1, false)
545 MUX_CFG(DA850, AXR_11, 1, 16, 15, 1, false)
546 MUX_CFG(DA850, AXR_10, 1, 20, 15, 1, false)
547 MUX_CFG(DA850, AXR_9, 1, 24, 15, 1, false)
548 MUX_CFG(DA850, AXR_8, 1, 28, 15, 1, false)
549 MUX_CFG(DA850, AXR_7, 2, 0, 15, 1, false)
550 MUX_CFG(DA850, AXR_6, 2, 4, 15, 1, false)
551 MUX_CFG(DA850, AXR_5, 2, 8, 15, 1, false)
552 MUX_CFG(DA850, AXR_4, 2, 12, 15, 1, false)
553 MUX_CFG(DA850, AXR_3, 2, 16, 15, 1, false)
554 MUX_CFG(DA850, AXR_2, 2, 20, 15, 1, false)
555 MUX_CFG(DA850, AXR_1, 2, 24, 15, 1, false)
556 MUX_CFG(DA850, AXR_0, 2, 28, 15, 1, false)
557 /* LCD function */
558 MUX_CFG(DA850, LCD_D_7, 16, 8, 15, 2, false)
559 MUX_CFG(DA850, LCD_D_6, 16, 12, 15, 2, false)
560 MUX_CFG(DA850, LCD_D_5, 16, 16, 15, 2, false)
561 MUX_CFG(DA850, LCD_D_4, 16, 20, 15, 2, false)
562 MUX_CFG(DA850, LCD_D_3, 16, 24, 15, 2, false)
563 MUX_CFG(DA850, LCD_D_2, 16, 28, 15, 2, false)
564 MUX_CFG(DA850, LCD_D_1, 17, 0, 15, 2, false)
565 MUX_CFG(DA850, LCD_D_0, 17, 4, 15, 2, false)
566 MUX_CFG(DA850, LCD_D_15, 17, 8, 15, 2, false)
567 MUX_CFG(DA850, LCD_D_14, 17, 12, 15, 2, false)
568 MUX_CFG(DA850, LCD_D_13, 17, 16, 15, 2, false)
569 MUX_CFG(DA850, LCD_D_12, 17, 20, 15, 2, false)
570 MUX_CFG(DA850, LCD_D_11, 17, 24, 15, 2, false)
571 MUX_CFG(DA850, LCD_D_10, 17, 28, 15, 2, false)
572 MUX_CFG(DA850, LCD_D_9, 18, 0, 15, 2, false)
573 MUX_CFG(DA850, LCD_D_8, 18, 4, 15, 2, false)
574 MUX_CFG(DA850, LCD_PCLK, 18, 24, 15, 2, false)
575 MUX_CFG(DA850, LCD_HSYNC, 19, 0, 15, 2, false)
576 MUX_CFG(DA850, LCD_VSYNC, 19, 4, 15, 2, false)
577 MUX_CFG(DA850, NLCD_AC_ENB_CS, 19, 24, 15, 2, false)
578 /* MMC/SD0 function */
579 MUX_CFG(DA850, MMCSD0_DAT_0, 10, 8, 15, 2, false)
580 MUX_CFG(DA850, MMCSD0_DAT_1, 10, 12, 15, 2, false)
581 MUX_CFG(DA850, MMCSD0_DAT_2, 10, 16, 15, 2, false)
582 MUX_CFG(DA850, MMCSD0_DAT_3, 10, 20, 15, 2, false)
583 MUX_CFG(DA850, MMCSD0_CLK, 10, 0, 15, 2, false)
584 MUX_CFG(DA850, MMCSD0_CMD, 10, 4, 15, 2, false)
585 /* MMC/SD1 function */
586 MUX_CFG(DA850, MMCSD1_DAT_0, 18, 8, 15, 2, false)
587 MUX_CFG(DA850, MMCSD1_DAT_1, 19, 16, 15, 2, false)
588 MUX_CFG(DA850, MMCSD1_DAT_2, 19, 12, 15, 2, false)
589 MUX_CFG(DA850, MMCSD1_DAT_3, 19, 8, 15, 2, false)
590 MUX_CFG(DA850, MMCSD1_CLK, 18, 12, 15, 2, false)
591 MUX_CFG(DA850, MMCSD1_CMD, 18, 16, 15, 2, false)
592 /* EMIF2.5/EMIFA function */
593 MUX_CFG(DA850, EMA_D_7, 9, 0, 15, 1, false)
594 MUX_CFG(DA850, EMA_D_6, 9, 4, 15, 1, false)
595 MUX_CFG(DA850, EMA_D_5, 9, 8, 15, 1, false)
596 MUX_CFG(DA850, EMA_D_4, 9, 12, 15, 1, false)
597 MUX_CFG(DA850, EMA_D_3, 9, 16, 15, 1, false)
598 MUX_CFG(DA850, EMA_D_2, 9, 20, 15, 1, false)
599 MUX_CFG(DA850, EMA_D_1, 9, 24, 15, 1, false)
600 MUX_CFG(DA850, EMA_D_0, 9, 28, 15, 1, false)
601 MUX_CFG(DA850, EMA_A_1, 12, 24, 15, 1, false)
602 MUX_CFG(DA850, EMA_A_2, 12, 20, 15, 1, false)
603 MUX_CFG(DA850, NEMA_CS_3, 7, 4, 15, 1, false)
604 MUX_CFG(DA850, NEMA_CS_4, 7, 8, 15, 1, false)
605 MUX_CFG(DA850, NEMA_WE, 7, 16, 15, 1, false)
606 MUX_CFG(DA850, NEMA_OE, 7, 20, 15, 1, false)
607 MUX_CFG(DA850, EMA_A_0, 12, 28, 15, 1, false)
608 MUX_CFG(DA850, EMA_A_3, 12, 16, 15, 1, false)
609 MUX_CFG(DA850, EMA_A_4, 12, 12, 15, 1, false)
610 MUX_CFG(DA850, EMA_A_5, 12, 8, 15, 1, false)
611 MUX_CFG(DA850, EMA_A_6, 12, 4, 15, 1, false)
612 MUX_CFG(DA850, EMA_A_7, 12, 0, 15, 1, false)
613 MUX_CFG(DA850, EMA_A_8, 11, 28, 15, 1, false)
614 MUX_CFG(DA850, EMA_A_9, 11, 24, 15, 1, false)
615 MUX_CFG(DA850, EMA_A_10, 11, 20, 15, 1, false)
616 MUX_CFG(DA850, EMA_A_11, 11, 16, 15, 1, false)
617 MUX_CFG(DA850, EMA_A_12, 11, 12, 15, 1, false)
618 MUX_CFG(DA850, EMA_A_13, 11, 8, 15, 1, false)
619 MUX_CFG(DA850, EMA_A_14, 11, 4, 15, 1, false)
620 MUX_CFG(DA850, EMA_A_15, 11, 0, 15, 1, false)
621 MUX_CFG(DA850, EMA_A_16, 10, 28, 15, 1, false)
622 MUX_CFG(DA850, EMA_A_17, 10, 24, 15, 1, false)
623 MUX_CFG(DA850, EMA_A_18, 10, 20, 15, 1, false)
624 MUX_CFG(DA850, EMA_A_19, 10, 16, 15, 1, false)
625 MUX_CFG(DA850, EMA_A_20, 10, 12, 15, 1, false)
626 MUX_CFG(DA850, EMA_A_21, 10, 8, 15, 1, false)
627 MUX_CFG(DA850, EMA_A_22, 10, 4, 15, 1, false)
628 MUX_CFG(DA850, EMA_A_23, 10, 0, 15, 1, false)
629 MUX_CFG(DA850, EMA_D_8, 8, 28, 15, 1, false)
630 MUX_CFG(DA850, EMA_D_9, 8, 24, 15, 1, false)
631 MUX_CFG(DA850, EMA_D_10, 8, 20, 15, 1, false)
632 MUX_CFG(DA850, EMA_D_11, 8, 16, 15, 1, false)
633 MUX_CFG(DA850, EMA_D_12, 8, 12, 15, 1, false)
634 MUX_CFG(DA850, EMA_D_13, 8, 8, 15, 1, false)
635 MUX_CFG(DA850, EMA_D_14, 8, 4, 15, 1, false)
636 MUX_CFG(DA850, EMA_D_15, 8, 0, 15, 1, false)
637 MUX_CFG(DA850, EMA_BA_1, 5, 24, 15, 1, false)
638 MUX_CFG(DA850, EMA_CLK, 6, 0, 15, 1, false)
639 MUX_CFG(DA850, EMA_WAIT_1, 6, 24, 15, 1, false)
640 MUX_CFG(DA850, NEMA_CS_2, 7, 0, 15, 1, false)
641 /* GPIO function */
642 MUX_CFG(DA850, GPIO2_4, 6, 12, 15, 8, false)
643 MUX_CFG(DA850, GPIO2_6, 6, 4, 15, 8, false)
644 MUX_CFG(DA850, GPIO2_8, 5, 28, 15, 8, false)
645 MUX_CFG(DA850, GPIO2_15, 5, 0, 15, 8, false)
646 MUX_CFG(DA850, GPIO3_12, 7, 12, 15, 8, false)
647 MUX_CFG(DA850, GPIO3_13, 7, 8, 15, 8, false)
648 MUX_CFG(DA850, GPIO4_0, 10, 28, 15, 8, false)
649 MUX_CFG(DA850, GPIO4_1, 10, 24, 15, 8, false)
650 MUX_CFG(DA850, GPIO6_9, 13, 24, 15, 8, false)
651 MUX_CFG(DA850, GPIO6_10, 13, 20, 15, 8, false)
652 MUX_CFG(DA850, GPIO6_13, 13, 8, 15, 8, false)
653 MUX_CFG(DA850, RTC_ALARM, 0, 28, 15, 2, false)
654 /* VPIF Capture */
655 MUX_CFG(DA850, VPIF_DIN0, 15, 4, 15, 1, false)
656 MUX_CFG(DA850, VPIF_DIN1, 15, 0, 15, 1, false)
657 MUX_CFG(DA850, VPIF_DIN2, 14, 28, 15, 1, false)
658 MUX_CFG(DA850, VPIF_DIN3, 14, 24, 15, 1, false)
659 MUX_CFG(DA850, VPIF_DIN4, 14, 20, 15, 1, false)
660 MUX_CFG(DA850, VPIF_DIN5, 14, 16, 15, 1, false)
661 MUX_CFG(DA850, VPIF_DIN6, 14, 12, 15, 1, false)
662 MUX_CFG(DA850, VPIF_DIN7, 14, 8, 15, 1, false)
663 MUX_CFG(DA850, VPIF_DIN8, 16, 4, 15, 1, false)
664 MUX_CFG(DA850, VPIF_DIN9, 16, 0, 15, 1, false)
665 MUX_CFG(DA850, VPIF_DIN10, 15, 28, 15, 1, false)
666 MUX_CFG(DA850, VPIF_DIN11, 15, 24, 15, 1, false)
667 MUX_CFG(DA850, VPIF_DIN12, 15, 20, 15, 1, false)
668 MUX_CFG(DA850, VPIF_DIN13, 15, 16, 15, 1, false)
669 MUX_CFG(DA850, VPIF_DIN14, 15, 12, 15, 1, false)
670 MUX_CFG(DA850, VPIF_DIN15, 15, 8, 15, 1, false)
671 MUX_CFG(DA850, VPIF_CLKIN0, 14, 0, 15, 1, false)
672 MUX_CFG(DA850, VPIF_CLKIN1, 14, 4, 15, 1, false)
673 MUX_CFG(DA850, VPIF_CLKIN2, 19, 8, 15, 1, false)
674 MUX_CFG(DA850, VPIF_CLKIN3, 19, 16, 15, 1, false)
675 /* VPIF Display */
676 MUX_CFG(DA850, VPIF_DOUT0, 17, 4, 15, 1, false)
677 MUX_CFG(DA850, VPIF_DOUT1, 17, 0, 15, 1, false)
678 MUX_CFG(DA850, VPIF_DOUT2, 16, 28, 15, 1, false)
679 MUX_CFG(DA850, VPIF_DOUT3, 16, 24, 15, 1, false)
680 MUX_CFG(DA850, VPIF_DOUT4, 16, 20, 15, 1, false)
681 MUX_CFG(DA850, VPIF_DOUT5, 16, 16, 15, 1, false)
682 MUX_CFG(DA850, VPIF_DOUT6, 16, 12, 15, 1, false)
683 MUX_CFG(DA850, VPIF_DOUT7, 16, 8, 15, 1, false)
684 MUX_CFG(DA850, VPIF_DOUT8, 18, 4, 15, 1, false)
685 MUX_CFG(DA850, VPIF_DOUT9, 18, 0, 15, 1, false)
686 MUX_CFG(DA850, VPIF_DOUT10, 17, 28, 15, 1, false)
687 MUX_CFG(DA850, VPIF_DOUT11, 17, 24, 15, 1, false)
688 MUX_CFG(DA850, VPIF_DOUT12, 17, 20, 15, 1, false)
689 MUX_CFG(DA850, VPIF_DOUT13, 17, 16, 15, 1, false)
690 MUX_CFG(DA850, VPIF_DOUT14, 17, 12, 15, 1, false)
691 MUX_CFG(DA850, VPIF_DOUT15, 17, 8, 15, 1, false)
692 MUX_CFG(DA850, VPIF_CLKO2, 19, 12, 15, 1, false)
693 MUX_CFG(DA850, VPIF_CLKO3, 19, 20, 15, 1, false)
694 #endif
695 };
696
697 const short da850_i2c0_pins[] __initconst = {
698 DA850_I2C0_SDA, DA850_I2C0_SCL,
699 -1
700 };
701
702 const short da850_i2c1_pins[] __initconst = {
703 DA850_I2C1_SCL, DA850_I2C1_SDA,
704 -1
705 };
706
707 const short da850_lcdcntl_pins[] __initconst = {
708 DA850_LCD_D_0, DA850_LCD_D_1, DA850_LCD_D_2, DA850_LCD_D_3,
709 DA850_LCD_D_4, DA850_LCD_D_5, DA850_LCD_D_6, DA850_LCD_D_7,
710 DA850_LCD_D_8, DA850_LCD_D_9, DA850_LCD_D_10, DA850_LCD_D_11,
711 DA850_LCD_D_12, DA850_LCD_D_13, DA850_LCD_D_14, DA850_LCD_D_15,
712 DA850_LCD_PCLK, DA850_LCD_HSYNC, DA850_LCD_VSYNC, DA850_NLCD_AC_ENB_CS,
713 -1
714 };
715
716 const short da850_vpif_capture_pins[] __initdata = {
717 DA850_VPIF_DIN0, DA850_VPIF_DIN1, DA850_VPIF_DIN2, DA850_VPIF_DIN3,
718 DA850_VPIF_DIN4, DA850_VPIF_DIN5, DA850_VPIF_DIN6, DA850_VPIF_DIN7,
719 DA850_VPIF_DIN8, DA850_VPIF_DIN9, DA850_VPIF_DIN10, DA850_VPIF_DIN11,
720 DA850_VPIF_DIN12, DA850_VPIF_DIN13, DA850_VPIF_DIN14, DA850_VPIF_DIN15,
721 DA850_VPIF_CLKIN0, DA850_VPIF_CLKIN1, DA850_VPIF_CLKIN2,
722 DA850_VPIF_CLKIN3,
723 -1
724 };
725
726 const short da850_vpif_display_pins[] __initdata = {
727 DA850_VPIF_DOUT0, DA850_VPIF_DOUT1, DA850_VPIF_DOUT2, DA850_VPIF_DOUT3,
728 DA850_VPIF_DOUT4, DA850_VPIF_DOUT5, DA850_VPIF_DOUT6, DA850_VPIF_DOUT7,
729 DA850_VPIF_DOUT8, DA850_VPIF_DOUT9, DA850_VPIF_DOUT10,
730 DA850_VPIF_DOUT11, DA850_VPIF_DOUT12, DA850_VPIF_DOUT13,
731 DA850_VPIF_DOUT14, DA850_VPIF_DOUT15, DA850_VPIF_CLKO2,
732 DA850_VPIF_CLKO3,
733 -1
734 };
735
736 /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
737 static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = {
738 [IRQ_DA8XX_COMMTX] = 7,
739 [IRQ_DA8XX_COMMRX] = 7,
740 [IRQ_DA8XX_NINT] = 7,
741 [IRQ_DA8XX_EVTOUT0] = 7,
742 [IRQ_DA8XX_EVTOUT1] = 7,
743 [IRQ_DA8XX_EVTOUT2] = 7,
744 [IRQ_DA8XX_EVTOUT3] = 7,
745 [IRQ_DA8XX_EVTOUT4] = 7,
746 [IRQ_DA8XX_EVTOUT5] = 7,
747 [IRQ_DA8XX_EVTOUT6] = 7,
748 [IRQ_DA8XX_EVTOUT7] = 7,
749 [IRQ_DA8XX_CCINT0] = 7,
750 [IRQ_DA8XX_CCERRINT] = 7,
751 [IRQ_DA8XX_TCERRINT0] = 7,
752 [IRQ_DA8XX_AEMIFINT] = 7,
753 [IRQ_DA8XX_I2CINT0] = 7,
754 [IRQ_DA8XX_MMCSDINT0] = 7,
755 [IRQ_DA8XX_MMCSDINT1] = 7,
756 [IRQ_DA8XX_ALLINT0] = 7,
757 [IRQ_DA8XX_RTC] = 7,
758 [IRQ_DA8XX_SPINT0] = 7,
759 [IRQ_DA8XX_TINT12_0] = 7,
760 [IRQ_DA8XX_TINT34_0] = 7,
761 [IRQ_DA8XX_TINT12_1] = 7,
762 [IRQ_DA8XX_TINT34_1] = 7,
763 [IRQ_DA8XX_UARTINT0] = 7,
764 [IRQ_DA8XX_KEYMGRINT] = 7,
765 [IRQ_DA850_MPUADDRERR0] = 7,
766 [IRQ_DA8XX_CHIPINT0] = 7,
767 [IRQ_DA8XX_CHIPINT1] = 7,
768 [IRQ_DA8XX_CHIPINT2] = 7,
769 [IRQ_DA8XX_CHIPINT3] = 7,
770 [IRQ_DA8XX_TCERRINT1] = 7,
771 [IRQ_DA8XX_C0_RX_THRESH_PULSE] = 7,
772 [IRQ_DA8XX_C0_RX_PULSE] = 7,
773 [IRQ_DA8XX_C0_TX_PULSE] = 7,
774 [IRQ_DA8XX_C0_MISC_PULSE] = 7,
775 [IRQ_DA8XX_C1_RX_THRESH_PULSE] = 7,
776 [IRQ_DA8XX_C1_RX_PULSE] = 7,
777 [IRQ_DA8XX_C1_TX_PULSE] = 7,
778 [IRQ_DA8XX_C1_MISC_PULSE] = 7,
779 [IRQ_DA8XX_MEMERR] = 7,
780 [IRQ_DA8XX_GPIO0] = 7,
781 [IRQ_DA8XX_GPIO1] = 7,
782 [IRQ_DA8XX_GPIO2] = 7,
783 [IRQ_DA8XX_GPIO3] = 7,
784 [IRQ_DA8XX_GPIO4] = 7,
785 [IRQ_DA8XX_GPIO5] = 7,
786 [IRQ_DA8XX_GPIO6] = 7,
787 [IRQ_DA8XX_GPIO7] = 7,
788 [IRQ_DA8XX_GPIO8] = 7,
789 [IRQ_DA8XX_I2CINT1] = 7,
790 [IRQ_DA8XX_LCDINT] = 7,
791 [IRQ_DA8XX_UARTINT1] = 7,
792 [IRQ_DA8XX_MCASPINT] = 7,
793 [IRQ_DA8XX_ALLINT1] = 7,
794 [IRQ_DA8XX_SPINT1] = 7,
795 [IRQ_DA8XX_UHPI_INT1] = 7,
796 [IRQ_DA8XX_USB_INT] = 7,
797 [IRQ_DA8XX_IRQN] = 7,
798 [IRQ_DA8XX_RWAKEUP] = 7,
799 [IRQ_DA8XX_UARTINT2] = 7,
800 [IRQ_DA8XX_DFTSSINT] = 7,
801 [IRQ_DA8XX_EHRPWM0] = 7,
802 [IRQ_DA8XX_EHRPWM0TZ] = 7,
803 [IRQ_DA8XX_EHRPWM1] = 7,
804 [IRQ_DA8XX_EHRPWM1TZ] = 7,
805 [IRQ_DA850_SATAINT] = 7,
806 [IRQ_DA850_TINTALL_2] = 7,
807 [IRQ_DA8XX_ECAP0] = 7,
808 [IRQ_DA8XX_ECAP1] = 7,
809 [IRQ_DA8XX_ECAP2] = 7,
810 [IRQ_DA850_MMCSDINT0_1] = 7,
811 [IRQ_DA850_MMCSDINT1_1] = 7,
812 [IRQ_DA850_T12CMPINT0_2] = 7,
813 [IRQ_DA850_T12CMPINT1_2] = 7,
814 [IRQ_DA850_T12CMPINT2_2] = 7,
815 [IRQ_DA850_T12CMPINT3_2] = 7,
816 [IRQ_DA850_T12CMPINT4_2] = 7,
817 [IRQ_DA850_T12CMPINT5_2] = 7,
818 [IRQ_DA850_T12CMPINT6_2] = 7,
819 [IRQ_DA850_T12CMPINT7_2] = 7,
820 [IRQ_DA850_T12CMPINT0_3] = 7,
821 [IRQ_DA850_T12CMPINT1_3] = 7,
822 [IRQ_DA850_T12CMPINT2_3] = 7,
823 [IRQ_DA850_T12CMPINT3_3] = 7,
824 [IRQ_DA850_T12CMPINT4_3] = 7,
825 [IRQ_DA850_T12CMPINT5_3] = 7,
826 [IRQ_DA850_T12CMPINT6_3] = 7,
827 [IRQ_DA850_T12CMPINT7_3] = 7,
828 [IRQ_DA850_RPIINT] = 7,
829 [IRQ_DA850_VPIFINT] = 7,
830 [IRQ_DA850_CCINT1] = 7,
831 [IRQ_DA850_CCERRINT1] = 7,
832 [IRQ_DA850_TCERRINT2] = 7,
833 [IRQ_DA850_TINTALL_3] = 7,
834 [IRQ_DA850_MCBSP0RINT] = 7,
835 [IRQ_DA850_MCBSP0XINT] = 7,
836 [IRQ_DA850_MCBSP1RINT] = 7,
837 [IRQ_DA850_MCBSP1XINT] = 7,
838 [IRQ_DA8XX_ARMCLKSTOPREQ] = 7,
839 };
840
841 static struct map_desc da850_io_desc[] = {
842 {
843 .virtual = IO_VIRT,
844 .pfn = __phys_to_pfn(IO_PHYS),
845 .length = IO_SIZE,
846 .type = MT_DEVICE
847 },
848 {
849 .virtual = DA8XX_CP_INTC_VIRT,
850 .pfn = __phys_to_pfn(DA8XX_CP_INTC_BASE),
851 .length = DA8XX_CP_INTC_SIZE,
852 .type = MT_DEVICE
853 },
854 };
855
856 static u32 da850_psc_bases[] = { DA8XX_PSC0_BASE, DA8XX_PSC1_BASE };
857
858 /* Contents of JTAG ID register used to identify exact cpu type */
859 static struct davinci_id da850_ids[] = {
860 {
861 .variant = 0x0,
862 .part_no = 0xb7d1,
863 .manufacturer = 0x017, /* 0x02f >> 1 */
864 .cpu_id = DAVINCI_CPU_ID_DA850,
865 .name = "da850/omap-l138",
866 },
867 {
868 .variant = 0x1,
869 .part_no = 0xb7d1,
870 .manufacturer = 0x017, /* 0x02f >> 1 */
871 .cpu_id = DAVINCI_CPU_ID_DA850,
872 .name = "da850/omap-l138/am18x",
873 },
874 };
875
876 static struct davinci_timer_instance da850_timer_instance[4] = {
877 {
878 .base = DA8XX_TIMER64P0_BASE,
879 .bottom_irq = IRQ_DA8XX_TINT12_0,
880 .top_irq = IRQ_DA8XX_TINT34_0,
881 },
882 {
883 .base = DA8XX_TIMER64P1_BASE,
884 .bottom_irq = IRQ_DA8XX_TINT12_1,
885 .top_irq = IRQ_DA8XX_TINT34_1,
886 },
887 {
888 .base = DA850_TIMER64P2_BASE,
889 .bottom_irq = IRQ_DA850_TINT12_2,
890 .top_irq = IRQ_DA850_TINT34_2,
891 },
892 {
893 .base = DA850_TIMER64P3_BASE,
894 .bottom_irq = IRQ_DA850_TINT12_3,
895 .top_irq = IRQ_DA850_TINT34_3,
896 },
897 };
898
899 /*
900 * T0_BOT: Timer 0, bottom : Used for clock_event
901 * T0_TOP: Timer 0, top : Used for clocksource
902 * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
903 */
904 static struct davinci_timer_info da850_timer_info = {
905 .timers = da850_timer_instance,
906 .clockevent_id = T0_BOT,
907 .clocksource_id = T0_TOP,
908 };
909
910 static void da850_set_async3_src(int pllnum)
911 {
912 struct clk *clk, *newparent = pllnum ? &pll1_sysclk2 : &pll0_sysclk2;
913 struct clk_lookup *c;
914 unsigned int v;
915 int ret;
916
917 for (c = da850_clks; c->clk; c++) {
918 clk = c->clk;
919 if (clk->flags & DA850_CLK_ASYNC3) {
920 ret = clk_set_parent(clk, newparent);
921 WARN(ret, "DA850: unable to re-parent clock %s",
922 clk->name);
923 }
924 }
925
926 v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
927 if (pllnum)
928 v |= CFGCHIP3_ASYNC3_CLKSRC;
929 else
930 v &= ~CFGCHIP3_ASYNC3_CLKSRC;
931 __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
932 }
933
934 #ifdef CONFIG_CPU_FREQ
935 /*
936 * Notes:
937 * According to the TRM, minimum PLLM results in maximum power savings.
938 * The OPP definitions below should keep the PLLM as low as possible.
939 *
940 * The output of the PLLM must be between 300 to 600 MHz.
941 */
942 struct da850_opp {
943 unsigned int freq; /* in KHz */
944 unsigned int prediv;
945 unsigned int mult;
946 unsigned int postdiv;
947 unsigned int cvdd_min; /* in uV */
948 unsigned int cvdd_max; /* in uV */
949 };
950
951 static const struct da850_opp da850_opp_456 = {
952 .freq = 456000,
953 .prediv = 1,
954 .mult = 19,
955 .postdiv = 1,
956 .cvdd_min = 1300000,
957 .cvdd_max = 1350000,
958 };
959
960 static const struct da850_opp da850_opp_408 = {
961 .freq = 408000,
962 .prediv = 1,
963 .mult = 17,
964 .postdiv = 1,
965 .cvdd_min = 1300000,
966 .cvdd_max = 1350000,
967 };
968
969 static const struct da850_opp da850_opp_372 = {
970 .freq = 372000,
971 .prediv = 2,
972 .mult = 31,
973 .postdiv = 1,
974 .cvdd_min = 1200000,
975 .cvdd_max = 1320000,
976 };
977
978 static const struct da850_opp da850_opp_300 = {
979 .freq = 300000,
980 .prediv = 1,
981 .mult = 25,
982 .postdiv = 2,
983 .cvdd_min = 1200000,
984 .cvdd_max = 1320000,
985 };
986
987 static const struct da850_opp da850_opp_200 = {
988 .freq = 200000,
989 .prediv = 1,
990 .mult = 25,
991 .postdiv = 3,
992 .cvdd_min = 1100000,
993 .cvdd_max = 1160000,
994 };
995
996 static const struct da850_opp da850_opp_96 = {
997 .freq = 96000,
998 .prediv = 1,
999 .mult = 20,
1000 .postdiv = 5,
1001 .cvdd_min = 1000000,
1002 .cvdd_max = 1050000,
1003 };
1004
1005 #define OPP(freq) \
1006 { \
1007 .driver_data = (unsigned int) &da850_opp_##freq, \
1008 .frequency = freq * 1000, \
1009 }
1010
1011 static struct cpufreq_frequency_table da850_freq_table[] = {
1012 OPP(456),
1013 OPP(408),
1014 OPP(372),
1015 OPP(300),
1016 OPP(200),
1017 OPP(96),
1018 {
1019 .driver_data = 0,
1020 .frequency = CPUFREQ_TABLE_END,
1021 },
1022 };
1023
1024 #ifdef CONFIG_REGULATOR
1025 static int da850_set_voltage(unsigned int index);
1026 static int da850_regulator_init(void);
1027 #endif
1028
1029 static struct davinci_cpufreq_config cpufreq_info = {
1030 .freq_table = da850_freq_table,
1031 #ifdef CONFIG_REGULATOR
1032 .init = da850_regulator_init,
1033 .set_voltage = da850_set_voltage,
1034 #endif
1035 };
1036
1037 #ifdef CONFIG_REGULATOR
1038 static struct regulator *cvdd;
1039
1040 static int da850_set_voltage(unsigned int index)
1041 {
1042 struct da850_opp *opp;
1043
1044 if (!cvdd)
1045 return -ENODEV;
1046
1047 opp = (struct da850_opp *) cpufreq_info.freq_table[index].driver_data;
1048
1049 return regulator_set_voltage(cvdd, opp->cvdd_min, opp->cvdd_max);
1050 }
1051
1052 static int da850_regulator_init(void)
1053 {
1054 cvdd = regulator_get(NULL, "cvdd");
1055 if (WARN(IS_ERR(cvdd), "Unable to obtain voltage regulator for CVDD;"
1056 " voltage scaling unsupported\n")) {
1057 return PTR_ERR(cvdd);
1058 }
1059
1060 return 0;
1061 }
1062 #endif
1063
1064 static struct platform_device da850_cpufreq_device = {
1065 .name = "cpufreq-davinci",
1066 .dev = {
1067 .platform_data = &cpufreq_info,
1068 },
1069 .id = -1,
1070 };
1071
1072 unsigned int da850_max_speed = 300000;
1073
1074 int da850_register_cpufreq(char *async_clk)
1075 {
1076 int i;
1077
1078 /* cpufreq driver can help keep an "async" clock constant */
1079 if (async_clk)
1080 clk_add_alias("async", da850_cpufreq_device.name,
1081 async_clk, NULL);
1082 for (i = 0; i < ARRAY_SIZE(da850_freq_table); i++) {
1083 if (da850_freq_table[i].frequency <= da850_max_speed) {
1084 cpufreq_info.freq_table = &da850_freq_table[i];
1085 break;
1086 }
1087 }
1088
1089 return platform_device_register(&da850_cpufreq_device);
1090 }
1091
1092 static int da850_round_armrate(struct clk *clk, unsigned long rate)
1093 {
1094 int i, ret = 0, diff;
1095 unsigned int best = (unsigned int) -1;
1096 struct cpufreq_frequency_table *table = cpufreq_info.freq_table;
1097
1098 rate /= 1000; /* convert to kHz */
1099
1100 for (i = 0; table[i].frequency != CPUFREQ_TABLE_END; i++) {
1101 diff = table[i].frequency - rate;
1102 if (diff < 0)
1103 diff = -diff;
1104
1105 if (diff < best) {
1106 best = diff;
1107 ret = table[i].frequency;
1108 }
1109 }
1110
1111 return ret * 1000;
1112 }
1113
1114 static int da850_set_armrate(struct clk *clk, unsigned long index)
1115 {
1116 struct clk *pllclk = &pll0_clk;
1117
1118 return clk_set_rate(pllclk, index);
1119 }
1120
1121 static int da850_set_pll0rate(struct clk *clk, unsigned long index)
1122 {
1123 unsigned int prediv, mult, postdiv;
1124 struct da850_opp *opp;
1125 struct pll_data *pll = clk->pll_data;
1126 int ret;
1127
1128 opp = (struct da850_opp *) cpufreq_info.freq_table[index].driver_data;
1129 prediv = opp->prediv;
1130 mult = opp->mult;
1131 postdiv = opp->postdiv;
1132
1133 ret = davinci_set_pllrate(pll, prediv, mult, postdiv);
1134 if (WARN_ON(ret))
1135 return ret;
1136
1137 return 0;
1138 }
1139 #else
1140 int __init da850_register_cpufreq(char *async_clk)
1141 {
1142 return 0;
1143 }
1144
1145 static int da850_set_armrate(struct clk *clk, unsigned long rate)
1146 {
1147 return -EINVAL;
1148 }
1149
1150 static int da850_set_pll0rate(struct clk *clk, unsigned long armrate)
1151 {
1152 return -EINVAL;
1153 }
1154
1155 static int da850_round_armrate(struct clk *clk, unsigned long rate)
1156 {
1157 return clk->rate;
1158 }
1159 #endif
1160
1161 int __init da850_register_pm(struct platform_device *pdev)
1162 {
1163 int ret;
1164 struct davinci_pm_config *pdata = pdev->dev.platform_data;
1165
1166 ret = davinci_cfg_reg(DA850_RTC_ALARM);
1167 if (ret)
1168 return ret;
1169
1170 pdata->ddr2_ctlr_base = da8xx_get_mem_ctlr();
1171 pdata->deepsleep_reg = DA8XX_SYSCFG1_VIRT(DA8XX_DEEPSLEEP_REG);
1172 pdata->ddrpsc_num = DA8XX_LPSC1_EMIF3C;
1173
1174 pdata->cpupll_reg_base = ioremap(DA8XX_PLL0_BASE, SZ_4K);
1175 if (!pdata->cpupll_reg_base)
1176 return -ENOMEM;
1177
1178 pdata->ddrpll_reg_base = ioremap(DA850_PLL1_BASE, SZ_4K);
1179 if (!pdata->ddrpll_reg_base) {
1180 ret = -ENOMEM;
1181 goto no_ddrpll_mem;
1182 }
1183
1184 pdata->ddrpsc_reg_base = ioremap(DA8XX_PSC1_BASE, SZ_4K);
1185 if (!pdata->ddrpsc_reg_base) {
1186 ret = -ENOMEM;
1187 goto no_ddrpsc_mem;
1188 }
1189
1190 return platform_device_register(pdev);
1191
1192 no_ddrpsc_mem:
1193 iounmap(pdata->ddrpll_reg_base);
1194 no_ddrpll_mem:
1195 iounmap(pdata->cpupll_reg_base);
1196 return ret;
1197 }
1198
1199 /* VPIF resource, platform data */
1200 static u64 da850_vpif_dma_mask = DMA_BIT_MASK(32);
1201
1202 static struct resource da850_vpif_resource[] = {
1203 {
1204 .start = DA8XX_VPIF_BASE,
1205 .end = DA8XX_VPIF_BASE + 0xfff,
1206 .flags = IORESOURCE_MEM,
1207 }
1208 };
1209
1210 static struct platform_device da850_vpif_dev = {
1211 .name = "vpif",
1212 .id = -1,
1213 .dev = {
1214 .dma_mask = &da850_vpif_dma_mask,
1215 .coherent_dma_mask = DMA_BIT_MASK(32),
1216 },
1217 .resource = da850_vpif_resource,
1218 .num_resources = ARRAY_SIZE(da850_vpif_resource),
1219 };
1220
1221 static struct resource da850_vpif_display_resource[] = {
1222 {
1223 .start = IRQ_DA850_VPIFINT,
1224 .end = IRQ_DA850_VPIFINT,
1225 .flags = IORESOURCE_IRQ,
1226 },
1227 };
1228
1229 static struct platform_device da850_vpif_display_dev = {
1230 .name = "vpif_display",
1231 .id = -1,
1232 .dev = {
1233 .dma_mask = &da850_vpif_dma_mask,
1234 .coherent_dma_mask = DMA_BIT_MASK(32),
1235 },
1236 .resource = da850_vpif_display_resource,
1237 .num_resources = ARRAY_SIZE(da850_vpif_display_resource),
1238 };
1239
1240 static struct resource da850_vpif_capture_resource[] = {
1241 {
1242 .start = IRQ_DA850_VPIFINT,
1243 .end = IRQ_DA850_VPIFINT,
1244 .flags = IORESOURCE_IRQ,
1245 },
1246 {
1247 .start = IRQ_DA850_VPIFINT,
1248 .end = IRQ_DA850_VPIFINT,
1249 .flags = IORESOURCE_IRQ,
1250 },
1251 };
1252
1253 static struct platform_device da850_vpif_capture_dev = {
1254 .name = "vpif_capture",
1255 .id = -1,
1256 .dev = {
1257 .dma_mask = &da850_vpif_dma_mask,
1258 .coherent_dma_mask = DMA_BIT_MASK(32),
1259 },
1260 .resource = da850_vpif_capture_resource,
1261 .num_resources = ARRAY_SIZE(da850_vpif_capture_resource),
1262 };
1263
1264 int __init da850_register_vpif(void)
1265 {
1266 return platform_device_register(&da850_vpif_dev);
1267 }
1268
1269 int __init da850_register_vpif_display(struct vpif_display_config
1270 *display_config)
1271 {
1272 da850_vpif_display_dev.dev.platform_data = display_config;
1273 return platform_device_register(&da850_vpif_display_dev);
1274 }
1275
1276 int __init da850_register_vpif_capture(struct vpif_capture_config
1277 *capture_config)
1278 {
1279 da850_vpif_capture_dev.dev.platform_data = capture_config;
1280 return platform_device_register(&da850_vpif_capture_dev);
1281 }
1282
1283 static struct davinci_soc_info davinci_soc_info_da850 = {
1284 .io_desc = da850_io_desc,
1285 .io_desc_num = ARRAY_SIZE(da850_io_desc),
1286 .jtag_id_reg = DA8XX_SYSCFG0_BASE + DA8XX_JTAG_ID_REG,
1287 .ids = da850_ids,
1288 .ids_num = ARRAY_SIZE(da850_ids),
1289 .cpu_clks = da850_clks,
1290 .psc_bases = da850_psc_bases,
1291 .psc_bases_num = ARRAY_SIZE(da850_psc_bases),
1292 .pinmux_base = DA8XX_SYSCFG0_BASE + 0x120,
1293 .pinmux_pins = da850_pins,
1294 .pinmux_pins_num = ARRAY_SIZE(da850_pins),
1295 .intc_base = DA8XX_CP_INTC_BASE,
1296 .intc_type = DAVINCI_INTC_TYPE_CP_INTC,
1297 .intc_irq_prios = da850_default_priorities,
1298 .intc_irq_num = DA850_N_CP_INTC_IRQ,
1299 .timer_info = &da850_timer_info,
1300 .gpio_type = GPIO_TYPE_DAVINCI,
1301 .gpio_base = DA8XX_GPIO_BASE,
1302 .gpio_num = 144,
1303 .gpio_irq = IRQ_DA8XX_GPIO0,
1304 .serial_dev = &da8xx_serial_device,
1305 .emac_pdata = &da8xx_emac_pdata,
1306 .sram_dma = DA8XX_SHARED_RAM_BASE,
1307 .sram_len = SZ_128K,
1308 };
1309
1310 void __init da850_init(void)
1311 {
1312 unsigned int v;
1313
1314 davinci_common_init(&davinci_soc_info_da850);
1315
1316 da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
1317 if (WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module"))
1318 return;
1319
1320 da8xx_syscfg1_base = ioremap(DA8XX_SYSCFG1_BASE, SZ_4K);
1321 if (WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module"))
1322 return;
1323
1324 /*
1325 * Move the clock source of Async3 domain to PLL1 SYSCLK2.
1326 * This helps keeping the peripherals on this domain insulated
1327 * from CPU frequency changes caused by DVFS. The firmware sets
1328 * both PLL0 and PLL1 to the same frequency so, there should not
1329 * be any noticeable change even in non-DVFS use cases.
1330 */
1331 da850_set_async3_src(1);
1332
1333 /* Unlock writing to PLL0 registers */
1334 v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG));
1335 v &= ~CFGCHIP0_PLL_MASTER_LOCK;
1336 __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG));
1337
1338 /* Unlock writing to PLL1 registers */
1339 v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
1340 v &= ~CFGCHIP3_PLL1_MASTER_LOCK;
1341 __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
1342 }
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