2 * arch/arm/mach-ep93xx/core.c
3 * Core routines for Cirrus EP93xx chips.
5 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
6 * Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org>
8 * Thanks go to Michael Burian and Ray Lehtiniemi for their key
9 * role in the ep93xx linux community.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
17 #define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/platform_device.h>
22 #include <linux/interrupt.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/timex.h>
25 #include <linux/irq.h>
27 #include <linux/gpio.h>
28 #include <linux/leds.h>
29 #include <linux/termios.h>
30 #include <linux/amba/bus.h>
31 #include <linux/amba/serial.h>
32 #include <linux/mtd/physmap.h>
33 #include <linux/i2c.h>
34 #include <linux/i2c-gpio.h>
35 #include <linux/spi/spi.h>
36 #include <linux/export.h>
37 #include <linux/irqchip/arm-vic.h>
38 #include <linux/reboot.h>
40 #include <mach/hardware.h>
41 #include <linux/platform_data/video-ep93xx.h>
42 #include <linux/platform_data/keypad-ep93xx.h>
43 #include <linux/platform_data/spi-ep93xx.h>
44 #include <mach/gpio-ep93xx.h>
46 #include <asm/mach/map.h>
47 #include <asm/mach/time.h>
51 /*************************************************************************
52 * Static I/O mappings that are needed for all EP93xx platforms
53 *************************************************************************/
54 static struct map_desc ep93xx_io_desc
[] __initdata
= {
56 .virtual = EP93XX_AHB_VIRT_BASE
,
57 .pfn
= __phys_to_pfn(EP93XX_AHB_PHYS_BASE
),
58 .length
= EP93XX_AHB_SIZE
,
61 .virtual = EP93XX_APB_VIRT_BASE
,
62 .pfn
= __phys_to_pfn(EP93XX_APB_PHYS_BASE
),
63 .length
= EP93XX_APB_SIZE
,
68 void __init
ep93xx_map_io(void)
70 iotable_init(ep93xx_io_desc
, ARRAY_SIZE(ep93xx_io_desc
));
74 /*************************************************************************
75 * Timer handling for EP93xx
76 *************************************************************************
77 * The ep93xx has four internal timers. Timers 1, 2 (both 16 bit) and
78 * 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate
79 * an interrupt on underflow. Timer 4 (40 bit) counts down at 983.04 kHz,
80 * is free-running, and can't generate interrupts.
82 * The 508 kHz timers are ideal for use for the timer interrupt, as the
83 * most common values of HZ divide 508 kHz nicely. We pick one of the 16
84 * bit timers (timer 1) since we don't need more than 16 bits of reload
85 * value as long as HZ >= 8.
87 * The higher clock rate of timer 4 makes it a better choice than the
88 * other timers for use in gettimeoffset(), while the fact that it can't
89 * generate interrupts means we don't have to worry about not being able
90 * to use this timer for something else. We also use timer 4 for keeping
91 * track of lost jiffies.
93 #define EP93XX_TIMER_REG(x) (EP93XX_TIMER_BASE + (x))
94 #define EP93XX_TIMER1_LOAD EP93XX_TIMER_REG(0x00)
95 #define EP93XX_TIMER1_VALUE EP93XX_TIMER_REG(0x04)
96 #define EP93XX_TIMER1_CONTROL EP93XX_TIMER_REG(0x08)
97 #define EP93XX_TIMER123_CONTROL_ENABLE (1 << 7)
98 #define EP93XX_TIMER123_CONTROL_MODE (1 << 6)
99 #define EP93XX_TIMER123_CONTROL_CLKSEL (1 << 3)
100 #define EP93XX_TIMER1_CLEAR EP93XX_TIMER_REG(0x0c)
101 #define EP93XX_TIMER2_LOAD EP93XX_TIMER_REG(0x20)
102 #define EP93XX_TIMER2_VALUE EP93XX_TIMER_REG(0x24)
103 #define EP93XX_TIMER2_CONTROL EP93XX_TIMER_REG(0x28)
104 #define EP93XX_TIMER2_CLEAR EP93XX_TIMER_REG(0x2c)
105 #define EP93XX_TIMER4_VALUE_LOW EP93XX_TIMER_REG(0x60)
106 #define EP93XX_TIMER4_VALUE_HIGH EP93XX_TIMER_REG(0x64)
107 #define EP93XX_TIMER4_VALUE_HIGH_ENABLE (1 << 8)
108 #define EP93XX_TIMER3_LOAD EP93XX_TIMER_REG(0x80)
109 #define EP93XX_TIMER3_VALUE EP93XX_TIMER_REG(0x84)
110 #define EP93XX_TIMER3_CONTROL EP93XX_TIMER_REG(0x88)
111 #define EP93XX_TIMER3_CLEAR EP93XX_TIMER_REG(0x8c)
113 #define EP93XX_TIMER123_CLOCK 508469
114 #define EP93XX_TIMER4_CLOCK 983040
116 #define TIMER1_RELOAD ((EP93XX_TIMER123_CLOCK / HZ) - 1)
117 #define TIMER4_TICKS_PER_JIFFY DIV_ROUND_CLOSEST(CLOCK_TICK_RATE, HZ)
119 static unsigned int last_jiffy_time
;
121 static irqreturn_t
ep93xx_timer_interrupt(int irq
, void *dev_id
)
123 /* Writing any value clears the timer interrupt */
124 __raw_writel(1, EP93XX_TIMER1_CLEAR
);
126 /* Recover lost jiffies */
128 (__raw_readl(EP93XX_TIMER4_VALUE_LOW
) - last_jiffy_time
)
129 >= TIMER4_TICKS_PER_JIFFY
) {
130 last_jiffy_time
+= TIMER4_TICKS_PER_JIFFY
;
137 static struct irqaction ep93xx_timer_irq
= {
138 .name
= "ep93xx timer",
139 .flags
= IRQF_DISABLED
| IRQF_TIMER
| IRQF_IRQPOLL
,
140 .handler
= ep93xx_timer_interrupt
,
143 static u32
ep93xx_gettimeoffset(void)
147 offset
= __raw_readl(EP93XX_TIMER4_VALUE_LOW
) - last_jiffy_time
;
150 * Timer 4 is based on a 983.04 kHz reference clock,
151 * so dividing by 983040 gives the fraction of a second,
152 * so dividing by 0.983040 converts to uS.
153 * Refactor the calculation to avoid overflow.
154 * Finally, multiply by 1000 to give nS.
156 return (offset
+ (53 * offset
/ 3072)) * 1000;
159 void __init
ep93xx_timer_init(void)
161 u32 tmode
= EP93XX_TIMER123_CONTROL_MODE
|
162 EP93XX_TIMER123_CONTROL_CLKSEL
;
164 arch_gettimeoffset
= ep93xx_gettimeoffset
;
166 /* Enable periodic HZ timer. */
167 __raw_writel(tmode
, EP93XX_TIMER1_CONTROL
);
168 __raw_writel(TIMER1_RELOAD
, EP93XX_TIMER1_LOAD
);
169 __raw_writel(tmode
| EP93XX_TIMER123_CONTROL_ENABLE
,
170 EP93XX_TIMER1_CONTROL
);
172 /* Enable lost jiffy timer. */
173 __raw_writel(EP93XX_TIMER4_VALUE_HIGH_ENABLE
,
174 EP93XX_TIMER4_VALUE_HIGH
);
176 setup_irq(IRQ_EP93XX_TIMER1
, &ep93xx_timer_irq
);
180 /*************************************************************************
181 * EP93xx IRQ handling
182 *************************************************************************/
183 void __init
ep93xx_init_irq(void)
185 vic_init(EP93XX_VIC1_BASE
, 0, EP93XX_VIC1_VALID_IRQ_MASK
, 0);
186 vic_init(EP93XX_VIC2_BASE
, 32, EP93XX_VIC2_VALID_IRQ_MASK
, 0);
190 /*************************************************************************
191 * EP93xx System Controller Software Locked register handling
192 *************************************************************************/
195 * syscon_swlock prevents anything else from writing to the syscon
196 * block while a software locked register is being written.
198 static DEFINE_SPINLOCK(syscon_swlock
);
200 void ep93xx_syscon_swlocked_write(unsigned int val
, void __iomem
*reg
)
204 spin_lock_irqsave(&syscon_swlock
, flags
);
206 __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK
);
207 __raw_writel(val
, reg
);
209 spin_unlock_irqrestore(&syscon_swlock
, flags
);
212 void ep93xx_devcfg_set_clear(unsigned int set_bits
, unsigned int clear_bits
)
217 spin_lock_irqsave(&syscon_swlock
, flags
);
219 val
= __raw_readl(EP93XX_SYSCON_DEVCFG
);
222 __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK
);
223 __raw_writel(val
, EP93XX_SYSCON_DEVCFG
);
225 spin_unlock_irqrestore(&syscon_swlock
, flags
);
229 * ep93xx_chip_revision() - returns the EP93xx chip revision
231 * See <mach/platform.h> for more information.
233 unsigned int ep93xx_chip_revision(void)
237 v
= __raw_readl(EP93XX_SYSCON_SYSCFG
);
238 v
&= EP93XX_SYSCON_SYSCFG_REV_MASK
;
239 v
>>= EP93XX_SYSCON_SYSCFG_REV_SHIFT
;
243 /*************************************************************************
245 *************************************************************************/
246 static struct resource ep93xx_gpio_resource
[] = {
247 DEFINE_RES_MEM(EP93XX_GPIO_PHYS_BASE
, 0xcc),
250 static struct platform_device ep93xx_gpio_device
= {
251 .name
= "gpio-ep93xx",
253 .num_resources
= ARRAY_SIZE(ep93xx_gpio_resource
),
254 .resource
= ep93xx_gpio_resource
,
257 /*************************************************************************
258 * EP93xx peripheral handling
259 *************************************************************************/
260 #define EP93XX_UART_MCR_OFFSET (0x0100)
262 static void ep93xx_uart_set_mctrl(struct amba_device
*dev
,
263 void __iomem
*base
, unsigned int mctrl
)
268 if (mctrl
& TIOCM_RTS
)
270 if (mctrl
& TIOCM_DTR
)
273 __raw_writel(mcr
, base
+ EP93XX_UART_MCR_OFFSET
);
276 static struct amba_pl010_data ep93xx_uart_data
= {
277 .set_mctrl
= ep93xx_uart_set_mctrl
,
280 static AMBA_APB_DEVICE(uart1
, "apb:uart1", 0x00041010, EP93XX_UART1_PHYS_BASE
,
281 { IRQ_EP93XX_UART1
}, &ep93xx_uart_data
);
283 static AMBA_APB_DEVICE(uart2
, "apb:uart2", 0x00041010, EP93XX_UART2_PHYS_BASE
,
284 { IRQ_EP93XX_UART2
}, &ep93xx_uart_data
);
286 static AMBA_APB_DEVICE(uart3
, "apb:uart3", 0x00041010, EP93XX_UART3_PHYS_BASE
,
287 { IRQ_EP93XX_UART3
}, &ep93xx_uart_data
);
289 static struct resource ep93xx_rtc_resource
[] = {
290 DEFINE_RES_MEM(EP93XX_RTC_PHYS_BASE
, 0x10c),
293 static struct platform_device ep93xx_rtc_device
= {
294 .name
= "ep93xx-rtc",
296 .num_resources
= ARRAY_SIZE(ep93xx_rtc_resource
),
297 .resource
= ep93xx_rtc_resource
,
301 static struct resource ep93xx_ohci_resources
[] = {
302 DEFINE_RES_MEM(EP93XX_USB_PHYS_BASE
, 0x1000),
303 DEFINE_RES_IRQ(IRQ_EP93XX_USB
),
307 static struct platform_device ep93xx_ohci_device
= {
308 .name
= "ep93xx-ohci",
311 .dma_mask
= &ep93xx_ohci_device
.dev
.coherent_dma_mask
,
312 .coherent_dma_mask
= DMA_BIT_MASK(32),
314 .num_resources
= ARRAY_SIZE(ep93xx_ohci_resources
),
315 .resource
= ep93xx_ohci_resources
,
319 /*************************************************************************
320 * EP93xx physmap'ed flash
321 *************************************************************************/
322 static struct physmap_flash_data ep93xx_flash_data
;
324 static struct resource ep93xx_flash_resource
= {
325 .flags
= IORESOURCE_MEM
,
328 static struct platform_device ep93xx_flash
= {
329 .name
= "physmap-flash",
332 .platform_data
= &ep93xx_flash_data
,
335 .resource
= &ep93xx_flash_resource
,
339 * ep93xx_register_flash() - Register the external flash device.
340 * @width: bank width in octets
341 * @start: resource start address
342 * @size: resource size
344 void __init
ep93xx_register_flash(unsigned int width
,
345 resource_size_t start
, resource_size_t size
)
347 ep93xx_flash_data
.width
= width
;
349 ep93xx_flash_resource
.start
= start
;
350 ep93xx_flash_resource
.end
= start
+ size
- 1;
352 platform_device_register(&ep93xx_flash
);
356 /*************************************************************************
357 * EP93xx ethernet peripheral handling
358 *************************************************************************/
359 static struct ep93xx_eth_data ep93xx_eth_data
;
361 static struct resource ep93xx_eth_resource
[] = {
362 DEFINE_RES_MEM(EP93XX_ETHERNET_PHYS_BASE
, 0x10000),
363 DEFINE_RES_IRQ(IRQ_EP93XX_ETHERNET
),
366 static u64 ep93xx_eth_dma_mask
= DMA_BIT_MASK(32);
368 static struct platform_device ep93xx_eth_device
= {
369 .name
= "ep93xx-eth",
372 .platform_data
= &ep93xx_eth_data
,
373 .coherent_dma_mask
= DMA_BIT_MASK(32),
374 .dma_mask
= &ep93xx_eth_dma_mask
,
376 .num_resources
= ARRAY_SIZE(ep93xx_eth_resource
),
377 .resource
= ep93xx_eth_resource
,
381 * ep93xx_register_eth - Register the built-in ethernet platform device.
382 * @data: platform specific ethernet configuration (__initdata)
383 * @copy_addr: flag indicating that the MAC address should be copied
384 * from the IndAd registers (as programmed by the bootloader)
386 void __init
ep93xx_register_eth(struct ep93xx_eth_data
*data
, int copy_addr
)
389 memcpy_fromio(data
->dev_addr
, EP93XX_ETHERNET_BASE
+ 0x50, 6);
391 ep93xx_eth_data
= *data
;
392 platform_device_register(&ep93xx_eth_device
);
396 /*************************************************************************
397 * EP93xx i2c peripheral handling
398 *************************************************************************/
399 static struct i2c_gpio_platform_data ep93xx_i2c_data
;
401 static struct platform_device ep93xx_i2c_device
= {
405 .platform_data
= &ep93xx_i2c_data
,
410 * ep93xx_register_i2c - Register the i2c platform device.
411 * @data: platform specific i2c-gpio configuration (__initdata)
412 * @devices: platform specific i2c bus device information (__initdata)
413 * @num: the number of devices on the i2c bus
415 void __init
ep93xx_register_i2c(struct i2c_gpio_platform_data
*data
,
416 struct i2c_board_info
*devices
, int num
)
419 * Set the EEPROM interface pin drive type control.
420 * Defines the driver type for the EECLK and EEDAT pins as either
421 * open drain, which will require an external pull-up, or a normal
424 if (data
->sda_is_open_drain
&& data
->sda_pin
!= EP93XX_GPIO_LINE_EEDAT
)
425 pr_warning("sda != EEDAT, open drain has no effect\n");
426 if (data
->scl_is_open_drain
&& data
->scl_pin
!= EP93XX_GPIO_LINE_EECLK
)
427 pr_warning("scl != EECLK, open drain has no effect\n");
429 __raw_writel((data
->sda_is_open_drain
<< 1) |
430 (data
->scl_is_open_drain
<< 0),
431 EP93XX_GPIO_EEDRIVE
);
433 ep93xx_i2c_data
= *data
;
434 i2c_register_board_info(0, devices
, num
);
435 platform_device_register(&ep93xx_i2c_device
);
438 /*************************************************************************
439 * EP93xx SPI peripheral handling
440 *************************************************************************/
441 static struct ep93xx_spi_info ep93xx_spi_master_data
;
443 static struct resource ep93xx_spi_resources
[] = {
444 DEFINE_RES_MEM(EP93XX_SPI_PHYS_BASE
, 0x18),
445 DEFINE_RES_IRQ(IRQ_EP93XX_SSP
),
448 static u64 ep93xx_spi_dma_mask
= DMA_BIT_MASK(32);
450 static struct platform_device ep93xx_spi_device
= {
451 .name
= "ep93xx-spi",
454 .platform_data
= &ep93xx_spi_master_data
,
455 .coherent_dma_mask
= DMA_BIT_MASK(32),
456 .dma_mask
= &ep93xx_spi_dma_mask
,
458 .num_resources
= ARRAY_SIZE(ep93xx_spi_resources
),
459 .resource
= ep93xx_spi_resources
,
463 * ep93xx_register_spi() - registers spi platform device
464 * @info: ep93xx board specific spi master info (__initdata)
465 * @devices: SPI devices to register (__initdata)
466 * @num: number of SPI devices to register
468 * This function registers platform device for the EP93xx SPI controller and
469 * also makes sure that SPI pins are muxed so that I2S is not using those pins.
471 void __init
ep93xx_register_spi(struct ep93xx_spi_info
*info
,
472 struct spi_board_info
*devices
, int num
)
475 * When SPI is used, we need to make sure that I2S is muxed off from
478 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_I2SONSSP
);
480 ep93xx_spi_master_data
= *info
;
481 spi_register_board_info(devices
, num
);
482 platform_device_register(&ep93xx_spi_device
);
485 /*************************************************************************
487 *************************************************************************/
488 static const struct gpio_led ep93xx_led_pins
[] __initconst
= {
490 .name
= "platform:grled",
491 .gpio
= EP93XX_GPIO_LINE_GRLED
,
493 .name
= "platform:rdled",
494 .gpio
= EP93XX_GPIO_LINE_RDLED
,
498 static const struct gpio_led_platform_data ep93xx_led_data __initconst
= {
499 .num_leds
= ARRAY_SIZE(ep93xx_led_pins
),
500 .leds
= ep93xx_led_pins
,
503 /*************************************************************************
504 * EP93xx pwm peripheral handling
505 *************************************************************************/
506 static struct resource ep93xx_pwm0_resource
[] = {
507 DEFINE_RES_MEM(EP93XX_PWM_PHYS_BASE
, 0x10),
510 static struct platform_device ep93xx_pwm0_device
= {
511 .name
= "ep93xx-pwm",
513 .num_resources
= ARRAY_SIZE(ep93xx_pwm0_resource
),
514 .resource
= ep93xx_pwm0_resource
,
517 static struct resource ep93xx_pwm1_resource
[] = {
518 DEFINE_RES_MEM(EP93XX_PWM_PHYS_BASE
+ 0x20, 0x10),
521 static struct platform_device ep93xx_pwm1_device
= {
522 .name
= "ep93xx-pwm",
524 .num_resources
= ARRAY_SIZE(ep93xx_pwm1_resource
),
525 .resource
= ep93xx_pwm1_resource
,
528 void __init
ep93xx_register_pwm(int pwm0
, int pwm1
)
531 platform_device_register(&ep93xx_pwm0_device
);
533 /* NOTE: EP9307 does not have PWMOUT1 (pin EGPIO14) */
535 platform_device_register(&ep93xx_pwm1_device
);
538 int ep93xx_pwm_acquire_gpio(struct platform_device
*pdev
)
544 } else if (pdev
->id
== 1) {
545 err
= gpio_request(EP93XX_GPIO_LINE_EGPIO14
,
546 dev_name(&pdev
->dev
));
549 err
= gpio_direction_output(EP93XX_GPIO_LINE_EGPIO14
, 0);
553 /* PWM 1 output on EGPIO[14] */
554 ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_PONG
);
562 gpio_free(EP93XX_GPIO_LINE_EGPIO14
);
565 EXPORT_SYMBOL(ep93xx_pwm_acquire_gpio
);
567 void ep93xx_pwm_release_gpio(struct platform_device
*pdev
)
570 gpio_direction_input(EP93XX_GPIO_LINE_EGPIO14
);
571 gpio_free(EP93XX_GPIO_LINE_EGPIO14
);
573 /* EGPIO[14] used for GPIO */
574 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_PONG
);
577 EXPORT_SYMBOL(ep93xx_pwm_release_gpio
);
580 /*************************************************************************
581 * EP93xx video peripheral handling
582 *************************************************************************/
583 static struct ep93xxfb_mach_info ep93xxfb_data
;
585 static struct resource ep93xx_fb_resource
[] = {
586 DEFINE_RES_MEM(EP93XX_RASTER_PHYS_BASE
, 0x800),
589 static struct platform_device ep93xx_fb_device
= {
593 .platform_data
= &ep93xxfb_data
,
594 .coherent_dma_mask
= DMA_BIT_MASK(32),
595 .dma_mask
= &ep93xx_fb_device
.dev
.coherent_dma_mask
,
597 .num_resources
= ARRAY_SIZE(ep93xx_fb_resource
),
598 .resource
= ep93xx_fb_resource
,
601 /* The backlight use a single register in the framebuffer's register space */
602 #define EP93XX_RASTER_REG_BRIGHTNESS 0x20
604 static struct resource ep93xx_bl_resources
[] = {
605 DEFINE_RES_MEM(EP93XX_RASTER_PHYS_BASE
+
606 EP93XX_RASTER_REG_BRIGHTNESS
, 0x04),
609 static struct platform_device ep93xx_bl_device
= {
612 .num_resources
= ARRAY_SIZE(ep93xx_bl_resources
),
613 .resource
= ep93xx_bl_resources
,
617 * ep93xx_register_fb - Register the framebuffer platform device.
618 * @data: platform specific framebuffer configuration (__initdata)
620 void __init
ep93xx_register_fb(struct ep93xxfb_mach_info
*data
)
622 ep93xxfb_data
= *data
;
623 platform_device_register(&ep93xx_fb_device
);
624 platform_device_register(&ep93xx_bl_device
);
628 /*************************************************************************
629 * EP93xx matrix keypad peripheral handling
630 *************************************************************************/
631 static struct ep93xx_keypad_platform_data ep93xx_keypad_data
;
633 static struct resource ep93xx_keypad_resource
[] = {
634 DEFINE_RES_MEM(EP93XX_KEY_MATRIX_PHYS_BASE
, 0x0c),
635 DEFINE_RES_IRQ(IRQ_EP93XX_KEY
),
638 static struct platform_device ep93xx_keypad_device
= {
639 .name
= "ep93xx-keypad",
642 .platform_data
= &ep93xx_keypad_data
,
644 .num_resources
= ARRAY_SIZE(ep93xx_keypad_resource
),
645 .resource
= ep93xx_keypad_resource
,
649 * ep93xx_register_keypad - Register the keypad platform device.
650 * @data: platform specific keypad configuration (__initdata)
652 void __init
ep93xx_register_keypad(struct ep93xx_keypad_platform_data
*data
)
654 ep93xx_keypad_data
= *data
;
655 platform_device_register(&ep93xx_keypad_device
);
658 int ep93xx_keypad_acquire_gpio(struct platform_device
*pdev
)
663 for (i
= 0; i
< 8; i
++) {
664 err
= gpio_request(EP93XX_GPIO_LINE_C(i
), dev_name(&pdev
->dev
));
667 err
= gpio_request(EP93XX_GPIO_LINE_D(i
), dev_name(&pdev
->dev
));
672 /* Enable the keypad controller; GPIO ports C and D used for keypad */
673 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_KEYS
|
674 EP93XX_SYSCON_DEVCFG_GONK
);
679 gpio_free(EP93XX_GPIO_LINE_C(i
));
681 for (--i
; i
>= 0; --i
) {
682 gpio_free(EP93XX_GPIO_LINE_C(i
));
683 gpio_free(EP93XX_GPIO_LINE_D(i
));
687 EXPORT_SYMBOL(ep93xx_keypad_acquire_gpio
);
689 void ep93xx_keypad_release_gpio(struct platform_device
*pdev
)
693 for (i
= 0; i
< 8; i
++) {
694 gpio_free(EP93XX_GPIO_LINE_C(i
));
695 gpio_free(EP93XX_GPIO_LINE_D(i
));
698 /* Disable the keypad controller; GPIO ports C and D used for GPIO */
699 ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_KEYS
|
700 EP93XX_SYSCON_DEVCFG_GONK
);
702 EXPORT_SYMBOL(ep93xx_keypad_release_gpio
);
704 /*************************************************************************
705 * EP93xx I2S audio peripheral handling
706 *************************************************************************/
707 static struct resource ep93xx_i2s_resource
[] = {
708 DEFINE_RES_MEM(EP93XX_I2S_PHYS_BASE
, 0x100),
711 static struct platform_device ep93xx_i2s_device
= {
712 .name
= "ep93xx-i2s",
714 .num_resources
= ARRAY_SIZE(ep93xx_i2s_resource
),
715 .resource
= ep93xx_i2s_resource
,
718 static struct platform_device ep93xx_pcm_device
= {
719 .name
= "ep93xx-pcm-audio",
723 void __init
ep93xx_register_i2s(void)
725 platform_device_register(&ep93xx_i2s_device
);
726 platform_device_register(&ep93xx_pcm_device
);
729 #define EP93XX_SYSCON_DEVCFG_I2S_MASK (EP93XX_SYSCON_DEVCFG_I2SONSSP | \
730 EP93XX_SYSCON_DEVCFG_I2SONAC97)
732 #define EP93XX_I2SCLKDIV_MASK (EP93XX_SYSCON_I2SCLKDIV_ORIDE | \
733 EP93XX_SYSCON_I2SCLKDIV_SPOL)
735 int ep93xx_i2s_acquire(void)
739 ep93xx_devcfg_set_clear(EP93XX_SYSCON_DEVCFG_I2SONAC97
,
740 EP93XX_SYSCON_DEVCFG_I2S_MASK
);
743 * This is potentially racy with the clock api for i2s_mclk, sclk and
744 * lrclk. Since the i2s driver is the only user of those clocks we
745 * rely on it to prevent parallel use of this function and the
746 * clock api for the i2s clocks.
748 val
= __raw_readl(EP93XX_SYSCON_I2SCLKDIV
);
749 val
&= ~EP93XX_I2SCLKDIV_MASK
;
750 val
|= EP93XX_SYSCON_I2SCLKDIV_ORIDE
| EP93XX_SYSCON_I2SCLKDIV_SPOL
;
751 ep93xx_syscon_swlocked_write(val
, EP93XX_SYSCON_I2SCLKDIV
);
755 EXPORT_SYMBOL(ep93xx_i2s_acquire
);
757 void ep93xx_i2s_release(void)
759 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_I2S_MASK
);
761 EXPORT_SYMBOL(ep93xx_i2s_release
);
763 /*************************************************************************
764 * EP93xx AC97 audio peripheral handling
765 *************************************************************************/
766 static struct resource ep93xx_ac97_resources
[] = {
767 DEFINE_RES_MEM(EP93XX_AAC_PHYS_BASE
, 0xac),
768 DEFINE_RES_IRQ(IRQ_EP93XX_AACINTR
),
771 static struct platform_device ep93xx_ac97_device
= {
772 .name
= "ep93xx-ac97",
774 .num_resources
= ARRAY_SIZE(ep93xx_ac97_resources
),
775 .resource
= ep93xx_ac97_resources
,
778 void __init
ep93xx_register_ac97(void)
781 * Make sure that the AC97 pins are not used by I2S.
783 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_I2SONAC97
);
785 platform_device_register(&ep93xx_ac97_device
);
786 platform_device_register(&ep93xx_pcm_device
);
789 /*************************************************************************
791 *************************************************************************/
792 static struct resource ep93xx_wdt_resources
[] = {
793 DEFINE_RES_MEM(EP93XX_WATCHDOG_PHYS_BASE
, 0x08),
796 static struct platform_device ep93xx_wdt_device
= {
797 .name
= "ep93xx-wdt",
799 .num_resources
= ARRAY_SIZE(ep93xx_wdt_resources
),
800 .resource
= ep93xx_wdt_resources
,
803 /*************************************************************************
805 *************************************************************************/
806 static struct resource ep93xx_ide_resources
[] = {
807 DEFINE_RES_MEM(EP93XX_IDE_PHYS_BASE
, 0x38),
808 DEFINE_RES_IRQ(IRQ_EP93XX_EXT3
),
811 static struct platform_device ep93xx_ide_device
= {
812 .name
= "ep93xx-ide",
815 .dma_mask
= &ep93xx_ide_device
.dev
.coherent_dma_mask
,
816 .coherent_dma_mask
= DMA_BIT_MASK(32),
818 .num_resources
= ARRAY_SIZE(ep93xx_ide_resources
),
819 .resource
= ep93xx_ide_resources
,
822 void __init
ep93xx_register_ide(void)
824 platform_device_register(&ep93xx_ide_device
);
827 int ep93xx_ide_acquire_gpio(struct platform_device
*pdev
)
832 err
= gpio_request(EP93XX_GPIO_LINE_EGPIO2
, dev_name(&pdev
->dev
));
835 err
= gpio_request(EP93XX_GPIO_LINE_EGPIO15
, dev_name(&pdev
->dev
));
838 for (i
= 2; i
< 8; i
++) {
839 err
= gpio_request(EP93XX_GPIO_LINE_E(i
), dev_name(&pdev
->dev
));
843 for (i
= 4; i
< 8; i
++) {
844 err
= gpio_request(EP93XX_GPIO_LINE_G(i
), dev_name(&pdev
->dev
));
848 for (i
= 0; i
< 8; i
++) {
849 err
= gpio_request(EP93XX_GPIO_LINE_H(i
), dev_name(&pdev
->dev
));
854 /* GPIO ports E[7:2], G[7:4] and H used by IDE */
855 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_EONIDE
|
856 EP93XX_SYSCON_DEVCFG_GONIDE
|
857 EP93XX_SYSCON_DEVCFG_HONIDE
);
861 for (--i
; i
>= 0; --i
)
862 gpio_free(EP93XX_GPIO_LINE_H(i
));
865 for (--i
; i
>= 4; --i
)
866 gpio_free(EP93XX_GPIO_LINE_G(i
));
869 for (--i
; i
>= 2; --i
)
870 gpio_free(EP93XX_GPIO_LINE_E(i
));
871 gpio_free(EP93XX_GPIO_LINE_EGPIO15
);
873 gpio_free(EP93XX_GPIO_LINE_EGPIO2
);
876 EXPORT_SYMBOL(ep93xx_ide_acquire_gpio
);
878 void ep93xx_ide_release_gpio(struct platform_device
*pdev
)
882 for (i
= 2; i
< 8; i
++)
883 gpio_free(EP93XX_GPIO_LINE_E(i
));
884 for (i
= 4; i
< 8; i
++)
885 gpio_free(EP93XX_GPIO_LINE_G(i
));
886 for (i
= 0; i
< 8; i
++)
887 gpio_free(EP93XX_GPIO_LINE_H(i
));
888 gpio_free(EP93XX_GPIO_LINE_EGPIO15
);
889 gpio_free(EP93XX_GPIO_LINE_EGPIO2
);
892 /* GPIO ports E[7:2], G[7:4] and H used by GPIO */
893 ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_EONIDE
|
894 EP93XX_SYSCON_DEVCFG_GONIDE
|
895 EP93XX_SYSCON_DEVCFG_HONIDE
);
897 EXPORT_SYMBOL(ep93xx_ide_release_gpio
);
899 void __init
ep93xx_init_devices(void)
901 /* Disallow access to MaverickCrunch initially */
902 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_CPENA
);
904 /* Default all ports to GPIO */
905 ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_KEYS
|
906 EP93XX_SYSCON_DEVCFG_GONK
|
907 EP93XX_SYSCON_DEVCFG_EONIDE
|
908 EP93XX_SYSCON_DEVCFG_GONIDE
|
909 EP93XX_SYSCON_DEVCFG_HONIDE
);
911 /* Get the GPIO working early, other devices need it */
912 platform_device_register(&ep93xx_gpio_device
);
914 amba_device_register(&uart1_device
, &iomem_resource
);
915 amba_device_register(&uart2_device
, &iomem_resource
);
916 amba_device_register(&uart3_device
, &iomem_resource
);
918 platform_device_register(&ep93xx_rtc_device
);
919 platform_device_register(&ep93xx_ohci_device
);
920 platform_device_register(&ep93xx_wdt_device
);
922 gpio_led_register_device(-1, &ep93xx_led_data
);
925 void ep93xx_restart(enum reboot_mode mode
, const char *cmd
)
928 * Set then clear the SWRST bit to initiate a software reset
930 ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_SWRST
);
931 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_SWRST
);
937 void __init
ep93xx_init_late(void)