arch/arm/mach-exynos/common.c

   1 /*
   2  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * Common Codes for EXYNOS
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/bitops.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/irq.h>
  16 #include <linux/irqchip.h>
  17 #include <linux/io.h>
  18 #include <linux/device.h>
  19 #include <linux/gpio.h>
  20 #include <clocksource/samsung_pwm.h>
  21 #include <linux/sched.h>
  22 #include <linux/serial_core.h>
  23 #include <linux/of.h>
  24 #include <linux/of_fdt.h>
  25 #include <linux/of_irq.h>
  26 #include <linux/export.h>
  27 #include <linux/irqdomain.h>
  28 #include <linux/of_address.h>
  29 #include <linux/clocksource.h>
  30 #include <linux/clk-provider.h>
  31 #include <linux/irqchip/arm-gic.h>
  32 #include <linux/irqchip/chained_irq.h>
  33
  34 #include <asm/proc-fns.h>
  35 #include <asm/exception.h>
  36 #include <asm/hardware/cache-l2x0.h>
  37 #include <asm/mach/map.h>
  38 #include <asm/mach/irq.h>
  39 #include <asm/cacheflush.h>
  40
  41 #include <mach/regs-irq.h>
  42 #include <mach/regs-pmu.h>
  43
  44 #include <plat/cpu.h>
  45 #include <plat/pm.h>
  46 #include <plat/regs-serial.h>
  47
  48 #include "common.h"
  49 #define L2_AUX_VAL 0x7C470001
  50 #define L2_AUX_MASK 0xC200ffff
  51
  52 static const char name_exynos4210[] = "EXYNOS4210";
  53 static const char name_exynos4212[] = "EXYNOS4212";
  54 static const char name_exynos4412[] = "EXYNOS4412";
  55 static const char name_exynos5250[] = "EXYNOS5250";
  56 static const char name_exynos5420[] = "EXYNOS5420";
  57 static const char name_exynos5440[] = "EXYNOS5440";
  58
  59 static void exynos4_map_io(void);
  60 static void exynos5_map_io(void);
  61 static int exynos_init(void);
  62
  63 static struct cpu_table cpu_ids[] __initdata = {
  64         {
  65                 .idcode         = EXYNOS4210_CPU_ID,
  66                 .idmask         = EXYNOS4_CPU_MASK,
  67                 .map_io         = exynos4_map_io,
  68                 .init           = exynos_init,
  69                 .name           = name_exynos4210,
  70         }, {
  71                 .idcode         = EXYNOS4212_CPU_ID,
  72                 .idmask         = EXYNOS4_CPU_MASK,
  73                 .map_io         = exynos4_map_io,
  74                 .init           = exynos_init,
  75                 .name           = name_exynos4212,
  76         }, {
  77                 .idcode         = EXYNOS4412_CPU_ID,
  78                 .idmask         = EXYNOS4_CPU_MASK,
  79                 .map_io         = exynos4_map_io,
  80                 .init           = exynos_init,
  81                 .name           = name_exynos4412,
  82         }, {
  83                 .idcode         = EXYNOS5250_SOC_ID,
  84                 .idmask         = EXYNOS5_SOC_MASK,
  85                 .map_io         = exynos5_map_io,
  86                 .init           = exynos_init,
  87                 .name           = name_exynos5250,
  88         }, {
  89                 .idcode         = EXYNOS5420_SOC_ID,
  90                 .idmask         = EXYNOS5_SOC_MASK,
  91                 .map_io         = exynos5_map_io,
  92                 .init           = exynos_init,
  93                 .name           = name_exynos5420,
  94         }, {
  95                 .idcode         = EXYNOS5440_SOC_ID,
  96                 .idmask         = EXYNOS5_SOC_MASK,
  97                 .init           = exynos_init,
  98                 .name           = name_exynos5440,
  99         },
 100 };
 101
 102 /* Initial IO mappings */
 103
 104 static struct map_desc exynos4_iodesc[] __initdata = {
 105         {
 106                 .virtual        = (unsigned long)S3C_VA_SYS,
 107                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSCON),
 108                 .length         = SZ_64K,
 109                 .type           = MT_DEVICE,
 110         }, {
 111                 .virtual        = (unsigned long)S3C_VA_TIMER,
 112                 .pfn            = __phys_to_pfn(EXYNOS4_PA_TIMER),
 113                 .length         = SZ_16K,
 114                 .type           = MT_DEVICE,
 115         }, {
 116                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
 117                 .pfn            = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
 118                 .length         = SZ_4K,
 119                 .type           = MT_DEVICE,
 120         }, {
 121                 .virtual        = (unsigned long)S5P_VA_SROMC,
 122                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SROMC),
 123                 .length         = SZ_4K,
 124                 .type           = MT_DEVICE,
 125         }, {
 126                 .virtual        = (unsigned long)S5P_VA_SYSTIMER,
 127                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
 128                 .length         = SZ_4K,
 129                 .type           = MT_DEVICE,
 130         }, {
 131                 .virtual        = (unsigned long)S5P_VA_PMU,
 132                 .pfn            = __phys_to_pfn(EXYNOS4_PA_PMU),
 133                 .length         = SZ_64K,
 134                 .type           = MT_DEVICE,
 135         }, {
 136                 .virtual        = (unsigned long)S5P_VA_COMBINER_BASE,
 137                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COMBINER),
 138                 .length         = SZ_4K,
 139                 .type           = MT_DEVICE,
 140         }, {
 141                 .virtual        = (unsigned long)S5P_VA_GIC_CPU,
 142                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
 143                 .length         = SZ_64K,
 144                 .type           = MT_DEVICE,
 145         }, {
 146                 .virtual        = (unsigned long)S5P_VA_GIC_DIST,
 147                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
 148                 .length         = SZ_64K,
 149                 .type           = MT_DEVICE,
 150         }, {
 151                 .virtual        = (unsigned long)S5P_VA_CMU,
 152                 .pfn            = __phys_to_pfn(EXYNOS4_PA_CMU),
 153                 .length         = SZ_128K,
 154                 .type           = MT_DEVICE,
 155         }, {
 156                 .virtual        = (unsigned long)S5P_VA_COREPERI_BASE,
 157                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COREPERI),
 158                 .length         = SZ_8K,
 159                 .type           = MT_DEVICE,
 160         }, {
 161                 .virtual        = (unsigned long)S5P_VA_L2CC,
 162                 .pfn            = __phys_to_pfn(EXYNOS4_PA_L2CC),
 163                 .length         = SZ_4K,
 164                 .type           = MT_DEVICE,
 165         }, {
 166                 .virtual        = (unsigned long)S5P_VA_DMC0,
 167                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC0),
 168                 .length         = SZ_64K,
 169                 .type           = MT_DEVICE,
 170         }, {
 171                 .virtual        = (unsigned long)S5P_VA_DMC1,
 172                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC1),
 173                 .length         = SZ_64K,
 174                 .type           = MT_DEVICE,
 175         }, {
 176                 .virtual        = (unsigned long)S3C_VA_USB_HSPHY,
 177                 .pfn            = __phys_to_pfn(EXYNOS4_PA_HSPHY),
 178                 .length         = SZ_4K,
 179                 .type           = MT_DEVICE,
 180         },
 181 };
 182
 183 static struct map_desc exynos4_iodesc0[] __initdata = {
 184         {
 185                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 186                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
 187                 .length         = SZ_4K,
 188                 .type           = MT_DEVICE,
 189         },
 190 };
 191
 192 static struct map_desc exynos4_iodesc1[] __initdata = {
 193         {
 194                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 195                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
 196                 .length         = SZ_4K,
 197                 .type           = MT_DEVICE,
 198         },
 199 };
 200
 201 static struct map_desc exynos4210_iodesc[] __initdata = {
 202         {
 203                 .virtual        = (unsigned long)S5P_VA_SYSRAM_NS,
 204                 .pfn            = __phys_to_pfn(EXYNOS4210_PA_SYSRAM_NS),
 205                 .length         = SZ_4K,
 206                 .type           = MT_DEVICE,
 207         },
 208 };
 209
 210 static struct map_desc exynos4x12_iodesc[] __initdata = {
 211         {
 212                 .virtual        = (unsigned long)S5P_VA_SYSRAM_NS,
 213                 .pfn            = __phys_to_pfn(EXYNOS4x12_PA_SYSRAM_NS),
 214                 .length         = SZ_4K,
 215                 .type           = MT_DEVICE,
 216         },
 217 };
 218
 219 static struct map_desc exynos5250_iodesc[] __initdata = {
 220         {
 221                 .virtual        = (unsigned long)S5P_VA_SYSRAM_NS,
 222                 .pfn            = __phys_to_pfn(EXYNOS5250_PA_SYSRAM_NS),
 223                 .length         = SZ_4K,
 224                 .type           = MT_DEVICE,
 225         },
 226 };
 227
 228 static struct map_desc exynos5_iodesc[] __initdata = {
 229         {
 230                 .virtual        = (unsigned long)S3C_VA_SYS,
 231                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSCON),
 232                 .length         = SZ_64K,
 233                 .type           = MT_DEVICE,
 234         }, {
 235                 .virtual        = (unsigned long)S3C_VA_TIMER,
 236                 .pfn            = __phys_to_pfn(EXYNOS5_PA_TIMER),
 237                 .length         = SZ_16K,
 238                 .type           = MT_DEVICE,
 239         }, {
 240                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
 241                 .pfn            = __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
 242                 .length         = SZ_4K,
 243                 .type           = MT_DEVICE,
 244         }, {
 245                 .virtual        = (unsigned long)S5P_VA_SROMC,
 246                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SROMC),
 247                 .length         = SZ_4K,
 248                 .type           = MT_DEVICE,
 249         }, {
 250                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 251                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
 252                 .length         = SZ_4K,
 253                 .type           = MT_DEVICE,
 254         }, {
 255                 .virtual        = (unsigned long)S5P_VA_CMU,
 256                 .pfn            = __phys_to_pfn(EXYNOS5_PA_CMU),
 257                 .length         = 144 * SZ_1K,
 258                 .type           = MT_DEVICE,
 259         }, {
 260                 .virtual        = (unsigned long)S5P_VA_PMU,
 261                 .pfn            = __phys_to_pfn(EXYNOS5_PA_PMU),
 262                 .length         = SZ_64K,
 263                 .type           = MT_DEVICE,
 264         },
 265 };
 266
 267 void exynos4_restart(enum reboot_mode mode, const char *cmd)
 268 {
 269         __raw_writel(0x1, S5P_SWRESET);
 270 }
 271
 272 void exynos5_restart(enum reboot_mode mode, const char *cmd)
 273 {
 274         struct device_node *np;
 275         u32 val;
 276         void __iomem *addr;
 277
 278         val = 0x1;
 279         addr = EXYNOS_SWRESET;
 280
 281         if (of_machine_is_compatible("samsung,exynos5440")) {
 282                 u32 status;
 283                 np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock");
 284
 285                 addr = of_iomap(np, 0) + 0xbc;
 286                 status = __raw_readl(addr);
 287
 288                 addr = of_iomap(np, 0) + 0xcc;
 289                 val = __raw_readl(addr);
 290
 291                 val = (val & 0xffff0000) | (status & 0xffff);
 292         }
 293
 294         __raw_writel(val, addr);
 295 }
 296
 297 void __init exynos_init_late(void)
 298 {
 299         if (of_machine_is_compatible("samsung,exynos5440"))
 300                 /* to be supported later */
 301                 return;
 302
 303         exynos_pm_late_initcall();
 304 }
 305
 306 static int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
 307                                         int depth, void *data)
 308 {
 309         struct map_desc iodesc;
 310         __be32 *reg;
 311         unsigned long len;
 312
 313         if (!of_flat_dt_is_compatible(node, "samsung,exynos4210-chipid") &&
 314                 !of_flat_dt_is_compatible(node, "samsung,exynos5440-clock"))
 315                 return 0;
 316
 317         reg = of_get_flat_dt_prop(node, "reg", &len);
 318         if (reg == NULL || len != (sizeof(unsigned long) * 2))
 319                 return 0;
 320
 321         iodesc.pfn = __phys_to_pfn(be32_to_cpu(reg[0]));
 322         iodesc.length = be32_to_cpu(reg[1]) - 1;
 323         iodesc.virtual = (unsigned long)S5P_VA_CHIPID;
 324         iodesc.type = MT_DEVICE;
 325         iotable_init(&iodesc, 1);
 326         return 1;
 327 }
 328
 329 /*
 330  * exynos_map_io
 331  *
 332  * register the standard cpu IO areas
 333  */
 334
 335 void __init exynos_init_io(void)
 336 {
 337         debug_ll_io_init();
 338
 339         of_scan_flat_dt(exynos_fdt_map_chipid, NULL);
 340
 341         /* detect cpu id and rev. */
 342         s5p_init_cpu(S5P_VA_CHIPID);
 343
 344         s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
 345 }
 346
 347 static void __init exynos4_map_io(void)
 348 {
 349         iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
 350
 351         if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
 352                 iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
 353         else
 354                 iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
 355
 356         if (soc_is_exynos4210())
 357                 iotable_init(exynos4210_iodesc, ARRAY_SIZE(exynos4210_iodesc));
 358         if (soc_is_exynos4212() || soc_is_exynos4412())
 359                 iotable_init(exynos4x12_iodesc, ARRAY_SIZE(exynos4x12_iodesc));
 360 }
 361
 362 static void __init exynos5_map_io(void)
 363 {
 364         iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
 365
 366         if (soc_is_exynos5250())
 367                 iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
 368 }
 369
 370 void __init exynos_init_time(void)
 371 {
 372         of_clk_init(NULL);
 373         clocksource_of_init();
 374 }
 375
 376 struct bus_type exynos_subsys = {
 377         .name           = "exynos-core",
 378         .dev_name       = "exynos-core",
 379 };
 380
 381 static struct device exynos4_dev = {
 382         .bus    = &exynos_subsys,
 383 };
 384
 385 static int __init exynos_core_init(void)
 386 {
 387         return subsys_system_register(&exynos_subsys, NULL);
 388 }
 389 core_initcall(exynos_core_init);
 390
 391 static int __init exynos4_l2x0_cache_init(void)
 392 {
 393         int ret;
 394
 395         ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
 396         if (ret)
 397                 return ret;
 398
 399         l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
 400         clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
 401         return 0;
 402 }
 403 early_initcall(exynos4_l2x0_cache_init);
 404
 405 static int __init exynos_init(void)
 406 {
 407         printk(KERN_INFO "EXYNOS: Initializing architecture\n");
 408
 409         return device_register(&exynos4_dev);
 410 }