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Linux 3.11-rc3
[cris-mirror.git] / arch / arm / mach-integrator / integrator_ap.c
blobd9e95e612fcbfaecf9855d4a39f5017d236edb6f
1 /*
2 * linux/arch/arm/mach-integrator/integrator_ap.c
3 *
4 * Copyright (C) 2000-2003 Deep Blue Solutions Ltd
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20 #include <linux/types.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/list.h>
24 #include <linux/platform_device.h>
25 #include <linux/slab.h>
26 #include <linux/string.h>
27 #include <linux/syscore_ops.h>
28 #include <linux/amba/bus.h>
29 #include <linux/amba/kmi.h>
30 #include <linux/clocksource.h>
31 #include <linux/clockchips.h>
32 #include <linux/interrupt.h>
33 #include <linux/io.h>
34 #include <linux/irqchip/versatile-fpga.h>
35 #include <linux/mtd/physmap.h>
36 #include <linux/clk.h>
37 #include <linux/platform_data/clk-integrator.h>
38 #include <linux/of_irq.h>
39 #include <linux/of_address.h>
40 #include <linux/of_platform.h>
41 #include <linux/stat.h>
42 #include <linux/sys_soc.h>
43 #include <linux/termios.h>
44 #include <linux/sched_clock.h>
45
46 #include <mach/hardware.h>
47 #include <mach/platform.h>
48 #include <asm/hardware/arm_timer.h>
49 #include <asm/setup.h>
50 #include <asm/param.h> /* HZ */
51 #include <asm/mach-types.h>
52
53 #include <mach/lm.h>
54 #include <mach/irqs.h>
55
56 #include <asm/mach/arch.h>
57 #include <asm/mach/irq.h>
58 #include <asm/mach/map.h>
59 #include <asm/mach/time.h>
60
61 #include "common.h"
62 #include "pci_v3.h"
63
64 /* Base address to the AP system controller */
65 void __iomem *ap_syscon_base;
66
67 /*
68 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
69 * is the (PA >> 12).
70 *
71 * Setup a VA for the Integrator interrupt controller (for header #0,
72 * just for now).
73 */
74 #define VA_IC_BASE __io_address(INTEGRATOR_IC_BASE)
75 #define VA_EBI_BASE __io_address(INTEGRATOR_EBI_BASE)
76 #define VA_CMIC_BASE __io_address(INTEGRATOR_HDR_IC)
77
78 /*
79 * Logical Physical
80 * ef000000 Cache flush
81 * f1000000 10000000 Core module registers
82 * f1100000 11000000 System controller registers
83 * f1200000 12000000 EBI registers
84 * f1300000 13000000 Counter/Timer
85 * f1400000 14000000 Interrupt controller
86 * f1600000 16000000 UART 0
87 * f1700000 17000000 UART 1
88 * f1a00000 1a000000 Debug LEDs
89 * f1b00000 1b000000 GPIO
90 */
91
92 static struct map_desc ap_io_desc[] __initdata __maybe_unused = {
93 {
94 .virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE),
95 .pfn = __phys_to_pfn(INTEGRATOR_HDR_BASE),
96 .length = SZ_4K,
97 .type = MT_DEVICE
98 }, {
99 .virtual = IO_ADDRESS(INTEGRATOR_EBI_BASE),
100 .pfn = __phys_to_pfn(INTEGRATOR_EBI_BASE),
101 .length = SZ_4K,
102 .type = MT_DEVICE
103 }, {
104 .virtual = IO_ADDRESS(INTEGRATOR_CT_BASE),
105 .pfn = __phys_to_pfn(INTEGRATOR_CT_BASE),
106 .length = SZ_4K,
107 .type = MT_DEVICE
108 }, {
109 .virtual = IO_ADDRESS(INTEGRATOR_IC_BASE),
110 .pfn = __phys_to_pfn(INTEGRATOR_IC_BASE),
111 .length = SZ_4K,
112 .type = MT_DEVICE
113 }, {
114 .virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE),
115 .pfn = __phys_to_pfn(INTEGRATOR_UART0_BASE),
116 .length = SZ_4K,
117 .type = MT_DEVICE
118 }, {
119 .virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE),
120 .pfn = __phys_to_pfn(INTEGRATOR_DBG_BASE),
121 .length = SZ_4K,
122 .type = MT_DEVICE
123 }, {
124 .virtual = IO_ADDRESS(INTEGRATOR_AP_GPIO_BASE),
125 .pfn = __phys_to_pfn(INTEGRATOR_AP_GPIO_BASE),
126 .length = SZ_4K,
127 .type = MT_DEVICE
128 }
129 };
130
131 static void __init ap_map_io(void)
132 {
133 iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
134 pci_v3_early_init();
135 }
136
137 #ifdef CONFIG_PM
138 static unsigned long ic_irq_enable;
139
140 static int irq_suspend(void)
141 {
142 ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE);
143 return 0;
144 }
145
146 static void irq_resume(void)
147 {
148 /* disable all irq sources */
149 writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
150 writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
151 writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
152
153 writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET);
154 }
155 #else
156 #define irq_suspend NULL
157 #define irq_resume NULL
158 #endif
159
160 static struct syscore_ops irq_syscore_ops = {
161 .suspend = irq_suspend,
162 .resume = irq_resume,
163 };
164
165 static int __init irq_syscore_init(void)
166 {
167 register_syscore_ops(&irq_syscore_ops);
168
169 return 0;
170 }
171
172 device_initcall(irq_syscore_init);
173
174 /*
175 * Flash handling.
176 */
177 #define EBI_CSR1 (VA_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
178 #define EBI_LOCK (VA_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)
179
180 static int ap_flash_init(struct platform_device *dev)
181 {
182 u32 tmp;
183
184 writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP,
185 ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
186
187 tmp = readl(EBI_CSR1) | INTEGRATOR_EBI_WRITE_ENABLE;
188 writel(tmp, EBI_CSR1);
189
190 if (!(readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE)) {
191 writel(0xa05f, EBI_LOCK);
192 writel(tmp, EBI_CSR1);
193 writel(0, EBI_LOCK);
194 }
195 return 0;
196 }
197
198 static void ap_flash_exit(struct platform_device *dev)
199 {
200 u32 tmp;
201
202 writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP,
203 ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
204
205 tmp = readl(EBI_CSR1) & ~INTEGRATOR_EBI_WRITE_ENABLE;
206 writel(tmp, EBI_CSR1);
207
208 if (readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE) {
209 writel(0xa05f, EBI_LOCK);
210 writel(tmp, EBI_CSR1);
211 writel(0, EBI_LOCK);
212 }
213 }
214
215 static void ap_flash_set_vpp(struct platform_device *pdev, int on)
216 {
217 if (on)
218 writel(INTEGRATOR_SC_CTRL_nFLVPPEN,
219 ap_syscon_base + INTEGRATOR_SC_CTRLS_OFFSET);
220 else
221 writel(INTEGRATOR_SC_CTRL_nFLVPPEN,
222 ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
223 }
224
225 static struct physmap_flash_data ap_flash_data = {
226 .width = 4,
227 .init = ap_flash_init,
228 .exit = ap_flash_exit,
229 .set_vpp = ap_flash_set_vpp,
230 };
231
232 /*
233 * For the PL010 found in the Integrator/AP some of the UART control is
234 * implemented in the system controller and accessed using a callback
235 * from the driver.
236 */
237 static void integrator_uart_set_mctrl(struct amba_device *dev,
238 void __iomem *base, unsigned int mctrl)
239 {
240 unsigned int ctrls = 0, ctrlc = 0, rts_mask, dtr_mask;
241 u32 phybase = dev->res.start;
242
243 if (phybase == INTEGRATOR_UART0_BASE) {
244 /* UART0 */
245 rts_mask = 1 << 4;
246 dtr_mask = 1 << 5;
247 } else {
248 /* UART1 */
249 rts_mask = 1 << 6;
250 dtr_mask = 1 << 7;
251 }
252
253 if (mctrl & TIOCM_RTS)
254 ctrlc |= rts_mask;
255 else
256 ctrls |= rts_mask;
257
258 if (mctrl & TIOCM_DTR)
259 ctrlc |= dtr_mask;
260 else
261 ctrls |= dtr_mask;
262
263 __raw_writel(ctrls, ap_syscon_base + INTEGRATOR_SC_CTRLS_OFFSET);
264 __raw_writel(ctrlc, ap_syscon_base + INTEGRATOR_SC_CTRLC_OFFSET);
265 }
266
267 struct amba_pl010_data ap_uart_data = {
268 .set_mctrl = integrator_uart_set_mctrl,
269 };
270
271 /*
272 * Where is the timer (VA)?
273 */
274 #define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE)
275 #define TIMER1_VA_BASE __io_address(INTEGRATOR_TIMER1_BASE)
276 #define TIMER2_VA_BASE __io_address(INTEGRATOR_TIMER2_BASE)
277
278 static unsigned long timer_reload;
279
280 static u32 notrace integrator_read_sched_clock(void)
281 {
282 return -readl((void __iomem *) TIMER2_VA_BASE + TIMER_VALUE);
283 }
284
285 static void integrator_clocksource_init(unsigned long inrate,
286 void __iomem *base)
287 {
288 u32 ctrl = TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC;
289 unsigned long rate = inrate;
290
291 if (rate >= 1500000) {
292 rate /= 16;
293 ctrl |= TIMER_CTRL_DIV16;
294 }
295
296 writel(0xffff, base + TIMER_LOAD);
297 writel(ctrl, base + TIMER_CTRL);
298
299 clocksource_mmio_init(base + TIMER_VALUE, "timer2",
300 rate, 200, 16, clocksource_mmio_readl_down);
301 setup_sched_clock(integrator_read_sched_clock, 16, rate);
302 }
303
304 static void __iomem * clkevt_base;
305
306 /*
307 * IRQ handler for the timer
308 */
309 static irqreturn_t integrator_timer_interrupt(int irq, void *dev_id)
310 {
311 struct clock_event_device *evt = dev_id;
312
313 /* clear the interrupt */
314 writel(1, clkevt_base + TIMER_INTCLR);
315
316 evt->event_handler(evt);
317
318 return IRQ_HANDLED;
319 }
320
321 static void clkevt_set_mode(enum clock_event_mode mode, struct clock_event_device *evt)
322 {
323 u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE;
324
325 /* Disable timer */
326 writel(ctrl, clkevt_base + TIMER_CTRL);
327
328 switch (mode) {
329 case CLOCK_EVT_MODE_PERIODIC:
330 /* Enable the timer and start the periodic tick */
331 writel(timer_reload, clkevt_base + TIMER_LOAD);
332 ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;
333 writel(ctrl, clkevt_base + TIMER_CTRL);
334 break;
335 case CLOCK_EVT_MODE_ONESHOT:
336 /* Leave the timer disabled, .set_next_event will enable it */
337 ctrl &= ~TIMER_CTRL_PERIODIC;
338 writel(ctrl, clkevt_base + TIMER_CTRL);
339 break;
340 case CLOCK_EVT_MODE_UNUSED:
341 case CLOCK_EVT_MODE_SHUTDOWN:
342 case CLOCK_EVT_MODE_RESUME:
343 default:
344 /* Just leave in disabled state */
345 break;
346 }
347
348 }
349
350 static int clkevt_set_next_event(unsigned long next, struct clock_event_device *evt)
351 {
352 unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);
353
354 writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
355 writel(next, clkevt_base + TIMER_LOAD);
356 writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
357
358 return 0;
359 }
360
361 static struct clock_event_device integrator_clockevent = {
362 .name = "timer1",
363 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
364 .set_mode = clkevt_set_mode,
365 .set_next_event = clkevt_set_next_event,
366 .rating = 300,
367 };
368
369 static struct irqaction integrator_timer_irq = {
370 .name = "timer",
371 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
372 .handler = integrator_timer_interrupt,
373 .dev_id = &integrator_clockevent,
374 };
375
376 static void integrator_clockevent_init(unsigned long inrate,
377 void __iomem *base, int irq)
378 {
379 unsigned long rate = inrate;
380 unsigned int ctrl = 0;
381
382 clkevt_base = base;
383 /* Calculate and program a divisor */
384 if (rate > 0x100000 * HZ) {
385 rate /= 256;
386 ctrl |= TIMER_CTRL_DIV256;
387 } else if (rate > 0x10000 * HZ) {
388 rate /= 16;
389 ctrl |= TIMER_CTRL_DIV16;
390 }
391 timer_reload = rate / HZ;
392 writel(ctrl, clkevt_base + TIMER_CTRL);
393
394 setup_irq(irq, &integrator_timer_irq);
395 clockevents_config_and_register(&integrator_clockevent,
396 rate,
397 1,
398 0xffffU);
399 }
400
401 void __init ap_init_early(void)
402 {
403 }
404
405 #ifdef CONFIG_OF
406
407 static void __init ap_of_timer_init(void)
408 {
409 struct device_node *node;
410 const char *path;
411 void __iomem *base;
412 int err;
413 int irq;
414 struct clk *clk;
415 unsigned long rate;
416
417 clk = clk_get_sys("ap_timer", NULL);
418 BUG_ON(IS_ERR(clk));
419 clk_prepare_enable(clk);
420 rate = clk_get_rate(clk);
421
422 err = of_property_read_string(of_aliases,
423 "arm,timer-primary", &path);
424 if (WARN_ON(err))
425 return;
426 node = of_find_node_by_path(path);
427 base = of_iomap(node, 0);
428 if (WARN_ON(!base))
429 return;
430 writel(0, base + TIMER_CTRL);
431 integrator_clocksource_init(rate, base);
432
433 err = of_property_read_string(of_aliases,
434 "arm,timer-secondary", &path);
435 if (WARN_ON(err))
436 return;
437 node = of_find_node_by_path(path);
438 base = of_iomap(node, 0);
439 if (WARN_ON(!base))
440 return;
441 irq = irq_of_parse_and_map(node, 0);
442 writel(0, base + TIMER_CTRL);
443 integrator_clockevent_init(rate, base, irq);
444 }
445
446 static const struct of_device_id fpga_irq_of_match[] __initconst = {
447 { .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, },
448 { /* Sentinel */ }
449 };
450
451 static void __init ap_init_irq_of(void)
452 {
453 /* disable core module IRQs */
454 writel(0xffffffffU, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
455 of_irq_init(fpga_irq_of_match);
456 integrator_clk_init(false);
457 }
458
459 /* For the Device Tree, add in the UART callbacks as AUXDATA */
460 static struct of_dev_auxdata ap_auxdata_lookup[] __initdata = {
461 OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE,
462 "rtc", NULL),
463 OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
464 "uart0", &ap_uart_data),
465 OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
466 "uart1", &ap_uart_data),
467 OF_DEV_AUXDATA("arm,primecell", KMI0_BASE,
468 "kmi0", NULL),
469 OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
470 "kmi1", NULL),
471 OF_DEV_AUXDATA("cfi-flash", INTEGRATOR_FLASH_BASE,
472 "physmap-flash", &ap_flash_data),
473 { /* sentinel */ },
474 };
475
476 static void __init ap_init_of(void)
477 {
478 unsigned long sc_dec;
479 struct device_node *root;
480 struct device_node *syscon;
481 struct device *parent;
482 struct soc_device *soc_dev;
483 struct soc_device_attribute *soc_dev_attr;
484 u32 ap_sc_id;
485 int err;
486 int i;
487
488 /* Here we create an SoC device for the root node */
489 root = of_find_node_by_path("/");
490 if (!root)
491 return;
492 syscon = of_find_node_by_path("/syscon");
493 if (!syscon)
494 return;
495
496 ap_syscon_base = of_iomap(syscon, 0);
497 if (!ap_syscon_base)
498 return;
499
500 ap_sc_id = readl(ap_syscon_base);
501
502 soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
503 if (!soc_dev_attr)
504 return;
505
506 err = of_property_read_string(root, "compatible",
507 &soc_dev_attr->soc_id);
508 if (err)
509 return;
510 err = of_property_read_string(root, "model", &soc_dev_attr->machine);
511 if (err)
512 return;
513 soc_dev_attr->family = "Integrator";
514 soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%c",
515 'A' + (ap_sc_id & 0x0f));
516
517 soc_dev = soc_device_register(soc_dev_attr);
518 if (IS_ERR(soc_dev)) {
519 kfree(soc_dev_attr->revision);
520 kfree(soc_dev_attr);
521 return;
522 }
523
524 parent = soc_device_to_device(soc_dev);
525 integrator_init_sysfs(parent, ap_sc_id);
526
527 of_platform_populate(root, of_default_bus_match_table,
528 ap_auxdata_lookup, parent);
529
530 sc_dec = readl(ap_syscon_base + INTEGRATOR_SC_DEC_OFFSET);
531 for (i = 0; i < 4; i++) {
532 struct lm_device *lmdev;
533
534 if ((sc_dec & (16 << i)) == 0)
535 continue;
536
537 lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
538 if (!lmdev)
539 continue;
540
541 lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
542 lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
543 lmdev->resource.flags = IORESOURCE_MEM;
544 lmdev->irq = IRQ_AP_EXPINT0 + i;
545 lmdev->id = i;
546
547 lm_device_register(lmdev);
548 }
549 }
550
551 static const char * ap_dt_board_compat[] = {
552 "arm,integrator-ap",
553 NULL,
554 };
555
556 DT_MACHINE_START(INTEGRATOR_AP_DT, "ARM Integrator/AP (Device Tree)")
557 .reserve = integrator_reserve,
558 .map_io = ap_map_io,
559 .init_early = ap_init_early,
560 .init_irq = ap_init_irq_of,
561 .handle_irq = fpga_handle_irq,
562 .init_time = ap_of_timer_init,
563 .init_machine = ap_init_of,
564 .restart = integrator_restart,
565 .dt_compat = ap_dt_board_compat,
566 MACHINE_END
567
568 #endif
569
570 #ifdef CONFIG_ATAGS
571
572 /*
573 * For the ATAG boot some static mappings are needed. This will
574 * go away with the ATAG support down the road.
575 */
576
577 static struct map_desc ap_io_desc_atag[] __initdata = {
578 {
579 .virtual = IO_ADDRESS(INTEGRATOR_SC_BASE),
580 .pfn = __phys_to_pfn(INTEGRATOR_SC_BASE),
581 .length = SZ_4K,
582 .type = MT_DEVICE
583 },
584 };
585
586 static void __init ap_map_io_atag(void)
587 {
588 iotable_init(ap_io_desc_atag, ARRAY_SIZE(ap_io_desc_atag));
589 ap_map_io();
590 }
591
592 /*
593 * This is where non-devicetree initialization code is collected and stashed
594 * for eventual deletion.
595 */
596
597 static struct platform_device pci_v3_device = {
598 .name = "pci-v3",
599 .id = 0,
600 };
601
602 static struct resource cfi_flash_resource = {
603 .start = INTEGRATOR_FLASH_BASE,
604 .end = INTEGRATOR_FLASH_BASE + INTEGRATOR_FLASH_SIZE - 1,
605 .flags = IORESOURCE_MEM,
606 };
607
608 static struct platform_device cfi_flash_device = {
609 .name = "physmap-flash",
610 .id = 0,
611 .dev = {
612 .platform_data = &ap_flash_data,
613 },
614 .num_resources = 1,
615 .resource = &cfi_flash_resource,
616 };
617
618 static void __init ap_timer_init(void)
619 {
620 struct clk *clk;
621 unsigned long rate;
622
623 clk = clk_get_sys("ap_timer", NULL);
624 BUG_ON(IS_ERR(clk));
625 clk_prepare_enable(clk);
626 rate = clk_get_rate(clk);
627
628 writel(0, TIMER0_VA_BASE + TIMER_CTRL);
629 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
630 writel(0, TIMER2_VA_BASE + TIMER_CTRL);
631
632 integrator_clocksource_init(rate, (void __iomem *)TIMER2_VA_BASE);
633 integrator_clockevent_init(rate, (void __iomem *)TIMER1_VA_BASE,
634 IRQ_TIMERINT1);
635 }
636
637 #define INTEGRATOR_SC_VALID_INT 0x003fffff
638
639 static void __init ap_init_irq(void)
640 {
641 /* Disable all interrupts initially. */
642 /* Do the core module ones */
643 writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
644
645 /* do the header card stuff next */
646 writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
647 writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
648
649 fpga_irq_init(VA_IC_BASE, "SC", IRQ_PIC_START,
650 -1, INTEGRATOR_SC_VALID_INT, NULL);
651 integrator_clk_init(false);
652 }
653
654 static void __init ap_init(void)
655 {
656 unsigned long sc_dec;
657 int i;
658
659 platform_device_register(&pci_v3_device);
660 platform_device_register(&cfi_flash_device);
661
662 ap_syscon_base = __io_address(INTEGRATOR_SC_BASE);
663 sc_dec = readl(ap_syscon_base + INTEGRATOR_SC_DEC_OFFSET);
664 for (i = 0; i < 4; i++) {
665 struct lm_device *lmdev;
666
667 if ((sc_dec & (16 << i)) == 0)
668 continue;
669
670 lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
671 if (!lmdev)
672 continue;
673
674 lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
675 lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
676 lmdev->resource.flags = IORESOURCE_MEM;
677 lmdev->irq = IRQ_AP_EXPINT0 + i;
678 lmdev->id = i;
679
680 lm_device_register(lmdev);
681 }
682
683 integrator_init(false);
684 }
685
686 MACHINE_START(INTEGRATOR, "ARM-Integrator")
687 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
688 .atag_offset = 0x100,
689 .reserve = integrator_reserve,
690 .map_io = ap_map_io_atag,
691 .init_early = ap_init_early,
692 .init_irq = ap_init_irq,
693 .handle_irq = fpga_handle_irq,
694 .init_time = ap_timer_init,
695 .init_machine = ap_init,
696 .restart = integrator_restart,
697 MACHINE_END
698
699 #endif
CRIS linux kernel tree