2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994 - 2000, 2001, 2003 Ralf Baechle
7 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
8 * Copyright (C) 2002, 2007 Maciej W. Rozycki
9 * Copyright (C) 2001, 2012 MIPS Technologies, Inc. All rights reserved.
11 #include <linux/init.h>
14 #include <asm/asmmacro.h>
15 #include <asm/cacheops.h>
16 #include <asm/irqflags.h>
17 #include <asm/regdef.h>
18 #include <asm/fpregdef.h>
19 #include <asm/mipsregs.h>
20 #include <asm/stackframe.h>
22 #include <asm/thread_info.h>
24 #ifdef CONFIG_MIPS_MT_SMTC
25 #define PANIC_PIC(msg) \
41 * General exception vector for all other CPUs.
43 * Be careful when changing this, it has to be at most 128 bytes
44 * to fit into space reserved for the exception handler.
46 NESTED(except_vec3_generic, 0, sp)
49 #if R5432_CP0_INTERRUPT_WAR
57 PTR_L k0, exception_handlers(k1)
60 END(except_vec3_generic)
63 * General exception handler for CPUs with virtual coherency exception.
65 * Be careful when changing this, it has to be at most 256 (as a special
66 * exception) bytes to fit into space reserved for the exception handler.
68 NESTED(except_vec3_r4000, 0, sp)
78 beq k1, k0, handle_vced
80 beq k1, k0, handle_vcei
85 PTR_L k0, exception_handlers(k1)
89 * Big shit, we now may have two dirty primary cache lines for the same
90 * physical address. We can safely invalidate the line pointed to by
91 * c0_badvaddr because after return from this exception handler the
92 * load / store will be re-executed.
96 li k1, -4 # Is this ...
97 and k0, k1 # ... really needed?
99 cache Index_Store_Tag_D, (k0)
100 cache Hit_Writeback_Inv_SD, (k0)
101 #ifdef CONFIG_PROC_FS
102 PTR_LA k0, vced_count
110 MFC0 k0, CP0_BADVADDR
111 cache Hit_Writeback_Inv_SD, (k0) # also cleans pi
112 #ifdef CONFIG_PROC_FS
113 PTR_LA k0, vcei_count
120 END(except_vec3_r4000)
124 .align 5 /* 32 byte rollback region */
128 /* start of rollback region */
129 LONG_L t0, TI_FLAGS($28)
131 andi t0, _TIF_NEED_RESCHED
136 #ifdef CONFIG_CPU_MICROMIPS
144 /* end of rollback region (the region size must be power of two) */
151 .macro BUILD_ROLLBACK_PROLOGUE handler
152 FEXPORT(rollback_\handler)
156 PTR_LA k1, __r4k_wait
157 ori k0, 0x1f /* 32 byte rollback region */
166 BUILD_ROLLBACK_PROLOGUE handle_int
167 NESTED(handle_int, PT_SIZE, sp)
168 #ifdef CONFIG_TRACE_IRQFLAGS
170 * Check to see if the interrupted code has just disabled
171 * interrupts and ignore this interrupt for now if so.
173 * local_irq_disable() disables interrupts and then calls
174 * trace_hardirqs_off() to track the state. If an interrupt is taken
175 * after interrupts are disabled but before the state is updated
176 * it will appear to restore_all that it is incorrectly returning with
177 * interrupts disabled
182 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
203 LONG_L s0, TI_REGS($28)
204 LONG_S sp, TI_REGS($28)
205 PTR_LA ra, ret_from_irq
206 PTR_LA v0, plat_irq_dispatch
208 #ifdef CONFIG_CPU_MICROMIPS
216 * Special interrupt vector for MIPS64 ISA & embedded MIPS processors.
217 * This is a dedicated interrupt exception vector which reduces the
218 * interrupt processing overhead. The jump instruction will be replaced
219 * at the initialization time.
221 * Be careful when changing this, it has to be at most 128 bytes
222 * to fit into space reserved for the exception handler.
224 NESTED(except_vec4, 0, sp)
225 1: j 1b /* Dummy, will be replaced */
229 * EJTAG debug exception handler.
230 * The EJTAG debug exception entry point is 0xbfc00480, which
231 * normally is in the boot PROM, so the boot PROM must do an
232 * unconditional jump to this vector.
234 NESTED(except_vec_ejtag_debug, 0, sp)
235 j ejtag_debug_handler
236 #ifdef CONFIG_CPU_MICROMIPS
239 END(except_vec_ejtag_debug)
244 * Vectored interrupt handler.
245 * This prototype is copied to ebase + n*IntCtl.VS and patched
246 * to invoke the handler
248 BUILD_ROLLBACK_PROLOGUE except_vec_vi
249 NESTED(except_vec_vi, 0, sp)
254 #ifdef CONFIG_MIPS_MT_SMTC
256 * To keep from blindly blocking *all* interrupts
257 * during service by SMTC kernel, we also want to
258 * pass the IM value to be cleared.
260 FEXPORT(except_vec_vi_mori)
262 #endif /* CONFIG_MIPS_MT_SMTC */
263 PTR_LA v1, except_vec_vi_handler
264 FEXPORT(except_vec_vi_lui)
265 lui v0, 0 /* Patched */
267 FEXPORT(except_vec_vi_ori)
268 ori v0, 0 /* Patched */
271 EXPORT(except_vec_vi_end)
274 * Common Vectored Interrupt code
275 * Complete the register saves and invoke the handler which is passed in $v0
277 NESTED(except_vec_vi_handler, 0, sp)
280 #ifdef CONFIG_MIPS_MT_SMTC
282 * SMTC has an interesting problem that interrupts are level-triggered,
283 * and the CLI macro will clear EXL, potentially causing a duplicate
284 * interrupt service invocation. So we need to clear the associated
285 * IM bit of Status prior to doing CLI, and restore it after the
286 * service routine has been invoked - we must assume that the
287 * service routine will have cleared the state, and any active
288 * level represents a new or otherwised unserviced event...
292 #ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP
293 mfc0 t2, CP0_TCCONTEXT
295 mtc0 t2, CP0_TCCONTEXT
296 #endif /* CONFIG_MIPS_MT_SMTC_IM_BACKSTOP */
300 #endif /* CONFIG_MIPS_MT_SMTC */
302 #ifdef CONFIG_TRACE_IRQFLAGS
304 #ifdef CONFIG_MIPS_MT_SMTC
308 #ifdef CONFIG_MIPS_MT_SMTC
314 LONG_L s0, TI_REGS($28)
315 LONG_S sp, TI_REGS($28)
316 PTR_LA ra, ret_from_irq
318 END(except_vec_vi_handler)
321 * EJTAG debug exception handler.
323 NESTED(ejtag_debug_handler, PT_SIZE, sp)
329 sll k0, k0, 30 # Check for SDBBP.
330 bgez k0, ejtag_return
332 PTR_LA k0, ejtag_debug_buffer
336 jal ejtag_exception_handler
338 PTR_LA k0, ejtag_debug_buffer
346 END(ejtag_debug_handler)
349 * This buffer is reserved for the use of the EJTAG debug
353 EXPORT(ejtag_debug_buffer)
360 * NMI debug exception handler for MIPS reference boards.
361 * The NMI debug exception entry point is 0xbfc00000, which
362 * normally is in the boot PROM, so the boot PROM must do a
363 * unconditional jump to this vector.
365 NESTED(except_vec_nmi, 0, sp)
367 #ifdef CONFIG_CPU_MICROMIPS
374 NESTED(nmi_handler, PT_SIZE, sp)
379 jal nmi_exception_handler
386 .macro __build_clear_none
389 .macro __build_clear_sti
394 .macro __build_clear_cli
399 .macro __build_clear_fpe
401 /* gas fails to assemble cfc1 for some archs (octeon).*/ \
412 .macro __build_clear_ade
413 MFC0 t0, CP0_BADVADDR
414 PTR_S t0, PT_BVADDR(sp)
418 .macro __BUILD_silent exception
421 /* Gas tries to parse the PRINT argument as a string containing
422 string escapes and emits bogus warnings if it believes to
423 recognize an unknown escape code. So make the arguments
424 start with an n and gas will believe \n is ok ... */
425 .macro __BUILD_verbose nexception
426 LONG_L a1, PT_EPC(sp)
428 PRINT("Got \nexception at %08lx\012")
431 PRINT("Got \nexception at %016lx\012")
435 .macro __BUILD_count exception
436 LONG_L t0,exception_count_\exception
438 LONG_S t0,exception_count_\exception
439 .comm exception_count\exception, 8, 8
442 .macro __BUILD_HANDLER exception handler clear verbose ext
444 NESTED(handle_\exception, PT_SIZE, sp)
447 FEXPORT(handle_\exception\ext)
450 __BUILD_\verbose \exception
452 PTR_LA ra, ret_from_exception
454 END(handle_\exception)
457 .macro BUILD_HANDLER exception handler clear verbose
458 __BUILD_HANDLER \exception \handler \clear \verbose _int
461 BUILD_HANDLER adel ade ade silent /* #4 */
462 BUILD_HANDLER ades ade ade silent /* #5 */
463 BUILD_HANDLER ibe be cli silent /* #6 */
464 BUILD_HANDLER dbe be cli silent /* #7 */
465 BUILD_HANDLER bp bp sti silent /* #9 */
466 BUILD_HANDLER ri ri sti silent /* #10 */
467 BUILD_HANDLER cpu cpu sti silent /* #11 */
468 BUILD_HANDLER ov ov sti silent /* #12 */
469 BUILD_HANDLER tr tr sti silent /* #13 */
470 BUILD_HANDLER fpe fpe fpe silent /* #15 */
471 BUILD_HANDLER mdmx mdmx sti silent /* #22 */
472 #ifdef CONFIG_HARDWARE_WATCHPOINTS
474 * For watch, interrupts will be enabled after the watch
475 * registers are read.
477 BUILD_HANDLER watch watch cli silent /* #23 */
479 BUILD_HANDLER watch watch sti verbose /* #23 */
481 BUILD_HANDLER mcheck mcheck cli verbose /* #24 */
482 BUILD_HANDLER mt mt sti silent /* #25 */
483 BUILD_HANDLER dsp dsp sti silent /* #26 */
484 BUILD_HANDLER reserved reserved sti verbose /* others */
487 LEAF(handle_ri_rdhwr_vivt)
488 #ifdef CONFIG_MIPS_MT_SMTC
489 PANIC_PIC("handle_ri_rdhwr_vivt called")
494 /* check if TLB contains a entry for EPC */
496 andi k1, 0xff /* ASID_MASK */
498 PTR_SRL k0, _PAGE_SHIFT + 1
499 PTR_SLL k0, _PAGE_SHIFT + 1
507 bltz k1, handle_ri /* slow path */
510 END(handle_ri_rdhwr_vivt)
512 LEAF(handle_ri_rdhwr)
516 /* MIPS32: 0x7c03e83b: rdhwr v1,$29 */
517 /* microMIPS: 0x007d6b3c: rdhwr v1,$29 */
519 #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_MIPS32_R2) || defined(CONFIG_CPU_MIPS64_R2)
542 bne k0, k1, handle_ri /* if not ours */
545 /* The insn is rdhwr. No need to check CAUSE.BD here. */
546 get_saved_sp /* k1 := current_thread_info */
549 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
551 xori k1, _THREAD_MASK
552 LONG_L v1, TI_TP_VALUE(k1)
557 #ifndef CONFIG_CPU_DADDI_WORKAROUNDS
558 LONG_ADDIU k0, 4 /* stall on $k0 */
565 /* I hope three instructions between MTC0 and ERET are enough... */
567 xori k1, _THREAD_MASK
568 LONG_L v1, TI_TP_VALUE(k1)
577 /* A temporary overflow handler used by check_daddi(). */
581 BUILD_HANDLER daddi_ov daddi_ov none silent /* #12 */