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Linux 3.11-rc3
[cris-mirror.git] / arch / x86 / include / asm / processor.h
blob24cf5aefb7048b496082fd271755e3b186e23540
1 #ifndef _ASM_X86_PROCESSOR_H
2 #define _ASM_X86_PROCESSOR_H
3
4 #include <asm/processor-flags.h>
5
6 /* Forward declaration, a strange C thing */
7 struct task_struct;
8 struct mm_struct;
9
10 #include <asm/vm86.h>
11 #include <asm/math_emu.h>
12 #include <asm/segment.h>
13 #include <asm/types.h>
14 #include <asm/sigcontext.h>
15 #include <asm/current.h>
16 #include <asm/cpufeature.h>
17 #include <asm/page.h>
18 #include <asm/pgtable_types.h>
19 #include <asm/percpu.h>
20 #include <asm/msr.h>
21 #include <asm/desc_defs.h>
22 #include <asm/nops.h>
23 #include <asm/special_insns.h>
24
25 #include <linux/personality.h>
26 #include <linux/cpumask.h>
27 #include <linux/cache.h>
28 #include <linux/threads.h>
29 #include <linux/math64.h>
30 #include <linux/init.h>
31 #include <linux/err.h>
32 #include <linux/irqflags.h>
33
34 /*
35 * We handle most unaligned accesses in hardware. On the other hand
36 * unaligned DMA can be quite expensive on some Nehalem processors.
37 *
38 * Based on this we disable the IP header alignment in network drivers.
39 */
40 #define NET_IP_ALIGN 0
41
42 #define HBP_NUM 4
43 /*
44 * Default implementation of macro that returns current
45 * instruction pointer ("program counter").
46 */
47 static inline void *current_text_addr(void)
48 {
49 void *pc;
50
51 asm volatile("mov $1f, %0; 1:":"=r" (pc));
52
53 return pc;
54 }
55
56 #ifdef CONFIG_X86_VSMP
57 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
58 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
59 #else
60 # define ARCH_MIN_TASKALIGN 16
61 # define ARCH_MIN_MMSTRUCT_ALIGN 0
62 #endif
63
64 enum tlb_infos {
65 ENTRIES,
66 NR_INFO
67 };
68
69 extern u16 __read_mostly tlb_lli_4k[NR_INFO];
70 extern u16 __read_mostly tlb_lli_2m[NR_INFO];
71 extern u16 __read_mostly tlb_lli_4m[NR_INFO];
72 extern u16 __read_mostly tlb_lld_4k[NR_INFO];
73 extern u16 __read_mostly tlb_lld_2m[NR_INFO];
74 extern u16 __read_mostly tlb_lld_4m[NR_INFO];
75 extern s8 __read_mostly tlb_flushall_shift;
76
77 /*
78 * CPU type and hardware bug flags. Kept separately for each CPU.
79 * Members of this structure are referenced in head.S, so think twice
80 * before touching them. [mj]
81 */
82
83 struct cpuinfo_x86 {
84 __u8 x86; /* CPU family */
85 __u8 x86_vendor; /* CPU vendor */
86 __u8 x86_model;
87 __u8 x86_mask;
88 #ifdef CONFIG_X86_32
89 char wp_works_ok; /* It doesn't on 386's */
90
91 /* Problems on some 486Dx4's and old 386's: */
92 char rfu;
93 char pad0;
94 char pad1;
95 #else
96 /* Number of 4K pages in DTLB/ITLB combined(in pages): */
97 int x86_tlbsize;
98 #endif
99 __u8 x86_virt_bits;
100 __u8 x86_phys_bits;
101 /* CPUID returned core id bits: */
102 __u8 x86_coreid_bits;
103 /* Max extended CPUID function supported: */
104 __u32 extended_cpuid_level;
105 /* Maximum supported CPUID level, -1=no CPUID: */
106 int cpuid_level;
107 __u32 x86_capability[NCAPINTS + NBUGINTS];
108 char x86_vendor_id[16];
109 char x86_model_id[64];
110 /* in KB - valid for CPUS which support this call: */
111 int x86_cache_size;
112 int x86_cache_alignment; /* In bytes */
113 int x86_power;
114 unsigned long loops_per_jiffy;
115 /* cpuid returned max cores value: */
116 u16 x86_max_cores;
117 u16 apicid;
118 u16 initial_apicid;
119 u16 x86_clflush_size;
120 /* number of cores as seen by the OS: */
121 u16 booted_cores;
122 /* Physical processor id: */
123 u16 phys_proc_id;
124 /* Core id: */
125 u16 cpu_core_id;
126 /* Compute unit id */
127 u8 compute_unit_id;
128 /* Index into per_cpu list: */
129 u16 cpu_index;
130 u32 microcode;
131 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
132
133 #define X86_VENDOR_INTEL 0
134 #define X86_VENDOR_CYRIX 1
135 #define X86_VENDOR_AMD 2
136 #define X86_VENDOR_UMC 3
137 #define X86_VENDOR_CENTAUR 5
138 #define X86_VENDOR_TRANSMETA 7
139 #define X86_VENDOR_NSC 8
140 #define X86_VENDOR_NUM 9
141
142 #define X86_VENDOR_UNKNOWN 0xff
143
144 /*
145 * capabilities of CPUs
146 */
147 extern struct cpuinfo_x86 boot_cpu_data;
148 extern struct cpuinfo_x86 new_cpu_data;
149
150 extern struct tss_struct doublefault_tss;
151 extern __u32 cpu_caps_cleared[NCAPINTS];
152 extern __u32 cpu_caps_set[NCAPINTS];
153
154 #ifdef CONFIG_SMP
155 DECLARE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
156 #define cpu_data(cpu) per_cpu(cpu_info, cpu)
157 #else
158 #define cpu_info boot_cpu_data
159 #define cpu_data(cpu) boot_cpu_data
160 #endif
161
162 extern const struct seq_operations cpuinfo_op;
163
164 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
165
166 extern void cpu_detect(struct cpuinfo_x86 *c);
167 extern void fpu_detect(struct cpuinfo_x86 *c);
168
169 extern void early_cpu_init(void);
170 extern void identify_boot_cpu(void);
171 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
172 extern void print_cpu_info(struct cpuinfo_x86 *);
173 void print_cpu_msr(struct cpuinfo_x86 *);
174 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
175 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
176 extern void init_amd_cacheinfo(struct cpuinfo_x86 *c);
177
178 extern void detect_extended_topology(struct cpuinfo_x86 *c);
179 extern void detect_ht(struct cpuinfo_x86 *c);
180
181 #ifdef CONFIG_X86_32
182 extern int have_cpuid_p(void);
183 #else
184 static inline int have_cpuid_p(void)
185 {
186 return 1;
187 }
188 #endif
189 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
190 unsigned int *ecx, unsigned int *edx)
191 {
192 /* ecx is often an input as well as an output. */
193 asm volatile("cpuid"
194 : "=a" (*eax),
195 "=b" (*ebx),
196 "=c" (*ecx),
197 "=d" (*edx)
198 : "0" (*eax), "2" (*ecx)
199 : "memory");
200 }
201
202 static inline void load_cr3(pgd_t *pgdir)
203 {
204 write_cr3(__pa(pgdir));
205 }
206
207 #ifdef CONFIG_X86_32
208 /* This is the TSS defined by the hardware. */
209 struct x86_hw_tss {
210 unsigned short back_link, __blh;
211 unsigned long sp0;
212 unsigned short ss0, __ss0h;
213 unsigned long sp1;
214 /* ss1 caches MSR_IA32_SYSENTER_CS: */
215 unsigned short ss1, __ss1h;
216 unsigned long sp2;
217 unsigned short ss2, __ss2h;
218 unsigned long __cr3;
219 unsigned long ip;
220 unsigned long flags;
221 unsigned long ax;
222 unsigned long cx;
223 unsigned long dx;
224 unsigned long bx;
225 unsigned long sp;
226 unsigned long bp;
227 unsigned long si;
228 unsigned long di;
229 unsigned short es, __esh;
230 unsigned short cs, __csh;
231 unsigned short ss, __ssh;
232 unsigned short ds, __dsh;
233 unsigned short fs, __fsh;
234 unsigned short gs, __gsh;
235 unsigned short ldt, __ldth;
236 unsigned short trace;
237 unsigned short io_bitmap_base;
238
239 } __attribute__((packed));
240 #else
241 struct x86_hw_tss {
242 u32 reserved1;
243 u64 sp0;
244 u64 sp1;
245 u64 sp2;
246 u64 reserved2;
247 u64 ist[7];
248 u32 reserved3;
249 u32 reserved4;
250 u16 reserved5;
251 u16 io_bitmap_base;
252
253 } __attribute__((packed)) ____cacheline_aligned;
254 #endif
255
256 /*
257 * IO-bitmap sizes:
258 */
259 #define IO_BITMAP_BITS 65536
260 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
261 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
262 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap)
263 #define INVALID_IO_BITMAP_OFFSET 0x8000
264
265 struct tss_struct {
266 /*
267 * The hardware state:
268 */
269 struct x86_hw_tss x86_tss;
270
271 /*
272 * The extra 1 is there because the CPU will access an
273 * additional byte beyond the end of the IO permission
274 * bitmap. The extra byte must be all 1 bits, and must
275 * be within the limit.
276 */
277 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
278
279 /*
280 * .. and then another 0x100 bytes for the emergency kernel stack:
281 */
282 unsigned long stack[64];
283
284 } ____cacheline_aligned;
285
286 DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct, init_tss);
287
288 /*
289 * Save the original ist values for checking stack pointers during debugging
290 */
291 struct orig_ist {
292 unsigned long ist[7];
293 };
294
295 #define MXCSR_DEFAULT 0x1f80
296
297 struct i387_fsave_struct {
298 u32 cwd; /* FPU Control Word */
299 u32 swd; /* FPU Status Word */
300 u32 twd; /* FPU Tag Word */
301 u32 fip; /* FPU IP Offset */
302 u32 fcs; /* FPU IP Selector */
303 u32 foo; /* FPU Operand Pointer Offset */
304 u32 fos; /* FPU Operand Pointer Selector */
305
306 /* 8*10 bytes for each FP-reg = 80 bytes: */
307 u32 st_space[20];
308
309 /* Software status information [not touched by FSAVE ]: */
310 u32 status;
311 };
312
313 struct i387_fxsave_struct {
314 u16 cwd; /* Control Word */
315 u16 swd; /* Status Word */
316 u16 twd; /* Tag Word */
317 u16 fop; /* Last Instruction Opcode */
318 union {
319 struct {
320 u64 rip; /* Instruction Pointer */
321 u64 rdp; /* Data Pointer */
322 };
323 struct {
324 u32 fip; /* FPU IP Offset */
325 u32 fcs; /* FPU IP Selector */
326 u32 foo; /* FPU Operand Offset */
327 u32 fos; /* FPU Operand Selector */
328 };
329 };
330 u32 mxcsr; /* MXCSR Register State */
331 u32 mxcsr_mask; /* MXCSR Mask */
332
333 /* 8*16 bytes for each FP-reg = 128 bytes: */
334 u32 st_space[32];
335
336 /* 16*16 bytes for each XMM-reg = 256 bytes: */
337 u32 xmm_space[64];
338
339 u32 padding[12];
340
341 union {
342 u32 padding1[12];
343 u32 sw_reserved[12];
344 };
345
346 } __attribute__((aligned(16)));
347
348 struct i387_soft_struct {
349 u32 cwd;
350 u32 swd;
351 u32 twd;
352 u32 fip;
353 u32 fcs;
354 u32 foo;
355 u32 fos;
356 /* 8*10 bytes for each FP-reg = 80 bytes: */
357 u32 st_space[20];
358 u8 ftop;
359 u8 changed;
360 u8 lookahead;
361 u8 no_update;
362 u8 rm;
363 u8 alimit;
364 struct math_emu_info *info;
365 u32 entry_eip;
366 };
367
368 struct ymmh_struct {
369 /* 16 * 16 bytes for each YMMH-reg = 256 bytes */
370 u32 ymmh_space[64];
371 };
372
373 struct xsave_hdr_struct {
374 u64 xstate_bv;
375 u64 reserved1[2];
376 u64 reserved2[5];
377 } __attribute__((packed));
378
379 struct xsave_struct {
380 struct i387_fxsave_struct i387;
381 struct xsave_hdr_struct xsave_hdr;
382 struct ymmh_struct ymmh;
383 /* new processor state extensions will go here */
384 } __attribute__ ((packed, aligned (64)));
385
386 union thread_xstate {
387 struct i387_fsave_struct fsave;
388 struct i387_fxsave_struct fxsave;
389 struct i387_soft_struct soft;
390 struct xsave_struct xsave;
391 };
392
393 struct fpu {
394 unsigned int last_cpu;
395 unsigned int has_fpu;
396 union thread_xstate *state;
397 };
398
399 #ifdef CONFIG_X86_64
400 DECLARE_PER_CPU(struct orig_ist, orig_ist);
401
402 union irq_stack_union {
403 char irq_stack[IRQ_STACK_SIZE];
404 /*
405 * GCC hardcodes the stack canary as %gs:40. Since the
406 * irq_stack is the object at %gs:0, we reserve the bottom
407 * 48 bytes of the irq stack for the canary.
408 */
409 struct {
410 char gs_base[40];
411 unsigned long stack_canary;
412 };
413 };
414
415 DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union);
416 DECLARE_INIT_PER_CPU(irq_stack_union);
417
418 DECLARE_PER_CPU(char *, irq_stack_ptr);
419 DECLARE_PER_CPU(unsigned int, irq_count);
420 extern asmlinkage void ignore_sysret(void);
421 #else /* X86_64 */
422 #ifdef CONFIG_CC_STACKPROTECTOR
423 /*
424 * Make sure stack canary segment base is cached-aligned:
425 * "For Intel Atom processors, avoid non zero segment base address
426 * that is not aligned to cache line boundary at all cost."
427 * (Optim Ref Manual Assembly/Compiler Coding Rule 15.)
428 */
429 struct stack_canary {
430 char __pad[20]; /* canary at %gs:20 */
431 unsigned long canary;
432 };
433 DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
434 #endif
435 #endif /* X86_64 */
436
437 extern unsigned int xstate_size;
438 extern void free_thread_xstate(struct task_struct *);
439 extern struct kmem_cache *task_xstate_cachep;
440
441 struct perf_event;
442
443 struct thread_struct {
444 /* Cached TLS descriptors: */
445 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
446 unsigned long sp0;
447 unsigned long sp;
448 #ifdef CONFIG_X86_32
449 unsigned long sysenter_cs;
450 #else
451 unsigned long usersp; /* Copy from PDA */
452 unsigned short es;
453 unsigned short ds;
454 unsigned short fsindex;
455 unsigned short gsindex;
456 #endif
457 #ifdef CONFIG_X86_32
458 unsigned long ip;
459 #endif
460 #ifdef CONFIG_X86_64
461 unsigned long fs;
462 #endif
463 unsigned long gs;
464 /* Save middle states of ptrace breakpoints */
465 struct perf_event *ptrace_bps[HBP_NUM];
466 /* Debug status used for traps, single steps, etc... */
467 unsigned long debugreg6;
468 /* Keep track of the exact dr7 value set by the user */
469 unsigned long ptrace_dr7;
470 /* Fault info: */
471 unsigned long cr2;
472 unsigned long trap_nr;
473 unsigned long error_code;
474 /* floating point and extended processor state */
475 struct fpu fpu;
476 #ifdef CONFIG_X86_32
477 /* Virtual 86 mode info */
478 struct vm86_struct __user *vm86_info;
479 unsigned long screen_bitmap;
480 unsigned long v86flags;
481 unsigned long v86mask;
482 unsigned long saved_sp0;
483 unsigned int saved_fs;
484 unsigned int saved_gs;
485 #endif
486 /* IO permissions: */
487 unsigned long *io_bitmap_ptr;
488 unsigned long iopl;
489 /* Max allowed port in the bitmap, in bytes: */
490 unsigned io_bitmap_max;
491 };
492
493 /*
494 * Set IOPL bits in EFLAGS from given mask
495 */
496 static inline void native_set_iopl_mask(unsigned mask)
497 {
498 #ifdef CONFIG_X86_32
499 unsigned int reg;
500
501 asm volatile ("pushfl;"
502 "popl %0;"
503 "andl %1, %0;"
504 "orl %2, %0;"
505 "pushl %0;"
506 "popfl"
507 : "=&r" (reg)
508 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
509 #endif
510 }
511
512 static inline void
513 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
514 {
515 tss->x86_tss.sp0 = thread->sp0;
516 #ifdef CONFIG_X86_32
517 /* Only happens when SEP is enabled, no need to test "SEP"arately: */
518 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
519 tss->x86_tss.ss1 = thread->sysenter_cs;
520 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
521 }
522 #endif
523 }
524
525 static inline void native_swapgs(void)
526 {
527 #ifdef CONFIG_X86_64
528 asm volatile("swapgs" ::: "memory");
529 #endif
530 }
531
532 #ifdef CONFIG_PARAVIRT
533 #include <asm/paravirt.h>
534 #else
535 #define __cpuid native_cpuid
536 #define paravirt_enabled() 0
537
538 static inline void load_sp0(struct tss_struct *tss,
539 struct thread_struct *thread)
540 {
541 native_load_sp0(tss, thread);
542 }
543
544 #define set_iopl_mask native_set_iopl_mask
545 #endif /* CONFIG_PARAVIRT */
546
547 /*
548 * Save the cr4 feature set we're using (ie
549 * Pentium 4MB enable and PPro Global page
550 * enable), so that any CPU's that boot up
551 * after us can get the correct flags.
552 */
553 extern unsigned long mmu_cr4_features;
554 extern u32 *trampoline_cr4_features;
555
556 static inline void set_in_cr4(unsigned long mask)
557 {
558 unsigned long cr4;
559
560 mmu_cr4_features |= mask;
561 if (trampoline_cr4_features)
562 *trampoline_cr4_features = mmu_cr4_features;
563 cr4 = read_cr4();
564 cr4 |= mask;
565 write_cr4(cr4);
566 }
567
568 static inline void clear_in_cr4(unsigned long mask)
569 {
570 unsigned long cr4;
571
572 mmu_cr4_features &= ~mask;
573 if (trampoline_cr4_features)
574 *trampoline_cr4_features = mmu_cr4_features;
575 cr4 = read_cr4();
576 cr4 &= ~mask;
577 write_cr4(cr4);
578 }
579
580 typedef struct {
581 unsigned long seg;
582 } mm_segment_t;
583
584
585 /* Free all resources held by a thread. */
586 extern void release_thread(struct task_struct *);
587
588 unsigned long get_wchan(struct task_struct *p);
589
590 /*
591 * Generic CPUID function
592 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
593 * resulting in stale register contents being returned.
594 */
595 static inline void cpuid(unsigned int op,
596 unsigned int *eax, unsigned int *ebx,
597 unsigned int *ecx, unsigned int *edx)
598 {
599 *eax = op;
600 *ecx = 0;
601 __cpuid(eax, ebx, ecx, edx);
602 }
603
604 /* Some CPUID calls want 'count' to be placed in ecx */
605 static inline void cpuid_count(unsigned int op, int count,
606 unsigned int *eax, unsigned int *ebx,
607 unsigned int *ecx, unsigned int *edx)
608 {
609 *eax = op;
610 *ecx = count;
611 __cpuid(eax, ebx, ecx, edx);
612 }
613
614 /*
615 * CPUID functions returning a single datum
616 */
617 static inline unsigned int cpuid_eax(unsigned int op)
618 {
619 unsigned int eax, ebx, ecx, edx;
620
621 cpuid(op, &eax, &ebx, &ecx, &edx);
622
623 return eax;
624 }
625
626 static inline unsigned int cpuid_ebx(unsigned int op)
627 {
628 unsigned int eax, ebx, ecx, edx;
629
630 cpuid(op, &eax, &ebx, &ecx, &edx);
631
632 return ebx;
633 }
634
635 static inline unsigned int cpuid_ecx(unsigned int op)
636 {
637 unsigned int eax, ebx, ecx, edx;
638
639 cpuid(op, &eax, &ebx, &ecx, &edx);
640
641 return ecx;
642 }
643
644 static inline unsigned int cpuid_edx(unsigned int op)
645 {
646 unsigned int eax, ebx, ecx, edx;
647
648 cpuid(op, &eax, &ebx, &ecx, &edx);
649
650 return edx;
651 }
652
653 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
654 static inline void rep_nop(void)
655 {
656 asm volatile("rep; nop" ::: "memory");
657 }
658
659 static inline void cpu_relax(void)
660 {
661 rep_nop();
662 }
663
664 /* Stop speculative execution and prefetching of modified code. */
665 static inline void sync_core(void)
666 {
667 int tmp;
668
669 #ifdef CONFIG_M486
670 /*
671 * Do a CPUID if available, otherwise do a jump. The jump
672 * can conveniently enough be the jump around CPUID.
673 */
674 asm volatile("cmpl %2,%1\n\t"
675 "jl 1f\n\t"
676 "cpuid\n"
677 "1:"
678 : "=a" (tmp)
679 : "rm" (boot_cpu_data.cpuid_level), "ri" (0), "0" (1)
680 : "ebx", "ecx", "edx", "memory");
681 #else
682 /*
683 * CPUID is a barrier to speculative execution.
684 * Prefetched instructions are automatically
685 * invalidated when modified.
686 */
687 asm volatile("cpuid"
688 : "=a" (tmp)
689 : "0" (1)
690 : "ebx", "ecx", "edx", "memory");
691 #endif
692 }
693
694 static inline void __monitor(const void *eax, unsigned long ecx,
695 unsigned long edx)
696 {
697 /* "monitor %eax, %ecx, %edx;" */
698 asm volatile(".byte 0x0f, 0x01, 0xc8;"
699 :: "a" (eax), "c" (ecx), "d"(edx));
700 }
701
702 static inline void __mwait(unsigned long eax, unsigned long ecx)
703 {
704 /* "mwait %eax, %ecx;" */
705 asm volatile(".byte 0x0f, 0x01, 0xc9;"
706 :: "a" (eax), "c" (ecx));
707 }
708
709 static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
710 {
711 trace_hardirqs_on();
712 /* "mwait %eax, %ecx;" */
713 asm volatile("sti; .byte 0x0f, 0x01, 0xc9;"
714 :: "a" (eax), "c" (ecx));
715 }
716
717 extern void select_idle_routine(const struct cpuinfo_x86 *c);
718 extern void init_amd_e400_c1e_mask(void);
719
720 extern unsigned long boot_option_idle_override;
721 extern bool amd_e400_c1e_detected;
722
723 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT,
724 IDLE_POLL};
725
726 extern void enable_sep_cpu(void);
727 extern int sysenter_setup(void);
728
729 extern void early_trap_init(void);
730 void early_trap_pf_init(void);
731
732 /* Defined in head.S */
733 extern struct desc_ptr early_gdt_descr;
734
735 extern void cpu_set_gdt(int);
736 extern void switch_to_new_gdt(int);
737 extern void load_percpu_segment(int);
738 extern void cpu_init(void);
739
740 static inline unsigned long get_debugctlmsr(void)
741 {
742 unsigned long debugctlmsr = 0;
743
744 #ifndef CONFIG_X86_DEBUGCTLMSR
745 if (boot_cpu_data.x86 < 6)
746 return 0;
747 #endif
748 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
749
750 return debugctlmsr;
751 }
752
753 static inline void update_debugctlmsr(unsigned long debugctlmsr)
754 {
755 #ifndef CONFIG_X86_DEBUGCTLMSR
756 if (boot_cpu_data.x86 < 6)
757 return;
758 #endif
759 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
760 }
761
762 extern void set_task_blockstep(struct task_struct *task, bool on);
763
764 /*
765 * from system description table in BIOS. Mostly for MCA use, but
766 * others may find it useful:
767 */
768 extern unsigned int machine_id;
769 extern unsigned int machine_submodel_id;
770 extern unsigned int BIOS_revision;
771
772 /* Boot loader type from the setup header: */
773 extern int bootloader_type;
774 extern int bootloader_version;
775
776 extern char ignore_fpu_irq;
777
778 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
779 #define ARCH_HAS_PREFETCHW
780 #define ARCH_HAS_SPINLOCK_PREFETCH
781
782 #ifdef CONFIG_X86_32
783 # define BASE_PREFETCH ASM_NOP4
784 # define ARCH_HAS_PREFETCH
785 #else
786 # define BASE_PREFETCH "prefetcht0 (%1)"
787 #endif
788
789 /*
790 * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
791 *
792 * It's not worth to care about 3dnow prefetches for the K6
793 * because they are microcoded there and very slow.
794 */
795 static inline void prefetch(const void *x)
796 {
797 alternative_input(BASE_PREFETCH,
798 "prefetchnta (%1)",
799 X86_FEATURE_XMM,
800 "r" (x));
801 }
802
803 /*
804 * 3dnow prefetch to get an exclusive cache line.
805 * Useful for spinlocks to avoid one state transition in the
806 * cache coherency protocol:
807 */
808 static inline void prefetchw(const void *x)
809 {
810 alternative_input(BASE_PREFETCH,
811 "prefetchw (%1)",
812 X86_FEATURE_3DNOW,
813 "r" (x));
814 }
815
816 static inline void spin_lock_prefetch(const void *x)
817 {
818 prefetchw(x);
819 }
820
821 #ifdef CONFIG_X86_32
822 /*
823 * User space process size: 3GB (default).
824 */
825 #define TASK_SIZE PAGE_OFFSET
826 #define TASK_SIZE_MAX TASK_SIZE
827 #define STACK_TOP TASK_SIZE
828 #define STACK_TOP_MAX STACK_TOP
829
830 #define INIT_THREAD { \
831 .sp0 = sizeof(init_stack) + (long)&init_stack, \
832 .vm86_info = NULL, \
833 .sysenter_cs = __KERNEL_CS, \
834 .io_bitmap_ptr = NULL, \
835 }
836
837 /*
838 * Note that the .io_bitmap member must be extra-big. This is because
839 * the CPU will access an additional byte beyond the end of the IO
840 * permission bitmap. The extra byte must be all 1 bits, and must
841 * be within the limit.
842 */
843 #define INIT_TSS { \
844 .x86_tss = { \
845 .sp0 = sizeof(init_stack) + (long)&init_stack, \
846 .ss0 = __KERNEL_DS, \
847 .ss1 = __KERNEL_CS, \
848 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
849 }, \
850 .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, \
851 }
852
853 extern unsigned long thread_saved_pc(struct task_struct *tsk);
854
855 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
856 #define KSTK_TOP(info) \
857 ({ \
858 unsigned long *__ptr = (unsigned long *)(info); \
859 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
860 })
861
862 /*
863 * The below -8 is to reserve 8 bytes on top of the ring0 stack.
864 * This is necessary to guarantee that the entire "struct pt_regs"
865 * is accessible even if the CPU haven't stored the SS/ESP registers
866 * on the stack (interrupt gate does not save these registers
867 * when switching to the same priv ring).
868 * Therefore beware: accessing the ss/esp fields of the
869 * "struct pt_regs" is possible, but they may contain the
870 * completely wrong values.
871 */
872 #define task_pt_regs(task) \
873 ({ \
874 struct pt_regs *__regs__; \
875 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
876 __regs__ - 1; \
877 })
878
879 #define KSTK_ESP(task) (task_pt_regs(task)->sp)
880
881 #else
882 /*
883 * User space process size. 47bits minus one guard page.
884 */
885 #define TASK_SIZE_MAX ((1UL << 47) - PAGE_SIZE)
886
887 /* This decides where the kernel will search for a free chunk of vm
888 * space during mmap's.
889 */
890 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
891 0xc0000000 : 0xFFFFe000)
892
893 #define TASK_SIZE (test_thread_flag(TIF_ADDR32) ? \
894 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
895 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \
896 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
897
898 #define STACK_TOP TASK_SIZE
899 #define STACK_TOP_MAX TASK_SIZE_MAX
900
901 #define INIT_THREAD { \
902 .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
903 }
904
905 #define INIT_TSS { \
906 .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
907 }
908
909 /*
910 * Return saved PC of a blocked thread.
911 * What is this good for? it will be always the scheduler or ret_from_fork.
912 */
913 #define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8))
914
915 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1)
916 extern unsigned long KSTK_ESP(struct task_struct *task);
917
918 /*
919 * User space RSP while inside the SYSCALL fast path
920 */
921 DECLARE_PER_CPU(unsigned long, old_rsp);
922
923 #endif /* CONFIG_X86_64 */
924
925 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
926 unsigned long new_sp);
927
928 /*
929 * This decides where the kernel will search for a free chunk of vm
930 * space during mmap's.
931 */
932 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
933
934 #define KSTK_EIP(task) (task_pt_regs(task)->ip)
935
936 /* Get/set a process' ability to use the timestamp counter instruction */
937 #define GET_TSC_CTL(adr) get_tsc_mode((adr))
938 #define SET_TSC_CTL(val) set_tsc_mode((val))
939
940 extern int get_tsc_mode(unsigned long adr);
941 extern int set_tsc_mode(unsigned int val);
942
943 extern u16 amd_get_nb_id(int cpu);
944
945 struct aperfmperf {
946 u64 aperf, mperf;
947 };
948
949 static inline void get_aperfmperf(struct aperfmperf *am)
950 {
951 WARN_ON_ONCE(!boot_cpu_has(X86_FEATURE_APERFMPERF));
952
953 rdmsrl(MSR_IA32_APERF, am->aperf);
954 rdmsrl(MSR_IA32_MPERF, am->mperf);
955 }
956
957 #define APERFMPERF_SHIFT 10
958
959 static inline
960 unsigned long calc_aperfmperf_ratio(struct aperfmperf *old,
961 struct aperfmperf *new)
962 {
963 u64 aperf = new->aperf - old->aperf;
964 u64 mperf = new->mperf - old->mperf;
965 unsigned long ratio = aperf;
966
967 mperf >>= APERFMPERF_SHIFT;
968 if (mperf)
969 ratio = div64_u64(aperf, mperf);
970
971 return ratio;
972 }
973
974 extern unsigned long arch_align_stack(unsigned long sp);
975 extern void free_init_pages(char *what, unsigned long begin, unsigned long end);
976
977 void default_idle(void);
978 #ifdef CONFIG_XEN
979 bool xen_set_default_idle(void);
980 #else
981 #define xen_set_default_idle 0
982 #endif
983
984 void stop_this_cpu(void *dummy);
985 void df_debug(struct pt_regs *regs, long error_code);
986 #endif /* _ASM_X86_PROCESSOR_H */
CRIS linux kernel tree