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Linux 3.11-rc3
[cris-mirror.git] / drivers / infiniband / hw / qib / qib_verbs.c
blob092b0bb1bb789aaa78cc74add2fcb0aae24bb94e
1 /*
2 * Copyright (c) 2012, 2013 Intel Corporation. All rights reserved.
3 * Copyright (c) 2006 - 2012 QLogic Corporation. All rights reserved.
4 * Copyright (c) 2005, 2006 PathScale, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35 #include <rdma/ib_mad.h>
36 #include <rdma/ib_user_verbs.h>
37 #include <linux/io.h>
38 #include <linux/module.h>
39 #include <linux/utsname.h>
40 #include <linux/rculist.h>
41 #include <linux/mm.h>
42 #include <linux/random.h>
43
44 #include "qib.h"
45 #include "qib_common.h"
46
47 static unsigned int ib_qib_qp_table_size = 256;
48 module_param_named(qp_table_size, ib_qib_qp_table_size, uint, S_IRUGO);
49 MODULE_PARM_DESC(qp_table_size, "QP table size");
50
51 unsigned int ib_qib_lkey_table_size = 16;
52 module_param_named(lkey_table_size, ib_qib_lkey_table_size, uint,
53 S_IRUGO);
54 MODULE_PARM_DESC(lkey_table_size,
55 "LKEY table size in bits (2^n, 1 <= n <= 23)");
56
57 static unsigned int ib_qib_max_pds = 0xFFFF;
58 module_param_named(max_pds, ib_qib_max_pds, uint, S_IRUGO);
59 MODULE_PARM_DESC(max_pds,
60 "Maximum number of protection domains to support");
61
62 static unsigned int ib_qib_max_ahs = 0xFFFF;
63 module_param_named(max_ahs, ib_qib_max_ahs, uint, S_IRUGO);
64 MODULE_PARM_DESC(max_ahs, "Maximum number of address handles to support");
65
66 unsigned int ib_qib_max_cqes = 0x2FFFF;
67 module_param_named(max_cqes, ib_qib_max_cqes, uint, S_IRUGO);
68 MODULE_PARM_DESC(max_cqes,
69 "Maximum number of completion queue entries to support");
70
71 unsigned int ib_qib_max_cqs = 0x1FFFF;
72 module_param_named(max_cqs, ib_qib_max_cqs, uint, S_IRUGO);
73 MODULE_PARM_DESC(max_cqs, "Maximum number of completion queues to support");
74
75 unsigned int ib_qib_max_qp_wrs = 0x3FFF;
76 module_param_named(max_qp_wrs, ib_qib_max_qp_wrs, uint, S_IRUGO);
77 MODULE_PARM_DESC(max_qp_wrs, "Maximum number of QP WRs to support");
78
79 unsigned int ib_qib_max_qps = 16384;
80 module_param_named(max_qps, ib_qib_max_qps, uint, S_IRUGO);
81 MODULE_PARM_DESC(max_qps, "Maximum number of QPs to support");
82
83 unsigned int ib_qib_max_sges = 0x60;
84 module_param_named(max_sges, ib_qib_max_sges, uint, S_IRUGO);
85 MODULE_PARM_DESC(max_sges, "Maximum number of SGEs to support");
86
87 unsigned int ib_qib_max_mcast_grps = 16384;
88 module_param_named(max_mcast_grps, ib_qib_max_mcast_grps, uint, S_IRUGO);
89 MODULE_PARM_DESC(max_mcast_grps,
90 "Maximum number of multicast groups to support");
91
92 unsigned int ib_qib_max_mcast_qp_attached = 16;
93 module_param_named(max_mcast_qp_attached, ib_qib_max_mcast_qp_attached,
94 uint, S_IRUGO);
95 MODULE_PARM_DESC(max_mcast_qp_attached,
96 "Maximum number of attached QPs to support");
97
98 unsigned int ib_qib_max_srqs = 1024;
99 module_param_named(max_srqs, ib_qib_max_srqs, uint, S_IRUGO);
100 MODULE_PARM_DESC(max_srqs, "Maximum number of SRQs to support");
101
102 unsigned int ib_qib_max_srq_sges = 128;
103 module_param_named(max_srq_sges, ib_qib_max_srq_sges, uint, S_IRUGO);
104 MODULE_PARM_DESC(max_srq_sges, "Maximum number of SRQ SGEs to support");
105
106 unsigned int ib_qib_max_srq_wrs = 0x1FFFF;
107 module_param_named(max_srq_wrs, ib_qib_max_srq_wrs, uint, S_IRUGO);
108 MODULE_PARM_DESC(max_srq_wrs, "Maximum number of SRQ WRs support");
109
110 static unsigned int ib_qib_disable_sma;
111 module_param_named(disable_sma, ib_qib_disable_sma, uint, S_IWUSR | S_IRUGO);
112 MODULE_PARM_DESC(disable_sma, "Disable the SMA");
113
114 /*
115 * Note that it is OK to post send work requests in the SQE and ERR
116 * states; qib_do_send() will process them and generate error
117 * completions as per IB 1.2 C10-96.
118 */
119 const int ib_qib_state_ops[IB_QPS_ERR + 1] = {
120 [IB_QPS_RESET] = 0,
121 [IB_QPS_INIT] = QIB_POST_RECV_OK,
122 [IB_QPS_RTR] = QIB_POST_RECV_OK | QIB_PROCESS_RECV_OK,
123 [IB_QPS_RTS] = QIB_POST_RECV_OK | QIB_PROCESS_RECV_OK |
124 QIB_POST_SEND_OK | QIB_PROCESS_SEND_OK |
125 QIB_PROCESS_NEXT_SEND_OK,
126 [IB_QPS_SQD] = QIB_POST_RECV_OK | QIB_PROCESS_RECV_OK |
127 QIB_POST_SEND_OK | QIB_PROCESS_SEND_OK,
128 [IB_QPS_SQE] = QIB_POST_RECV_OK | QIB_PROCESS_RECV_OK |
129 QIB_POST_SEND_OK | QIB_FLUSH_SEND,
130 [IB_QPS_ERR] = QIB_POST_RECV_OK | QIB_FLUSH_RECV |
131 QIB_POST_SEND_OK | QIB_FLUSH_SEND,
132 };
133
134 struct qib_ucontext {
135 struct ib_ucontext ibucontext;
136 };
137
138 static inline struct qib_ucontext *to_iucontext(struct ib_ucontext
139 *ibucontext)
140 {
141 return container_of(ibucontext, struct qib_ucontext, ibucontext);
142 }
143
144 /*
145 * Translate ib_wr_opcode into ib_wc_opcode.
146 */
147 const enum ib_wc_opcode ib_qib_wc_opcode[] = {
148 [IB_WR_RDMA_WRITE] = IB_WC_RDMA_WRITE,
149 [IB_WR_RDMA_WRITE_WITH_IMM] = IB_WC_RDMA_WRITE,
150 [IB_WR_SEND] = IB_WC_SEND,
151 [IB_WR_SEND_WITH_IMM] = IB_WC_SEND,
152 [IB_WR_RDMA_READ] = IB_WC_RDMA_READ,
153 [IB_WR_ATOMIC_CMP_AND_SWP] = IB_WC_COMP_SWAP,
154 [IB_WR_ATOMIC_FETCH_AND_ADD] = IB_WC_FETCH_ADD
155 };
156
157 /*
158 * System image GUID.
159 */
160 __be64 ib_qib_sys_image_guid;
161
162 /**
163 * qib_copy_sge - copy data to SGE memory
164 * @ss: the SGE state
165 * @data: the data to copy
166 * @length: the length of the data
167 */
168 void qib_copy_sge(struct qib_sge_state *ss, void *data, u32 length, int release)
169 {
170 struct qib_sge *sge = &ss->sge;
171
172 while (length) {
173 u32 len = sge->length;
174
175 if (len > length)
176 len = length;
177 if (len > sge->sge_length)
178 len = sge->sge_length;
179 BUG_ON(len == 0);
180 memcpy(sge->vaddr, data, len);
181 sge->vaddr += len;
182 sge->length -= len;
183 sge->sge_length -= len;
184 if (sge->sge_length == 0) {
185 if (release)
186 qib_put_mr(sge->mr);
187 if (--ss->num_sge)
188 *sge = *ss->sg_list++;
189 } else if (sge->length == 0 && sge->mr->lkey) {
190 if (++sge->n >= QIB_SEGSZ) {
191 if (++sge->m >= sge->mr->mapsz)
192 break;
193 sge->n = 0;
194 }
195 sge->vaddr =
196 sge->mr->map[sge->m]->segs[sge->n].vaddr;
197 sge->length =
198 sge->mr->map[sge->m]->segs[sge->n].length;
199 }
200 data += len;
201 length -= len;
202 }
203 }
204
205 /**
206 * qib_skip_sge - skip over SGE memory - XXX almost dup of prev func
207 * @ss: the SGE state
208 * @length: the number of bytes to skip
209 */
210 void qib_skip_sge(struct qib_sge_state *ss, u32 length, int release)
211 {
212 struct qib_sge *sge = &ss->sge;
213
214 while (length) {
215 u32 len = sge->length;
216
217 if (len > length)
218 len = length;
219 if (len > sge->sge_length)
220 len = sge->sge_length;
221 BUG_ON(len == 0);
222 sge->vaddr += len;
223 sge->length -= len;
224 sge->sge_length -= len;
225 if (sge->sge_length == 0) {
226 if (release)
227 qib_put_mr(sge->mr);
228 if (--ss->num_sge)
229 *sge = *ss->sg_list++;
230 } else if (sge->length == 0 && sge->mr->lkey) {
231 if (++sge->n >= QIB_SEGSZ) {
232 if (++sge->m >= sge->mr->mapsz)
233 break;
234 sge->n = 0;
235 }
236 sge->vaddr =
237 sge->mr->map[sge->m]->segs[sge->n].vaddr;
238 sge->length =
239 sge->mr->map[sge->m]->segs[sge->n].length;
240 }
241 length -= len;
242 }
243 }
244
245 /*
246 * Count the number of DMA descriptors needed to send length bytes of data.
247 * Don't modify the qib_sge_state to get the count.
248 * Return zero if any of the segments is not aligned.
249 */
250 static u32 qib_count_sge(struct qib_sge_state *ss, u32 length)
251 {
252 struct qib_sge *sg_list = ss->sg_list;
253 struct qib_sge sge = ss->sge;
254 u8 num_sge = ss->num_sge;
255 u32 ndesc = 1; /* count the header */
256
257 while (length) {
258 u32 len = sge.length;
259
260 if (len > length)
261 len = length;
262 if (len > sge.sge_length)
263 len = sge.sge_length;
264 BUG_ON(len == 0);
265 if (((long) sge.vaddr & (sizeof(u32) - 1)) ||
266 (len != length && (len & (sizeof(u32) - 1)))) {
267 ndesc = 0;
268 break;
269 }
270 ndesc++;
271 sge.vaddr += len;
272 sge.length -= len;
273 sge.sge_length -= len;
274 if (sge.sge_length == 0) {
275 if (--num_sge)
276 sge = *sg_list++;
277 } else if (sge.length == 0 && sge.mr->lkey) {
278 if (++sge.n >= QIB_SEGSZ) {
279 if (++sge.m >= sge.mr->mapsz)
280 break;
281 sge.n = 0;
282 }
283 sge.vaddr =
284 sge.mr->map[sge.m]->segs[sge.n].vaddr;
285 sge.length =
286 sge.mr->map[sge.m]->segs[sge.n].length;
287 }
288 length -= len;
289 }
290 return ndesc;
291 }
292
293 /*
294 * Copy from the SGEs to the data buffer.
295 */
296 static void qib_copy_from_sge(void *data, struct qib_sge_state *ss, u32 length)
297 {
298 struct qib_sge *sge = &ss->sge;
299
300 while (length) {
301 u32 len = sge->length;
302
303 if (len > length)
304 len = length;
305 if (len > sge->sge_length)
306 len = sge->sge_length;
307 BUG_ON(len == 0);
308 memcpy(data, sge->vaddr, len);
309 sge->vaddr += len;
310 sge->length -= len;
311 sge->sge_length -= len;
312 if (sge->sge_length == 0) {
313 if (--ss->num_sge)
314 *sge = *ss->sg_list++;
315 } else if (sge->length == 0 && sge->mr->lkey) {
316 if (++sge->n >= QIB_SEGSZ) {
317 if (++sge->m >= sge->mr->mapsz)
318 break;
319 sge->n = 0;
320 }
321 sge->vaddr =
322 sge->mr->map[sge->m]->segs[sge->n].vaddr;
323 sge->length =
324 sge->mr->map[sge->m]->segs[sge->n].length;
325 }
326 data += len;
327 length -= len;
328 }
329 }
330
331 /**
332 * qib_post_one_send - post one RC, UC, or UD send work request
333 * @qp: the QP to post on
334 * @wr: the work request to send
335 */
336 static int qib_post_one_send(struct qib_qp *qp, struct ib_send_wr *wr,
337 int *scheduled)
338 {
339 struct qib_swqe *wqe;
340 u32 next;
341 int i;
342 int j;
343 int acc;
344 int ret;
345 unsigned long flags;
346 struct qib_lkey_table *rkt;
347 struct qib_pd *pd;
348
349 spin_lock_irqsave(&qp->s_lock, flags);
350
351 /* Check that state is OK to post send. */
352 if (unlikely(!(ib_qib_state_ops[qp->state] & QIB_POST_SEND_OK)))
353 goto bail_inval;
354
355 /* IB spec says that num_sge == 0 is OK. */
356 if (wr->num_sge > qp->s_max_sge)
357 goto bail_inval;
358
359 /*
360 * Don't allow RDMA reads or atomic operations on UC or
361 * undefined operations.
362 * Make sure buffer is large enough to hold the result for atomics.
363 */
364 if (wr->opcode == IB_WR_FAST_REG_MR) {
365 if (qib_fast_reg_mr(qp, wr))
366 goto bail_inval;
367 } else if (qp->ibqp.qp_type == IB_QPT_UC) {
368 if ((unsigned) wr->opcode >= IB_WR_RDMA_READ)
369 goto bail_inval;
370 } else if (qp->ibqp.qp_type != IB_QPT_RC) {
371 /* Check IB_QPT_SMI, IB_QPT_GSI, IB_QPT_UD opcode */
372 if (wr->opcode != IB_WR_SEND &&
373 wr->opcode != IB_WR_SEND_WITH_IMM)
374 goto bail_inval;
375 /* Check UD destination address PD */
376 if (qp->ibqp.pd != wr->wr.ud.ah->pd)
377 goto bail_inval;
378 } else if ((unsigned) wr->opcode > IB_WR_ATOMIC_FETCH_AND_ADD)
379 goto bail_inval;
380 else if (wr->opcode >= IB_WR_ATOMIC_CMP_AND_SWP &&
381 (wr->num_sge == 0 ||
382 wr->sg_list[0].length < sizeof(u64) ||
383 wr->sg_list[0].addr & (sizeof(u64) - 1)))
384 goto bail_inval;
385 else if (wr->opcode >= IB_WR_RDMA_READ && !qp->s_max_rd_atomic)
386 goto bail_inval;
387
388 next = qp->s_head + 1;
389 if (next >= qp->s_size)
390 next = 0;
391 if (next == qp->s_last) {
392 ret = -ENOMEM;
393 goto bail;
394 }
395
396 rkt = &to_idev(qp->ibqp.device)->lk_table;
397 pd = to_ipd(qp->ibqp.pd);
398 wqe = get_swqe_ptr(qp, qp->s_head);
399 wqe->wr = *wr;
400 wqe->length = 0;
401 j = 0;
402 if (wr->num_sge) {
403 acc = wr->opcode >= IB_WR_RDMA_READ ?
404 IB_ACCESS_LOCAL_WRITE : 0;
405 for (i = 0; i < wr->num_sge; i++) {
406 u32 length = wr->sg_list[i].length;
407 int ok;
408
409 if (length == 0)
410 continue;
411 ok = qib_lkey_ok(rkt, pd, &wqe->sg_list[j],
412 &wr->sg_list[i], acc);
413 if (!ok)
414 goto bail_inval_free;
415 wqe->length += length;
416 j++;
417 }
418 wqe->wr.num_sge = j;
419 }
420 if (qp->ibqp.qp_type == IB_QPT_UC ||
421 qp->ibqp.qp_type == IB_QPT_RC) {
422 if (wqe->length > 0x80000000U)
423 goto bail_inval_free;
424 } else if (wqe->length > (dd_from_ibdev(qp->ibqp.device)->pport +
425 qp->port_num - 1)->ibmtu)
426 goto bail_inval_free;
427 else
428 atomic_inc(&to_iah(wr->wr.ud.ah)->refcount);
429 wqe->ssn = qp->s_ssn++;
430 qp->s_head = next;
431
432 ret = 0;
433 goto bail;
434
435 bail_inval_free:
436 while (j) {
437 struct qib_sge *sge = &wqe->sg_list[--j];
438
439 qib_put_mr(sge->mr);
440 }
441 bail_inval:
442 ret = -EINVAL;
443 bail:
444 if (!ret && !wr->next &&
445 !qib_sdma_empty(
446 dd_from_ibdev(qp->ibqp.device)->pport + qp->port_num - 1)) {
447 qib_schedule_send(qp);
448 *scheduled = 1;
449 }
450 spin_unlock_irqrestore(&qp->s_lock, flags);
451 return ret;
452 }
453
454 /**
455 * qib_post_send - post a send on a QP
456 * @ibqp: the QP to post the send on
457 * @wr: the list of work requests to post
458 * @bad_wr: the first bad WR is put here
459 *
460 * This may be called from interrupt context.
461 */
462 static int qib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
463 struct ib_send_wr **bad_wr)
464 {
465 struct qib_qp *qp = to_iqp(ibqp);
466 int err = 0;
467 int scheduled = 0;
468
469 for (; wr; wr = wr->next) {
470 err = qib_post_one_send(qp, wr, &scheduled);
471 if (err) {
472 *bad_wr = wr;
473 goto bail;
474 }
475 }
476
477 /* Try to do the send work in the caller's context. */
478 if (!scheduled)
479 qib_do_send(&qp->s_work);
480
481 bail:
482 return err;
483 }
484
485 /**
486 * qib_post_receive - post a receive on a QP
487 * @ibqp: the QP to post the receive on
488 * @wr: the WR to post
489 * @bad_wr: the first bad WR is put here
490 *
491 * This may be called from interrupt context.
492 */
493 static int qib_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
494 struct ib_recv_wr **bad_wr)
495 {
496 struct qib_qp *qp = to_iqp(ibqp);
497 struct qib_rwq *wq = qp->r_rq.wq;
498 unsigned long flags;
499 int ret;
500
501 /* Check that state is OK to post receive. */
502 if (!(ib_qib_state_ops[qp->state] & QIB_POST_RECV_OK) || !wq) {
503 *bad_wr = wr;
504 ret = -EINVAL;
505 goto bail;
506 }
507
508 for (; wr; wr = wr->next) {
509 struct qib_rwqe *wqe;
510 u32 next;
511 int i;
512
513 if ((unsigned) wr->num_sge > qp->r_rq.max_sge) {
514 *bad_wr = wr;
515 ret = -EINVAL;
516 goto bail;
517 }
518
519 spin_lock_irqsave(&qp->r_rq.lock, flags);
520 next = wq->head + 1;
521 if (next >= qp->r_rq.size)
522 next = 0;
523 if (next == wq->tail) {
524 spin_unlock_irqrestore(&qp->r_rq.lock, flags);
525 *bad_wr = wr;
526 ret = -ENOMEM;
527 goto bail;
528 }
529
530 wqe = get_rwqe_ptr(&qp->r_rq, wq->head);
531 wqe->wr_id = wr->wr_id;
532 wqe->num_sge = wr->num_sge;
533 for (i = 0; i < wr->num_sge; i++)
534 wqe->sg_list[i] = wr->sg_list[i];
535 /* Make sure queue entry is written before the head index. */
536 smp_wmb();
537 wq->head = next;
538 spin_unlock_irqrestore(&qp->r_rq.lock, flags);
539 }
540 ret = 0;
541
542 bail:
543 return ret;
544 }
545
546 /**
547 * qib_qp_rcv - processing an incoming packet on a QP
548 * @rcd: the context pointer
549 * @hdr: the packet header
550 * @has_grh: true if the packet has a GRH
551 * @data: the packet data
552 * @tlen: the packet length
553 * @qp: the QP the packet came on
554 *
555 * This is called from qib_ib_rcv() to process an incoming packet
556 * for the given QP.
557 * Called at interrupt level.
558 */
559 static void qib_qp_rcv(struct qib_ctxtdata *rcd, struct qib_ib_header *hdr,
560 int has_grh, void *data, u32 tlen, struct qib_qp *qp)
561 {
562 struct qib_ibport *ibp = &rcd->ppd->ibport_data;
563
564 spin_lock(&qp->r_lock);
565
566 /* Check for valid receive state. */
567 if (!(ib_qib_state_ops[qp->state] & QIB_PROCESS_RECV_OK)) {
568 ibp->n_pkt_drops++;
569 goto unlock;
570 }
571
572 switch (qp->ibqp.qp_type) {
573 case IB_QPT_SMI:
574 case IB_QPT_GSI:
575 if (ib_qib_disable_sma)
576 break;
577 /* FALLTHROUGH */
578 case IB_QPT_UD:
579 qib_ud_rcv(ibp, hdr, has_grh, data, tlen, qp);
580 break;
581
582 case IB_QPT_RC:
583 qib_rc_rcv(rcd, hdr, has_grh, data, tlen, qp);
584 break;
585
586 case IB_QPT_UC:
587 qib_uc_rcv(ibp, hdr, has_grh, data, tlen, qp);
588 break;
589
590 default:
591 break;
592 }
593
594 unlock:
595 spin_unlock(&qp->r_lock);
596 }
597
598 /**
599 * qib_ib_rcv - process an incoming packet
600 * @rcd: the context pointer
601 * @rhdr: the header of the packet
602 * @data: the packet payload
603 * @tlen: the packet length
604 *
605 * This is called from qib_kreceive() to process an incoming packet at
606 * interrupt level. Tlen is the length of the header + data + CRC in bytes.
607 */
608 void qib_ib_rcv(struct qib_ctxtdata *rcd, void *rhdr, void *data, u32 tlen)
609 {
610 struct qib_pportdata *ppd = rcd->ppd;
611 struct qib_ibport *ibp = &ppd->ibport_data;
612 struct qib_ib_header *hdr = rhdr;
613 struct qib_other_headers *ohdr;
614 struct qib_qp *qp;
615 u32 qp_num;
616 int lnh;
617 u8 opcode;
618 u16 lid;
619
620 /* 24 == LRH+BTH+CRC */
621 if (unlikely(tlen < 24))
622 goto drop;
623
624 /* Check for a valid destination LID (see ch. 7.11.1). */
625 lid = be16_to_cpu(hdr->lrh[1]);
626 if (lid < QIB_MULTICAST_LID_BASE) {
627 lid &= ~((1 << ppd->lmc) - 1);
628 if (unlikely(lid != ppd->lid))
629 goto drop;
630 }
631
632 /* Check for GRH */
633 lnh = be16_to_cpu(hdr->lrh[0]) & 3;
634 if (lnh == QIB_LRH_BTH)
635 ohdr = &hdr->u.oth;
636 else if (lnh == QIB_LRH_GRH) {
637 u32 vtf;
638
639 ohdr = &hdr->u.l.oth;
640 if (hdr->u.l.grh.next_hdr != IB_GRH_NEXT_HDR)
641 goto drop;
642 vtf = be32_to_cpu(hdr->u.l.grh.version_tclass_flow);
643 if ((vtf >> IB_GRH_VERSION_SHIFT) != IB_GRH_VERSION)
644 goto drop;
645 } else
646 goto drop;
647
648 opcode = (be32_to_cpu(ohdr->bth[0]) >> 24) & 0x7f;
649 #ifdef CONFIG_DEBUG_FS
650 rcd->opstats->stats[opcode].n_bytes += tlen;
651 rcd->opstats->stats[opcode].n_packets++;
652 #endif
653
654 /* Get the destination QP number. */
655 qp_num = be32_to_cpu(ohdr->bth[1]) & QIB_QPN_MASK;
656 if (qp_num == QIB_MULTICAST_QPN) {
657 struct qib_mcast *mcast;
658 struct qib_mcast_qp *p;
659
660 if (lnh != QIB_LRH_GRH)
661 goto drop;
662 mcast = qib_mcast_find(ibp, &hdr->u.l.grh.dgid);
663 if (mcast == NULL)
664 goto drop;
665 ibp->n_multicast_rcv++;
666 list_for_each_entry_rcu(p, &mcast->qp_list, list)
667 qib_qp_rcv(rcd, hdr, 1, data, tlen, p->qp);
668 /*
669 * Notify qib_multicast_detach() if it is waiting for us
670 * to finish.
671 */
672 if (atomic_dec_return(&mcast->refcount) <= 1)
673 wake_up(&mcast->wait);
674 } else {
675 if (rcd->lookaside_qp) {
676 if (rcd->lookaside_qpn != qp_num) {
677 if (atomic_dec_and_test(
678 &rcd->lookaside_qp->refcount))
679 wake_up(
680 &rcd->lookaside_qp->wait);
681 rcd->lookaside_qp = NULL;
682 }
683 }
684 if (!rcd->lookaside_qp) {
685 qp = qib_lookup_qpn(ibp, qp_num);
686 if (!qp)
687 goto drop;
688 rcd->lookaside_qp = qp;
689 rcd->lookaside_qpn = qp_num;
690 } else
691 qp = rcd->lookaside_qp;
692 ibp->n_unicast_rcv++;
693 qib_qp_rcv(rcd, hdr, lnh == QIB_LRH_GRH, data, tlen, qp);
694 }
695 return;
696
697 drop:
698 ibp->n_pkt_drops++;
699 }
700
701 /*
702 * This is called from a timer to check for QPs
703 * which need kernel memory in order to send a packet.
704 */
705 static void mem_timer(unsigned long data)
706 {
707 struct qib_ibdev *dev = (struct qib_ibdev *) data;
708 struct list_head *list = &dev->memwait;
709 struct qib_qp *qp = NULL;
710 unsigned long flags;
711
712 spin_lock_irqsave(&dev->pending_lock, flags);
713 if (!list_empty(list)) {
714 qp = list_entry(list->next, struct qib_qp, iowait);
715 list_del_init(&qp->iowait);
716 atomic_inc(&qp->refcount);
717 if (!list_empty(list))
718 mod_timer(&dev->mem_timer, jiffies + 1);
719 }
720 spin_unlock_irqrestore(&dev->pending_lock, flags);
721
722 if (qp) {
723 spin_lock_irqsave(&qp->s_lock, flags);
724 if (qp->s_flags & QIB_S_WAIT_KMEM) {
725 qp->s_flags &= ~QIB_S_WAIT_KMEM;
726 qib_schedule_send(qp);
727 }
728 spin_unlock_irqrestore(&qp->s_lock, flags);
729 if (atomic_dec_and_test(&qp->refcount))
730 wake_up(&qp->wait);
731 }
732 }
733
734 static void update_sge(struct qib_sge_state *ss, u32 length)
735 {
736 struct qib_sge *sge = &ss->sge;
737
738 sge->vaddr += length;
739 sge->length -= length;
740 sge->sge_length -= length;
741 if (sge->sge_length == 0) {
742 if (--ss->num_sge)
743 *sge = *ss->sg_list++;
744 } else if (sge->length == 0 && sge->mr->lkey) {
745 if (++sge->n >= QIB_SEGSZ) {
746 if (++sge->m >= sge->mr->mapsz)
747 return;
748 sge->n = 0;
749 }
750 sge->vaddr = sge->mr->map[sge->m]->segs[sge->n].vaddr;
751 sge->length = sge->mr->map[sge->m]->segs[sge->n].length;
752 }
753 }
754
755 #ifdef __LITTLE_ENDIAN
756 static inline u32 get_upper_bits(u32 data, u32 shift)
757 {
758 return data >> shift;
759 }
760
761 static inline u32 set_upper_bits(u32 data, u32 shift)
762 {
763 return data << shift;
764 }
765
766 static inline u32 clear_upper_bytes(u32 data, u32 n, u32 off)
767 {
768 data <<= ((sizeof(u32) - n) * BITS_PER_BYTE);
769 data >>= ((sizeof(u32) - n - off) * BITS_PER_BYTE);
770 return data;
771 }
772 #else
773 static inline u32 get_upper_bits(u32 data, u32 shift)
774 {
775 return data << shift;
776 }
777
778 static inline u32 set_upper_bits(u32 data, u32 shift)
779 {
780 return data >> shift;
781 }
782
783 static inline u32 clear_upper_bytes(u32 data, u32 n, u32 off)
784 {
785 data >>= ((sizeof(u32) - n) * BITS_PER_BYTE);
786 data <<= ((sizeof(u32) - n - off) * BITS_PER_BYTE);
787 return data;
788 }
789 #endif
790
791 static void copy_io(u32 __iomem *piobuf, struct qib_sge_state *ss,
792 u32 length, unsigned flush_wc)
793 {
794 u32 extra = 0;
795 u32 data = 0;
796 u32 last;
797
798 while (1) {
799 u32 len = ss->sge.length;
800 u32 off;
801
802 if (len > length)
803 len = length;
804 if (len > ss->sge.sge_length)
805 len = ss->sge.sge_length;
806 BUG_ON(len == 0);
807 /* If the source address is not aligned, try to align it. */
808 off = (unsigned long)ss->sge.vaddr & (sizeof(u32) - 1);
809 if (off) {
810 u32 *addr = (u32 *)((unsigned long)ss->sge.vaddr &
811 ~(sizeof(u32) - 1));
812 u32 v = get_upper_bits(*addr, off * BITS_PER_BYTE);
813 u32 y;
814
815 y = sizeof(u32) - off;
816 if (len > y)
817 len = y;
818 if (len + extra >= sizeof(u32)) {
819 data |= set_upper_bits(v, extra *
820 BITS_PER_BYTE);
821 len = sizeof(u32) - extra;
822 if (len == length) {
823 last = data;
824 break;
825 }
826 __raw_writel(data, piobuf);
827 piobuf++;
828 extra = 0;
829 data = 0;
830 } else {
831 /* Clear unused upper bytes */
832 data |= clear_upper_bytes(v, len, extra);
833 if (len == length) {
834 last = data;
835 break;
836 }
837 extra += len;
838 }
839 } else if (extra) {
840 /* Source address is aligned. */
841 u32 *addr = (u32 *) ss->sge.vaddr;
842 int shift = extra * BITS_PER_BYTE;
843 int ushift = 32 - shift;
844 u32 l = len;
845
846 while (l >= sizeof(u32)) {
847 u32 v = *addr;
848
849 data |= set_upper_bits(v, shift);
850 __raw_writel(data, piobuf);
851 data = get_upper_bits(v, ushift);
852 piobuf++;
853 addr++;
854 l -= sizeof(u32);
855 }
856 /*
857 * We still have 'extra' number of bytes leftover.
858 */
859 if (l) {
860 u32 v = *addr;
861
862 if (l + extra >= sizeof(u32)) {
863 data |= set_upper_bits(v, shift);
864 len -= l + extra - sizeof(u32);
865 if (len == length) {
866 last = data;
867 break;
868 }
869 __raw_writel(data, piobuf);
870 piobuf++;
871 extra = 0;
872 data = 0;
873 } else {
874 /* Clear unused upper bytes */
875 data |= clear_upper_bytes(v, l, extra);
876 if (len == length) {
877 last = data;
878 break;
879 }
880 extra += l;
881 }
882 } else if (len == length) {
883 last = data;
884 break;
885 }
886 } else if (len == length) {
887 u32 w;
888
889 /*
890 * Need to round up for the last dword in the
891 * packet.
892 */
893 w = (len + 3) >> 2;
894 qib_pio_copy(piobuf, ss->sge.vaddr, w - 1);
895 piobuf += w - 1;
896 last = ((u32 *) ss->sge.vaddr)[w - 1];
897 break;
898 } else {
899 u32 w = len >> 2;
900
901 qib_pio_copy(piobuf, ss->sge.vaddr, w);
902 piobuf += w;
903
904 extra = len & (sizeof(u32) - 1);
905 if (extra) {
906 u32 v = ((u32 *) ss->sge.vaddr)[w];
907
908 /* Clear unused upper bytes */
909 data = clear_upper_bytes(v, extra, 0);
910 }
911 }
912 update_sge(ss, len);
913 length -= len;
914 }
915 /* Update address before sending packet. */
916 update_sge(ss, length);
917 if (flush_wc) {
918 /* must flush early everything before trigger word */
919 qib_flush_wc();
920 __raw_writel(last, piobuf);
921 /* be sure trigger word is written */
922 qib_flush_wc();
923 } else
924 __raw_writel(last, piobuf);
925 }
926
927 static noinline struct qib_verbs_txreq *__get_txreq(struct qib_ibdev *dev,
928 struct qib_qp *qp)
929 {
930 struct qib_verbs_txreq *tx;
931 unsigned long flags;
932
933 spin_lock_irqsave(&qp->s_lock, flags);
934 spin_lock(&dev->pending_lock);
935
936 if (!list_empty(&dev->txreq_free)) {
937 struct list_head *l = dev->txreq_free.next;
938
939 list_del(l);
940 spin_unlock(&dev->pending_lock);
941 spin_unlock_irqrestore(&qp->s_lock, flags);
942 tx = list_entry(l, struct qib_verbs_txreq, txreq.list);
943 } else {
944 if (ib_qib_state_ops[qp->state] & QIB_PROCESS_RECV_OK &&
945 list_empty(&qp->iowait)) {
946 dev->n_txwait++;
947 qp->s_flags |= QIB_S_WAIT_TX;
948 list_add_tail(&qp->iowait, &dev->txwait);
949 }
950 qp->s_flags &= ~QIB_S_BUSY;
951 spin_unlock(&dev->pending_lock);
952 spin_unlock_irqrestore(&qp->s_lock, flags);
953 tx = ERR_PTR(-EBUSY);
954 }
955 return tx;
956 }
957
958 static inline struct qib_verbs_txreq *get_txreq(struct qib_ibdev *dev,
959 struct qib_qp *qp)
960 {
961 struct qib_verbs_txreq *tx;
962 unsigned long flags;
963
964 spin_lock_irqsave(&dev->pending_lock, flags);
965 /* assume the list non empty */
966 if (likely(!list_empty(&dev->txreq_free))) {
967 struct list_head *l = dev->txreq_free.next;
968
969 list_del(l);
970 spin_unlock_irqrestore(&dev->pending_lock, flags);
971 tx = list_entry(l, struct qib_verbs_txreq, txreq.list);
972 } else {
973 /* call slow path to get the extra lock */
974 spin_unlock_irqrestore(&dev->pending_lock, flags);
975 tx = __get_txreq(dev, qp);
976 }
977 return tx;
978 }
979
980 void qib_put_txreq(struct qib_verbs_txreq *tx)
981 {
982 struct qib_ibdev *dev;
983 struct qib_qp *qp;
984 unsigned long flags;
985
986 qp = tx->qp;
987 dev = to_idev(qp->ibqp.device);
988
989 if (atomic_dec_and_test(&qp->refcount))
990 wake_up(&qp->wait);
991 if (tx->mr) {
992 qib_put_mr(tx->mr);
993 tx->mr = NULL;
994 }
995 if (tx->txreq.flags & QIB_SDMA_TXREQ_F_FREEBUF) {
996 tx->txreq.flags &= ~QIB_SDMA_TXREQ_F_FREEBUF;
997 dma_unmap_single(&dd_from_dev(dev)->pcidev->dev,
998 tx->txreq.addr, tx->hdr_dwords << 2,
999 DMA_TO_DEVICE);
1000 kfree(tx->align_buf);
1001 }
1002
1003 spin_lock_irqsave(&dev->pending_lock, flags);
1004
1005 /* Put struct back on free list */
1006 list_add(&tx->txreq.list, &dev->txreq_free);
1007
1008 if (!list_empty(&dev->txwait)) {
1009 /* Wake up first QP wanting a free struct */
1010 qp = list_entry(dev->txwait.next, struct qib_qp, iowait);
1011 list_del_init(&qp->iowait);
1012 atomic_inc(&qp->refcount);
1013 spin_unlock_irqrestore(&dev->pending_lock, flags);
1014
1015 spin_lock_irqsave(&qp->s_lock, flags);
1016 if (qp->s_flags & QIB_S_WAIT_TX) {
1017 qp->s_flags &= ~QIB_S_WAIT_TX;
1018 qib_schedule_send(qp);
1019 }
1020 spin_unlock_irqrestore(&qp->s_lock, flags);
1021
1022 if (atomic_dec_and_test(&qp->refcount))
1023 wake_up(&qp->wait);
1024 } else
1025 spin_unlock_irqrestore(&dev->pending_lock, flags);
1026 }
1027
1028 /*
1029 * This is called when there are send DMA descriptors that might be
1030 * available.
1031 *
1032 * This is called with ppd->sdma_lock held.
1033 */
1034 void qib_verbs_sdma_desc_avail(struct qib_pportdata *ppd, unsigned avail)
1035 {
1036 struct qib_qp *qp, *nqp;
1037 struct qib_qp *qps[20];
1038 struct qib_ibdev *dev;
1039 unsigned i, n;
1040
1041 n = 0;
1042 dev = &ppd->dd->verbs_dev;
1043 spin_lock(&dev->pending_lock);
1044
1045 /* Search wait list for first QP wanting DMA descriptors. */
1046 list_for_each_entry_safe(qp, nqp, &dev->dmawait, iowait) {
1047 if (qp->port_num != ppd->port)
1048 continue;
1049 if (n == ARRAY_SIZE(qps))
1050 break;
1051 if (qp->s_tx->txreq.sg_count > avail)
1052 break;
1053 avail -= qp->s_tx->txreq.sg_count;
1054 list_del_init(&qp->iowait);
1055 atomic_inc(&qp->refcount);
1056 qps[n++] = qp;
1057 }
1058
1059 spin_unlock(&dev->pending_lock);
1060
1061 for (i = 0; i < n; i++) {
1062 qp = qps[i];
1063 spin_lock(&qp->s_lock);
1064 if (qp->s_flags & QIB_S_WAIT_DMA_DESC) {
1065 qp->s_flags &= ~QIB_S_WAIT_DMA_DESC;
1066 qib_schedule_send(qp);
1067 }
1068 spin_unlock(&qp->s_lock);
1069 if (atomic_dec_and_test(&qp->refcount))
1070 wake_up(&qp->wait);
1071 }
1072 }
1073
1074 /*
1075 * This is called with ppd->sdma_lock held.
1076 */
1077 static void sdma_complete(struct qib_sdma_txreq *cookie, int status)
1078 {
1079 struct qib_verbs_txreq *tx =
1080 container_of(cookie, struct qib_verbs_txreq, txreq);
1081 struct qib_qp *qp = tx->qp;
1082
1083 spin_lock(&qp->s_lock);
1084 if (tx->wqe)
1085 qib_send_complete(qp, tx->wqe, IB_WC_SUCCESS);
1086 else if (qp->ibqp.qp_type == IB_QPT_RC) {
1087 struct qib_ib_header *hdr;
1088
1089 if (tx->txreq.flags & QIB_SDMA_TXREQ_F_FREEBUF)
1090 hdr = &tx->align_buf->hdr;
1091 else {
1092 struct qib_ibdev *dev = to_idev(qp->ibqp.device);
1093
1094 hdr = &dev->pio_hdrs[tx->hdr_inx].hdr;
1095 }
1096 qib_rc_send_complete(qp, hdr);
1097 }
1098 if (atomic_dec_and_test(&qp->s_dma_busy)) {
1099 if (qp->state == IB_QPS_RESET)
1100 wake_up(&qp->wait_dma);
1101 else if (qp->s_flags & QIB_S_WAIT_DMA) {
1102 qp->s_flags &= ~QIB_S_WAIT_DMA;
1103 qib_schedule_send(qp);
1104 }
1105 }
1106 spin_unlock(&qp->s_lock);
1107
1108 qib_put_txreq(tx);
1109 }
1110
1111 static int wait_kmem(struct qib_ibdev *dev, struct qib_qp *qp)
1112 {
1113 unsigned long flags;
1114 int ret = 0;
1115
1116 spin_lock_irqsave(&qp->s_lock, flags);
1117 if (ib_qib_state_ops[qp->state] & QIB_PROCESS_RECV_OK) {
1118 spin_lock(&dev->pending_lock);
1119 if (list_empty(&qp->iowait)) {
1120 if (list_empty(&dev->memwait))
1121 mod_timer(&dev->mem_timer, jiffies + 1);
1122 qp->s_flags |= QIB_S_WAIT_KMEM;
1123 list_add_tail(&qp->iowait, &dev->memwait);
1124 }
1125 spin_unlock(&dev->pending_lock);
1126 qp->s_flags &= ~QIB_S_BUSY;
1127 ret = -EBUSY;
1128 }
1129 spin_unlock_irqrestore(&qp->s_lock, flags);
1130
1131 return ret;
1132 }
1133
1134 static int qib_verbs_send_dma(struct qib_qp *qp, struct qib_ib_header *hdr,
1135 u32 hdrwords, struct qib_sge_state *ss, u32 len,
1136 u32 plen, u32 dwords)
1137 {
1138 struct qib_ibdev *dev = to_idev(qp->ibqp.device);
1139 struct qib_devdata *dd = dd_from_dev(dev);
1140 struct qib_ibport *ibp = to_iport(qp->ibqp.device, qp->port_num);
1141 struct qib_pportdata *ppd = ppd_from_ibp(ibp);
1142 struct qib_verbs_txreq *tx;
1143 struct qib_pio_header *phdr;
1144 u32 control;
1145 u32 ndesc;
1146 int ret;
1147
1148 tx = qp->s_tx;
1149 if (tx) {
1150 qp->s_tx = NULL;
1151 /* resend previously constructed packet */
1152 ret = qib_sdma_verbs_send(ppd, tx->ss, tx->dwords, tx);
1153 goto bail;
1154 }
1155
1156 tx = get_txreq(dev, qp);
1157 if (IS_ERR(tx))
1158 goto bail_tx;
1159
1160 control = dd->f_setpbc_control(ppd, plen, qp->s_srate,
1161 be16_to_cpu(hdr->lrh[0]) >> 12);
1162 tx->qp = qp;
1163 atomic_inc(&qp->refcount);
1164 tx->wqe = qp->s_wqe;
1165 tx->mr = qp->s_rdma_mr;
1166 if (qp->s_rdma_mr)
1167 qp->s_rdma_mr = NULL;
1168 tx->txreq.callback = sdma_complete;
1169 if (dd->flags & QIB_HAS_SDMA_TIMEOUT)
1170 tx->txreq.flags = QIB_SDMA_TXREQ_F_HEADTOHOST;
1171 else
1172 tx->txreq.flags = QIB_SDMA_TXREQ_F_INTREQ;
1173 if (plen + 1 > dd->piosize2kmax_dwords)
1174 tx->txreq.flags |= QIB_SDMA_TXREQ_F_USELARGEBUF;
1175
1176 if (len) {
1177 /*
1178 * Don't try to DMA if it takes more descriptors than
1179 * the queue holds.
1180 */
1181 ndesc = qib_count_sge(ss, len);
1182 if (ndesc >= ppd->sdma_descq_cnt)
1183 ndesc = 0;
1184 } else
1185 ndesc = 1;
1186 if (ndesc) {
1187 phdr = &dev->pio_hdrs[tx->hdr_inx];
1188 phdr->pbc[0] = cpu_to_le32(plen);
1189 phdr->pbc[1] = cpu_to_le32(control);
1190 memcpy(&phdr->hdr, hdr, hdrwords << 2);
1191 tx->txreq.flags |= QIB_SDMA_TXREQ_F_FREEDESC;
1192 tx->txreq.sg_count = ndesc;
1193 tx->txreq.addr = dev->pio_hdrs_phys +
1194 tx->hdr_inx * sizeof(struct qib_pio_header);
1195 tx->hdr_dwords = hdrwords + 2; /* add PBC length */
1196 ret = qib_sdma_verbs_send(ppd, ss, dwords, tx);
1197 goto bail;
1198 }
1199
1200 /* Allocate a buffer and copy the header and payload to it. */
1201 tx->hdr_dwords = plen + 1;
1202 phdr = kmalloc(tx->hdr_dwords << 2, GFP_ATOMIC);
1203 if (!phdr)
1204 goto err_tx;
1205 phdr->pbc[0] = cpu_to_le32(plen);
1206 phdr->pbc[1] = cpu_to_le32(control);
1207 memcpy(&phdr->hdr, hdr, hdrwords << 2);
1208 qib_copy_from_sge((u32 *) &phdr->hdr + hdrwords, ss, len);
1209
1210 tx->txreq.addr = dma_map_single(&dd->pcidev->dev, phdr,
1211 tx->hdr_dwords << 2, DMA_TO_DEVICE);
1212 if (dma_mapping_error(&dd->pcidev->dev, tx->txreq.addr))
1213 goto map_err;
1214 tx->align_buf = phdr;
1215 tx->txreq.flags |= QIB_SDMA_TXREQ_F_FREEBUF;
1216 tx->txreq.sg_count = 1;
1217 ret = qib_sdma_verbs_send(ppd, NULL, 0, tx);
1218 goto unaligned;
1219
1220 map_err:
1221 kfree(phdr);
1222 err_tx:
1223 qib_put_txreq(tx);
1224 ret = wait_kmem(dev, qp);
1225 unaligned:
1226 ibp->n_unaligned++;
1227 bail:
1228 return ret;
1229 bail_tx:
1230 ret = PTR_ERR(tx);
1231 goto bail;
1232 }
1233
1234 /*
1235 * If we are now in the error state, return zero to flush the
1236 * send work request.
1237 */
1238 static int no_bufs_available(struct qib_qp *qp)
1239 {
1240 struct qib_ibdev *dev = to_idev(qp->ibqp.device);
1241 struct qib_devdata *dd;
1242 unsigned long flags;
1243 int ret = 0;
1244
1245 /*
1246 * Note that as soon as want_buffer() is called and
1247 * possibly before it returns, qib_ib_piobufavail()
1248 * could be called. Therefore, put QP on the I/O wait list before
1249 * enabling the PIO avail interrupt.
1250 */
1251 spin_lock_irqsave(&qp->s_lock, flags);
1252 if (ib_qib_state_ops[qp->state] & QIB_PROCESS_RECV_OK) {
1253 spin_lock(&dev->pending_lock);
1254 if (list_empty(&qp->iowait)) {
1255 dev->n_piowait++;
1256 qp->s_flags |= QIB_S_WAIT_PIO;
1257 list_add_tail(&qp->iowait, &dev->piowait);
1258 dd = dd_from_dev(dev);
1259 dd->f_wantpiobuf_intr(dd, 1);
1260 }
1261 spin_unlock(&dev->pending_lock);
1262 qp->s_flags &= ~QIB_S_BUSY;
1263 ret = -EBUSY;
1264 }
1265 spin_unlock_irqrestore(&qp->s_lock, flags);
1266 return ret;
1267 }
1268
1269 static int qib_verbs_send_pio(struct qib_qp *qp, struct qib_ib_header *ibhdr,
1270 u32 hdrwords, struct qib_sge_state *ss, u32 len,
1271 u32 plen, u32 dwords)
1272 {
1273 struct qib_devdata *dd = dd_from_ibdev(qp->ibqp.device);
1274 struct qib_pportdata *ppd = dd->pport + qp->port_num - 1;
1275 u32 *hdr = (u32 *) ibhdr;
1276 u32 __iomem *piobuf_orig;
1277 u32 __iomem *piobuf;
1278 u64 pbc;
1279 unsigned long flags;
1280 unsigned flush_wc;
1281 u32 control;
1282 u32 pbufn;
1283
1284 control = dd->f_setpbc_control(ppd, plen, qp->s_srate,
1285 be16_to_cpu(ibhdr->lrh[0]) >> 12);
1286 pbc = ((u64) control << 32) | plen;
1287 piobuf = dd->f_getsendbuf(ppd, pbc, &pbufn);
1288 if (unlikely(piobuf == NULL))
1289 return no_bufs_available(qp);
1290
1291 /*
1292 * Write the pbc.
1293 * We have to flush after the PBC for correctness on some cpus
1294 * or WC buffer can be written out of order.
1295 */
1296 writeq(pbc, piobuf);
1297 piobuf_orig = piobuf;
1298 piobuf += 2;
1299
1300 flush_wc = dd->flags & QIB_PIO_FLUSH_WC;
1301 if (len == 0) {
1302 /*
1303 * If there is just the header portion, must flush before
1304 * writing last word of header for correctness, and after
1305 * the last header word (trigger word).
1306 */
1307 if (flush_wc) {
1308 qib_flush_wc();
1309 qib_pio_copy(piobuf, hdr, hdrwords - 1);
1310 qib_flush_wc();
1311 __raw_writel(hdr[hdrwords - 1], piobuf + hdrwords - 1);
1312 qib_flush_wc();
1313 } else
1314 qib_pio_copy(piobuf, hdr, hdrwords);
1315 goto done;
1316 }
1317
1318 if (flush_wc)
1319 qib_flush_wc();
1320 qib_pio_copy(piobuf, hdr, hdrwords);
1321 piobuf += hdrwords;
1322
1323 /* The common case is aligned and contained in one segment. */
1324 if (likely(ss->num_sge == 1 && len <= ss->sge.length &&
1325 !((unsigned long)ss->sge.vaddr & (sizeof(u32) - 1)))) {
1326 u32 *addr = (u32 *) ss->sge.vaddr;
1327
1328 /* Update address before sending packet. */
1329 update_sge(ss, len);
1330 if (flush_wc) {
1331 qib_pio_copy(piobuf, addr, dwords - 1);
1332 /* must flush early everything before trigger word */
1333 qib_flush_wc();
1334 __raw_writel(addr[dwords - 1], piobuf + dwords - 1);
1335 /* be sure trigger word is written */
1336 qib_flush_wc();
1337 } else
1338 qib_pio_copy(piobuf, addr, dwords);
1339 goto done;
1340 }
1341 copy_io(piobuf, ss, len, flush_wc);
1342 done:
1343 if (dd->flags & QIB_USE_SPCL_TRIG) {
1344 u32 spcl_off = (pbufn >= dd->piobcnt2k) ? 2047 : 1023;
1345 qib_flush_wc();
1346 __raw_writel(0xaebecede, piobuf_orig + spcl_off);
1347 }
1348 qib_sendbuf_done(dd, pbufn);
1349 if (qp->s_rdma_mr) {
1350 qib_put_mr(qp->s_rdma_mr);
1351 qp->s_rdma_mr = NULL;
1352 }
1353 if (qp->s_wqe) {
1354 spin_lock_irqsave(&qp->s_lock, flags);
1355 qib_send_complete(qp, qp->s_wqe, IB_WC_SUCCESS);
1356 spin_unlock_irqrestore(&qp->s_lock, flags);
1357 } else if (qp->ibqp.qp_type == IB_QPT_RC) {
1358 spin_lock_irqsave(&qp->s_lock, flags);
1359 qib_rc_send_complete(qp, ibhdr);
1360 spin_unlock_irqrestore(&qp->s_lock, flags);
1361 }
1362 return 0;
1363 }
1364
1365 /**
1366 * qib_verbs_send - send a packet
1367 * @qp: the QP to send on
1368 * @hdr: the packet header
1369 * @hdrwords: the number of 32-bit words in the header
1370 * @ss: the SGE to send
1371 * @len: the length of the packet in bytes
1372 *
1373 * Return zero if packet is sent or queued OK.
1374 * Return non-zero and clear qp->s_flags QIB_S_BUSY otherwise.
1375 */
1376 int qib_verbs_send(struct qib_qp *qp, struct qib_ib_header *hdr,
1377 u32 hdrwords, struct qib_sge_state *ss, u32 len)
1378 {
1379 struct qib_devdata *dd = dd_from_ibdev(qp->ibqp.device);
1380 u32 plen;
1381 int ret;
1382 u32 dwords = (len + 3) >> 2;
1383
1384 /*
1385 * Calculate the send buffer trigger address.
1386 * The +1 counts for the pbc control dword following the pbc length.
1387 */
1388 plen = hdrwords + dwords + 1;
1389
1390 /*
1391 * VL15 packets (IB_QPT_SMI) will always use PIO, so we
1392 * can defer SDMA restart until link goes ACTIVE without
1393 * worrying about just how we got there.
1394 */
1395 if (qp->ibqp.qp_type == IB_QPT_SMI ||
1396 !(dd->flags & QIB_HAS_SEND_DMA))
1397 ret = qib_verbs_send_pio(qp, hdr, hdrwords, ss, len,
1398 plen, dwords);
1399 else
1400 ret = qib_verbs_send_dma(qp, hdr, hdrwords, ss, len,
1401 plen, dwords);
1402
1403 return ret;
1404 }
1405
1406 int qib_snapshot_counters(struct qib_pportdata *ppd, u64 *swords,
1407 u64 *rwords, u64 *spkts, u64 *rpkts,
1408 u64 *xmit_wait)
1409 {
1410 int ret;
1411 struct qib_devdata *dd = ppd->dd;
1412
1413 if (!(dd->flags & QIB_PRESENT)) {
1414 /* no hardware, freeze, etc. */
1415 ret = -EINVAL;
1416 goto bail;
1417 }
1418 *swords = dd->f_portcntr(ppd, QIBPORTCNTR_WORDSEND);
1419 *rwords = dd->f_portcntr(ppd, QIBPORTCNTR_WORDRCV);
1420 *spkts = dd->f_portcntr(ppd, QIBPORTCNTR_PKTSEND);
1421 *rpkts = dd->f_portcntr(ppd, QIBPORTCNTR_PKTRCV);
1422 *xmit_wait = dd->f_portcntr(ppd, QIBPORTCNTR_SENDSTALL);
1423
1424 ret = 0;
1425
1426 bail:
1427 return ret;
1428 }
1429
1430 /**
1431 * qib_get_counters - get various chip counters
1432 * @dd: the qlogic_ib device
1433 * @cntrs: counters are placed here
1434 *
1435 * Return the counters needed by recv_pma_get_portcounters().
1436 */
1437 int qib_get_counters(struct qib_pportdata *ppd,
1438 struct qib_verbs_counters *cntrs)
1439 {
1440 int ret;
1441
1442 if (!(ppd->dd->flags & QIB_PRESENT)) {
1443 /* no hardware, freeze, etc. */
1444 ret = -EINVAL;
1445 goto bail;
1446 }
1447 cntrs->symbol_error_counter =
1448 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_IBSYMBOLERR);
1449 cntrs->link_error_recovery_counter =
1450 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_IBLINKERRRECOV);
1451 /*
1452 * The link downed counter counts when the other side downs the
1453 * connection. We add in the number of times we downed the link
1454 * due to local link integrity errors to compensate.
1455 */
1456 cntrs->link_downed_counter =
1457 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_IBLINKDOWN);
1458 cntrs->port_rcv_errors =
1459 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_RXDROPPKT) +
1460 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_RCVOVFL) +
1461 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_ERR_RLEN) +
1462 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_INVALIDRLEN) +
1463 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_ERRLINK) +
1464 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_ERRICRC) +
1465 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_ERRVCRC) +
1466 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_ERRLPCRC) +
1467 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_BADFORMAT);
1468 cntrs->port_rcv_errors +=
1469 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_RXLOCALPHYERR);
1470 cntrs->port_rcv_errors +=
1471 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_RXVLERR);
1472 cntrs->port_rcv_remphys_errors =
1473 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_RCVEBP);
1474 cntrs->port_xmit_discards =
1475 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_UNSUPVL);
1476 cntrs->port_xmit_data = ppd->dd->f_portcntr(ppd,
1477 QIBPORTCNTR_WORDSEND);
1478 cntrs->port_rcv_data = ppd->dd->f_portcntr(ppd,
1479 QIBPORTCNTR_WORDRCV);
1480 cntrs->port_xmit_packets = ppd->dd->f_portcntr(ppd,
1481 QIBPORTCNTR_PKTSEND);
1482 cntrs->port_rcv_packets = ppd->dd->f_portcntr(ppd,
1483 QIBPORTCNTR_PKTRCV);
1484 cntrs->local_link_integrity_errors =
1485 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_LLI);
1486 cntrs->excessive_buffer_overrun_errors =
1487 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_EXCESSBUFOVFL);
1488 cntrs->vl15_dropped =
1489 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_VL15PKTDROP);
1490
1491 ret = 0;
1492
1493 bail:
1494 return ret;
1495 }
1496
1497 /**
1498 * qib_ib_piobufavail - callback when a PIO buffer is available
1499 * @dd: the device pointer
1500 *
1501 * This is called from qib_intr() at interrupt level when a PIO buffer is
1502 * available after qib_verbs_send() returned an error that no buffers were
1503 * available. Disable the interrupt if there are no more QPs waiting.
1504 */
1505 void qib_ib_piobufavail(struct qib_devdata *dd)
1506 {
1507 struct qib_ibdev *dev = &dd->verbs_dev;
1508 struct list_head *list;
1509 struct qib_qp *qps[5];
1510 struct qib_qp *qp;
1511 unsigned long flags;
1512 unsigned i, n;
1513
1514 list = &dev->piowait;
1515 n = 0;
1516
1517 /*
1518 * Note: checking that the piowait list is empty and clearing
1519 * the buffer available interrupt needs to be atomic or we
1520 * could end up with QPs on the wait list with the interrupt
1521 * disabled.
1522 */
1523 spin_lock_irqsave(&dev->pending_lock, flags);
1524 while (!list_empty(list)) {
1525 if (n == ARRAY_SIZE(qps))
1526 goto full;
1527 qp = list_entry(list->next, struct qib_qp, iowait);
1528 list_del_init(&qp->iowait);
1529 atomic_inc(&qp->refcount);
1530 qps[n++] = qp;
1531 }
1532 dd->f_wantpiobuf_intr(dd, 0);
1533 full:
1534 spin_unlock_irqrestore(&dev->pending_lock, flags);
1535
1536 for (i = 0; i < n; i++) {
1537 qp = qps[i];
1538
1539 spin_lock_irqsave(&qp->s_lock, flags);
1540 if (qp->s_flags & QIB_S_WAIT_PIO) {
1541 qp->s_flags &= ~QIB_S_WAIT_PIO;
1542 qib_schedule_send(qp);
1543 }
1544 spin_unlock_irqrestore(&qp->s_lock, flags);
1545
1546 /* Notify qib_destroy_qp() if it is waiting. */
1547 if (atomic_dec_and_test(&qp->refcount))
1548 wake_up(&qp->wait);
1549 }
1550 }
1551
1552 static int qib_query_device(struct ib_device *ibdev,
1553 struct ib_device_attr *props)
1554 {
1555 struct qib_devdata *dd = dd_from_ibdev(ibdev);
1556 struct qib_ibdev *dev = to_idev(ibdev);
1557
1558 memset(props, 0, sizeof(*props));
1559
1560 props->device_cap_flags = IB_DEVICE_BAD_PKEY_CNTR |
1561 IB_DEVICE_BAD_QKEY_CNTR | IB_DEVICE_SHUTDOWN_PORT |
1562 IB_DEVICE_SYS_IMAGE_GUID | IB_DEVICE_RC_RNR_NAK_GEN |
1563 IB_DEVICE_PORT_ACTIVE_EVENT | IB_DEVICE_SRQ_RESIZE;
1564 props->page_size_cap = PAGE_SIZE;
1565 props->vendor_id =
1566 QIB_SRC_OUI_1 << 16 | QIB_SRC_OUI_2 << 8 | QIB_SRC_OUI_3;
1567 props->vendor_part_id = dd->deviceid;
1568 props->hw_ver = dd->minrev;
1569 props->sys_image_guid = ib_qib_sys_image_guid;
1570 props->max_mr_size = ~0ULL;
1571 props->max_qp = ib_qib_max_qps;
1572 props->max_qp_wr = ib_qib_max_qp_wrs;
1573 props->max_sge = ib_qib_max_sges;
1574 props->max_cq = ib_qib_max_cqs;
1575 props->max_ah = ib_qib_max_ahs;
1576 props->max_cqe = ib_qib_max_cqes;
1577 props->max_mr = dev->lk_table.max;
1578 props->max_fmr = dev->lk_table.max;
1579 props->max_map_per_fmr = 32767;
1580 props->max_pd = ib_qib_max_pds;
1581 props->max_qp_rd_atom = QIB_MAX_RDMA_ATOMIC;
1582 props->max_qp_init_rd_atom = 255;
1583 /* props->max_res_rd_atom */
1584 props->max_srq = ib_qib_max_srqs;
1585 props->max_srq_wr = ib_qib_max_srq_wrs;
1586 props->max_srq_sge = ib_qib_max_srq_sges;
1587 /* props->local_ca_ack_delay */
1588 props->atomic_cap = IB_ATOMIC_GLOB;
1589 props->max_pkeys = qib_get_npkeys(dd);
1590 props->max_mcast_grp = ib_qib_max_mcast_grps;
1591 props->max_mcast_qp_attach = ib_qib_max_mcast_qp_attached;
1592 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
1593 props->max_mcast_grp;
1594
1595 return 0;
1596 }
1597
1598 static int qib_query_port(struct ib_device *ibdev, u8 port,
1599 struct ib_port_attr *props)
1600 {
1601 struct qib_devdata *dd = dd_from_ibdev(ibdev);
1602 struct qib_ibport *ibp = to_iport(ibdev, port);
1603 struct qib_pportdata *ppd = ppd_from_ibp(ibp);
1604 enum ib_mtu mtu;
1605 u16 lid = ppd->lid;
1606
1607 memset(props, 0, sizeof(*props));
1608 props->lid = lid ? lid : be16_to_cpu(IB_LID_PERMISSIVE);
1609 props->lmc = ppd->lmc;
1610 props->sm_lid = ibp->sm_lid;
1611 props->sm_sl = ibp->sm_sl;
1612 props->state = dd->f_iblink_state(ppd->lastibcstat);
1613 props->phys_state = dd->f_ibphys_portstate(ppd->lastibcstat);
1614 props->port_cap_flags = ibp->port_cap_flags;
1615 props->gid_tbl_len = QIB_GUIDS_PER_PORT;
1616 props->max_msg_sz = 0x80000000;
1617 props->pkey_tbl_len = qib_get_npkeys(dd);
1618 props->bad_pkey_cntr = ibp->pkey_violations;
1619 props->qkey_viol_cntr = ibp->qkey_violations;
1620 props->active_width = ppd->link_width_active;
1621 /* See rate_show() */
1622 props->active_speed = ppd->link_speed_active;
1623 props->max_vl_num = qib_num_vls(ppd->vls_supported);
1624 props->init_type_reply = 0;
1625
1626 props->max_mtu = qib_ibmtu ? qib_ibmtu : IB_MTU_4096;
1627 switch (ppd->ibmtu) {
1628 case 4096:
1629 mtu = IB_MTU_4096;
1630 break;
1631 case 2048:
1632 mtu = IB_MTU_2048;
1633 break;
1634 case 1024:
1635 mtu = IB_MTU_1024;
1636 break;
1637 case 512:
1638 mtu = IB_MTU_512;
1639 break;
1640 case 256:
1641 mtu = IB_MTU_256;
1642 break;
1643 default:
1644 mtu = IB_MTU_2048;
1645 }
1646 props->active_mtu = mtu;
1647 props->subnet_timeout = ibp->subnet_timeout;
1648
1649 return 0;
1650 }
1651
1652 static int qib_modify_device(struct ib_device *device,
1653 int device_modify_mask,
1654 struct ib_device_modify *device_modify)
1655 {
1656 struct qib_devdata *dd = dd_from_ibdev(device);
1657 unsigned i;
1658 int ret;
1659
1660 if (device_modify_mask & ~(IB_DEVICE_MODIFY_SYS_IMAGE_GUID |
1661 IB_DEVICE_MODIFY_NODE_DESC)) {
1662 ret = -EOPNOTSUPP;
1663 goto bail;
1664 }
1665
1666 if (device_modify_mask & IB_DEVICE_MODIFY_NODE_DESC) {
1667 memcpy(device->node_desc, device_modify->node_desc, 64);
1668 for (i = 0; i < dd->num_pports; i++) {
1669 struct qib_ibport *ibp = &dd->pport[i].ibport_data;
1670
1671 qib_node_desc_chg(ibp);
1672 }
1673 }
1674
1675 if (device_modify_mask & IB_DEVICE_MODIFY_SYS_IMAGE_GUID) {
1676 ib_qib_sys_image_guid =
1677 cpu_to_be64(device_modify->sys_image_guid);
1678 for (i = 0; i < dd->num_pports; i++) {
1679 struct qib_ibport *ibp = &dd->pport[i].ibport_data;
1680
1681 qib_sys_guid_chg(ibp);
1682 }
1683 }
1684
1685 ret = 0;
1686
1687 bail:
1688 return ret;
1689 }
1690
1691 static int qib_modify_port(struct ib_device *ibdev, u8 port,
1692 int port_modify_mask, struct ib_port_modify *props)
1693 {
1694 struct qib_ibport *ibp = to_iport(ibdev, port);
1695 struct qib_pportdata *ppd = ppd_from_ibp(ibp);
1696
1697 ibp->port_cap_flags |= props->set_port_cap_mask;
1698 ibp->port_cap_flags &= ~props->clr_port_cap_mask;
1699 if (props->set_port_cap_mask || props->clr_port_cap_mask)
1700 qib_cap_mask_chg(ibp);
1701 if (port_modify_mask & IB_PORT_SHUTDOWN)
1702 qib_set_linkstate(ppd, QIB_IB_LINKDOWN);
1703 if (port_modify_mask & IB_PORT_RESET_QKEY_CNTR)
1704 ibp->qkey_violations = 0;
1705 return 0;
1706 }
1707
1708 static int qib_query_gid(struct ib_device *ibdev, u8 port,
1709 int index, union ib_gid *gid)
1710 {
1711 struct qib_devdata *dd = dd_from_ibdev(ibdev);
1712 int ret = 0;
1713
1714 if (!port || port > dd->num_pports)
1715 ret = -EINVAL;
1716 else {
1717 struct qib_ibport *ibp = to_iport(ibdev, port);
1718 struct qib_pportdata *ppd = ppd_from_ibp(ibp);
1719
1720 gid->global.subnet_prefix = ibp->gid_prefix;
1721 if (index == 0)
1722 gid->global.interface_id = ppd->guid;
1723 else if (index < QIB_GUIDS_PER_PORT)
1724 gid->global.interface_id = ibp->guids[index - 1];
1725 else
1726 ret = -EINVAL;
1727 }
1728
1729 return ret;
1730 }
1731
1732 static struct ib_pd *qib_alloc_pd(struct ib_device *ibdev,
1733 struct ib_ucontext *context,
1734 struct ib_udata *udata)
1735 {
1736 struct qib_ibdev *dev = to_idev(ibdev);
1737 struct qib_pd *pd;
1738 struct ib_pd *ret;
1739
1740 /*
1741 * This is actually totally arbitrary. Some correctness tests
1742 * assume there's a maximum number of PDs that can be allocated.
1743 * We don't actually have this limit, but we fail the test if
1744 * we allow allocations of more than we report for this value.
1745 */
1746
1747 pd = kmalloc(sizeof *pd, GFP_KERNEL);
1748 if (!pd) {
1749 ret = ERR_PTR(-ENOMEM);
1750 goto bail;
1751 }
1752
1753 spin_lock(&dev->n_pds_lock);
1754 if (dev->n_pds_allocated == ib_qib_max_pds) {
1755 spin_unlock(&dev->n_pds_lock);
1756 kfree(pd);
1757 ret = ERR_PTR(-ENOMEM);
1758 goto bail;
1759 }
1760
1761 dev->n_pds_allocated++;
1762 spin_unlock(&dev->n_pds_lock);
1763
1764 /* ib_alloc_pd() will initialize pd->ibpd. */
1765 pd->user = udata != NULL;
1766
1767 ret = &pd->ibpd;
1768
1769 bail:
1770 return ret;
1771 }
1772
1773 static int qib_dealloc_pd(struct ib_pd *ibpd)
1774 {
1775 struct qib_pd *pd = to_ipd(ibpd);
1776 struct qib_ibdev *dev = to_idev(ibpd->device);
1777
1778 spin_lock(&dev->n_pds_lock);
1779 dev->n_pds_allocated--;
1780 spin_unlock(&dev->n_pds_lock);
1781
1782 kfree(pd);
1783
1784 return 0;
1785 }
1786
1787 int qib_check_ah(struct ib_device *ibdev, struct ib_ah_attr *ah_attr)
1788 {
1789 /* A multicast address requires a GRH (see ch. 8.4.1). */
1790 if (ah_attr->dlid >= QIB_MULTICAST_LID_BASE &&
1791 ah_attr->dlid != QIB_PERMISSIVE_LID &&
1792 !(ah_attr->ah_flags & IB_AH_GRH))
1793 goto bail;
1794 if ((ah_attr->ah_flags & IB_AH_GRH) &&
1795 ah_attr->grh.sgid_index >= QIB_GUIDS_PER_PORT)
1796 goto bail;
1797 if (ah_attr->dlid == 0)
1798 goto bail;
1799 if (ah_attr->port_num < 1 ||
1800 ah_attr->port_num > ibdev->phys_port_cnt)
1801 goto bail;
1802 if (ah_attr->static_rate != IB_RATE_PORT_CURRENT &&
1803 ib_rate_to_mult(ah_attr->static_rate) < 0)
1804 goto bail;
1805 if (ah_attr->sl > 15)
1806 goto bail;
1807 return 0;
1808 bail:
1809 return -EINVAL;
1810 }
1811
1812 /**
1813 * qib_create_ah - create an address handle
1814 * @pd: the protection domain
1815 * @ah_attr: the attributes of the AH
1816 *
1817 * This may be called from interrupt context.
1818 */
1819 static struct ib_ah *qib_create_ah(struct ib_pd *pd,
1820 struct ib_ah_attr *ah_attr)
1821 {
1822 struct qib_ah *ah;
1823 struct ib_ah *ret;
1824 struct qib_ibdev *dev = to_idev(pd->device);
1825 unsigned long flags;
1826
1827 if (qib_check_ah(pd->device, ah_attr)) {
1828 ret = ERR_PTR(-EINVAL);
1829 goto bail;
1830 }
1831
1832 ah = kmalloc(sizeof *ah, GFP_ATOMIC);
1833 if (!ah) {
1834 ret = ERR_PTR(-ENOMEM);
1835 goto bail;
1836 }
1837
1838 spin_lock_irqsave(&dev->n_ahs_lock, flags);
1839 if (dev->n_ahs_allocated == ib_qib_max_ahs) {
1840 spin_unlock_irqrestore(&dev->n_ahs_lock, flags);
1841 kfree(ah);
1842 ret = ERR_PTR(-ENOMEM);
1843 goto bail;
1844 }
1845
1846 dev->n_ahs_allocated++;
1847 spin_unlock_irqrestore(&dev->n_ahs_lock, flags);
1848
1849 /* ib_create_ah() will initialize ah->ibah. */
1850 ah->attr = *ah_attr;
1851 atomic_set(&ah->refcount, 0);
1852
1853 ret = &ah->ibah;
1854
1855 bail:
1856 return ret;
1857 }
1858
1859 struct ib_ah *qib_create_qp0_ah(struct qib_ibport *ibp, u16 dlid)
1860 {
1861 struct ib_ah_attr attr;
1862 struct ib_ah *ah = ERR_PTR(-EINVAL);
1863 struct qib_qp *qp0;
1864
1865 memset(&attr, 0, sizeof attr);
1866 attr.dlid = dlid;
1867 attr.port_num = ppd_from_ibp(ibp)->port;
1868 rcu_read_lock();
1869 qp0 = rcu_dereference(ibp->qp0);
1870 if (qp0)
1871 ah = ib_create_ah(qp0->ibqp.pd, &attr);
1872 rcu_read_unlock();
1873 return ah;
1874 }
1875
1876 /**
1877 * qib_destroy_ah - destroy an address handle
1878 * @ibah: the AH to destroy
1879 *
1880 * This may be called from interrupt context.
1881 */
1882 static int qib_destroy_ah(struct ib_ah *ibah)
1883 {
1884 struct qib_ibdev *dev = to_idev(ibah->device);
1885 struct qib_ah *ah = to_iah(ibah);
1886 unsigned long flags;
1887
1888 if (atomic_read(&ah->refcount) != 0)
1889 return -EBUSY;
1890
1891 spin_lock_irqsave(&dev->n_ahs_lock, flags);
1892 dev->n_ahs_allocated--;
1893 spin_unlock_irqrestore(&dev->n_ahs_lock, flags);
1894
1895 kfree(ah);
1896
1897 return 0;
1898 }
1899
1900 static int qib_modify_ah(struct ib_ah *ibah, struct ib_ah_attr *ah_attr)
1901 {
1902 struct qib_ah *ah = to_iah(ibah);
1903
1904 if (qib_check_ah(ibah->device, ah_attr))
1905 return -EINVAL;
1906
1907 ah->attr = *ah_attr;
1908
1909 return 0;
1910 }
1911
1912 static int qib_query_ah(struct ib_ah *ibah, struct ib_ah_attr *ah_attr)
1913 {
1914 struct qib_ah *ah = to_iah(ibah);
1915
1916 *ah_attr = ah->attr;
1917
1918 return 0;
1919 }
1920
1921 /**
1922 * qib_get_npkeys - return the size of the PKEY table for context 0
1923 * @dd: the qlogic_ib device
1924 */
1925 unsigned qib_get_npkeys(struct qib_devdata *dd)
1926 {
1927 return ARRAY_SIZE(dd->rcd[0]->pkeys);
1928 }
1929
1930 /*
1931 * Return the indexed PKEY from the port PKEY table.
1932 * No need to validate rcd[ctxt]; the port is setup if we are here.
1933 */
1934 unsigned qib_get_pkey(struct qib_ibport *ibp, unsigned index)
1935 {
1936 struct qib_pportdata *ppd = ppd_from_ibp(ibp);
1937 struct qib_devdata *dd = ppd->dd;
1938 unsigned ctxt = ppd->hw_pidx;
1939 unsigned ret;
1940
1941 /* dd->rcd null if mini_init or some init failures */
1942 if (!dd->rcd || index >= ARRAY_SIZE(dd->rcd[ctxt]->pkeys))
1943 ret = 0;
1944 else
1945 ret = dd->rcd[ctxt]->pkeys[index];
1946
1947 return ret;
1948 }
1949
1950 static int qib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1951 u16 *pkey)
1952 {
1953 struct qib_devdata *dd = dd_from_ibdev(ibdev);
1954 int ret;
1955
1956 if (index >= qib_get_npkeys(dd)) {
1957 ret = -EINVAL;
1958 goto bail;
1959 }
1960
1961 *pkey = qib_get_pkey(to_iport(ibdev, port), index);
1962 ret = 0;
1963
1964 bail:
1965 return ret;
1966 }
1967
1968 /**
1969 * qib_alloc_ucontext - allocate a ucontest
1970 * @ibdev: the infiniband device
1971 * @udata: not used by the QLogic_IB driver
1972 */
1973
1974 static struct ib_ucontext *qib_alloc_ucontext(struct ib_device *ibdev,
1975 struct ib_udata *udata)
1976 {
1977 struct qib_ucontext *context;
1978 struct ib_ucontext *ret;
1979
1980 context = kmalloc(sizeof *context, GFP_KERNEL);
1981 if (!context) {
1982 ret = ERR_PTR(-ENOMEM);
1983 goto bail;
1984 }
1985
1986 ret = &context->ibucontext;
1987
1988 bail:
1989 return ret;
1990 }
1991
1992 static int qib_dealloc_ucontext(struct ib_ucontext *context)
1993 {
1994 kfree(to_iucontext(context));
1995 return 0;
1996 }
1997
1998 static void init_ibport(struct qib_pportdata *ppd)
1999 {
2000 struct qib_verbs_counters cntrs;
2001 struct qib_ibport *ibp = &ppd->ibport_data;
2002
2003 spin_lock_init(&ibp->lock);
2004 /* Set the prefix to the default value (see ch. 4.1.1) */
2005 ibp->gid_prefix = IB_DEFAULT_GID_PREFIX;
2006 ibp->sm_lid = be16_to_cpu(IB_LID_PERMISSIVE);
2007 ibp->port_cap_flags = IB_PORT_SYS_IMAGE_GUID_SUP |
2008 IB_PORT_CLIENT_REG_SUP | IB_PORT_SL_MAP_SUP |
2009 IB_PORT_TRAP_SUP | IB_PORT_AUTO_MIGR_SUP |
2010 IB_PORT_DR_NOTICE_SUP | IB_PORT_CAP_MASK_NOTICE_SUP |
2011 IB_PORT_OTHER_LOCAL_CHANGES_SUP;
2012 if (ppd->dd->flags & QIB_HAS_LINK_LATENCY)
2013 ibp->port_cap_flags |= IB_PORT_LINK_LATENCY_SUP;
2014 ibp->pma_counter_select[0] = IB_PMA_PORT_XMIT_DATA;
2015 ibp->pma_counter_select[1] = IB_PMA_PORT_RCV_DATA;
2016 ibp->pma_counter_select[2] = IB_PMA_PORT_XMIT_PKTS;
2017 ibp->pma_counter_select[3] = IB_PMA_PORT_RCV_PKTS;
2018 ibp->pma_counter_select[4] = IB_PMA_PORT_XMIT_WAIT;
2019
2020 /* Snapshot current HW counters to "clear" them. */
2021 qib_get_counters(ppd, &cntrs);
2022 ibp->z_symbol_error_counter = cntrs.symbol_error_counter;
2023 ibp->z_link_error_recovery_counter =
2024 cntrs.link_error_recovery_counter;
2025 ibp->z_link_downed_counter = cntrs.link_downed_counter;
2026 ibp->z_port_rcv_errors = cntrs.port_rcv_errors;
2027 ibp->z_port_rcv_remphys_errors = cntrs.port_rcv_remphys_errors;
2028 ibp->z_port_xmit_discards = cntrs.port_xmit_discards;
2029 ibp->z_port_xmit_data = cntrs.port_xmit_data;
2030 ibp->z_port_rcv_data = cntrs.port_rcv_data;
2031 ibp->z_port_xmit_packets = cntrs.port_xmit_packets;
2032 ibp->z_port_rcv_packets = cntrs.port_rcv_packets;
2033 ibp->z_local_link_integrity_errors =
2034 cntrs.local_link_integrity_errors;
2035 ibp->z_excessive_buffer_overrun_errors =
2036 cntrs.excessive_buffer_overrun_errors;
2037 ibp->z_vl15_dropped = cntrs.vl15_dropped;
2038 RCU_INIT_POINTER(ibp->qp0, NULL);
2039 RCU_INIT_POINTER(ibp->qp1, NULL);
2040 }
2041
2042 /**
2043 * qib_register_ib_device - register our device with the infiniband core
2044 * @dd: the device data structure
2045 * Return the allocated qib_ibdev pointer or NULL on error.
2046 */
2047 int qib_register_ib_device(struct qib_devdata *dd)
2048 {
2049 struct qib_ibdev *dev = &dd->verbs_dev;
2050 struct ib_device *ibdev = &dev->ibdev;
2051 struct qib_pportdata *ppd = dd->pport;
2052 unsigned i, lk_tab_size;
2053 int ret;
2054
2055 dev->qp_table_size = ib_qib_qp_table_size;
2056 get_random_bytes(&dev->qp_rnd, sizeof(dev->qp_rnd));
2057 dev->qp_table = kmalloc(dev->qp_table_size * sizeof *dev->qp_table,
2058 GFP_KERNEL);
2059 if (!dev->qp_table) {
2060 ret = -ENOMEM;
2061 goto err_qpt;
2062 }
2063 for (i = 0; i < dev->qp_table_size; i++)
2064 RCU_INIT_POINTER(dev->qp_table[i], NULL);
2065
2066 for (i = 0; i < dd->num_pports; i++)
2067 init_ibport(ppd + i);
2068
2069 /* Only need to initialize non-zero fields. */
2070 spin_lock_init(&dev->qpt_lock);
2071 spin_lock_init(&dev->n_pds_lock);
2072 spin_lock_init(&dev->n_ahs_lock);
2073 spin_lock_init(&dev->n_cqs_lock);
2074 spin_lock_init(&dev->n_qps_lock);
2075 spin_lock_init(&dev->n_srqs_lock);
2076 spin_lock_init(&dev->n_mcast_grps_lock);
2077 init_timer(&dev->mem_timer);
2078 dev->mem_timer.function = mem_timer;
2079 dev->mem_timer.data = (unsigned long) dev;
2080
2081 qib_init_qpn_table(dd, &dev->qpn_table);
2082
2083 /*
2084 * The top ib_qib_lkey_table_size bits are used to index the
2085 * table. The lower 8 bits can be owned by the user (copied from
2086 * the LKEY). The remaining bits act as a generation number or tag.
2087 */
2088 spin_lock_init(&dev->lk_table.lock);
2089 dev->lk_table.max = 1 << ib_qib_lkey_table_size;
2090 lk_tab_size = dev->lk_table.max * sizeof(*dev->lk_table.table);
2091 dev->lk_table.table = (struct qib_mregion __rcu **)
2092 __get_free_pages(GFP_KERNEL, get_order(lk_tab_size));
2093 if (dev->lk_table.table == NULL) {
2094 ret = -ENOMEM;
2095 goto err_lk;
2096 }
2097 RCU_INIT_POINTER(dev->dma_mr, NULL);
2098 for (i = 0; i < dev->lk_table.max; i++)
2099 RCU_INIT_POINTER(dev->lk_table.table[i], NULL);
2100 INIT_LIST_HEAD(&dev->pending_mmaps);
2101 spin_lock_init(&dev->pending_lock);
2102 dev->mmap_offset = PAGE_SIZE;
2103 spin_lock_init(&dev->mmap_offset_lock);
2104 INIT_LIST_HEAD(&dev->piowait);
2105 INIT_LIST_HEAD(&dev->dmawait);
2106 INIT_LIST_HEAD(&dev->txwait);
2107 INIT_LIST_HEAD(&dev->memwait);
2108 INIT_LIST_HEAD(&dev->txreq_free);
2109
2110 if (ppd->sdma_descq_cnt) {
2111 dev->pio_hdrs = dma_alloc_coherent(&dd->pcidev->dev,
2112 ppd->sdma_descq_cnt *
2113 sizeof(struct qib_pio_header),
2114 &dev->pio_hdrs_phys,
2115 GFP_KERNEL);
2116 if (!dev->pio_hdrs) {
2117 ret = -ENOMEM;
2118 goto err_hdrs;
2119 }
2120 }
2121
2122 for (i = 0; i < ppd->sdma_descq_cnt; i++) {
2123 struct qib_verbs_txreq *tx;
2124
2125 tx = kzalloc(sizeof *tx, GFP_KERNEL);
2126 if (!tx) {
2127 ret = -ENOMEM;
2128 goto err_tx;
2129 }
2130 tx->hdr_inx = i;
2131 list_add(&tx->txreq.list, &dev->txreq_free);
2132 }
2133
2134 /*
2135 * The system image GUID is supposed to be the same for all
2136 * IB HCAs in a single system but since there can be other
2137 * device types in the system, we can't be sure this is unique.
2138 */
2139 if (!ib_qib_sys_image_guid)
2140 ib_qib_sys_image_guid = ppd->guid;
2141
2142 strlcpy(ibdev->name, "qib%d", IB_DEVICE_NAME_MAX);
2143 ibdev->owner = THIS_MODULE;
2144 ibdev->node_guid = ppd->guid;
2145 ibdev->uverbs_abi_ver = QIB_UVERBS_ABI_VERSION;
2146 ibdev->uverbs_cmd_mask =
2147 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
2148 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
2149 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
2150 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
2151 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
2152 (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
2153 (1ull << IB_USER_VERBS_CMD_MODIFY_AH) |
2154 (1ull << IB_USER_VERBS_CMD_QUERY_AH) |
2155 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
2156 (1ull << IB_USER_VERBS_CMD_REG_MR) |
2157 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
2158 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
2159 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
2160 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
2161 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
2162 (1ull << IB_USER_VERBS_CMD_POLL_CQ) |
2163 (1ull << IB_USER_VERBS_CMD_REQ_NOTIFY_CQ) |
2164 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
2165 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
2166 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
2167 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
2168 (1ull << IB_USER_VERBS_CMD_POST_SEND) |
2169 (1ull << IB_USER_VERBS_CMD_POST_RECV) |
2170 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
2171 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
2172 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
2173 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
2174 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
2175 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
2176 (1ull << IB_USER_VERBS_CMD_POST_SRQ_RECV);
2177 ibdev->node_type = RDMA_NODE_IB_CA;
2178 ibdev->phys_port_cnt = dd->num_pports;
2179 ibdev->num_comp_vectors = 1;
2180 ibdev->dma_device = &dd->pcidev->dev;
2181 ibdev->query_device = qib_query_device;
2182 ibdev->modify_device = qib_modify_device;
2183 ibdev->query_port = qib_query_port;
2184 ibdev->modify_port = qib_modify_port;
2185 ibdev->query_pkey = qib_query_pkey;
2186 ibdev->query_gid = qib_query_gid;
2187 ibdev->alloc_ucontext = qib_alloc_ucontext;
2188 ibdev->dealloc_ucontext = qib_dealloc_ucontext;
2189 ibdev->alloc_pd = qib_alloc_pd;
2190 ibdev->dealloc_pd = qib_dealloc_pd;
2191 ibdev->create_ah = qib_create_ah;
2192 ibdev->destroy_ah = qib_destroy_ah;
2193 ibdev->modify_ah = qib_modify_ah;
2194 ibdev->query_ah = qib_query_ah;
2195 ibdev->create_srq = qib_create_srq;
2196 ibdev->modify_srq = qib_modify_srq;
2197 ibdev->query_srq = qib_query_srq;
2198 ibdev->destroy_srq = qib_destroy_srq;
2199 ibdev->create_qp = qib_create_qp;
2200 ibdev->modify_qp = qib_modify_qp;
2201 ibdev->query_qp = qib_query_qp;
2202 ibdev->destroy_qp = qib_destroy_qp;
2203 ibdev->post_send = qib_post_send;
2204 ibdev->post_recv = qib_post_receive;
2205 ibdev->post_srq_recv = qib_post_srq_receive;
2206 ibdev->create_cq = qib_create_cq;
2207 ibdev->destroy_cq = qib_destroy_cq;
2208 ibdev->resize_cq = qib_resize_cq;
2209 ibdev->poll_cq = qib_poll_cq;
2210 ibdev->req_notify_cq = qib_req_notify_cq;
2211 ibdev->get_dma_mr = qib_get_dma_mr;
2212 ibdev->reg_phys_mr = qib_reg_phys_mr;
2213 ibdev->reg_user_mr = qib_reg_user_mr;
2214 ibdev->dereg_mr = qib_dereg_mr;
2215 ibdev->alloc_fast_reg_mr = qib_alloc_fast_reg_mr;
2216 ibdev->alloc_fast_reg_page_list = qib_alloc_fast_reg_page_list;
2217 ibdev->free_fast_reg_page_list = qib_free_fast_reg_page_list;
2218 ibdev->alloc_fmr = qib_alloc_fmr;
2219 ibdev->map_phys_fmr = qib_map_phys_fmr;
2220 ibdev->unmap_fmr = qib_unmap_fmr;
2221 ibdev->dealloc_fmr = qib_dealloc_fmr;
2222 ibdev->attach_mcast = qib_multicast_attach;
2223 ibdev->detach_mcast = qib_multicast_detach;
2224 ibdev->process_mad = qib_process_mad;
2225 ibdev->mmap = qib_mmap;
2226 ibdev->dma_ops = &qib_dma_mapping_ops;
2227
2228 snprintf(ibdev->node_desc, sizeof(ibdev->node_desc),
2229 "Intel Infiniband HCA %s", init_utsname()->nodename);
2230
2231 ret = ib_register_device(ibdev, qib_create_port_files);
2232 if (ret)
2233 goto err_reg;
2234
2235 ret = qib_create_agents(dev);
2236 if (ret)
2237 goto err_agents;
2238
2239 ret = qib_verbs_register_sysfs(dd);
2240 if (ret)
2241 goto err_class;
2242
2243 goto bail;
2244
2245 err_class:
2246 qib_free_agents(dev);
2247 err_agents:
2248 ib_unregister_device(ibdev);
2249 err_reg:
2250 err_tx:
2251 while (!list_empty(&dev->txreq_free)) {
2252 struct list_head *l = dev->txreq_free.next;
2253 struct qib_verbs_txreq *tx;
2254
2255 list_del(l);
2256 tx = list_entry(l, struct qib_verbs_txreq, txreq.list);
2257 kfree(tx);
2258 }
2259 if (ppd->sdma_descq_cnt)
2260 dma_free_coherent(&dd->pcidev->dev,
2261 ppd->sdma_descq_cnt *
2262 sizeof(struct qib_pio_header),
2263 dev->pio_hdrs, dev->pio_hdrs_phys);
2264 err_hdrs:
2265 free_pages((unsigned long) dev->lk_table.table, get_order(lk_tab_size));
2266 err_lk:
2267 kfree(dev->qp_table);
2268 err_qpt:
2269 qib_dev_err(dd, "cannot register verbs: %d!\n", -ret);
2270 bail:
2271 return ret;
2272 }
2273
2274 void qib_unregister_ib_device(struct qib_devdata *dd)
2275 {
2276 struct qib_ibdev *dev = &dd->verbs_dev;
2277 struct ib_device *ibdev = &dev->ibdev;
2278 u32 qps_inuse;
2279 unsigned lk_tab_size;
2280
2281 qib_verbs_unregister_sysfs(dd);
2282
2283 qib_free_agents(dev);
2284
2285 ib_unregister_device(ibdev);
2286
2287 if (!list_empty(&dev->piowait))
2288 qib_dev_err(dd, "piowait list not empty!\n");
2289 if (!list_empty(&dev->dmawait))
2290 qib_dev_err(dd, "dmawait list not empty!\n");
2291 if (!list_empty(&dev->txwait))
2292 qib_dev_err(dd, "txwait list not empty!\n");
2293 if (!list_empty(&dev->memwait))
2294 qib_dev_err(dd, "memwait list not empty!\n");
2295 if (dev->dma_mr)
2296 qib_dev_err(dd, "DMA MR not NULL!\n");
2297
2298 qps_inuse = qib_free_all_qps(dd);
2299 if (qps_inuse)
2300 qib_dev_err(dd, "QP memory leak! %u still in use\n",
2301 qps_inuse);
2302
2303 del_timer_sync(&dev->mem_timer);
2304 qib_free_qpn_table(&dev->qpn_table);
2305 while (!list_empty(&dev->txreq_free)) {
2306 struct list_head *l = dev->txreq_free.next;
2307 struct qib_verbs_txreq *tx;
2308
2309 list_del(l);
2310 tx = list_entry(l, struct qib_verbs_txreq, txreq.list);
2311 kfree(tx);
2312 }
2313 if (dd->pport->sdma_descq_cnt)
2314 dma_free_coherent(&dd->pcidev->dev,
2315 dd->pport->sdma_descq_cnt *
2316 sizeof(struct qib_pio_header),
2317 dev->pio_hdrs, dev->pio_hdrs_phys);
2318 lk_tab_size = dev->lk_table.max * sizeof(*dev->lk_table.table);
2319 free_pages((unsigned long) dev->lk_table.table,
2320 get_order(lk_tab_size));
2321 kfree(dev->qp_table);
2322 }
2323
2324 /*
2325 * This must be called with s_lock held.
2326 */
2327 void qib_schedule_send(struct qib_qp *qp)
2328 {
2329 if (qib_send_ok(qp)) {
2330 struct qib_ibport *ibp =
2331 to_iport(qp->ibqp.device, qp->port_num);
2332 struct qib_pportdata *ppd = ppd_from_ibp(ibp);
2333
2334 queue_work(ppd->qib_wq, &qp->s_work);
2335 }
2336 }
CRIS linux kernel tree