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Linux 3.11-rc3
[cris-mirror.git] / drivers / media / i2c / ad9389b.c
blobba4364dfae6687a8ec60325b698a06e97fc87513
1 /*
2 * Analog Devices AD9389B/AD9889B video encoder driver
3 *
4 * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
5 *
6 * This program is free software; you may redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
12 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
14 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
15 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
16 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
17 * SOFTWARE.
18 */
19
20 /*
21 * References (c = chapter, p = page):
22 * REF_01 - Analog Devices, Programming Guide, AD9889B/AD9389B,
23 * HDMI Transitter, Rev. A, October 2010
24 */
25
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/slab.h>
29 #include <linux/i2c.h>
30 #include <linux/delay.h>
31 #include <linux/videodev2.h>
32 #include <linux/workqueue.h>
33 #include <linux/v4l2-dv-timings.h>
34 #include <media/v4l2-device.h>
35 #include <media/v4l2-common.h>
36 #include <media/v4l2-ctrls.h>
37 #include <media/ad9389b.h>
38
39 static int debug;
40 module_param(debug, int, 0644);
41 MODULE_PARM_DESC(debug, "debug level (0-2)");
42
43 MODULE_DESCRIPTION("Analog Devices AD9389B/AD9889B video encoder driver");
44 MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
45 MODULE_AUTHOR("Martin Bugge <marbugge@cisco.com>");
46 MODULE_LICENSE("GPL");
47
48 #define MASK_AD9389B_EDID_RDY_INT 0x04
49 #define MASK_AD9389B_MSEN_INT 0x40
50 #define MASK_AD9389B_HPD_INT 0x80
51
52 #define MASK_AD9389B_HPD_DETECT 0x40
53 #define MASK_AD9389B_MSEN_DETECT 0x20
54 #define MASK_AD9389B_EDID_RDY 0x10
55
56 #define EDID_MAX_RETRIES (8)
57 #define EDID_DELAY 250
58 #define EDID_MAX_SEGM 8
59
60 /*
61 **********************************************************************
62 *
63 * Arrays with configuration parameters for the AD9389B
64 *
65 **********************************************************************
66 */
67
68 struct i2c_reg_value {
69 u8 reg;
70 u8 value;
71 };
72
73 struct ad9389b_state_edid {
74 /* total number of blocks */
75 u32 blocks;
76 /* Number of segments read */
77 u32 segments;
78 u8 data[EDID_MAX_SEGM * 256];
79 /* Number of EDID read retries left */
80 unsigned read_retries;
81 };
82
83 struct ad9389b_state {
84 struct ad9389b_platform_data pdata;
85 struct v4l2_subdev sd;
86 struct media_pad pad;
87 struct v4l2_ctrl_handler hdl;
88 int chip_revision;
89 /* Is the ad9389b powered on? */
90 bool power_on;
91 /* Did we receive hotplug and rx-sense signals? */
92 bool have_monitor;
93 /* timings from s_dv_timings */
94 struct v4l2_dv_timings dv_timings;
95 /* controls */
96 struct v4l2_ctrl *hdmi_mode_ctrl;
97 struct v4l2_ctrl *hotplug_ctrl;
98 struct v4l2_ctrl *rx_sense_ctrl;
99 struct v4l2_ctrl *have_edid0_ctrl;
100 struct v4l2_ctrl *rgb_quantization_range_ctrl;
101 struct i2c_client *edid_i2c_client;
102 struct ad9389b_state_edid edid;
103 /* Running counter of the number of detected EDIDs (for debugging) */
104 unsigned edid_detect_counter;
105 struct workqueue_struct *work_queue;
106 struct delayed_work edid_handler; /* work entry */
107 };
108
109 static void ad9389b_check_monitor_present_status(struct v4l2_subdev *sd);
110 static bool ad9389b_check_edid_status(struct v4l2_subdev *sd);
111 static void ad9389b_setup(struct v4l2_subdev *sd);
112 static int ad9389b_s_i2s_clock_freq(struct v4l2_subdev *sd, u32 freq);
113 static int ad9389b_s_clock_freq(struct v4l2_subdev *sd, u32 freq);
114
115 static inline struct ad9389b_state *get_ad9389b_state(struct v4l2_subdev *sd)
116 {
117 return container_of(sd, struct ad9389b_state, sd);
118 }
119
120 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
121 {
122 return &container_of(ctrl->handler, struct ad9389b_state, hdl)->sd;
123 }
124
125 /* ------------------------ I2C ----------------------------------------------- */
126
127 static int ad9389b_rd(struct v4l2_subdev *sd, u8 reg)
128 {
129 struct i2c_client *client = v4l2_get_subdevdata(sd);
130
131 return i2c_smbus_read_byte_data(client, reg);
132 }
133
134 static int ad9389b_wr(struct v4l2_subdev *sd, u8 reg, u8 val)
135 {
136 struct i2c_client *client = v4l2_get_subdevdata(sd);
137 int ret;
138 int i;
139
140 for (i = 0; i < 3; i++) {
141 ret = i2c_smbus_write_byte_data(client, reg, val);
142 if (ret == 0)
143 return 0;
144 }
145 v4l2_err(sd, "I2C Write Problem\n");
146 return ret;
147 }
148
149 /* To set specific bits in the register, a clear-mask is given (to be AND-ed),
150 and then the value-mask (to be OR-ed). */
151 static inline void ad9389b_wr_and_or(struct v4l2_subdev *sd, u8 reg,
152 u8 clr_mask, u8 val_mask)
153 {
154 ad9389b_wr(sd, reg, (ad9389b_rd(sd, reg) & clr_mask) | val_mask);
155 }
156
157 static void ad9389b_edid_rd(struct v4l2_subdev *sd, u16 len, u8 *buf)
158 {
159 struct ad9389b_state *state = get_ad9389b_state(sd);
160 int i;
161
162 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
163
164 for (i = 0; i < len; i++)
165 buf[i] = i2c_smbus_read_byte_data(state->edid_i2c_client, i);
166 }
167
168 static inline bool ad9389b_have_hotplug(struct v4l2_subdev *sd)
169 {
170 return ad9389b_rd(sd, 0x42) & MASK_AD9389B_HPD_DETECT;
171 }
172
173 static inline bool ad9389b_have_rx_sense(struct v4l2_subdev *sd)
174 {
175 return ad9389b_rd(sd, 0x42) & MASK_AD9389B_MSEN_DETECT;
176 }
177
178 static void ad9389b_csc_conversion_mode(struct v4l2_subdev *sd, u8 mode)
179 {
180 ad9389b_wr_and_or(sd, 0x17, 0xe7, (mode & 0x3)<<3);
181 ad9389b_wr_and_or(sd, 0x18, 0x9f, (mode & 0x3)<<5);
182 }
183
184 static void ad9389b_csc_coeff(struct v4l2_subdev *sd,
185 u16 A1, u16 A2, u16 A3, u16 A4,
186 u16 B1, u16 B2, u16 B3, u16 B4,
187 u16 C1, u16 C2, u16 C3, u16 C4)
188 {
189 /* A */
190 ad9389b_wr_and_or(sd, 0x18, 0xe0, A1>>8);
191 ad9389b_wr(sd, 0x19, A1);
192 ad9389b_wr_and_or(sd, 0x1A, 0xe0, A2>>8);
193 ad9389b_wr(sd, 0x1B, A2);
194 ad9389b_wr_and_or(sd, 0x1c, 0xe0, A3>>8);
195 ad9389b_wr(sd, 0x1d, A3);
196 ad9389b_wr_and_or(sd, 0x1e, 0xe0, A4>>8);
197 ad9389b_wr(sd, 0x1f, A4);
198
199 /* B */
200 ad9389b_wr_and_or(sd, 0x20, 0xe0, B1>>8);
201 ad9389b_wr(sd, 0x21, B1);
202 ad9389b_wr_and_or(sd, 0x22, 0xe0, B2>>8);
203 ad9389b_wr(sd, 0x23, B2);
204 ad9389b_wr_and_or(sd, 0x24, 0xe0, B3>>8);
205 ad9389b_wr(sd, 0x25, B3);
206 ad9389b_wr_and_or(sd, 0x26, 0xe0, B4>>8);
207 ad9389b_wr(sd, 0x27, B4);
208
209 /* C */
210 ad9389b_wr_and_or(sd, 0x28, 0xe0, C1>>8);
211 ad9389b_wr(sd, 0x29, C1);
212 ad9389b_wr_and_or(sd, 0x2A, 0xe0, C2>>8);
213 ad9389b_wr(sd, 0x2B, C2);
214 ad9389b_wr_and_or(sd, 0x2C, 0xe0, C3>>8);
215 ad9389b_wr(sd, 0x2D, C3);
216 ad9389b_wr_and_or(sd, 0x2E, 0xe0, C4>>8);
217 ad9389b_wr(sd, 0x2F, C4);
218 }
219
220 static void ad9389b_csc_rgb_full2limit(struct v4l2_subdev *sd, bool enable)
221 {
222 if (enable) {
223 u8 csc_mode = 0;
224
225 ad9389b_csc_conversion_mode(sd, csc_mode);
226 ad9389b_csc_coeff(sd,
227 4096-564, 0, 0, 256,
228 0, 4096-564, 0, 256,
229 0, 0, 4096-564, 256);
230 /* enable CSC */
231 ad9389b_wr_and_or(sd, 0x3b, 0xfe, 0x1);
232 /* AVI infoframe: Limited range RGB (16-235) */
233 ad9389b_wr_and_or(sd, 0xcd, 0xf9, 0x02);
234 } else {
235 /* disable CSC */
236 ad9389b_wr_and_or(sd, 0x3b, 0xfe, 0x0);
237 /* AVI infoframe: Full range RGB (0-255) */
238 ad9389b_wr_and_or(sd, 0xcd, 0xf9, 0x04);
239 }
240 }
241
242 static void ad9389b_set_IT_content_AVI_InfoFrame(struct v4l2_subdev *sd)
243 {
244 struct ad9389b_state *state = get_ad9389b_state(sd);
245
246 if (state->dv_timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
247 /* CEA format, not IT */
248 ad9389b_wr_and_or(sd, 0xcd, 0xbf, 0x00);
249 } else {
250 /* IT format */
251 ad9389b_wr_and_or(sd, 0xcd, 0xbf, 0x40);
252 }
253 }
254
255 static int ad9389b_set_rgb_quantization_mode(struct v4l2_subdev *sd, struct v4l2_ctrl *ctrl)
256 {
257 struct ad9389b_state *state = get_ad9389b_state(sd);
258
259 switch (ctrl->val) {
260 case V4L2_DV_RGB_RANGE_AUTO:
261 /* automatic */
262 if (state->dv_timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
263 /* cea format, RGB limited range (16-235) */
264 ad9389b_csc_rgb_full2limit(sd, true);
265 } else {
266 /* not cea format, RGB full range (0-255) */
267 ad9389b_csc_rgb_full2limit(sd, false);
268 }
269 break;
270 case V4L2_DV_RGB_RANGE_LIMITED:
271 /* RGB limited range (16-235) */
272 ad9389b_csc_rgb_full2limit(sd, true);
273 break;
274 case V4L2_DV_RGB_RANGE_FULL:
275 /* RGB full range (0-255) */
276 ad9389b_csc_rgb_full2limit(sd, false);
277 break;
278 default:
279 return -EINVAL;
280 }
281 return 0;
282 }
283
284 static void ad9389b_set_manual_pll_gear(struct v4l2_subdev *sd, u32 pixelclock)
285 {
286 u8 gear;
287
288 /* Workaround for TMDS PLL problem
289 * The TMDS PLL in AD9389b change gear when the chip is heated above a
290 * certain temperature. The output is disabled when the PLL change gear
291 * so the monitor has to lock on the signal again. A workaround for
292 * this is to use the manual PLL gears. This is a solution from Analog
293 * Devices that is not documented in the datasheets.
294 * 0x98 [7] = enable manual gearing. 0x98 [6:4] = gear
295 *
296 * The pixel frequency ranges are based on readout of the gear the
297 * automatic gearing selects for different pixel clocks
298 * (read from 0x9e [3:1]).
299 */
300
301 if (pixelclock > 140000000)
302 gear = 0xc0; /* 4th gear */
303 else if (pixelclock > 117000000)
304 gear = 0xb0; /* 3rd gear */
305 else if (pixelclock > 87000000)
306 gear = 0xa0; /* 2nd gear */
307 else if (pixelclock > 60000000)
308 gear = 0x90; /* 1st gear */
309 else
310 gear = 0x80; /* 0th gear */
311
312 ad9389b_wr_and_or(sd, 0x98, 0x0f, gear);
313 }
314
315 /* ------------------------------ CTRL OPS ------------------------------ */
316
317 static int ad9389b_s_ctrl(struct v4l2_ctrl *ctrl)
318 {
319 struct v4l2_subdev *sd = to_sd(ctrl);
320 struct ad9389b_state *state = get_ad9389b_state(sd);
321
322 v4l2_dbg(1, debug, sd,
323 "%s: ctrl id: %d, ctrl->val %d\n", __func__, ctrl->id, ctrl->val);
324
325 if (state->hdmi_mode_ctrl == ctrl) {
326 /* Set HDMI or DVI-D */
327 ad9389b_wr_and_or(sd, 0xaf, 0xfd,
328 ctrl->val == V4L2_DV_TX_MODE_HDMI ? 0x02 : 0x00);
329 return 0;
330 }
331 if (state->rgb_quantization_range_ctrl == ctrl)
332 return ad9389b_set_rgb_quantization_mode(sd, ctrl);
333 return -EINVAL;
334 }
335
336 static const struct v4l2_ctrl_ops ad9389b_ctrl_ops = {
337 .s_ctrl = ad9389b_s_ctrl,
338 };
339
340 /* ---------------------------- CORE OPS ------------------------------------------- */
341
342 #ifdef CONFIG_VIDEO_ADV_DEBUG
343 static int ad9389b_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
344 {
345 reg->val = ad9389b_rd(sd, reg->reg & 0xff);
346 reg->size = 1;
347 return 0;
348 }
349
350 static int ad9389b_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
351 {
352 ad9389b_wr(sd, reg->reg & 0xff, reg->val & 0xff);
353 return 0;
354 }
355 #endif
356
357 static int ad9389b_log_status(struct v4l2_subdev *sd)
358 {
359 struct ad9389b_state *state = get_ad9389b_state(sd);
360 struct ad9389b_state_edid *edid = &state->edid;
361
362 static const char * const states[] = {
363 "in reset",
364 "reading EDID",
365 "idle",
366 "initializing HDCP",
367 "HDCP enabled",
368 "initializing HDCP repeater",
369 "6", "7", "8", "9", "A", "B", "C", "D", "E", "F"
370 };
371 static const char * const errors[] = {
372 "no error",
373 "bad receiver BKSV",
374 "Ri mismatch",
375 "Pj mismatch",
376 "i2c error",
377 "timed out",
378 "max repeater cascade exceeded",
379 "hash check failed",
380 "too many devices",
381 "9", "A", "B", "C", "D", "E", "F"
382 };
383
384 u8 manual_gear;
385
386 v4l2_info(sd, "chip revision %d\n", state->chip_revision);
387 v4l2_info(sd, "power %s\n", state->power_on ? "on" : "off");
388 v4l2_info(sd, "%s hotplug, %s Rx Sense, %s EDID (%d block(s))\n",
389 (ad9389b_rd(sd, 0x42) & MASK_AD9389B_HPD_DETECT) ?
390 "detected" : "no",
391 (ad9389b_rd(sd, 0x42) & MASK_AD9389B_MSEN_DETECT) ?
392 "detected" : "no",
393 edid->segments ? "found" : "no", edid->blocks);
394 if (state->have_monitor) {
395 v4l2_info(sd, "%s output %s\n",
396 (ad9389b_rd(sd, 0xaf) & 0x02) ?
397 "HDMI" : "DVI-D",
398 (ad9389b_rd(sd, 0xa1) & 0x3c) ?
399 "disabled" : "enabled");
400 }
401 v4l2_info(sd, "ad9389b: %s\n", (ad9389b_rd(sd, 0xb8) & 0x40) ?
402 "encrypted" : "no encryption");
403 v4l2_info(sd, "state: %s, error: %s, detect count: %u, msk/irq: %02x/%02x\n",
404 states[ad9389b_rd(sd, 0xc8) & 0xf],
405 errors[ad9389b_rd(sd, 0xc8) >> 4],
406 state->edid_detect_counter,
407 ad9389b_rd(sd, 0x94), ad9389b_rd(sd, 0x96));
408 manual_gear = ad9389b_rd(sd, 0x98) & 0x80;
409 v4l2_info(sd, "ad9389b: RGB quantization: %s range\n",
410 ad9389b_rd(sd, 0x3b) & 0x01 ? "limited" : "full");
411 v4l2_info(sd, "ad9389b: %s gear %d\n",
412 manual_gear ? "manual" : "automatic",
413 manual_gear ? ((ad9389b_rd(sd, 0x98) & 0x70) >> 4) :
414 ((ad9389b_rd(sd, 0x9e) & 0x0e) >> 1));
415 if (state->have_monitor) {
416 if (ad9389b_rd(sd, 0xaf) & 0x02) {
417 /* HDMI only */
418 u8 manual_cts = ad9389b_rd(sd, 0x0a) & 0x80;
419 u32 N = (ad9389b_rd(sd, 0x01) & 0xf) << 16 |
420 ad9389b_rd(sd, 0x02) << 8 |
421 ad9389b_rd(sd, 0x03);
422 u8 vic_detect = ad9389b_rd(sd, 0x3e) >> 2;
423 u8 vic_sent = ad9389b_rd(sd, 0x3d) & 0x3f;
424 u32 CTS;
425
426 if (manual_cts)
427 CTS = (ad9389b_rd(sd, 0x07) & 0xf) << 16 |
428 ad9389b_rd(sd, 0x08) << 8 |
429 ad9389b_rd(sd, 0x09);
430 else
431 CTS = (ad9389b_rd(sd, 0x04) & 0xf) << 16 |
432 ad9389b_rd(sd, 0x05) << 8 |
433 ad9389b_rd(sd, 0x06);
434 N = (ad9389b_rd(sd, 0x01) & 0xf) << 16 |
435 ad9389b_rd(sd, 0x02) << 8 |
436 ad9389b_rd(sd, 0x03);
437
438 v4l2_info(sd, "ad9389b: CTS %s mode: N %d, CTS %d\n",
439 manual_cts ? "manual" : "automatic", N, CTS);
440
441 v4l2_info(sd, "ad9389b: VIC: detected %d, sent %d\n",
442 vic_detect, vic_sent);
443 }
444 }
445 if (state->dv_timings.type == V4L2_DV_BT_656_1120) {
446 struct v4l2_bt_timings *bt = bt = &state->dv_timings.bt;
447 u32 frame_width = bt->width + bt->hfrontporch +
448 bt->hsync + bt->hbackporch;
449 u32 frame_height = bt->height + bt->vfrontporch +
450 bt->vsync + bt->vbackporch;
451 u32 frame_size = frame_width * frame_height;
452
453 v4l2_info(sd, "timings: %ux%u%s%u (%ux%u). Pix freq. = %u Hz. Polarities = 0x%x\n",
454 bt->width, bt->height, bt->interlaced ? "i" : "p",
455 frame_size > 0 ? (unsigned)bt->pixelclock / frame_size : 0,
456 frame_width, frame_height,
457 (unsigned)bt->pixelclock, bt->polarities);
458 } else {
459 v4l2_info(sd, "no timings set\n");
460 }
461 return 0;
462 }
463
464 /* Power up/down ad9389b */
465 static int ad9389b_s_power(struct v4l2_subdev *sd, int on)
466 {
467 struct ad9389b_state *state = get_ad9389b_state(sd);
468 struct ad9389b_platform_data *pdata = &state->pdata;
469 const int retries = 20;
470 int i;
471
472 v4l2_dbg(1, debug, sd, "%s: power %s\n", __func__, on ? "on" : "off");
473
474 state->power_on = on;
475
476 if (!on) {
477 /* Power down */
478 ad9389b_wr_and_or(sd, 0x41, 0xbf, 0x40);
479 return true;
480 }
481
482 /* Power up */
483 /* The ad9389b does not always come up immediately.
484 Retry multiple times. */
485 for (i = 0; i < retries; i++) {
486 ad9389b_wr_and_or(sd, 0x41, 0xbf, 0x0);
487 if ((ad9389b_rd(sd, 0x41) & 0x40) == 0)
488 break;
489 ad9389b_wr_and_or(sd, 0x41, 0xbf, 0x40);
490 msleep(10);
491 }
492 if (i == retries) {
493 v4l2_dbg(1, debug, sd, "failed to powerup the ad9389b\n");
494 ad9389b_s_power(sd, 0);
495 return false;
496 }
497 if (i > 1)
498 v4l2_dbg(1, debug, sd,
499 "needed %d retries to powerup the ad9389b\n", i);
500
501 /* Select chip: AD9389B */
502 ad9389b_wr_and_or(sd, 0xba, 0xef, 0x10);
503
504 /* Reserved registers that must be set according to REF_01 p. 11*/
505 ad9389b_wr_and_or(sd, 0x98, 0xf0, 0x07);
506 ad9389b_wr(sd, 0x9c, 0x38);
507 ad9389b_wr_and_or(sd, 0x9d, 0xfc, 0x01);
508
509 /* Differential output drive strength */
510 if (pdata->diff_data_drive_strength > 0)
511 ad9389b_wr(sd, 0xa2, pdata->diff_data_drive_strength);
512 else
513 ad9389b_wr(sd, 0xa2, 0x87);
514
515 if (pdata->diff_clk_drive_strength > 0)
516 ad9389b_wr(sd, 0xa3, pdata->diff_clk_drive_strength);
517 else
518 ad9389b_wr(sd, 0xa3, 0x87);
519
520 ad9389b_wr(sd, 0x0a, 0x01);
521 ad9389b_wr(sd, 0xbb, 0xff);
522
523 /* Set number of attempts to read the EDID */
524 ad9389b_wr(sd, 0xc9, 0xf);
525 return true;
526 }
527
528 /* Enable interrupts */
529 static void ad9389b_set_isr(struct v4l2_subdev *sd, bool enable)
530 {
531 u8 irqs = MASK_AD9389B_HPD_INT | MASK_AD9389B_MSEN_INT;
532 u8 irqs_rd;
533 int retries = 100;
534
535 /* The datasheet says that the EDID ready interrupt should be
536 disabled if there is no hotplug. */
537 if (!enable)
538 irqs = 0;
539 else if (ad9389b_have_hotplug(sd))
540 irqs |= MASK_AD9389B_EDID_RDY_INT;
541
542 /*
543 * This i2c write can fail (approx. 1 in 1000 writes). But it
544 * is essential that this register is correct, so retry it
545 * multiple times.
546 *
547 * Note that the i2c write does not report an error, but the readback
548 * clearly shows the wrong value.
549 */
550 do {
551 ad9389b_wr(sd, 0x94, irqs);
552 irqs_rd = ad9389b_rd(sd, 0x94);
553 } while (retries-- && irqs_rd != irqs);
554
555 if (irqs_rd != irqs)
556 v4l2_err(sd, "Could not set interrupts: hw failure?\n");
557 }
558
559 /* Interrupt handler */
560 static int ad9389b_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
561 {
562 u8 irq_status;
563
564 /* disable interrupts to prevent a race condition */
565 ad9389b_set_isr(sd, false);
566 irq_status = ad9389b_rd(sd, 0x96);
567 /* clear detected interrupts */
568 ad9389b_wr(sd, 0x96, irq_status);
569
570 if (irq_status & (MASK_AD9389B_HPD_INT | MASK_AD9389B_MSEN_INT))
571 ad9389b_check_monitor_present_status(sd);
572 if (irq_status & MASK_AD9389B_EDID_RDY_INT)
573 ad9389b_check_edid_status(sd);
574
575 /* enable interrupts */
576 ad9389b_set_isr(sd, true);
577 *handled = true;
578 return 0;
579 }
580
581 static const struct v4l2_subdev_core_ops ad9389b_core_ops = {
582 .log_status = ad9389b_log_status,
583 #ifdef CONFIG_VIDEO_ADV_DEBUG
584 .g_register = ad9389b_g_register,
585 .s_register = ad9389b_s_register,
586 #endif
587 .s_power = ad9389b_s_power,
588 .interrupt_service_routine = ad9389b_isr,
589 };
590
591 /* ------------------------------ PAD OPS ------------------------------ */
592
593 static int ad9389b_get_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *edid)
594 {
595 struct ad9389b_state *state = get_ad9389b_state(sd);
596
597 if (edid->pad != 0)
598 return -EINVAL;
599 if (edid->blocks == 0 || edid->blocks > 256)
600 return -EINVAL;
601 if (!edid->edid)
602 return -EINVAL;
603 if (!state->edid.segments) {
604 v4l2_dbg(1, debug, sd, "EDID segment 0 not found\n");
605 return -ENODATA;
606 }
607 if (edid->start_block >= state->edid.segments * 2)
608 return -E2BIG;
609 if (edid->blocks + edid->start_block >= state->edid.segments * 2)
610 edid->blocks = state->edid.segments * 2 - edid->start_block;
611 memcpy(edid->edid, &state->edid.data[edid->start_block * 128],
612 128 * edid->blocks);
613 return 0;
614 }
615
616 static const struct v4l2_subdev_pad_ops ad9389b_pad_ops = {
617 .get_edid = ad9389b_get_edid,
618 };
619
620 /* ------------------------------ VIDEO OPS ------------------------------ */
621
622 /* Enable/disable ad9389b output */
623 static int ad9389b_s_stream(struct v4l2_subdev *sd, int enable)
624 {
625 struct ad9389b_state *state = get_ad9389b_state(sd);
626
627 v4l2_dbg(1, debug, sd, "%s: %sable\n", __func__, (enable ? "en" : "dis"));
628
629 ad9389b_wr_and_or(sd, 0xa1, ~0x3c, (enable ? 0 : 0x3c));
630 if (enable) {
631 ad9389b_check_monitor_present_status(sd);
632 } else {
633 ad9389b_s_power(sd, 0);
634 state->have_monitor = false;
635 }
636 return 0;
637 }
638
639 static const struct v4l2_dv_timings ad9389b_timings[] = {
640 V4L2_DV_BT_CEA_720X480P59_94,
641 V4L2_DV_BT_CEA_720X576P50,
642 V4L2_DV_BT_CEA_1280X720P24,
643 V4L2_DV_BT_CEA_1280X720P25,
644 V4L2_DV_BT_CEA_1280X720P30,
645 V4L2_DV_BT_CEA_1280X720P50,
646 V4L2_DV_BT_CEA_1280X720P60,
647 V4L2_DV_BT_CEA_1920X1080P24,
648 V4L2_DV_BT_CEA_1920X1080P25,
649 V4L2_DV_BT_CEA_1920X1080P30,
650 V4L2_DV_BT_CEA_1920X1080P50,
651 V4L2_DV_BT_CEA_1920X1080P60,
652
653 V4L2_DV_BT_DMT_640X350P85,
654 V4L2_DV_BT_DMT_640X400P85,
655 V4L2_DV_BT_DMT_720X400P85,
656 V4L2_DV_BT_DMT_640X480P60,
657 V4L2_DV_BT_DMT_640X480P72,
658 V4L2_DV_BT_DMT_640X480P75,
659 V4L2_DV_BT_DMT_640X480P85,
660 V4L2_DV_BT_DMT_800X600P56,
661 V4L2_DV_BT_DMT_800X600P60,
662 V4L2_DV_BT_DMT_800X600P72,
663 V4L2_DV_BT_DMT_800X600P75,
664 V4L2_DV_BT_DMT_800X600P85,
665 V4L2_DV_BT_DMT_848X480P60,
666 V4L2_DV_BT_DMT_1024X768P60,
667 V4L2_DV_BT_DMT_1024X768P70,
668 V4L2_DV_BT_DMT_1024X768P75,
669 V4L2_DV_BT_DMT_1024X768P85,
670 V4L2_DV_BT_DMT_1152X864P75,
671 V4L2_DV_BT_DMT_1280X768P60_RB,
672 V4L2_DV_BT_DMT_1280X768P60,
673 V4L2_DV_BT_DMT_1280X768P75,
674 V4L2_DV_BT_DMT_1280X768P85,
675 V4L2_DV_BT_DMT_1280X800P60_RB,
676 V4L2_DV_BT_DMT_1280X800P60,
677 V4L2_DV_BT_DMT_1280X800P75,
678 V4L2_DV_BT_DMT_1280X800P85,
679 V4L2_DV_BT_DMT_1280X960P60,
680 V4L2_DV_BT_DMT_1280X960P85,
681 V4L2_DV_BT_DMT_1280X1024P60,
682 V4L2_DV_BT_DMT_1280X1024P75,
683 V4L2_DV_BT_DMT_1280X1024P85,
684 V4L2_DV_BT_DMT_1360X768P60,
685 V4L2_DV_BT_DMT_1400X1050P60_RB,
686 V4L2_DV_BT_DMT_1400X1050P60,
687 V4L2_DV_BT_DMT_1400X1050P75,
688 V4L2_DV_BT_DMT_1400X1050P85,
689 V4L2_DV_BT_DMT_1440X900P60_RB,
690 V4L2_DV_BT_DMT_1440X900P60,
691 V4L2_DV_BT_DMT_1600X1200P60,
692 V4L2_DV_BT_DMT_1680X1050P60_RB,
693 V4L2_DV_BT_DMT_1680X1050P60,
694 V4L2_DV_BT_DMT_1792X1344P60,
695 V4L2_DV_BT_DMT_1856X1392P60,
696 V4L2_DV_BT_DMT_1920X1200P60_RB,
697 V4L2_DV_BT_DMT_1366X768P60,
698 V4L2_DV_BT_DMT_1920X1080P60,
699 {},
700 };
701
702 static int ad9389b_s_dv_timings(struct v4l2_subdev *sd,
703 struct v4l2_dv_timings *timings)
704 {
705 struct ad9389b_state *state = get_ad9389b_state(sd);
706 int i;
707
708 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
709
710 /* quick sanity check */
711 if (timings->type != V4L2_DV_BT_656_1120)
712 return -EINVAL;
713
714 if (timings->bt.interlaced)
715 return -EINVAL;
716 if (timings->bt.pixelclock < 27000000 ||
717 timings->bt.pixelclock > 170000000)
718 return -EINVAL;
719
720 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
721 if the format is listed in ad9389b_timings[] */
722 for (i = 0; ad9389b_timings[i].bt.width; i++) {
723 if (v4l_match_dv_timings(timings, &ad9389b_timings[i], 0)) {
724 *timings = ad9389b_timings[i];
725 break;
726 }
727 }
728
729 timings->bt.flags &= ~V4L2_DV_FL_REDUCED_FPS;
730
731 /* save timings */
732 state->dv_timings = *timings;
733
734 /* update quantization range based on new dv_timings */
735 ad9389b_set_rgb_quantization_mode(sd, state->rgb_quantization_range_ctrl);
736
737 /* update PLL gear based on new dv_timings */
738 if (state->pdata.tmds_pll_gear == AD9389B_TMDS_PLL_GEAR_SEMI_AUTOMATIC)
739 ad9389b_set_manual_pll_gear(sd, (u32)timings->bt.pixelclock);
740
741 /* update AVI infoframe */
742 ad9389b_set_IT_content_AVI_InfoFrame(sd);
743
744 return 0;
745 }
746
747 static int ad9389b_g_dv_timings(struct v4l2_subdev *sd,
748 struct v4l2_dv_timings *timings)
749 {
750 struct ad9389b_state *state = get_ad9389b_state(sd);
751
752 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
753
754 if (!timings)
755 return -EINVAL;
756
757 *timings = state->dv_timings;
758
759 return 0;
760 }
761
762 static int ad9389b_enum_dv_timings(struct v4l2_subdev *sd,
763 struct v4l2_enum_dv_timings *timings)
764 {
765 if (timings->index >= ARRAY_SIZE(ad9389b_timings))
766 return -EINVAL;
767
768 memset(timings->reserved, 0, sizeof(timings->reserved));
769 timings->timings = ad9389b_timings[timings->index];
770 return 0;
771 }
772
773 static int ad9389b_dv_timings_cap(struct v4l2_subdev *sd,
774 struct v4l2_dv_timings_cap *cap)
775 {
776 cap->type = V4L2_DV_BT_656_1120;
777 cap->bt.max_width = 1920;
778 cap->bt.max_height = 1200;
779 cap->bt.min_pixelclock = 27000000;
780 cap->bt.max_pixelclock = 170000000;
781 cap->bt.standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
782 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT;
783 cap->bt.capabilities = V4L2_DV_BT_CAP_PROGRESSIVE |
784 V4L2_DV_BT_CAP_REDUCED_BLANKING | V4L2_DV_BT_CAP_CUSTOM;
785 return 0;
786 }
787
788 static const struct v4l2_subdev_video_ops ad9389b_video_ops = {
789 .s_stream = ad9389b_s_stream,
790 .s_dv_timings = ad9389b_s_dv_timings,
791 .g_dv_timings = ad9389b_g_dv_timings,
792 .enum_dv_timings = ad9389b_enum_dv_timings,
793 .dv_timings_cap = ad9389b_dv_timings_cap,
794 };
795
796 static int ad9389b_s_audio_stream(struct v4l2_subdev *sd, int enable)
797 {
798 v4l2_dbg(1, debug, sd, "%s: %sable\n", __func__, (enable ? "en" : "dis"));
799
800 if (enable)
801 ad9389b_wr_and_or(sd, 0x45, 0x3f, 0x80);
802 else
803 ad9389b_wr_and_or(sd, 0x45, 0x3f, 0x40);
804
805 return 0;
806 }
807
808 static int ad9389b_s_clock_freq(struct v4l2_subdev *sd, u32 freq)
809 {
810 u32 N;
811
812 switch (freq) {
813 case 32000: N = 4096; break;
814 case 44100: N = 6272; break;
815 case 48000: N = 6144; break;
816 case 88200: N = 12544; break;
817 case 96000: N = 12288; break;
818 case 176400: N = 25088; break;
819 case 192000: N = 24576; break;
820 default:
821 return -EINVAL;
822 }
823
824 /* Set N (used with CTS to regenerate the audio clock) */
825 ad9389b_wr(sd, 0x01, (N >> 16) & 0xf);
826 ad9389b_wr(sd, 0x02, (N >> 8) & 0xff);
827 ad9389b_wr(sd, 0x03, N & 0xff);
828
829 return 0;
830 }
831
832 static int ad9389b_s_i2s_clock_freq(struct v4l2_subdev *sd, u32 freq)
833 {
834 u32 i2s_sf;
835
836 switch (freq) {
837 case 32000: i2s_sf = 0x30; break;
838 case 44100: i2s_sf = 0x00; break;
839 case 48000: i2s_sf = 0x20; break;
840 case 88200: i2s_sf = 0x80; break;
841 case 96000: i2s_sf = 0xa0; break;
842 case 176400: i2s_sf = 0xc0; break;
843 case 192000: i2s_sf = 0xe0; break;
844 default:
845 return -EINVAL;
846 }
847
848 /* Set sampling frequency for I2S audio to 48 kHz */
849 ad9389b_wr_and_or(sd, 0x15, 0xf, i2s_sf);
850
851 return 0;
852 }
853
854 static int ad9389b_s_routing(struct v4l2_subdev *sd, u32 input, u32 output, u32 config)
855 {
856 /* TODO based on input/output/config */
857 /* TODO See datasheet "Programmers guide" p. 39-40 */
858
859 /* Only 2 channels in use for application */
860 ad9389b_wr_and_or(sd, 0x50, 0x1f, 0x20);
861 /* Speaker mapping */
862 ad9389b_wr(sd, 0x51, 0x00);
863
864 /* TODO Where should this be placed? */
865 /* 16 bit audio word length */
866 ad9389b_wr_and_or(sd, 0x14, 0xf0, 0x02);
867
868 return 0;
869 }
870
871 static const struct v4l2_subdev_audio_ops ad9389b_audio_ops = {
872 .s_stream = ad9389b_s_audio_stream,
873 .s_clock_freq = ad9389b_s_clock_freq,
874 .s_i2s_clock_freq = ad9389b_s_i2s_clock_freq,
875 .s_routing = ad9389b_s_routing,
876 };
877
878 /* --------------------- SUBDEV OPS --------------------------------------- */
879
880 static const struct v4l2_subdev_ops ad9389b_ops = {
881 .core = &ad9389b_core_ops,
882 .video = &ad9389b_video_ops,
883 .audio = &ad9389b_audio_ops,
884 .pad = &ad9389b_pad_ops,
885 };
886
887 /* ----------------------------------------------------------------------- */
888 static void ad9389b_dbg_dump_edid(int lvl, int debug, struct v4l2_subdev *sd,
889 int segment, u8 *buf)
890 {
891 int i, j;
892
893 if (debug < lvl)
894 return;
895
896 v4l2_dbg(lvl, debug, sd, "edid segment %d\n", segment);
897 for (i = 0; i < 256; i += 16) {
898 u8 b[128];
899 u8 *bp = b;
900
901 if (i == 128)
902 v4l2_dbg(lvl, debug, sd, "\n");
903 for (j = i; j < i + 16; j++) {
904 sprintf(bp, "0x%02x, ", buf[j]);
905 bp += 6;
906 }
907 bp[0] = '\0';
908 v4l2_dbg(lvl, debug, sd, "%s\n", b);
909 }
910 }
911
912 static void ad9389b_edid_handler(struct work_struct *work)
913 {
914 struct delayed_work *dwork = to_delayed_work(work);
915 struct ad9389b_state *state = container_of(dwork,
916 struct ad9389b_state, edid_handler);
917 struct v4l2_subdev *sd = &state->sd;
918 struct ad9389b_edid_detect ed;
919
920 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
921
922 if (ad9389b_check_edid_status(sd)) {
923 /* Return if we received the EDID. */
924 return;
925 }
926
927 if (ad9389b_have_hotplug(sd)) {
928 /* We must retry reading the EDID several times, it is possible
929 * that initially the EDID couldn't be read due to i2c errors
930 * (DVI connectors are particularly prone to this problem). */
931 if (state->edid.read_retries) {
932 state->edid.read_retries--;
933 /* EDID read failed, trigger a retry */
934 ad9389b_wr(sd, 0xc9, 0xf);
935 queue_delayed_work(state->work_queue,
936 &state->edid_handler, EDID_DELAY);
937 return;
938 }
939 }
940
941 /* We failed to read the EDID, so send an event for this. */
942 ed.present = false;
943 ed.segment = ad9389b_rd(sd, 0xc4);
944 v4l2_subdev_notify(sd, AD9389B_EDID_DETECT, (void *)&ed);
945 v4l2_dbg(1, debug, sd, "%s: no edid found\n", __func__);
946 }
947
948 static void ad9389b_audio_setup(struct v4l2_subdev *sd)
949 {
950 v4l2_dbg(1, debug, sd, "%s\n", __func__);
951
952 ad9389b_s_i2s_clock_freq(sd, 48000);
953 ad9389b_s_clock_freq(sd, 48000);
954 ad9389b_s_routing(sd, 0, 0, 0);
955 }
956
957 /* Initial setup of AD9389b */
958
959 /* Configure hdmi transmitter. */
960 static void ad9389b_setup(struct v4l2_subdev *sd)
961 {
962 struct ad9389b_state *state = get_ad9389b_state(sd);
963
964 v4l2_dbg(1, debug, sd, "%s\n", __func__);
965
966 /* Input format: RGB 4:4:4 */
967 ad9389b_wr_and_or(sd, 0x15, 0xf1, 0x0);
968 /* Output format: RGB 4:4:4 */
969 ad9389b_wr_and_or(sd, 0x16, 0x3f, 0x0);
970 /* CSC fixed point: +/-2, 1st order interpolation 4:2:2 -> 4:4:4 up
971 conversion, Aspect ratio: 16:9 */
972 ad9389b_wr_and_or(sd, 0x17, 0xe1, 0x0e);
973 /* Disable pixel repetition and CSC */
974 ad9389b_wr_and_or(sd, 0x3b, 0x9e, 0x0);
975 /* Output format: RGB 4:4:4, Active Format Information is valid. */
976 ad9389b_wr_and_or(sd, 0x45, 0xc7, 0x08);
977 /* Underscanned */
978 ad9389b_wr_and_or(sd, 0x46, 0x3f, 0x80);
979 /* Setup video format */
980 ad9389b_wr(sd, 0x3c, 0x0);
981 /* Active format aspect ratio: same as picure. */
982 ad9389b_wr(sd, 0x47, 0x80);
983 /* No encryption */
984 ad9389b_wr_and_or(sd, 0xaf, 0xef, 0x0);
985 /* Positive clk edge capture for input video clock */
986 ad9389b_wr_and_or(sd, 0xba, 0x1f, 0x60);
987
988 ad9389b_audio_setup(sd);
989
990 v4l2_ctrl_handler_setup(&state->hdl);
991
992 ad9389b_set_IT_content_AVI_InfoFrame(sd);
993 }
994
995 static void ad9389b_notify_monitor_detect(struct v4l2_subdev *sd)
996 {
997 struct ad9389b_monitor_detect mdt;
998 struct ad9389b_state *state = get_ad9389b_state(sd);
999
1000 mdt.present = state->have_monitor;
1001 v4l2_subdev_notify(sd, AD9389B_MONITOR_DETECT, (void *)&mdt);
1002 }
1003
1004 static void ad9389b_check_monitor_present_status(struct v4l2_subdev *sd)
1005 {
1006 struct ad9389b_state *state = get_ad9389b_state(sd);
1007 /* read hotplug and rx-sense state */
1008 u8 status = ad9389b_rd(sd, 0x42);
1009
1010 v4l2_dbg(1, debug, sd, "%s: status: 0x%x%s%s\n",
1011 __func__,
1012 status,
1013 status & MASK_AD9389B_HPD_DETECT ? ", hotplug" : "",
1014 status & MASK_AD9389B_MSEN_DETECT ? ", rx-sense" : "");
1015
1016 if ((status & MASK_AD9389B_HPD_DETECT) &&
1017 ((status & MASK_AD9389B_MSEN_DETECT) || state->edid.segments)) {
1018 v4l2_dbg(1, debug, sd,
1019 "%s: hotplug and (rx-sense or edid)\n", __func__);
1020 if (!state->have_monitor) {
1021 v4l2_dbg(1, debug, sd, "%s: monitor detected\n", __func__);
1022 state->have_monitor = true;
1023 ad9389b_set_isr(sd, true);
1024 if (!ad9389b_s_power(sd, true)) {
1025 v4l2_dbg(1, debug, sd,
1026 "%s: monitor detected, powerup failed\n", __func__);
1027 return;
1028 }
1029 ad9389b_setup(sd);
1030 ad9389b_notify_monitor_detect(sd);
1031 state->edid.read_retries = EDID_MAX_RETRIES;
1032 queue_delayed_work(state->work_queue,
1033 &state->edid_handler, EDID_DELAY);
1034 }
1035 } else if (status & MASK_AD9389B_HPD_DETECT) {
1036 v4l2_dbg(1, debug, sd, "%s: hotplug detected\n", __func__);
1037 state->edid.read_retries = EDID_MAX_RETRIES;
1038 queue_delayed_work(state->work_queue,
1039 &state->edid_handler, EDID_DELAY);
1040 } else if (!(status & MASK_AD9389B_HPD_DETECT)) {
1041 v4l2_dbg(1, debug, sd, "%s: hotplug not detected\n", __func__);
1042 if (state->have_monitor) {
1043 v4l2_dbg(1, debug, sd, "%s: monitor not detected\n", __func__);
1044 state->have_monitor = false;
1045 ad9389b_notify_monitor_detect(sd);
1046 }
1047 ad9389b_s_power(sd, false);
1048 memset(&state->edid, 0, sizeof(struct ad9389b_state_edid));
1049 }
1050
1051 /* update read only ctrls */
1052 v4l2_ctrl_s_ctrl(state->hotplug_ctrl, ad9389b_have_hotplug(sd) ? 0x1 : 0x0);
1053 v4l2_ctrl_s_ctrl(state->rx_sense_ctrl, ad9389b_have_rx_sense(sd) ? 0x1 : 0x0);
1054 v4l2_ctrl_s_ctrl(state->have_edid0_ctrl, state->edid.segments ? 0x1 : 0x0);
1055 }
1056
1057 static bool edid_block_verify_crc(u8 *edid_block)
1058 {
1059 int i;
1060 u8 sum = 0;
1061
1062 for (i = 0; i < 127; i++)
1063 sum += *(edid_block + i);
1064 return ((255 - sum + 1) == edid_block[127]);
1065 }
1066
1067 static bool edid_segment_verify_crc(struct v4l2_subdev *sd, u32 segment)
1068 {
1069 struct ad9389b_state *state = get_ad9389b_state(sd);
1070 u32 blocks = state->edid.blocks;
1071 u8 *data = state->edid.data;
1072
1073 if (edid_block_verify_crc(&data[segment * 256])) {
1074 if ((segment + 1) * 2 <= blocks)
1075 return edid_block_verify_crc(&data[segment * 256 + 128]);
1076 return true;
1077 }
1078 return false;
1079 }
1080
1081 static bool ad9389b_check_edid_status(struct v4l2_subdev *sd)
1082 {
1083 struct ad9389b_state *state = get_ad9389b_state(sd);
1084 struct ad9389b_edid_detect ed;
1085 int segment;
1086 u8 edidRdy = ad9389b_rd(sd, 0xc5);
1087
1088 v4l2_dbg(1, debug, sd, "%s: edid ready (retries: %d)\n",
1089 __func__, EDID_MAX_RETRIES - state->edid.read_retries);
1090
1091 if (!(edidRdy & MASK_AD9389B_EDID_RDY))
1092 return false;
1093
1094 segment = ad9389b_rd(sd, 0xc4);
1095 if (segment >= EDID_MAX_SEGM) {
1096 v4l2_err(sd, "edid segment number too big\n");
1097 return false;
1098 }
1099 v4l2_dbg(1, debug, sd, "%s: got segment %d\n", __func__, segment);
1100 ad9389b_edid_rd(sd, 256, &state->edid.data[segment * 256]);
1101 ad9389b_dbg_dump_edid(2, debug, sd, segment,
1102 &state->edid.data[segment * 256]);
1103 if (segment == 0) {
1104 state->edid.blocks = state->edid.data[0x7e] + 1;
1105 v4l2_dbg(1, debug, sd, "%s: %d blocks in total\n",
1106 __func__, state->edid.blocks);
1107 }
1108 if (!edid_segment_verify_crc(sd, segment)) {
1109 /* edid crc error, force reread of edid segment */
1110 ad9389b_s_power(sd, false);
1111 ad9389b_s_power(sd, true);
1112 return false;
1113 }
1114 /* one more segment read ok */
1115 state->edid.segments = segment + 1;
1116 if (((state->edid.data[0x7e] >> 1) + 1) > state->edid.segments) {
1117 /* Request next EDID segment */
1118 v4l2_dbg(1, debug, sd, "%s: request segment %d\n",
1119 __func__, state->edid.segments);
1120 ad9389b_wr(sd, 0xc9, 0xf);
1121 ad9389b_wr(sd, 0xc4, state->edid.segments);
1122 state->edid.read_retries = EDID_MAX_RETRIES;
1123 queue_delayed_work(state->work_queue,
1124 &state->edid_handler, EDID_DELAY);
1125 return false;
1126 }
1127
1128 /* report when we have all segments but report only for segment 0 */
1129 ed.present = true;
1130 ed.segment = 0;
1131 v4l2_subdev_notify(sd, AD9389B_EDID_DETECT, (void *)&ed);
1132 state->edid_detect_counter++;
1133 v4l2_ctrl_s_ctrl(state->have_edid0_ctrl, state->edid.segments ? 0x1 : 0x0);
1134 return ed.present;
1135 }
1136
1137 /* ----------------------------------------------------------------------- */
1138
1139 static void ad9389b_init_setup(struct v4l2_subdev *sd)
1140 {
1141 struct ad9389b_state *state = get_ad9389b_state(sd);
1142 struct ad9389b_state_edid *edid = &state->edid;
1143
1144 v4l2_dbg(1, debug, sd, "%s\n", __func__);
1145
1146 /* clear all interrupts */
1147 ad9389b_wr(sd, 0x96, 0xff);
1148
1149 memset(edid, 0, sizeof(struct ad9389b_state_edid));
1150 state->have_monitor = false;
1151 ad9389b_set_isr(sd, false);
1152 }
1153
1154 static int ad9389b_probe(struct i2c_client *client, const struct i2c_device_id *id)
1155 {
1156 const struct v4l2_dv_timings dv1080p60 = V4L2_DV_BT_CEA_1920X1080P60;
1157 struct ad9389b_state *state;
1158 struct ad9389b_platform_data *pdata = client->dev.platform_data;
1159 struct v4l2_ctrl_handler *hdl;
1160 struct v4l2_subdev *sd;
1161 int err = -EIO;
1162
1163 /* Check if the adapter supports the needed features */
1164 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1165 return -EIO;
1166
1167 v4l_dbg(1, debug, client, "detecting ad9389b client on address 0x%x\n",
1168 client->addr << 1);
1169
1170 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
1171 if (!state)
1172 return -ENOMEM;
1173
1174 /* Platform data */
1175 if (pdata == NULL) {
1176 v4l_err(client, "No platform data!\n");
1177 return -ENODEV;
1178 }
1179 memcpy(&state->pdata, pdata, sizeof(state->pdata));
1180
1181 sd = &state->sd;
1182 v4l2_i2c_subdev_init(sd, client, &ad9389b_ops);
1183 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1184
1185 hdl = &state->hdl;
1186 v4l2_ctrl_handler_init(hdl, 5);
1187
1188 /* private controls */
1189
1190 state->hdmi_mode_ctrl = v4l2_ctrl_new_std_menu(hdl, &ad9389b_ctrl_ops,
1191 V4L2_CID_DV_TX_MODE, V4L2_DV_TX_MODE_HDMI,
1192 0, V4L2_DV_TX_MODE_DVI_D);
1193 state->hdmi_mode_ctrl->is_private = true;
1194 state->hotplug_ctrl = v4l2_ctrl_new_std(hdl, NULL,
1195 V4L2_CID_DV_TX_HOTPLUG, 0, 1, 0, 0);
1196 state->hotplug_ctrl->is_private = true;
1197 state->rx_sense_ctrl = v4l2_ctrl_new_std(hdl, NULL,
1198 V4L2_CID_DV_TX_RXSENSE, 0, 1, 0, 0);
1199 state->rx_sense_ctrl->is_private = true;
1200 state->have_edid0_ctrl = v4l2_ctrl_new_std(hdl, NULL,
1201 V4L2_CID_DV_TX_EDID_PRESENT, 0, 1, 0, 0);
1202 state->have_edid0_ctrl->is_private = true;
1203 state->rgb_quantization_range_ctrl =
1204 v4l2_ctrl_new_std_menu(hdl, &ad9389b_ctrl_ops,
1205 V4L2_CID_DV_TX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
1206 0, V4L2_DV_RGB_RANGE_AUTO);
1207 state->rgb_quantization_range_ctrl->is_private = true;
1208 sd->ctrl_handler = hdl;
1209 if (hdl->error) {
1210 err = hdl->error;
1211
1212 goto err_hdl;
1213 }
1214
1215 state->pad.flags = MEDIA_PAD_FL_SINK;
1216 err = media_entity_init(&sd->entity, 1, &state->pad, 0);
1217 if (err)
1218 goto err_hdl;
1219
1220 state->chip_revision = ad9389b_rd(sd, 0x0);
1221 if (state->chip_revision != 2) {
1222 v4l2_err(sd, "chip_revision %d != 2\n", state->chip_revision);
1223 err = -EIO;
1224 goto err_entity;
1225 }
1226 v4l2_dbg(1, debug, sd, "reg 0x41 0x%x, chip version (reg 0x00) 0x%x\n",
1227 ad9389b_rd(sd, 0x41), state->chip_revision);
1228
1229 state->edid_i2c_client = i2c_new_dummy(client->adapter, (0x7e>>1));
1230 if (state->edid_i2c_client == NULL) {
1231 v4l2_err(sd, "failed to register edid i2c client\n");
1232 err = -ENOMEM;
1233 goto err_entity;
1234 }
1235
1236 state->work_queue = create_singlethread_workqueue(sd->name);
1237 if (state->work_queue == NULL) {
1238 v4l2_err(sd, "could not create workqueue\n");
1239 err = -ENOMEM;
1240 goto err_unreg;
1241 }
1242
1243 INIT_DELAYED_WORK(&state->edid_handler, ad9389b_edid_handler);
1244 state->dv_timings = dv1080p60;
1245
1246 ad9389b_init_setup(sd);
1247 ad9389b_set_isr(sd, true);
1248
1249 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
1250 client->addr << 1, client->adapter->name);
1251 return 0;
1252
1253 err_unreg:
1254 i2c_unregister_device(state->edid_i2c_client);
1255 err_entity:
1256 media_entity_cleanup(&sd->entity);
1257 err_hdl:
1258 v4l2_ctrl_handler_free(&state->hdl);
1259 return err;
1260 }
1261
1262 /* ----------------------------------------------------------------------- */
1263
1264 static int ad9389b_remove(struct i2c_client *client)
1265 {
1266 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1267 struct ad9389b_state *state = get_ad9389b_state(sd);
1268
1269 state->chip_revision = -1;
1270
1271 v4l2_dbg(1, debug, sd, "%s removed @ 0x%x (%s)\n", client->name,
1272 client->addr << 1, client->adapter->name);
1273
1274 ad9389b_s_stream(sd, false);
1275 ad9389b_s_audio_stream(sd, false);
1276 ad9389b_init_setup(sd);
1277 cancel_delayed_work(&state->edid_handler);
1278 i2c_unregister_device(state->edid_i2c_client);
1279 destroy_workqueue(state->work_queue);
1280 v4l2_device_unregister_subdev(sd);
1281 media_entity_cleanup(&sd->entity);
1282 v4l2_ctrl_handler_free(sd->ctrl_handler);
1283 return 0;
1284 }
1285
1286 /* ----------------------------------------------------------------------- */
1287
1288 static struct i2c_device_id ad9389b_id[] = {
1289 { "ad9389b", 0 },
1290 { "ad9889b", 0 },
1291 { }
1292 };
1293 MODULE_DEVICE_TABLE(i2c, ad9389b_id);
1294
1295 static struct i2c_driver ad9389b_driver = {
1296 .driver = {
1297 .owner = THIS_MODULE,
1298 .name = "ad9389b",
1299 },
1300 .probe = ad9389b_probe,
1301 .remove = ad9389b_remove,
1302 .id_table = ad9389b_id,
1303 };
1304
1305 module_i2c_driver(ad9389b_driver);
CRIS linux kernel tree