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Linux 3.11-rc3
[cris-mirror.git] / drivers / media / i2c / adv7604.c
blob1d675b58fd71bae6db5f5c80fd971745b0525fb6
1 /*
2 * adv7604 - Analog Devices ADV7604 video decoder driver
3 *
4 * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
5 *
6 * This program is free software; you may redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
12 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
14 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
15 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
16 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
17 * SOFTWARE.
18 *
19 */
20
21 /*
22 * References (c = chapter, p = page):
23 * REF_01 - Analog devices, ADV7604, Register Settings Recommendations,
24 * Revision 2.5, June 2010
25 * REF_02 - Analog devices, Register map documentation, Documentation of
26 * the register maps, Software manual, Rev. F, June 2010
27 * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010
28 */
29
30
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/slab.h>
34 #include <linux/i2c.h>
35 #include <linux/delay.h>
36 #include <linux/videodev2.h>
37 #include <linux/workqueue.h>
38 #include <linux/v4l2-dv-timings.h>
39 #include <media/v4l2-device.h>
40 #include <media/v4l2-ctrls.h>
41 #include <media/adv7604.h>
42
43 static int debug;
44 module_param(debug, int, 0644);
45 MODULE_PARM_DESC(debug, "debug level (0-2)");
46
47 MODULE_DESCRIPTION("Analog Devices ADV7604 video decoder driver");
48 MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
49 MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>");
50 MODULE_LICENSE("GPL");
51
52 /* ADV7604 system clock frequency */
53 #define ADV7604_fsc (28636360)
54
55 #define DIGITAL_INPUT (state->mode == ADV7604_MODE_HDMI)
56
57 /*
58 **********************************************************************
59 *
60 * Arrays with configuration parameters for the ADV7604
61 *
62 **********************************************************************
63 */
64 struct adv7604_state {
65 struct adv7604_platform_data pdata;
66 struct v4l2_subdev sd;
67 struct media_pad pad;
68 struct v4l2_ctrl_handler hdl;
69 enum adv7604_mode mode;
70 struct v4l2_dv_timings timings;
71 u8 edid[256];
72 unsigned edid_blocks;
73 struct v4l2_fract aspect_ratio;
74 u32 rgb_quantization_range;
75 struct workqueue_struct *work_queues;
76 struct delayed_work delayed_work_enable_hotplug;
77 bool connector_hdmi;
78 bool restart_stdi_once;
79
80 /* i2c clients */
81 struct i2c_client *i2c_avlink;
82 struct i2c_client *i2c_cec;
83 struct i2c_client *i2c_infoframe;
84 struct i2c_client *i2c_esdp;
85 struct i2c_client *i2c_dpp;
86 struct i2c_client *i2c_afe;
87 struct i2c_client *i2c_repeater;
88 struct i2c_client *i2c_edid;
89 struct i2c_client *i2c_hdmi;
90 struct i2c_client *i2c_test;
91 struct i2c_client *i2c_cp;
92 struct i2c_client *i2c_vdp;
93
94 /* controls */
95 struct v4l2_ctrl *detect_tx_5v_ctrl;
96 struct v4l2_ctrl *analog_sampling_phase_ctrl;
97 struct v4l2_ctrl *free_run_color_manual_ctrl;
98 struct v4l2_ctrl *free_run_color_ctrl;
99 struct v4l2_ctrl *rgb_quantization_range_ctrl;
100 };
101
102 /* Supported CEA and DMT timings */
103 static const struct v4l2_dv_timings adv7604_timings[] = {
104 V4L2_DV_BT_CEA_720X480P59_94,
105 V4L2_DV_BT_CEA_720X576P50,
106 V4L2_DV_BT_CEA_1280X720P24,
107 V4L2_DV_BT_CEA_1280X720P25,
108 V4L2_DV_BT_CEA_1280X720P50,
109 V4L2_DV_BT_CEA_1280X720P60,
110 V4L2_DV_BT_CEA_1920X1080P24,
111 V4L2_DV_BT_CEA_1920X1080P25,
112 V4L2_DV_BT_CEA_1920X1080P30,
113 V4L2_DV_BT_CEA_1920X1080P50,
114 V4L2_DV_BT_CEA_1920X1080P60,
115
116 /* sorted by DMT ID */
117 V4L2_DV_BT_DMT_640X350P85,
118 V4L2_DV_BT_DMT_640X400P85,
119 V4L2_DV_BT_DMT_720X400P85,
120 V4L2_DV_BT_DMT_640X480P60,
121 V4L2_DV_BT_DMT_640X480P72,
122 V4L2_DV_BT_DMT_640X480P75,
123 V4L2_DV_BT_DMT_640X480P85,
124 V4L2_DV_BT_DMT_800X600P56,
125 V4L2_DV_BT_DMT_800X600P60,
126 V4L2_DV_BT_DMT_800X600P72,
127 V4L2_DV_BT_DMT_800X600P75,
128 V4L2_DV_BT_DMT_800X600P85,
129 V4L2_DV_BT_DMT_848X480P60,
130 V4L2_DV_BT_DMT_1024X768P60,
131 V4L2_DV_BT_DMT_1024X768P70,
132 V4L2_DV_BT_DMT_1024X768P75,
133 V4L2_DV_BT_DMT_1024X768P85,
134 V4L2_DV_BT_DMT_1152X864P75,
135 V4L2_DV_BT_DMT_1280X768P60_RB,
136 V4L2_DV_BT_DMT_1280X768P60,
137 V4L2_DV_BT_DMT_1280X768P75,
138 V4L2_DV_BT_DMT_1280X768P85,
139 V4L2_DV_BT_DMT_1280X800P60_RB,
140 V4L2_DV_BT_DMT_1280X800P60,
141 V4L2_DV_BT_DMT_1280X800P75,
142 V4L2_DV_BT_DMT_1280X800P85,
143 V4L2_DV_BT_DMT_1280X960P60,
144 V4L2_DV_BT_DMT_1280X960P85,
145 V4L2_DV_BT_DMT_1280X1024P60,
146 V4L2_DV_BT_DMT_1280X1024P75,
147 V4L2_DV_BT_DMT_1280X1024P85,
148 V4L2_DV_BT_DMT_1360X768P60,
149 V4L2_DV_BT_DMT_1400X1050P60_RB,
150 V4L2_DV_BT_DMT_1400X1050P60,
151 V4L2_DV_BT_DMT_1400X1050P75,
152 V4L2_DV_BT_DMT_1400X1050P85,
153 V4L2_DV_BT_DMT_1440X900P60_RB,
154 V4L2_DV_BT_DMT_1440X900P60,
155 V4L2_DV_BT_DMT_1600X1200P60,
156 V4L2_DV_BT_DMT_1680X1050P60_RB,
157 V4L2_DV_BT_DMT_1680X1050P60,
158 V4L2_DV_BT_DMT_1792X1344P60,
159 V4L2_DV_BT_DMT_1856X1392P60,
160 V4L2_DV_BT_DMT_1920X1200P60_RB,
161 V4L2_DV_BT_DMT_1366X768P60,
162 V4L2_DV_BT_DMT_1920X1080P60,
163 { },
164 };
165
166 struct adv7604_video_standards {
167 struct v4l2_dv_timings timings;
168 u8 vid_std;
169 u8 v_freq;
170 };
171
172 /* sorted by number of lines */
173 static const struct adv7604_video_standards adv7604_prim_mode_comp[] = {
174 /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
175 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
176 { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
177 { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
178 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
179 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
180 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
181 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
182 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
183 /* TODO add 1920x1080P60_RB (CVT timing) */
184 { },
185 };
186
187 /* sorted by number of lines */
188 static const struct adv7604_video_standards adv7604_prim_mode_gr[] = {
189 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
190 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
191 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
192 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
193 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
194 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
195 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
196 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
197 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
198 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
199 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
200 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
201 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
202 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
203 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
204 { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
205 { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
206 { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
207 { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
208 { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */
209 /* TODO add 1600X1200P60_RB (not a DMT timing) */
210 { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
211 { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */
212 { },
213 };
214
215 /* sorted by number of lines */
216 static const struct adv7604_video_standards adv7604_prim_mode_hdmi_comp[] = {
217 { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
218 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
219 { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
220 { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
221 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
222 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
223 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
224 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
225 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
226 { },
227 };
228
229 /* sorted by number of lines */
230 static const struct adv7604_video_standards adv7604_prim_mode_hdmi_gr[] = {
231 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
232 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
233 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
234 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
235 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
236 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
237 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
238 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
239 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
240 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
241 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
242 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
243 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
244 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
245 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
246 { },
247 };
248
249 /* ----------------------------------------------------------------------- */
250
251 static inline struct adv7604_state *to_state(struct v4l2_subdev *sd)
252 {
253 return container_of(sd, struct adv7604_state, sd);
254 }
255
256 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
257 {
258 return &container_of(ctrl->handler, struct adv7604_state, hdl)->sd;
259 }
260
261 static inline unsigned hblanking(const struct v4l2_bt_timings *t)
262 {
263 return t->hfrontporch + t->hsync + t->hbackporch;
264 }
265
266 static inline unsigned htotal(const struct v4l2_bt_timings *t)
267 {
268 return t->width + t->hfrontporch + t->hsync + t->hbackporch;
269 }
270
271 static inline unsigned vblanking(const struct v4l2_bt_timings *t)
272 {
273 return t->vfrontporch + t->vsync + t->vbackporch;
274 }
275
276 static inline unsigned vtotal(const struct v4l2_bt_timings *t)
277 {
278 return t->height + t->vfrontporch + t->vsync + t->vbackporch;
279 }
280
281 /* ----------------------------------------------------------------------- */
282
283 static s32 adv_smbus_read_byte_data_check(struct i2c_client *client,
284 u8 command, bool check)
285 {
286 union i2c_smbus_data data;
287
288 if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags,
289 I2C_SMBUS_READ, command,
290 I2C_SMBUS_BYTE_DATA, &data))
291 return data.byte;
292 if (check)
293 v4l_err(client, "error reading %02x, %02x\n",
294 client->addr, command);
295 return -EIO;
296 }
297
298 static s32 adv_smbus_read_byte_data(struct i2c_client *client, u8 command)
299 {
300 return adv_smbus_read_byte_data_check(client, command, true);
301 }
302
303 static s32 adv_smbus_write_byte_data(struct i2c_client *client,
304 u8 command, u8 value)
305 {
306 union i2c_smbus_data data;
307 int err;
308 int i;
309
310 data.byte = value;
311 for (i = 0; i < 3; i++) {
312 err = i2c_smbus_xfer(client->adapter, client->addr,
313 client->flags,
314 I2C_SMBUS_WRITE, command,
315 I2C_SMBUS_BYTE_DATA, &data);
316 if (!err)
317 break;
318 }
319 if (err < 0)
320 v4l_err(client, "error writing %02x, %02x, %02x\n",
321 client->addr, command, value);
322 return err;
323 }
324
325 static s32 adv_smbus_write_i2c_block_data(struct i2c_client *client,
326 u8 command, unsigned length, const u8 *values)
327 {
328 union i2c_smbus_data data;
329
330 if (length > I2C_SMBUS_BLOCK_MAX)
331 length = I2C_SMBUS_BLOCK_MAX;
332 data.block[0] = length;
333 memcpy(data.block + 1, values, length);
334 return i2c_smbus_xfer(client->adapter, client->addr, client->flags,
335 I2C_SMBUS_WRITE, command,
336 I2C_SMBUS_I2C_BLOCK_DATA, &data);
337 }
338
339 /* ----------------------------------------------------------------------- */
340
341 static inline int io_read(struct v4l2_subdev *sd, u8 reg)
342 {
343 struct i2c_client *client = v4l2_get_subdevdata(sd);
344
345 return adv_smbus_read_byte_data(client, reg);
346 }
347
348 static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
349 {
350 struct i2c_client *client = v4l2_get_subdevdata(sd);
351
352 return adv_smbus_write_byte_data(client, reg, val);
353 }
354
355 static inline int io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
356 {
357 return io_write(sd, reg, (io_read(sd, reg) & mask) | val);
358 }
359
360 static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
361 {
362 struct adv7604_state *state = to_state(sd);
363
364 return adv_smbus_read_byte_data(state->i2c_avlink, reg);
365 }
366
367 static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
368 {
369 struct adv7604_state *state = to_state(sd);
370
371 return adv_smbus_write_byte_data(state->i2c_avlink, reg, val);
372 }
373
374 static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
375 {
376 struct adv7604_state *state = to_state(sd);
377
378 return adv_smbus_read_byte_data(state->i2c_cec, reg);
379 }
380
381 static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
382 {
383 struct adv7604_state *state = to_state(sd);
384
385 return adv_smbus_write_byte_data(state->i2c_cec, reg, val);
386 }
387
388 static inline int cec_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
389 {
390 return cec_write(sd, reg, (cec_read(sd, reg) & mask) | val);
391 }
392
393 static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
394 {
395 struct adv7604_state *state = to_state(sd);
396
397 return adv_smbus_read_byte_data(state->i2c_infoframe, reg);
398 }
399
400 static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
401 {
402 struct adv7604_state *state = to_state(sd);
403
404 return adv_smbus_write_byte_data(state->i2c_infoframe, reg, val);
405 }
406
407 static inline int esdp_read(struct v4l2_subdev *sd, u8 reg)
408 {
409 struct adv7604_state *state = to_state(sd);
410
411 return adv_smbus_read_byte_data(state->i2c_esdp, reg);
412 }
413
414 static inline int esdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
415 {
416 struct adv7604_state *state = to_state(sd);
417
418 return adv_smbus_write_byte_data(state->i2c_esdp, reg, val);
419 }
420
421 static inline int dpp_read(struct v4l2_subdev *sd, u8 reg)
422 {
423 struct adv7604_state *state = to_state(sd);
424
425 return adv_smbus_read_byte_data(state->i2c_dpp, reg);
426 }
427
428 static inline int dpp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
429 {
430 struct adv7604_state *state = to_state(sd);
431
432 return adv_smbus_write_byte_data(state->i2c_dpp, reg, val);
433 }
434
435 static inline int afe_read(struct v4l2_subdev *sd, u8 reg)
436 {
437 struct adv7604_state *state = to_state(sd);
438
439 return adv_smbus_read_byte_data(state->i2c_afe, reg);
440 }
441
442 static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
443 {
444 struct adv7604_state *state = to_state(sd);
445
446 return adv_smbus_write_byte_data(state->i2c_afe, reg, val);
447 }
448
449 static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
450 {
451 struct adv7604_state *state = to_state(sd);
452
453 return adv_smbus_read_byte_data(state->i2c_repeater, reg);
454 }
455
456 static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
457 {
458 struct adv7604_state *state = to_state(sd);
459
460 return adv_smbus_write_byte_data(state->i2c_repeater, reg, val);
461 }
462
463 static inline int rep_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
464 {
465 return rep_write(sd, reg, (rep_read(sd, reg) & mask) | val);
466 }
467
468 static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
469 {
470 struct adv7604_state *state = to_state(sd);
471
472 return adv_smbus_read_byte_data(state->i2c_edid, reg);
473 }
474
475 static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
476 {
477 struct adv7604_state *state = to_state(sd);
478
479 return adv_smbus_write_byte_data(state->i2c_edid, reg, val);
480 }
481
482 static inline int edid_read_block(struct v4l2_subdev *sd, unsigned len, u8 *val)
483 {
484 struct adv7604_state *state = to_state(sd);
485 struct i2c_client *client = state->i2c_edid;
486 u8 msgbuf0[1] = { 0 };
487 u8 msgbuf1[256];
488 struct i2c_msg msg[2] = {
489 {
490 .addr = client->addr,
491 .len = 1,
492 .buf = msgbuf0
493 },
494 {
495 .addr = client->addr,
496 .flags = I2C_M_RD,
497 .len = len,
498 .buf = msgbuf1
499 },
500 };
501
502 if (i2c_transfer(client->adapter, msg, 2) < 0)
503 return -EIO;
504 memcpy(val, msgbuf1, len);
505 return 0;
506 }
507
508 static void adv7604_delayed_work_enable_hotplug(struct work_struct *work)
509 {
510 struct delayed_work *dwork = to_delayed_work(work);
511 struct adv7604_state *state = container_of(dwork, struct adv7604_state,
512 delayed_work_enable_hotplug);
513 struct v4l2_subdev *sd = &state->sd;
514
515 v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__);
516
517 v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)1);
518 }
519
520 static inline int edid_write_block(struct v4l2_subdev *sd,
521 unsigned len, const u8 *val)
522 {
523 struct i2c_client *client = v4l2_get_subdevdata(sd);
524 struct adv7604_state *state = to_state(sd);
525 int err = 0;
526 int i;
527
528 v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n", __func__, len);
529
530 v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)0);
531
532 /* Disables I2C access to internal EDID ram from DDC port */
533 rep_write_and_or(sd, 0x77, 0xf0, 0x0);
534
535 for (i = 0; !err && i < len; i += I2C_SMBUS_BLOCK_MAX)
536 err = adv_smbus_write_i2c_block_data(state->i2c_edid, i,
537 I2C_SMBUS_BLOCK_MAX, val + i);
538 if (err)
539 return err;
540
541 /* adv7604 calculates the checksums and enables I2C access to internal
542 EDID ram from DDC port. */
543 rep_write_and_or(sd, 0x77, 0xf0, 0x1);
544
545 for (i = 0; i < 1000; i++) {
546 if (rep_read(sd, 0x7d) & 1)
547 break;
548 mdelay(1);
549 }
550 if (i == 1000) {
551 v4l_err(client, "error enabling edid\n");
552 return -EIO;
553 }
554
555 /* enable hotplug after 100 ms */
556 queue_delayed_work(state->work_queues,
557 &state->delayed_work_enable_hotplug, HZ / 10);
558 return 0;
559 }
560
561 static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
562 {
563 struct adv7604_state *state = to_state(sd);
564
565 return adv_smbus_read_byte_data(state->i2c_hdmi, reg);
566 }
567
568 static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
569 {
570 struct adv7604_state *state = to_state(sd);
571
572 return adv_smbus_write_byte_data(state->i2c_hdmi, reg, val);
573 }
574
575 static inline int test_read(struct v4l2_subdev *sd, u8 reg)
576 {
577 struct adv7604_state *state = to_state(sd);
578
579 return adv_smbus_read_byte_data(state->i2c_test, reg);
580 }
581
582 static inline int test_write(struct v4l2_subdev *sd, u8 reg, u8 val)
583 {
584 struct adv7604_state *state = to_state(sd);
585
586 return adv_smbus_write_byte_data(state->i2c_test, reg, val);
587 }
588
589 static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
590 {
591 struct adv7604_state *state = to_state(sd);
592
593 return adv_smbus_read_byte_data(state->i2c_cp, reg);
594 }
595
596 static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
597 {
598 struct adv7604_state *state = to_state(sd);
599
600 return adv_smbus_write_byte_data(state->i2c_cp, reg, val);
601 }
602
603 static inline int cp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
604 {
605 return cp_write(sd, reg, (cp_read(sd, reg) & mask) | val);
606 }
607
608 static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
609 {
610 struct adv7604_state *state = to_state(sd);
611
612 return adv_smbus_read_byte_data(state->i2c_vdp, reg);
613 }
614
615 static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
616 {
617 struct adv7604_state *state = to_state(sd);
618
619 return adv_smbus_write_byte_data(state->i2c_vdp, reg, val);
620 }
621
622 /* ----------------------------------------------------------------------- */
623
624 #ifdef CONFIG_VIDEO_ADV_DEBUG
625 static void adv7604_inv_register(struct v4l2_subdev *sd)
626 {
627 v4l2_info(sd, "0x000-0x0ff: IO Map\n");
628 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
629 v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
630 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
631 v4l2_info(sd, "0x400-0x4ff: ESDP Map\n");
632 v4l2_info(sd, "0x500-0x5ff: DPP Map\n");
633 v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
634 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
635 v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
636 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
637 v4l2_info(sd, "0xa00-0xaff: Test Map\n");
638 v4l2_info(sd, "0xb00-0xbff: CP Map\n");
639 v4l2_info(sd, "0xc00-0xcff: VDP Map\n");
640 }
641
642 static int adv7604_g_register(struct v4l2_subdev *sd,
643 struct v4l2_dbg_register *reg)
644 {
645 reg->size = 1;
646 switch (reg->reg >> 8) {
647 case 0:
648 reg->val = io_read(sd, reg->reg & 0xff);
649 break;
650 case 1:
651 reg->val = avlink_read(sd, reg->reg & 0xff);
652 break;
653 case 2:
654 reg->val = cec_read(sd, reg->reg & 0xff);
655 break;
656 case 3:
657 reg->val = infoframe_read(sd, reg->reg & 0xff);
658 break;
659 case 4:
660 reg->val = esdp_read(sd, reg->reg & 0xff);
661 break;
662 case 5:
663 reg->val = dpp_read(sd, reg->reg & 0xff);
664 break;
665 case 6:
666 reg->val = afe_read(sd, reg->reg & 0xff);
667 break;
668 case 7:
669 reg->val = rep_read(sd, reg->reg & 0xff);
670 break;
671 case 8:
672 reg->val = edid_read(sd, reg->reg & 0xff);
673 break;
674 case 9:
675 reg->val = hdmi_read(sd, reg->reg & 0xff);
676 break;
677 case 0xa:
678 reg->val = test_read(sd, reg->reg & 0xff);
679 break;
680 case 0xb:
681 reg->val = cp_read(sd, reg->reg & 0xff);
682 break;
683 case 0xc:
684 reg->val = vdp_read(sd, reg->reg & 0xff);
685 break;
686 default:
687 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
688 adv7604_inv_register(sd);
689 break;
690 }
691 return 0;
692 }
693
694 static int adv7604_s_register(struct v4l2_subdev *sd,
695 const struct v4l2_dbg_register *reg)
696 {
697 switch (reg->reg >> 8) {
698 case 0:
699 io_write(sd, reg->reg & 0xff, reg->val & 0xff);
700 break;
701 case 1:
702 avlink_write(sd, reg->reg & 0xff, reg->val & 0xff);
703 break;
704 case 2:
705 cec_write(sd, reg->reg & 0xff, reg->val & 0xff);
706 break;
707 case 3:
708 infoframe_write(sd, reg->reg & 0xff, reg->val & 0xff);
709 break;
710 case 4:
711 esdp_write(sd, reg->reg & 0xff, reg->val & 0xff);
712 break;
713 case 5:
714 dpp_write(sd, reg->reg & 0xff, reg->val & 0xff);
715 break;
716 case 6:
717 afe_write(sd, reg->reg & 0xff, reg->val & 0xff);
718 break;
719 case 7:
720 rep_write(sd, reg->reg & 0xff, reg->val & 0xff);
721 break;
722 case 8:
723 edid_write(sd, reg->reg & 0xff, reg->val & 0xff);
724 break;
725 case 9:
726 hdmi_write(sd, reg->reg & 0xff, reg->val & 0xff);
727 break;
728 case 0xa:
729 test_write(sd, reg->reg & 0xff, reg->val & 0xff);
730 break;
731 case 0xb:
732 cp_write(sd, reg->reg & 0xff, reg->val & 0xff);
733 break;
734 case 0xc:
735 vdp_write(sd, reg->reg & 0xff, reg->val & 0xff);
736 break;
737 default:
738 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
739 adv7604_inv_register(sd);
740 break;
741 }
742 return 0;
743 }
744 #endif
745
746 static int adv7604_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
747 {
748 struct adv7604_state *state = to_state(sd);
749
750 /* port A only */
751 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl,
752 ((io_read(sd, 0x6f) & 0x10) >> 4));
753 }
754
755 static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
756 u8 prim_mode,
757 const struct adv7604_video_standards *predef_vid_timings,
758 const struct v4l2_dv_timings *timings)
759 {
760 struct adv7604_state *state = to_state(sd);
761 int i;
762
763 for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {
764 if (!v4l_match_dv_timings(timings, &predef_vid_timings[i].timings,
765 DIGITAL_INPUT ? 250000 : 1000000))
766 continue;
767 io_write(sd, 0x00, predef_vid_timings[i].vid_std); /* video std */
768 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) +
769 prim_mode); /* v_freq and prim mode */
770 return 0;
771 }
772
773 return -1;
774 }
775
776 static int configure_predefined_video_timings(struct v4l2_subdev *sd,
777 struct v4l2_dv_timings *timings)
778 {
779 struct adv7604_state *state = to_state(sd);
780 int err;
781
782 v4l2_dbg(1, debug, sd, "%s", __func__);
783
784 /* reset to default values */
785 io_write(sd, 0x16, 0x43);
786 io_write(sd, 0x17, 0x5a);
787 /* disable embedded syncs for auto graphics mode */
788 cp_write_and_or(sd, 0x81, 0xef, 0x00);
789 cp_write(sd, 0x8f, 0x00);
790 cp_write(sd, 0x90, 0x00);
791 cp_write(sd, 0xa2, 0x00);
792 cp_write(sd, 0xa3, 0x00);
793 cp_write(sd, 0xa4, 0x00);
794 cp_write(sd, 0xa5, 0x00);
795 cp_write(sd, 0xa6, 0x00);
796 cp_write(sd, 0xa7, 0x00);
797 cp_write(sd, 0xab, 0x00);
798 cp_write(sd, 0xac, 0x00);
799
800 switch (state->mode) {
801 case ADV7604_MODE_COMP:
802 case ADV7604_MODE_GR:
803 err = find_and_set_predefined_video_timings(sd,
804 0x01, adv7604_prim_mode_comp, timings);
805 if (err)
806 err = find_and_set_predefined_video_timings(sd,
807 0x02, adv7604_prim_mode_gr, timings);
808 break;
809 case ADV7604_MODE_HDMI:
810 err = find_and_set_predefined_video_timings(sd,
811 0x05, adv7604_prim_mode_hdmi_comp, timings);
812 if (err)
813 err = find_and_set_predefined_video_timings(sd,
814 0x06, adv7604_prim_mode_hdmi_gr, timings);
815 break;
816 default:
817 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
818 __func__, state->mode);
819 err = -1;
820 break;
821 }
822
823
824 return err;
825 }
826
827 static void configure_custom_video_timings(struct v4l2_subdev *sd,
828 const struct v4l2_bt_timings *bt)
829 {
830 struct adv7604_state *state = to_state(sd);
831 struct i2c_client *client = v4l2_get_subdevdata(sd);
832 u32 width = htotal(bt);
833 u32 height = vtotal(bt);
834 u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
835 u16 cp_start_eav = width - bt->hfrontporch;
836 u16 cp_start_vbi = height - bt->vfrontporch;
837 u16 cp_end_vbi = bt->vsync + bt->vbackporch;
838 u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
839 ((width * (ADV7604_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0;
840 const u8 pll[2] = {
841 0xc0 | ((width >> 8) & 0x1f),
842 width & 0xff
843 };
844
845 v4l2_dbg(2, debug, sd, "%s\n", __func__);
846
847 switch (state->mode) {
848 case ADV7604_MODE_COMP:
849 case ADV7604_MODE_GR:
850 /* auto graphics */
851 io_write(sd, 0x00, 0x07); /* video std */
852 io_write(sd, 0x01, 0x02); /* prim mode */
853 /* enable embedded syncs for auto graphics mode */
854 cp_write_and_or(sd, 0x81, 0xef, 0x10);
855
856 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
857 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
858 /* IO-map reg. 0x16 and 0x17 should be written in sequence */
859 if (adv_smbus_write_i2c_block_data(client, 0x16, 2, pll)) {
860 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
861 break;
862 }
863
864 /* active video - horizontal timing */
865 cp_write(sd, 0xa2, (cp_start_sav >> 4) & 0xff);
866 cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) |
867 ((cp_start_eav >> 8) & 0x0f));
868 cp_write(sd, 0xa4, cp_start_eav & 0xff);
869
870 /* active video - vertical timing */
871 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
872 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
873 ((cp_end_vbi >> 8) & 0xf));
874 cp_write(sd, 0xa7, cp_end_vbi & 0xff);
875 break;
876 case ADV7604_MODE_HDMI:
877 /* set default prim_mode/vid_std for HDMI
878 accoring to [REF_03, c. 4.2] */
879 io_write(sd, 0x00, 0x02); /* video std */
880 io_write(sd, 0x01, 0x06); /* prim mode */
881 break;
882 default:
883 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
884 __func__, state->mode);
885 break;
886 }
887
888 cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
889 cp_write(sd, 0x90, ch1_fr_ll & 0xff);
890 cp_write(sd, 0xab, (height >> 4) & 0xff);
891 cp_write(sd, 0xac, (height & 0x0f) << 4);
892 }
893
894 static void set_rgb_quantization_range(struct v4l2_subdev *sd)
895 {
896 struct adv7604_state *state = to_state(sd);
897
898 switch (state->rgb_quantization_range) {
899 case V4L2_DV_RGB_RANGE_AUTO:
900 /* automatic */
901 if (DIGITAL_INPUT && !(hdmi_read(sd, 0x05) & 0x80)) {
902 /* receiving DVI-D signal */
903
904 /* ADV7604 selects RGB limited range regardless of
905 input format (CE/IT) in automatic mode */
906 if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
907 /* RGB limited range (16-235) */
908 io_write_and_or(sd, 0x02, 0x0f, 0x00);
909
910 } else {
911 /* RGB full range (0-255) */
912 io_write_and_or(sd, 0x02, 0x0f, 0x10);
913 }
914 } else {
915 /* receiving HDMI or analog signal, set automode */
916 io_write_and_or(sd, 0x02, 0x0f, 0xf0);
917 }
918 break;
919 case V4L2_DV_RGB_RANGE_LIMITED:
920 /* RGB limited range (16-235) */
921 io_write_and_or(sd, 0x02, 0x0f, 0x00);
922 break;
923 case V4L2_DV_RGB_RANGE_FULL:
924 /* RGB full range (0-255) */
925 io_write_and_or(sd, 0x02, 0x0f, 0x10);
926 break;
927 }
928 }
929
930
931 static int adv7604_s_ctrl(struct v4l2_ctrl *ctrl)
932 {
933 struct v4l2_subdev *sd = to_sd(ctrl);
934 struct adv7604_state *state = to_state(sd);
935
936 switch (ctrl->id) {
937 case V4L2_CID_BRIGHTNESS:
938 cp_write(sd, 0x3c, ctrl->val);
939 return 0;
940 case V4L2_CID_CONTRAST:
941 cp_write(sd, 0x3a, ctrl->val);
942 return 0;
943 case V4L2_CID_SATURATION:
944 cp_write(sd, 0x3b, ctrl->val);
945 return 0;
946 case V4L2_CID_HUE:
947 cp_write(sd, 0x3d, ctrl->val);
948 return 0;
949 case V4L2_CID_DV_RX_RGB_RANGE:
950 state->rgb_quantization_range = ctrl->val;
951 set_rgb_quantization_range(sd);
952 return 0;
953 case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
954 /* Set the analog sampling phase. This is needed to find the
955 best sampling phase for analog video: an application or
956 driver has to try a number of phases and analyze the picture
957 quality before settling on the best performing phase. */
958 afe_write(sd, 0xc8, ctrl->val);
959 return 0;
960 case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:
961 /* Use the default blue color for free running mode,
962 or supply your own. */
963 cp_write_and_or(sd, 0xbf, ~0x04, (ctrl->val << 2));
964 return 0;
965 case V4L2_CID_ADV_RX_FREE_RUN_COLOR:
966 cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16);
967 cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8);
968 cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff));
969 return 0;
970 }
971 return -EINVAL;
972 }
973
974 /* ----------------------------------------------------------------------- */
975
976 static inline bool no_power(struct v4l2_subdev *sd)
977 {
978 /* Entire chip or CP powered off */
979 return io_read(sd, 0x0c) & 0x24;
980 }
981
982 static inline bool no_signal_tmds(struct v4l2_subdev *sd)
983 {
984 /* TODO port B, C and D */
985 return !(io_read(sd, 0x6a) & 0x10);
986 }
987
988 static inline bool no_lock_tmds(struct v4l2_subdev *sd)
989 {
990 return (io_read(sd, 0x6a) & 0xe0) != 0xe0;
991 }
992
993 static inline bool no_lock_sspd(struct v4l2_subdev *sd)
994 {
995 /* TODO channel 2 */
996 return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0);
997 }
998
999 static inline bool no_lock_stdi(struct v4l2_subdev *sd)
1000 {
1001 /* TODO channel 2 */
1002 return !(cp_read(sd, 0xb1) & 0x80);
1003 }
1004
1005 static inline bool no_signal(struct v4l2_subdev *sd)
1006 {
1007 struct adv7604_state *state = to_state(sd);
1008 bool ret;
1009
1010 ret = no_power(sd);
1011
1012 ret |= no_lock_stdi(sd);
1013 ret |= no_lock_sspd(sd);
1014
1015 if (DIGITAL_INPUT) {
1016 ret |= no_lock_tmds(sd);
1017 ret |= no_signal_tmds(sd);
1018 }
1019
1020 return ret;
1021 }
1022
1023 static inline bool no_lock_cp(struct v4l2_subdev *sd)
1024 {
1025 /* CP has detected a non standard number of lines on the incoming
1026 video compared to what it is configured to receive by s_dv_timings */
1027 return io_read(sd, 0x12) & 0x01;
1028 }
1029
1030 static int adv7604_g_input_status(struct v4l2_subdev *sd, u32 *status)
1031 {
1032 struct adv7604_state *state = to_state(sd);
1033
1034 *status = 0;
1035 *status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0;
1036 *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
1037 if (no_lock_cp(sd))
1038 *status |= DIGITAL_INPUT ? V4L2_IN_ST_NO_SYNC : V4L2_IN_ST_NO_H_LOCK;
1039
1040 v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
1041
1042 return 0;
1043 }
1044
1045 /* ----------------------------------------------------------------------- */
1046
1047 static void adv7604_print_timings(struct v4l2_subdev *sd,
1048 struct v4l2_dv_timings *timings, const char *txt, bool detailed)
1049 {
1050 struct v4l2_bt_timings *bt = &timings->bt;
1051 u32 htot, vtot;
1052
1053 if (timings->type != V4L2_DV_BT_656_1120)
1054 return;
1055
1056 htot = htotal(bt);
1057 vtot = vtotal(bt);
1058
1059 v4l2_info(sd, "%s %dx%d%s%d (%dx%d)",
1060 txt, bt->width, bt->height, bt->interlaced ? "i" : "p",
1061 (htot * vtot) > 0 ? ((u32)bt->pixelclock /
1062 (htot * vtot)) : 0,
1063 htot, vtot);
1064
1065 if (detailed) {
1066 v4l2_info(sd, " horizontal: fp = %d, %ssync = %d, bp = %d\n",
1067 bt->hfrontporch,
1068 (bt->polarities & V4L2_DV_HSYNC_POS_POL) ? "+" : "-",
1069 bt->hsync, bt->hbackporch);
1070 v4l2_info(sd, " vertical: fp = %d, %ssync = %d, bp = %d\n",
1071 bt->vfrontporch,
1072 (bt->polarities & V4L2_DV_VSYNC_POS_POL) ? "+" : "-",
1073 bt->vsync, bt->vbackporch);
1074 v4l2_info(sd, " pixelclock: %lld, flags: 0x%x, standards: 0x%x\n",
1075 bt->pixelclock, bt->flags, bt->standards);
1076 }
1077 }
1078
1079 struct stdi_readback {
1080 u16 bl, lcf, lcvs;
1081 u8 hs_pol, vs_pol;
1082 bool interlaced;
1083 };
1084
1085 static int stdi2dv_timings(struct v4l2_subdev *sd,
1086 struct stdi_readback *stdi,
1087 struct v4l2_dv_timings *timings)
1088 {
1089 struct adv7604_state *state = to_state(sd);
1090 u32 hfreq = (ADV7604_fsc * 8) / stdi->bl;
1091 u32 pix_clk;
1092 int i;
1093
1094 for (i = 0; adv7604_timings[i].bt.height; i++) {
1095 if (vtotal(&adv7604_timings[i].bt) != stdi->lcf + 1)
1096 continue;
1097 if (adv7604_timings[i].bt.vsync != stdi->lcvs)
1098 continue;
1099
1100 pix_clk = hfreq * htotal(&adv7604_timings[i].bt);
1101
1102 if ((pix_clk < adv7604_timings[i].bt.pixelclock + 1000000) &&
1103 (pix_clk > adv7604_timings[i].bt.pixelclock - 1000000)) {
1104 *timings = adv7604_timings[i];
1105 return 0;
1106 }
1107 }
1108
1109 if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs,
1110 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1111 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1112 timings))
1113 return 0;
1114 if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,
1115 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1116 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1117 state->aspect_ratio, timings))
1118 return 0;
1119
1120 v4l2_dbg(2, debug, sd,
1121 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
1122 __func__, stdi->lcvs, stdi->lcf, stdi->bl,
1123 stdi->hs_pol, stdi->vs_pol);
1124 return -1;
1125 }
1126
1127 static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1128 {
1129 if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1130 v4l2_dbg(2, debug, sd, "%s: STDI and/or SSPD not locked\n", __func__);
1131 return -1;
1132 }
1133
1134 /* read STDI */
1135 stdi->bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);
1136 stdi->lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);
1137 stdi->lcvs = cp_read(sd, 0xb3) >> 3;
1138 stdi->interlaced = io_read(sd, 0x12) & 0x10;
1139
1140 /* read SSPD */
1141 if ((cp_read(sd, 0xb5) & 0x03) == 0x01) {
1142 stdi->hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?
1143 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');
1144 stdi->vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?
1145 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');
1146 } else {
1147 stdi->hs_pol = 'x';
1148 stdi->vs_pol = 'x';
1149 }
1150
1151 if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1152 v4l2_dbg(2, debug, sd,
1153 "%s: signal lost during readout of STDI/SSPD\n", __func__);
1154 return -1;
1155 }
1156
1157 if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {
1158 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
1159 memset(stdi, 0, sizeof(struct stdi_readback));
1160 return -1;
1161 }
1162
1163 v4l2_dbg(2, debug, sd,
1164 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
1165 __func__, stdi->lcf, stdi->bl, stdi->lcvs,
1166 stdi->hs_pol, stdi->vs_pol,
1167 stdi->interlaced ? "interlaced" : "progressive");
1168
1169 return 0;
1170 }
1171
1172 static int adv7604_enum_dv_timings(struct v4l2_subdev *sd,
1173 struct v4l2_enum_dv_timings *timings)
1174 {
1175 if (timings->index >= ARRAY_SIZE(adv7604_timings) - 1)
1176 return -EINVAL;
1177 memset(timings->reserved, 0, sizeof(timings->reserved));
1178 timings->timings = adv7604_timings[timings->index];
1179 return 0;
1180 }
1181
1182 static int adv7604_dv_timings_cap(struct v4l2_subdev *sd,
1183 struct v4l2_dv_timings_cap *cap)
1184 {
1185 struct adv7604_state *state = to_state(sd);
1186
1187 cap->type = V4L2_DV_BT_656_1120;
1188 cap->bt.max_width = 1920;
1189 cap->bt.max_height = 1200;
1190 cap->bt.min_pixelclock = 27000000;
1191 if (DIGITAL_INPUT)
1192 cap->bt.max_pixelclock = 225000000;
1193 else
1194 cap->bt.max_pixelclock = 170000000;
1195 cap->bt.standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
1196 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT;
1197 cap->bt.capabilities = V4L2_DV_BT_CAP_PROGRESSIVE |
1198 V4L2_DV_BT_CAP_REDUCED_BLANKING | V4L2_DV_BT_CAP_CUSTOM;
1199 return 0;
1200 }
1201
1202 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
1203 if the format is listed in adv7604_timings[] */
1204 static void adv7604_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
1205 struct v4l2_dv_timings *timings)
1206 {
1207 struct adv7604_state *state = to_state(sd);
1208 int i;
1209
1210 for (i = 0; adv7604_timings[i].bt.width; i++) {
1211 if (v4l_match_dv_timings(timings, &adv7604_timings[i],
1212 DIGITAL_INPUT ? 250000 : 1000000)) {
1213 *timings = adv7604_timings[i];
1214 break;
1215 }
1216 }
1217 }
1218
1219 static int adv7604_query_dv_timings(struct v4l2_subdev *sd,
1220 struct v4l2_dv_timings *timings)
1221 {
1222 struct adv7604_state *state = to_state(sd);
1223 struct v4l2_bt_timings *bt = &timings->bt;
1224 struct stdi_readback stdi;
1225
1226 if (!timings)
1227 return -EINVAL;
1228
1229 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1230
1231 if (no_signal(sd)) {
1232 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
1233 return -ENOLINK;
1234 }
1235
1236 /* read STDI */
1237 if (read_stdi(sd, &stdi)) {
1238 v4l2_dbg(1, debug, sd, "%s: STDI/SSPD not locked\n", __func__);
1239 return -ENOLINK;
1240 }
1241 bt->interlaced = stdi.interlaced ?
1242 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
1243
1244 if (DIGITAL_INPUT) {
1245 timings->type = V4L2_DV_BT_656_1120;
1246
1247 bt->width = (hdmi_read(sd, 0x07) & 0x0f) * 256 + hdmi_read(sd, 0x08);
1248 bt->height = (hdmi_read(sd, 0x09) & 0x0f) * 256 + hdmi_read(sd, 0x0a);
1249 bt->pixelclock = (hdmi_read(sd, 0x06) * 1000000) +
1250 ((hdmi_read(sd, 0x3b) & 0x30) >> 4) * 250000;
1251 bt->hfrontporch = (hdmi_read(sd, 0x20) & 0x03) * 256 +
1252 hdmi_read(sd, 0x21);
1253 bt->hsync = (hdmi_read(sd, 0x22) & 0x03) * 256 +
1254 hdmi_read(sd, 0x23);
1255 bt->hbackporch = (hdmi_read(sd, 0x24) & 0x03) * 256 +
1256 hdmi_read(sd, 0x25);
1257 bt->vfrontporch = ((hdmi_read(sd, 0x2a) & 0x1f) * 256 +
1258 hdmi_read(sd, 0x2b)) / 2;
1259 bt->vsync = ((hdmi_read(sd, 0x2e) & 0x1f) * 256 +
1260 hdmi_read(sd, 0x2f)) / 2;
1261 bt->vbackporch = ((hdmi_read(sd, 0x32) & 0x1f) * 256 +
1262 hdmi_read(sd, 0x33)) / 2;
1263 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
1264 ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
1265 if (bt->interlaced == V4L2_DV_INTERLACED) {
1266 bt->height += (hdmi_read(sd, 0x0b) & 0x0f) * 256 +
1267 hdmi_read(sd, 0x0c);
1268 bt->il_vfrontporch = ((hdmi_read(sd, 0x2c) & 0x1f) * 256 +
1269 hdmi_read(sd, 0x2d)) / 2;
1270 bt->il_vsync = ((hdmi_read(sd, 0x30) & 0x1f) * 256 +
1271 hdmi_read(sd, 0x31)) / 2;
1272 bt->vbackporch = ((hdmi_read(sd, 0x34) & 0x1f) * 256 +
1273 hdmi_read(sd, 0x35)) / 2;
1274 }
1275 adv7604_fill_optional_dv_timings_fields(sd, timings);
1276 } else {
1277 /* find format
1278 * Since LCVS values are inaccurate [REF_03, p. 275-276],
1279 * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails.
1280 */
1281 if (!stdi2dv_timings(sd, &stdi, timings))
1282 goto found;
1283 stdi.lcvs += 1;
1284 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs);
1285 if (!stdi2dv_timings(sd, &stdi, timings))
1286 goto found;
1287 stdi.lcvs -= 2;
1288 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs);
1289 if (stdi2dv_timings(sd, &stdi, timings)) {
1290 /*
1291 * The STDI block may measure wrong values, especially
1292 * for lcvs and lcf. If the driver can not find any
1293 * valid timing, the STDI block is restarted to measure
1294 * the video timings again. The function will return an
1295 * error, but the restart of STDI will generate a new
1296 * STDI interrupt and the format detection process will
1297 * restart.
1298 */
1299 if (state->restart_stdi_once) {
1300 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__);
1301 /* TODO restart STDI for Sync Channel 2 */
1302 /* enter one-shot mode */
1303 cp_write_and_or(sd, 0x86, 0xf9, 0x00);
1304 /* trigger STDI restart */
1305 cp_write_and_or(sd, 0x86, 0xf9, 0x04);
1306 /* reset to continuous mode */
1307 cp_write_and_or(sd, 0x86, 0xf9, 0x02);
1308 state->restart_stdi_once = false;
1309 return -ENOLINK;
1310 }
1311 v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
1312 return -ERANGE;
1313 }
1314 state->restart_stdi_once = true;
1315 }
1316 found:
1317
1318 if (no_signal(sd)) {
1319 v4l2_dbg(1, debug, sd, "%s: signal lost during readout\n", __func__);
1320 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1321 return -ENOLINK;
1322 }
1323
1324 if ((!DIGITAL_INPUT && bt->pixelclock > 170000000) ||
1325 (DIGITAL_INPUT && bt->pixelclock > 225000000)) {
1326 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1327 __func__, (u32)bt->pixelclock);
1328 return -ERANGE;
1329 }
1330
1331 if (debug > 1)
1332 adv7604_print_timings(sd, timings,
1333 "adv7604_query_dv_timings:", true);
1334
1335 return 0;
1336 }
1337
1338 static int adv7604_s_dv_timings(struct v4l2_subdev *sd,
1339 struct v4l2_dv_timings *timings)
1340 {
1341 struct adv7604_state *state = to_state(sd);
1342 struct v4l2_bt_timings *bt;
1343 int err;
1344
1345 if (!timings)
1346 return -EINVAL;
1347
1348 bt = &timings->bt;
1349
1350 if ((!DIGITAL_INPUT && bt->pixelclock > 170000000) ||
1351 (DIGITAL_INPUT && bt->pixelclock > 225000000)) {
1352 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1353 __func__, (u32)bt->pixelclock);
1354 return -ERANGE;
1355 }
1356
1357 adv7604_fill_optional_dv_timings_fields(sd, timings);
1358
1359 state->timings = *timings;
1360
1361 cp_write(sd, 0x91, bt->interlaced ? 0x50 : 0x10);
1362
1363 /* Use prim_mode and vid_std when available */
1364 err = configure_predefined_video_timings(sd, timings);
1365 if (err) {
1366 /* custom settings when the video format
1367 does not have prim_mode/vid_std */
1368 configure_custom_video_timings(sd, bt);
1369 }
1370
1371 set_rgb_quantization_range(sd);
1372
1373
1374 if (debug > 1)
1375 adv7604_print_timings(sd, timings,
1376 "adv7604_s_dv_timings:", true);
1377 return 0;
1378 }
1379
1380 static int adv7604_g_dv_timings(struct v4l2_subdev *sd,
1381 struct v4l2_dv_timings *timings)
1382 {
1383 struct adv7604_state *state = to_state(sd);
1384
1385 *timings = state->timings;
1386 return 0;
1387 }
1388
1389 static void enable_input(struct v4l2_subdev *sd)
1390 {
1391 struct adv7604_state *state = to_state(sd);
1392
1393 switch (state->mode) {
1394 case ADV7604_MODE_COMP:
1395 case ADV7604_MODE_GR:
1396 /* enable */
1397 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */
1398 break;
1399 case ADV7604_MODE_HDMI:
1400 /* enable */
1401 hdmi_write(sd, 0x1a, 0x0a); /* Unmute audio */
1402 hdmi_write(sd, 0x01, 0x00); /* Enable HDMI clock terminators */
1403 io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */
1404 break;
1405 default:
1406 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1407 __func__, state->mode);
1408 break;
1409 }
1410 }
1411
1412 static void disable_input(struct v4l2_subdev *sd)
1413 {
1414 /* disable */
1415 io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */
1416 hdmi_write(sd, 0x1a, 0x1a); /* Mute audio */
1417 hdmi_write(sd, 0x01, 0x78); /* Disable HDMI clock terminators */
1418 }
1419
1420 static void select_input(struct v4l2_subdev *sd)
1421 {
1422 struct adv7604_state *state = to_state(sd);
1423
1424 switch (state->mode) {
1425 case ADV7604_MODE_COMP:
1426 case ADV7604_MODE_GR:
1427 /* reset ADI recommended settings for HDMI: */
1428 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
1429 hdmi_write(sd, 0x0d, 0x04); /* HDMI filter optimization */
1430 hdmi_write(sd, 0x3d, 0x00); /* DDC bus active pull-up control */
1431 hdmi_write(sd, 0x3e, 0x74); /* TMDS PLL optimization */
1432 hdmi_write(sd, 0x4e, 0x3b); /* TMDS PLL optimization */
1433 hdmi_write(sd, 0x57, 0x74); /* TMDS PLL optimization */
1434 hdmi_write(sd, 0x58, 0x63); /* TMDS PLL optimization */
1435 hdmi_write(sd, 0x8d, 0x18); /* equaliser */
1436 hdmi_write(sd, 0x8e, 0x34); /* equaliser */
1437 hdmi_write(sd, 0x93, 0x88); /* equaliser */
1438 hdmi_write(sd, 0x94, 0x2e); /* equaliser */
1439 hdmi_write(sd, 0x96, 0x00); /* enable automatic EQ changing */
1440
1441 afe_write(sd, 0x00, 0x08); /* power up ADC */
1442 afe_write(sd, 0x01, 0x06); /* power up Analog Front End */
1443 afe_write(sd, 0xc8, 0x00); /* phase control */
1444
1445 /* set ADI recommended settings for digitizer */
1446 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
1447 afe_write(sd, 0x12, 0x7b); /* ADC noise shaping filter controls */
1448 afe_write(sd, 0x0c, 0x1f); /* CP core gain controls */
1449 cp_write(sd, 0x3e, 0x04); /* CP core pre-gain control */
1450 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1451 cp_write(sd, 0x40, 0x5c); /* CP core pre-gain control. Graphics mode */
1452 break;
1453
1454 case ADV7604_MODE_HDMI:
1455 /* set ADI recommended settings for HDMI: */
1456 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
1457 hdmi_write(sd, 0x0d, 0x84); /* HDMI filter optimization */
1458 hdmi_write(sd, 0x3d, 0x10); /* DDC bus active pull-up control */
1459 hdmi_write(sd, 0x3e, 0x39); /* TMDS PLL optimization */
1460 hdmi_write(sd, 0x4e, 0x3b); /* TMDS PLL optimization */
1461 hdmi_write(sd, 0x57, 0xb6); /* TMDS PLL optimization */
1462 hdmi_write(sd, 0x58, 0x03); /* TMDS PLL optimization */
1463 hdmi_write(sd, 0x8d, 0x18); /* equaliser */
1464 hdmi_write(sd, 0x8e, 0x34); /* equaliser */
1465 hdmi_write(sd, 0x93, 0x8b); /* equaliser */
1466 hdmi_write(sd, 0x94, 0x2d); /* equaliser */
1467 hdmi_write(sd, 0x96, 0x01); /* enable automatic EQ changing */
1468
1469 afe_write(sd, 0x00, 0xff); /* power down ADC */
1470 afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */
1471 afe_write(sd, 0xc8, 0x40); /* phase control */
1472
1473 /* reset ADI recommended settings for digitizer */
1474 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
1475 afe_write(sd, 0x12, 0xfb); /* ADC noise shaping filter controls */
1476 afe_write(sd, 0x0c, 0x0d); /* CP core gain controls */
1477 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */
1478 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1479 cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */
1480
1481 break;
1482 default:
1483 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1484 __func__, state->mode);
1485 break;
1486 }
1487 }
1488
1489 static int adv7604_s_routing(struct v4l2_subdev *sd,
1490 u32 input, u32 output, u32 config)
1491 {
1492 struct adv7604_state *state = to_state(sd);
1493
1494 v4l2_dbg(2, debug, sd, "%s: input %d", __func__, input);
1495
1496 state->mode = input;
1497
1498 disable_input(sd);
1499
1500 select_input(sd);
1501
1502 enable_input(sd);
1503
1504 return 0;
1505 }
1506
1507 static int adv7604_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned int index,
1508 enum v4l2_mbus_pixelcode *code)
1509 {
1510 if (index)
1511 return -EINVAL;
1512 /* Good enough for now */
1513 *code = V4L2_MBUS_FMT_FIXED;
1514 return 0;
1515 }
1516
1517 static int adv7604_g_mbus_fmt(struct v4l2_subdev *sd,
1518 struct v4l2_mbus_framefmt *fmt)
1519 {
1520 struct adv7604_state *state = to_state(sd);
1521
1522 fmt->width = state->timings.bt.width;
1523 fmt->height = state->timings.bt.height;
1524 fmt->code = V4L2_MBUS_FMT_FIXED;
1525 fmt->field = V4L2_FIELD_NONE;
1526 if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
1527 fmt->colorspace = (state->timings.bt.height <= 576) ?
1528 V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
1529 }
1530 return 0;
1531 }
1532
1533 static int adv7604_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
1534 {
1535 struct adv7604_state *state = to_state(sd);
1536 u8 fmt_change, fmt_change_digital, tx_5v;
1537
1538 /* format change */
1539 fmt_change = io_read(sd, 0x43) & 0x98;
1540 if (fmt_change)
1541 io_write(sd, 0x44, fmt_change);
1542 fmt_change_digital = DIGITAL_INPUT ? (io_read(sd, 0x6b) & 0xc0) : 0;
1543 if (fmt_change_digital)
1544 io_write(sd, 0x6c, fmt_change_digital);
1545 if (fmt_change || fmt_change_digital) {
1546 v4l2_dbg(1, debug, sd,
1547 "%s: ADV7604_FMT_CHANGE, fmt_change = 0x%x, fmt_change_digital = 0x%x\n",
1548 __func__, fmt_change, fmt_change_digital);
1549 v4l2_subdev_notify(sd, ADV7604_FMT_CHANGE, NULL);
1550 if (handled)
1551 *handled = true;
1552 }
1553 /* tx 5v detect */
1554 tx_5v = io_read(sd, 0x70) & 0x10;
1555 if (tx_5v) {
1556 v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v);
1557 io_write(sd, 0x71, tx_5v);
1558 adv7604_s_detect_tx_5v_ctrl(sd);
1559 if (handled)
1560 *handled = true;
1561 }
1562 return 0;
1563 }
1564
1565 static int adv7604_get_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *edid)
1566 {
1567 struct adv7604_state *state = to_state(sd);
1568
1569 if (edid->pad != 0)
1570 return -EINVAL;
1571 if (edid->blocks == 0)
1572 return -EINVAL;
1573 if (edid->start_block >= state->edid_blocks)
1574 return -EINVAL;
1575 if (edid->start_block + edid->blocks > state->edid_blocks)
1576 edid->blocks = state->edid_blocks - edid->start_block;
1577 if (!edid->edid)
1578 return -EINVAL;
1579 memcpy(edid->edid + edid->start_block * 128,
1580 state->edid + edid->start_block * 128,
1581 edid->blocks * 128);
1582 return 0;
1583 }
1584
1585 static int adv7604_set_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *edid)
1586 {
1587 struct adv7604_state *state = to_state(sd);
1588 int err;
1589
1590 if (edid->pad != 0)
1591 return -EINVAL;
1592 if (edid->start_block != 0)
1593 return -EINVAL;
1594 if (edid->blocks == 0) {
1595 /* Pull down the hotplug pin */
1596 v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)0);
1597 /* Disables I2C access to internal EDID ram from DDC port */
1598 rep_write_and_or(sd, 0x77, 0xf0, 0x0);
1599 state->edid_blocks = 0;
1600 /* Fall back to a 16:9 aspect ratio */
1601 state->aspect_ratio.numerator = 16;
1602 state->aspect_ratio.denominator = 9;
1603 return 0;
1604 }
1605 if (edid->blocks > 2)
1606 return -E2BIG;
1607 if (!edid->edid)
1608 return -EINVAL;
1609 memcpy(state->edid, edid->edid, 128 * edid->blocks);
1610 state->edid_blocks = edid->blocks;
1611 state->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15],
1612 edid->edid[0x16]);
1613 err = edid_write_block(sd, 128 * edid->blocks, state->edid);
1614 if (err < 0)
1615 v4l2_err(sd, "error %d writing edid\n", err);
1616 return err;
1617 }
1618
1619 /*********** avi info frame CEA-861-E **************/
1620
1621 static void print_avi_infoframe(struct v4l2_subdev *sd)
1622 {
1623 int i;
1624 u8 buf[14];
1625 u8 avi_len;
1626 u8 avi_ver;
1627
1628 if (!(hdmi_read(sd, 0x05) & 0x80)) {
1629 v4l2_info(sd, "receive DVI-D signal (AVI infoframe not supported)\n");
1630 return;
1631 }
1632 if (!(io_read(sd, 0x60) & 0x01)) {
1633 v4l2_info(sd, "AVI infoframe not received\n");
1634 return;
1635 }
1636
1637 if (io_read(sd, 0x83) & 0x01) {
1638 v4l2_info(sd, "AVI infoframe checksum error has occurred earlier\n");
1639 io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */
1640 if (io_read(sd, 0x83) & 0x01) {
1641 v4l2_info(sd, "AVI infoframe checksum error still present\n");
1642 io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */
1643 }
1644 }
1645
1646 avi_len = infoframe_read(sd, 0xe2);
1647 avi_ver = infoframe_read(sd, 0xe1);
1648 v4l2_info(sd, "AVI infoframe version %d (%d byte)\n",
1649 avi_ver, avi_len);
1650
1651 if (avi_ver != 0x02)
1652 return;
1653
1654 for (i = 0; i < 14; i++)
1655 buf[i] = infoframe_read(sd, i);
1656
1657 v4l2_info(sd,
1658 "\t%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
1659 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7],
1660 buf[8], buf[9], buf[10], buf[11], buf[12], buf[13]);
1661 }
1662
1663 static int adv7604_log_status(struct v4l2_subdev *sd)
1664 {
1665 struct adv7604_state *state = to_state(sd);
1666 struct v4l2_dv_timings timings;
1667 struct stdi_readback stdi;
1668 u8 reg_io_0x02 = io_read(sd, 0x02);
1669
1670 char *csc_coeff_sel_rb[16] = {
1671 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
1672 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
1673 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
1674 "reserved", "reserved", "reserved", "reserved", "manual"
1675 };
1676 char *input_color_space_txt[16] = {
1677 "RGB limited range (16-235)", "RGB full range (0-255)",
1678 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
1679 "XvYCC Bt.601", "XvYCC Bt.709",
1680 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
1681 "invalid", "invalid", "invalid", "invalid", "invalid",
1682 "invalid", "invalid", "automatic"
1683 };
1684 char *rgb_quantization_range_txt[] = {
1685 "Automatic",
1686 "RGB limited range (16-235)",
1687 "RGB full range (0-255)",
1688 };
1689
1690 v4l2_info(sd, "-----Chip status-----\n");
1691 v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
1692 v4l2_info(sd, "Connector type: %s\n", state->connector_hdmi ?
1693 "HDMI" : (DIGITAL_INPUT ? "DVI-D" : "DVI-A"));
1694 v4l2_info(sd, "EDID: %s\n", ((rep_read(sd, 0x7d) & 0x01) &&
1695 (rep_read(sd, 0x77) & 0x01)) ? "enabled" : "disabled ");
1696 v4l2_info(sd, "CEC: %s\n", !!(cec_read(sd, 0x2a) & 0x01) ?
1697 "enabled" : "disabled");
1698
1699 v4l2_info(sd, "-----Signal status-----\n");
1700 v4l2_info(sd, "Cable detected (+5V power): %s\n",
1701 (io_read(sd, 0x6f) & 0x10) ? "true" : "false");
1702 v4l2_info(sd, "TMDS signal detected: %s\n",
1703 no_signal_tmds(sd) ? "false" : "true");
1704 v4l2_info(sd, "TMDS signal locked: %s\n",
1705 no_lock_tmds(sd) ? "false" : "true");
1706 v4l2_info(sd, "SSPD locked: %s\n", no_lock_sspd(sd) ? "false" : "true");
1707 v4l2_info(sd, "STDI locked: %s\n", no_lock_stdi(sd) ? "false" : "true");
1708 v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true");
1709 v4l2_info(sd, "CP free run: %s\n",
1710 (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off"));
1711 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
1712 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
1713 (io_read(sd, 0x01) & 0x70) >> 4);
1714
1715 v4l2_info(sd, "-----Video Timings-----\n");
1716 if (read_stdi(sd, &stdi))
1717 v4l2_info(sd, "STDI: not locked\n");
1718 else
1719 v4l2_info(sd, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync\n",
1720 stdi.lcf, stdi.bl, stdi.lcvs,
1721 stdi.interlaced ? "interlaced" : "progressive",
1722 stdi.hs_pol, stdi.vs_pol);
1723 if (adv7604_query_dv_timings(sd, &timings))
1724 v4l2_info(sd, "No video detected\n");
1725 else
1726 adv7604_print_timings(sd, &timings, "Detected format:", true);
1727 adv7604_print_timings(sd, &state->timings, "Configured format:", true);
1728
1729 v4l2_info(sd, "-----Color space-----\n");
1730 v4l2_info(sd, "RGB quantization range ctrl: %s\n",
1731 rgb_quantization_range_txt[state->rgb_quantization_range]);
1732 v4l2_info(sd, "Input color space: %s\n",
1733 input_color_space_txt[reg_io_0x02 >> 4]);
1734 v4l2_info(sd, "Output color space: %s %s, saturator %s\n",
1735 (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr",
1736 (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)",
1737 ((reg_io_0x02 & 0x04) ^ (reg_io_0x02 & 0x01)) ?
1738 "enabled" : "disabled");
1739 v4l2_info(sd, "Color space conversion: %s\n",
1740 csc_coeff_sel_rb[cp_read(sd, 0xfc) >> 4]);
1741
1742 /* Digital video */
1743 if (DIGITAL_INPUT) {
1744 v4l2_info(sd, "-----HDMI status-----\n");
1745 v4l2_info(sd, "HDCP encrypted content: %s\n",
1746 hdmi_read(sd, 0x05) & 0x40 ? "true" : "false");
1747
1748 print_avi_infoframe(sd);
1749 }
1750
1751 return 0;
1752 }
1753
1754 /* ----------------------------------------------------------------------- */
1755
1756 static const struct v4l2_ctrl_ops adv7604_ctrl_ops = {
1757 .s_ctrl = adv7604_s_ctrl,
1758 };
1759
1760 static const struct v4l2_subdev_core_ops adv7604_core_ops = {
1761 .log_status = adv7604_log_status,
1762 .g_ext_ctrls = v4l2_subdev_g_ext_ctrls,
1763 .try_ext_ctrls = v4l2_subdev_try_ext_ctrls,
1764 .s_ext_ctrls = v4l2_subdev_s_ext_ctrls,
1765 .g_ctrl = v4l2_subdev_g_ctrl,
1766 .s_ctrl = v4l2_subdev_s_ctrl,
1767 .queryctrl = v4l2_subdev_queryctrl,
1768 .querymenu = v4l2_subdev_querymenu,
1769 .interrupt_service_routine = adv7604_isr,
1770 #ifdef CONFIG_VIDEO_ADV_DEBUG
1771 .g_register = adv7604_g_register,
1772 .s_register = adv7604_s_register,
1773 #endif
1774 };
1775
1776 static const struct v4l2_subdev_video_ops adv7604_video_ops = {
1777 .s_routing = adv7604_s_routing,
1778 .g_input_status = adv7604_g_input_status,
1779 .s_dv_timings = adv7604_s_dv_timings,
1780 .g_dv_timings = adv7604_g_dv_timings,
1781 .query_dv_timings = adv7604_query_dv_timings,
1782 .enum_dv_timings = adv7604_enum_dv_timings,
1783 .dv_timings_cap = adv7604_dv_timings_cap,
1784 .enum_mbus_fmt = adv7604_enum_mbus_fmt,
1785 .g_mbus_fmt = adv7604_g_mbus_fmt,
1786 .try_mbus_fmt = adv7604_g_mbus_fmt,
1787 .s_mbus_fmt = adv7604_g_mbus_fmt,
1788 };
1789
1790 static const struct v4l2_subdev_pad_ops adv7604_pad_ops = {
1791 .get_edid = adv7604_get_edid,
1792 .set_edid = adv7604_set_edid,
1793 };
1794
1795 static const struct v4l2_subdev_ops adv7604_ops = {
1796 .core = &adv7604_core_ops,
1797 .video = &adv7604_video_ops,
1798 .pad = &adv7604_pad_ops,
1799 };
1800
1801 /* -------------------------- custom ctrls ---------------------------------- */
1802
1803 static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = {
1804 .ops = &adv7604_ctrl_ops,
1805 .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
1806 .name = "Analog Sampling Phase",
1807 .type = V4L2_CTRL_TYPE_INTEGER,
1808 .min = 0,
1809 .max = 0x1f,
1810 .step = 1,
1811 .def = 0,
1812 };
1813
1814 static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color_manual = {
1815 .ops = &adv7604_ctrl_ops,
1816 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
1817 .name = "Free Running Color, Manual",
1818 .type = V4L2_CTRL_TYPE_BOOLEAN,
1819 .min = false,
1820 .max = true,
1821 .step = 1,
1822 .def = false,
1823 };
1824
1825 static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color = {
1826 .ops = &adv7604_ctrl_ops,
1827 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
1828 .name = "Free Running Color",
1829 .type = V4L2_CTRL_TYPE_INTEGER,
1830 .min = 0x0,
1831 .max = 0xffffff,
1832 .step = 0x1,
1833 .def = 0x0,
1834 };
1835
1836 /* ----------------------------------------------------------------------- */
1837
1838 static int adv7604_core_init(struct v4l2_subdev *sd)
1839 {
1840 struct adv7604_state *state = to_state(sd);
1841 struct adv7604_platform_data *pdata = &state->pdata;
1842
1843 hdmi_write(sd, 0x48,
1844 (pdata->disable_pwrdnb ? 0x80 : 0) |
1845 (pdata->disable_cable_det_rst ? 0x40 : 0));
1846
1847 disable_input(sd);
1848
1849 /* power */
1850 io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */
1851 io_write(sd, 0x0b, 0x44); /* Power down ESDP block */
1852 cp_write(sd, 0xcf, 0x01); /* Power down macrovision */
1853
1854 /* video format */
1855 io_write_and_or(sd, 0x02, 0xf0,
1856 pdata->alt_gamma << 3 |
1857 pdata->op_656_range << 2 |
1858 pdata->rgb_out << 1 |
1859 pdata->alt_data_sat << 0);
1860 io_write(sd, 0x03, pdata->op_format_sel);
1861 io_write_and_or(sd, 0x04, 0x1f, pdata->op_ch_sel << 5);
1862 io_write_and_or(sd, 0x05, 0xf0, pdata->blank_data << 3 |
1863 pdata->insert_av_codes << 2 |
1864 pdata->replicate_av_codes << 1 |
1865 pdata->invert_cbcr << 0);
1866
1867 /* TODO from platform data */
1868 cp_write(sd, 0x69, 0x30); /* Enable CP CSC */
1869 io_write(sd, 0x06, 0xa6); /* positive VS and HS */
1870 io_write(sd, 0x14, 0x7f); /* Drive strength adjusted to max */
1871 cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */
1872 cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
1873 cp_write(sd, 0xf9, 0x23); /* STDI ch. 1 - LCVS change threshold -
1874 ADI recommended setting [REF_01, c. 2.3.3] */
1875 cp_write(sd, 0x45, 0x23); /* STDI ch. 2 - LCVS change threshold -
1876 ADI recommended setting [REF_01, c. 2.3.3] */
1877 cp_write(sd, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution
1878 for digital formats */
1879
1880 /* TODO from platform data */
1881 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */
1882
1883 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
1884 io_write_and_or(sd, 0x30, ~(1 << 4), pdata->output_bus_lsb_to_msb << 4);
1885
1886 /* interrupts */
1887 io_write(sd, 0x40, 0xc2); /* Configure INT1 */
1888 io_write(sd, 0x41, 0xd7); /* STDI irq for any change, disable INT2 */
1889 io_write(sd, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */
1890 io_write(sd, 0x6e, 0xc0); /* Enable V_LOCKED and DE_REGEN_LCK interrupts */
1891 io_write(sd, 0x73, 0x10); /* Enable CABLE_DET_A_ST (+5v) interrupt */
1892
1893 return v4l2_ctrl_handler_setup(sd->ctrl_handler);
1894 }
1895
1896 static void adv7604_unregister_clients(struct adv7604_state *state)
1897 {
1898 if (state->i2c_avlink)
1899 i2c_unregister_device(state->i2c_avlink);
1900 if (state->i2c_cec)
1901 i2c_unregister_device(state->i2c_cec);
1902 if (state->i2c_infoframe)
1903 i2c_unregister_device(state->i2c_infoframe);
1904 if (state->i2c_esdp)
1905 i2c_unregister_device(state->i2c_esdp);
1906 if (state->i2c_dpp)
1907 i2c_unregister_device(state->i2c_dpp);
1908 if (state->i2c_afe)
1909 i2c_unregister_device(state->i2c_afe);
1910 if (state->i2c_repeater)
1911 i2c_unregister_device(state->i2c_repeater);
1912 if (state->i2c_edid)
1913 i2c_unregister_device(state->i2c_edid);
1914 if (state->i2c_hdmi)
1915 i2c_unregister_device(state->i2c_hdmi);
1916 if (state->i2c_test)
1917 i2c_unregister_device(state->i2c_test);
1918 if (state->i2c_cp)
1919 i2c_unregister_device(state->i2c_cp);
1920 if (state->i2c_vdp)
1921 i2c_unregister_device(state->i2c_vdp);
1922 }
1923
1924 static struct i2c_client *adv7604_dummy_client(struct v4l2_subdev *sd,
1925 u8 addr, u8 io_reg)
1926 {
1927 struct i2c_client *client = v4l2_get_subdevdata(sd);
1928
1929 if (addr)
1930 io_write(sd, io_reg, addr << 1);
1931 return i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1);
1932 }
1933
1934 static int adv7604_probe(struct i2c_client *client,
1935 const struct i2c_device_id *id)
1936 {
1937 struct adv7604_state *state;
1938 struct adv7604_platform_data *pdata = client->dev.platform_data;
1939 struct v4l2_ctrl_handler *hdl;
1940 struct v4l2_subdev *sd;
1941 int err;
1942
1943 /* Check if the adapter supports the needed features */
1944 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1945 return -EIO;
1946 v4l_dbg(1, debug, client, "detecting adv7604 client on address 0x%x\n",
1947 client->addr << 1);
1948
1949 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
1950 if (!state) {
1951 v4l_err(client, "Could not allocate adv7604_state memory!\n");
1952 return -ENOMEM;
1953 }
1954
1955 /* platform data */
1956 if (!pdata) {
1957 v4l_err(client, "No platform data!\n");
1958 return -ENODEV;
1959 }
1960 memcpy(&state->pdata, pdata, sizeof(state->pdata));
1961
1962 sd = &state->sd;
1963 v4l2_i2c_subdev_init(sd, client, &adv7604_ops);
1964 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1965 state->connector_hdmi = pdata->connector_hdmi;
1966
1967 /* i2c access to adv7604? */
1968 if (adv_smbus_read_byte_data_check(client, 0xfb, false) != 0x68) {
1969 v4l2_info(sd, "not an adv7604 on address 0x%x\n",
1970 client->addr << 1);
1971 return -ENODEV;
1972 }
1973
1974 /* control handlers */
1975 hdl = &state->hdl;
1976 v4l2_ctrl_handler_init(hdl, 9);
1977
1978 v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
1979 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
1980 v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
1981 V4L2_CID_CONTRAST, 0, 255, 1, 128);
1982 v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
1983 V4L2_CID_SATURATION, 0, 255, 1, 128);
1984 v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
1985 V4L2_CID_HUE, 0, 128, 1, 0);
1986
1987 /* private controls */
1988 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
1989 V4L2_CID_DV_RX_POWER_PRESENT, 0, 1, 0, 0);
1990 state->detect_tx_5v_ctrl->is_private = true;
1991 state->rgb_quantization_range_ctrl =
1992 v4l2_ctrl_new_std_menu(hdl, &adv7604_ctrl_ops,
1993 V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
1994 0, V4L2_DV_RGB_RANGE_AUTO);
1995 state->rgb_quantization_range_ctrl->is_private = true;
1996
1997 /* custom controls */
1998 state->analog_sampling_phase_ctrl =
1999 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_analog_sampling_phase, NULL);
2000 state->analog_sampling_phase_ctrl->is_private = true;
2001 state->free_run_color_manual_ctrl =
2002 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_free_run_color_manual, NULL);
2003 state->free_run_color_manual_ctrl->is_private = true;
2004 state->free_run_color_ctrl =
2005 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_free_run_color, NULL);
2006 state->free_run_color_ctrl->is_private = true;
2007
2008 sd->ctrl_handler = hdl;
2009 if (hdl->error) {
2010 err = hdl->error;
2011 goto err_hdl;
2012 }
2013 if (adv7604_s_detect_tx_5v_ctrl(sd)) {
2014 err = -ENODEV;
2015 goto err_hdl;
2016 }
2017
2018 state->i2c_avlink = adv7604_dummy_client(sd, pdata->i2c_avlink, 0xf3);
2019 state->i2c_cec = adv7604_dummy_client(sd, pdata->i2c_cec, 0xf4);
2020 state->i2c_infoframe = adv7604_dummy_client(sd, pdata->i2c_infoframe, 0xf5);
2021 state->i2c_esdp = adv7604_dummy_client(sd, pdata->i2c_esdp, 0xf6);
2022 state->i2c_dpp = adv7604_dummy_client(sd, pdata->i2c_dpp, 0xf7);
2023 state->i2c_afe = adv7604_dummy_client(sd, pdata->i2c_afe, 0xf8);
2024 state->i2c_repeater = adv7604_dummy_client(sd, pdata->i2c_repeater, 0xf9);
2025 state->i2c_edid = adv7604_dummy_client(sd, pdata->i2c_edid, 0xfa);
2026 state->i2c_hdmi = adv7604_dummy_client(sd, pdata->i2c_hdmi, 0xfb);
2027 state->i2c_test = adv7604_dummy_client(sd, pdata->i2c_test, 0xfc);
2028 state->i2c_cp = adv7604_dummy_client(sd, pdata->i2c_cp, 0xfd);
2029 state->i2c_vdp = adv7604_dummy_client(sd, pdata->i2c_vdp, 0xfe);
2030 if (!state->i2c_avlink || !state->i2c_cec || !state->i2c_infoframe ||
2031 !state->i2c_esdp || !state->i2c_dpp || !state->i2c_afe ||
2032 !state->i2c_repeater || !state->i2c_edid || !state->i2c_hdmi ||
2033 !state->i2c_test || !state->i2c_cp || !state->i2c_vdp) {
2034 err = -ENOMEM;
2035 v4l2_err(sd, "failed to create all i2c clients\n");
2036 goto err_i2c;
2037 }
2038 state->restart_stdi_once = true;
2039
2040 /* work queues */
2041 state->work_queues = create_singlethread_workqueue(client->name);
2042 if (!state->work_queues) {
2043 v4l2_err(sd, "Could not create work queue\n");
2044 err = -ENOMEM;
2045 goto err_i2c;
2046 }
2047
2048 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
2049 adv7604_delayed_work_enable_hotplug);
2050
2051 state->pad.flags = MEDIA_PAD_FL_SOURCE;
2052 err = media_entity_init(&sd->entity, 1, &state->pad, 0);
2053 if (err)
2054 goto err_work_queues;
2055
2056 err = adv7604_core_init(sd);
2057 if (err)
2058 goto err_entity;
2059 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
2060 client->addr << 1, client->adapter->name);
2061 return 0;
2062
2063 err_entity:
2064 media_entity_cleanup(&sd->entity);
2065 err_work_queues:
2066 cancel_delayed_work(&state->delayed_work_enable_hotplug);
2067 destroy_workqueue(state->work_queues);
2068 err_i2c:
2069 adv7604_unregister_clients(state);
2070 err_hdl:
2071 v4l2_ctrl_handler_free(hdl);
2072 return err;
2073 }
2074
2075 /* ----------------------------------------------------------------------- */
2076
2077 static int adv7604_remove(struct i2c_client *client)
2078 {
2079 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2080 struct adv7604_state *state = to_state(sd);
2081
2082 cancel_delayed_work(&state->delayed_work_enable_hotplug);
2083 destroy_workqueue(state->work_queues);
2084 v4l2_device_unregister_subdev(sd);
2085 media_entity_cleanup(&sd->entity);
2086 adv7604_unregister_clients(to_state(sd));
2087 v4l2_ctrl_handler_free(sd->ctrl_handler);
2088 return 0;
2089 }
2090
2091 /* ----------------------------------------------------------------------- */
2092
2093 static struct i2c_device_id adv7604_id[] = {
2094 { "adv7604", 0 },
2095 { }
2096 };
2097 MODULE_DEVICE_TABLE(i2c, adv7604_id);
2098
2099 static struct i2c_driver adv7604_driver = {
2100 .driver = {
2101 .owner = THIS_MODULE,
2102 .name = "adv7604",
2103 },
2104 .probe = adv7604_probe,
2105 .remove = adv7604_remove,
2106 .id_table = adv7604_id,
2107 };
2108
2109 module_i2c_driver(adv7604_driver);
CRIS linux kernel tree