drivers/media/usb/cx231xx/cx231xx-conf-reg.h

   1 /*
   2    cx231xx_conf-reg.h - driver for Conexant Cx23100/101/102 USB
   3                         video capture devices
   4
   5    Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
   6
   7    This program is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 2 of the License, or
  10    (at your option) any later version.
  11
  12    This program is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program; if not, write to the Free Software
  19    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20  */
  21
  22 #ifndef _POLARIS_REG_H_
  23 #define _POLARIS_REG_H_
  24
  25 #define BOARD_CFG_STAT          0x0
  26 #define TS_MODE_REG             0x4
  27 #define TS1_CFG_REG             0x8
  28 #define TS1_LENGTH_REG          0xc
  29 #define TS2_CFG_REG             0x10
  30 #define TS2_LENGTH_REG          0x14
  31 #define EP_MODE_SET             0x18
  32 #define CIR_PWR_PTN1            0x1c
  33 #define CIR_PWR_PTN2            0x20
  34 #define CIR_PWR_PTN3            0x24
  35 #define CIR_PWR_MASK0           0x28
  36 #define CIR_PWR_MASK1           0x2c
  37 #define CIR_PWR_MASK2           0x30
  38 #define CIR_GAIN                0x34
  39 #define CIR_CAR_REG             0x38
  40 #define CIR_OT_CFG1             0x40
  41 #define CIR_OT_CFG2             0x44
  42 #define GBULK_BIT_EN            0x68
  43 #define PWR_CTL_EN              0x74
  44
  45 /* Polaris Endpoints capture mask for register EP_MODE_SET */
  46 #define ENABLE_EP1              0x01   /* Bit[0]=1 */
  47 #define ENABLE_EP2              0x02   /* Bit[1]=1 */
  48 #define ENABLE_EP3              0x04   /* Bit[2]=1 */
  49 #define ENABLE_EP4              0x08   /* Bit[3]=1 */
  50 #define ENABLE_EP5              0x10   /* Bit[4]=1 */
  51 #define ENABLE_EP6              0x20   /* Bit[5]=1 */
  52
  53 /* Bit definition for register PWR_CTL_EN */
  54 #define PWR_MODE_MASK           0x17f
  55 #define PWR_AV_EN               0x08   /* bit3 */
  56 #define PWR_ISO_EN              0x40   /* bit6 */
  57 #define PWR_AV_MODE             0x30   /* bit4,5  */
  58 #define PWR_TUNER_EN            0x04   /* bit2 */
  59 #define PWR_DEMOD_EN            0x02   /* bit1 */
  60 #define I2C_DEMOD_EN            0x01   /* bit0 */
  61 #define PWR_RESETOUT_EN         0x100  /* bit8 */
  62
  63 enum AV_MODE{
  64         POLARIS_AVMODE_DEFAULT = 0,
  65         POLARIS_AVMODE_DIGITAL = 0x10,
  66         POLARIS_AVMODE_ANALOGT_TV = 0x20,
  67         POLARIS_AVMODE_ENXTERNAL_AV = 0x30,
  68
  69 };
  70
  71 /* Colibri Registers */
  72
  73 #define SINGLE_ENDED            0x0
  74 #define LOW_IF                  0x4
  75 #define EU_IF                   0x9
  76 #define US_IF                   0xa
  77
  78 #define SUP_BLK_TUNE1           0x00
  79 #define SUP_BLK_TUNE2           0x01
  80 #define SUP_BLK_TUNE3           0x02
  81 #define SUP_BLK_XTAL            0x03
  82 #define SUP_BLK_PLL1            0x04
  83 #define SUP_BLK_PLL2            0x05
  84 #define SUP_BLK_PLL3            0x06
  85 #define SUP_BLK_REF             0x07
  86 #define SUP_BLK_PWRDN           0x08
  87 #define SUP_BLK_TESTPAD         0x09
  88 #define ADC_COM_INT5_STAB_REF   0x0a
  89 #define ADC_COM_QUANT           0x0b
  90 #define ADC_COM_BIAS1           0x0c
  91 #define ADC_COM_BIAS2           0x0d
  92 #define ADC_COM_BIAS3           0x0e
  93 #define TESTBUS_CTRL            0x12
  94
  95 #define FLD_PWRDN_TUNING_BIAS   0x10
  96 #define FLD_PWRDN_ENABLE_PLL    0x08
  97 #define FLD_PWRDN_PD_BANDGAP    0x04
  98 #define FLD_PWRDN_PD_BIAS       0x02
  99 #define FLD_PWRDN_PD_TUNECK     0x01
 100
 101
 102 #define ADC_STATUS_CH1          0x20
 103 #define ADC_STATUS_CH2          0x40
 104 #define ADC_STATUS_CH3          0x60
 105
 106 #define ADC_STATUS2_CH1         0x21
 107 #define ADC_STATUS2_CH2         0x41
 108 #define ADC_STATUS2_CH3         0x61
 109
 110 #define ADC_CAL_ATEST_CH1       0x22
 111 #define ADC_CAL_ATEST_CH2       0x42
 112 #define ADC_CAL_ATEST_CH3       0x62
 113
 114 #define ADC_PWRDN_CLAMP_CH1     0x23
 115 #define ADC_PWRDN_CLAMP_CH2     0x43
 116 #define ADC_PWRDN_CLAMP_CH3     0x63
 117
 118 #define ADC_CTRL_DAC23_CH1      0x24
 119 #define ADC_CTRL_DAC23_CH2      0x44
 120 #define ADC_CTRL_DAC23_CH3      0x64
 121
 122 #define ADC_CTRL_DAC1_CH1       0x25
 123 #define ADC_CTRL_DAC1_CH2       0x45
 124 #define ADC_CTRL_DAC1_CH3       0x65
 125
 126 #define ADC_DCSERVO_DEM_CH1     0x26
 127 #define ADC_DCSERVO_DEM_CH2     0x46
 128 #define ADC_DCSERVO_DEM_CH3     0x66
 129
 130 #define ADC_FB_FRCRST_CH1       0x27
 131 #define ADC_FB_FRCRST_CH2       0x47
 132 #define ADC_FB_FRCRST_CH3       0x67
 133
 134 #define ADC_INPUT_CH1           0x28
 135 #define ADC_INPUT_CH2           0x48
 136 #define ADC_INPUT_CH3           0x68
 137 #define INPUT_SEL_MASK          0x30   /* [5:4] in_sel */
 138
 139 #define ADC_NTF_PRECLMP_EN_CH1  0x29
 140 #define ADC_NTF_PRECLMP_EN_CH2  0x49
 141 #define ADC_NTF_PRECLMP_EN_CH3  0x69
 142
 143 #define ADC_QGAIN_RES_TRM_CH1   0x2a
 144 #define ADC_QGAIN_RES_TRM_CH2   0x4a
 145 #define ADC_QGAIN_RES_TRM_CH3   0x6a
 146
 147 #define ADC_SOC_PRECLMP_TERM_CH1    0x2b
 148 #define ADC_SOC_PRECLMP_TERM_CH2    0x4b
 149 #define ADC_SOC_PRECLMP_TERM_CH3    0x6b
 150
 151 #define TESTBUS_CTRL_CH1        0x32
 152 #define TESTBUS_CTRL_CH2        0x52
 153 #define TESTBUS_CTRL_CH3        0x72
 154
 155 /******************************************************************************
 156                             * DIF registers *
 157  ******************************************************************************/
 158 #define      DIRECT_IF_REVB_BASE  0x00300
 159
 160 /*****************************************************************************/
 161 #define      DIF_PLL_FREQ_WORD        (DIRECT_IF_REVB_BASE + 0x00000000)
 162 /*****************************************************************************/
 163 #define      FLD_DIF_PLL_LOCK                           0x80000000
 164 /*  Reserved                                [30:29] */
 165 #define      FLD_DIF_PLL_FREE_RUN                       0x10000000
 166 #define      FLD_DIF_PLL_FREQ                           0x0fffffff
 167
 168 /*****************************************************************************/
 169 #define      DIF_PLL_CTRL             (DIRECT_IF_REVB_BASE + 0x00000004)
 170 /*****************************************************************************/
 171 #define      FLD_DIF_KD_PD                              0xff000000
 172 /*  Reserved                             [23:20] */
 173 #define      FLD_DIF_KDS_PD                             0x000f0000
 174 #define      FLD_DIF_KI_PD                              0x0000ff00
 175 /*  Reserved                             [7:4] */
 176 #define      FLD_DIF_KIS_PD                             0x0000000f
 177
 178 /*****************************************************************************/
 179 #define      DIF_PLL_CTRL1            (DIRECT_IF_REVB_BASE + 0x00000008)
 180 /*****************************************************************************/
 181 #define      FLD_DIF_KD_FD                              0xff000000
 182 /*  Reserved                             [23:20] */
 183 #define      FLD_DIF_KDS_FD                             0x000f0000
 184 #define      FLD_DIF_KI_FD                              0x0000ff00
 185 #define      FLD_DIF_SIG_PROP_SZ                        0x000000f0
 186 #define      FLD_DIF_KIS_FD                             0x0000000f
 187
 188 /*****************************************************************************/
 189 #define      DIF_PLL_CTRL2            (DIRECT_IF_REVB_BASE + 0x0000000c)
 190 /*****************************************************************************/
 191 #define      FLD_DIF_PLL_AGC_REF                        0xfff00000
 192 #define      FLD_DIF_PLL_AGC_KI                         0x000f0000
 193 /*  Reserved                             [15] */
 194 #define      FLD_DIF_FREQ_LIMIT                         0x00007000
 195 #define      FLD_DIF_K_FD                               0x00000f00
 196 #define      FLD_DIF_DOWNSMPL_FD                        0x000000ff
 197
 198 /*****************************************************************************/
 199 #define      DIF_PLL_CTRL3            (DIRECT_IF_REVB_BASE + 0x00000010)
 200 /*****************************************************************************/
 201 /*  Reserved                             [31:16] */
 202 #define      FLD_DIF_PLL_AGC_EN                         0x00008000
 203 /*  Reserved                             [14:12] */
 204 #define      FLD_DIF_PLL_MAN_GAIN                       0x00000fff
 205
 206 /*****************************************************************************/
 207 #define      DIF_AGC_IF_REF           (DIRECT_IF_REVB_BASE + 0x00000014)
 208 /*****************************************************************************/
 209 #define      FLD_DIF_K_AGC_RF                           0xf0000000
 210 #define      FLD_DIF_K_AGC_IF                           0x0f000000
 211 #define      FLD_DIF_K_AGC_INT                          0x00f00000
 212 /*  Reserved                             [19:12] */
 213 #define      FLD_DIF_IF_REF                             0x00000fff
 214
 215 /*****************************************************************************/
 216 #define      DIF_AGC_CTRL_IF          (DIRECT_IF_REVB_BASE + 0x00000018)
 217 /*****************************************************************************/
 218 #define      FLD_DIF_IF_MAX                             0xff000000
 219 #define      FLD_DIF_IF_MIN                             0x00ff0000
 220 #define      FLD_DIF_IF_AGC                             0x0000ffff
 221
 222 /*****************************************************************************/
 223 #define      DIF_AGC_CTRL_INT         (DIRECT_IF_REVB_BASE + 0x0000001c)
 224 /*****************************************************************************/
 225 #define      FLD_DIF_INT_MAX                            0xff000000
 226 #define      FLD_DIF_INT_MIN                            0x00ff0000
 227 #define      FLD_DIF_INT_AGC                            0x0000ffff
 228
 229 /*****************************************************************************/
 230 #define      DIF_AGC_CTRL_RF          (DIRECT_IF_REVB_BASE + 0x00000020)
 231 /*****************************************************************************/
 232 #define      FLD_DIF_RF_MAX                             0xff000000
 233 #define      FLD_DIF_RF_MIN                             0x00ff0000
 234 #define      FLD_DIF_RF_AGC                             0x0000ffff
 235
 236 /*****************************************************************************/
 237 #define      DIF_AGC_IF_INT_CURRENT   (DIRECT_IF_REVB_BASE + 0x00000024)
 238 /*****************************************************************************/
 239 #define      FLD_DIF_IF_AGC_IN                          0xffff0000
 240 #define      FLD_DIF_INT_AGC_IN                         0x0000ffff
 241
 242 /*****************************************************************************/
 243 #define      DIF_AGC_RF_CURRENT       (DIRECT_IF_REVB_BASE + 0x00000028)
 244 /*****************************************************************************/
 245 /*  Reserved                            [31:16] */
 246 #define      FLD_DIF_RF_AGC_IN                          0x0000ffff
 247
 248 /*****************************************************************************/
 249 #define      DIF_VIDEO_AGC_CTRL       (DIRECT_IF_REVB_BASE + 0x0000002c)
 250 /*****************************************************************************/
 251 #define      FLD_DIF_AFD                                0xc0000000
 252 #define      FLD_DIF_K_VID_AGC                          0x30000000
 253 #define      FLD_DIF_LINE_LENGTH                        0x0fff0000
 254 #define      FLD_DIF_AGC_GAIN                           0x0000ffff
 255
 256 /*****************************************************************************/
 257 #define      DIF_VID_AUD_OVERRIDE     (DIRECT_IF_REVB_BASE + 0x00000030)
 258 /*****************************************************************************/
 259 #define      FLD_DIF_AUDIO_AGC_OVERRIDE                 0x80000000
 260 /*  Reserved                             [30:30] */
 261 #define      FLD_DIF_AUDIO_MAN_GAIN                     0x3f000000
 262 /*  Reserved                             [23:17] */
 263 #define      FLD_DIF_VID_AGC_OVERRIDE                   0x00010000
 264 #define      FLD_DIF_VID_MAN_GAIN                       0x0000ffff
 265
 266 /*****************************************************************************/
 267 #define      DIF_AV_SEP_CTRL          (DIRECT_IF_REVB_BASE + 0x00000034)
 268 /*****************************************************************************/
 269 #define      FLD_DIF_LPF_FREQ                           0xc0000000
 270 #define      FLD_DIF_AV_PHASE_INC                       0x3f000000
 271 #define      FLD_DIF_AUDIO_FREQ                         0x00ffffff
 272
 273 /*****************************************************************************/
 274 #define      DIF_COMP_FLT_CTRL        (DIRECT_IF_REVB_BASE + 0x00000038)
 275 /*****************************************************************************/
 276 /*  Reserved                            [31:24] */
 277 #define      FLD_DIF_IIR23_R2                           0x00ff0000
 278 #define      FLD_DIF_IIR23_R1                           0x0000ff00
 279 #define      FLD_DIF_IIR1_R1                            0x000000ff
 280
 281 /*****************************************************************************/
 282 #define      DIF_MISC_CTRL            (DIRECT_IF_REVB_BASE + 0x0000003c)
 283 /*****************************************************************************/
 284 #define      FLD_DIF_DIF_BYPASS                         0x80000000
 285 #define      FLD_DIF_FM_NYQ_GAIN                        0x40000000
 286 #define      FLD_DIF_RF_AGC_ENA                         0x20000000
 287 #define      FLD_DIF_INT_AGC_ENA                        0x10000000
 288 #define      FLD_DIF_IF_AGC_ENA                         0x08000000
 289 #define      FLD_DIF_FORCE_RF_IF_LOCK                   0x04000000
 290 #define      FLD_DIF_VIDEO_AGC_ENA                      0x02000000
 291 #define      FLD_DIF_RF_AGC_INV                         0x01000000
 292 #define      FLD_DIF_INT_AGC_INV                        0x00800000
 293 #define      FLD_DIF_IF_AGC_INV                         0x00400000
 294 #define      FLD_DIF_SPEC_INV                           0x00200000
 295 #define      FLD_DIF_AUD_FULL_BW                        0x00100000
 296 #define      FLD_DIF_AUD_SRC_SEL                        0x00080000
 297 /*  Reserved                             [18] */
 298 #define      FLD_DIF_IF_FREQ                            0x00030000
 299 /*  Reserved                             [15:14] */
 300 #define      FLD_DIF_TIP_OFFSET                         0x00003f00
 301 /*  Reserved                             [7:5] */
 302 #define      FLD_DIF_DITHER_ENA                         0x00000010
 303 /*  Reserved                             [3:1] */
 304 #define      FLD_DIF_RF_IF_LOCK                         0x00000001
 305
 306 /*****************************************************************************/
 307 #define      DIF_SRC_PHASE_INC        (DIRECT_IF_REVB_BASE + 0x00000040)
 308 /*****************************************************************************/
 309 /*  Reserved                             [31:29] */
 310 #define      FLD_DIF_PHASE_INC                          0x1fffffff
 311
 312 /*****************************************************************************/
 313 #define      DIF_SRC_GAIN_CONTROL     (DIRECT_IF_REVB_BASE + 0x00000044)
 314 /*****************************************************************************/
 315 /*  Reserved                             [31:16] */
 316 #define      FLD_DIF_SRC_KI                             0x0000ff00
 317 #define      FLD_DIF_SRC_KD                             0x000000ff
 318
 319 /*****************************************************************************/
 320 #define      DIF_BPF_COEFF01          (DIRECT_IF_REVB_BASE + 0x00000048)
 321 /*****************************************************************************/
 322 /*  Reserved                             [31:19] */
 323 #define      FLD_DIF_BPF_COEFF_0                        0x00070000
 324 /*  Reserved                             [15:4] */
 325 #define      FLD_DIF_BPF_COEFF_1                        0x0000000f
 326
 327 /*****************************************************************************/
 328 #define      DIF_BPF_COEFF23          (DIRECT_IF_REVB_BASE + 0x0000004c)
 329 /*****************************************************************************/
 330 /*  Reserved                             [31:22] */
 331 #define      FLD_DIF_BPF_COEFF_2                        0x003f0000
 332 /*  Reserved                             [15:7] */
 333 #define      FLD_DIF_BPF_COEFF_3                        0x0000007f
 334
 335 /*****************************************************************************/
 336 #define      DIF_BPF_COEFF45          (DIRECT_IF_REVB_BASE + 0x00000050)
 337 /*****************************************************************************/
 338 /*  Reserved                             [31:24] */
 339 #define      FLD_DIF_BPF_COEFF_4                        0x00ff0000
 340 /*  Reserved                             [15:8] */
 341 #define      FLD_DIF_BPF_COEFF_5                        0x000000ff
 342
 343 /*****************************************************************************/
 344 #define      DIF_BPF_COEFF67          (DIRECT_IF_REVB_BASE + 0x00000054)
 345 /*****************************************************************************/
 346 /*  Reserved                             [31:25] */
 347 #define      FLD_DIF_BPF_COEFF_6                        0x01ff0000
 348 /*  Reserved                             [15:9] */
 349 #define      FLD_DIF_BPF_COEFF_7                        0x000001ff
 350
 351 /*****************************************************************************/
 352 #define      DIF_BPF_COEFF89          (DIRECT_IF_REVB_BASE + 0x00000058)
 353 /*****************************************************************************/
 354 /*  Reserved                             [31:26] */
 355 #define      FLD_DIF_BPF_COEFF_8                        0x03ff0000
 356 /*  Reserved                             [15:10] */
 357 #define      FLD_DIF_BPF_COEFF_9                        0x000003ff
 358
 359 /*****************************************************************************/
 360 #define      DIF_BPF_COEFF1011        (DIRECT_IF_REVB_BASE + 0x0000005c)
 361 /*****************************************************************************/
 362 /*  Reserved                             [31:27] */
 363 #define      FLD_DIF_BPF_COEFF_10                       0x07ff0000
 364 /*  Reserved                             [15:11] */
 365 #define      FLD_DIF_BPF_COEFF_11                       0x000007ff
 366
 367 /*****************************************************************************/
 368 #define      DIF_BPF_COEFF1213        (DIRECT_IF_REVB_BASE + 0x00000060)
 369 /*****************************************************************************/
 370 /*  Reserved                             [31:27] */
 371 #define      FLD_DIF_BPF_COEFF_12                       0x07ff0000
 372 /*  Reserved                             [15:12] */
 373 #define      FLD_DIF_BPF_COEFF_13                       0x00000fff
 374
 375 /*****************************************************************************/
 376 #define      DIF_BPF_COEFF1415        (DIRECT_IF_REVB_BASE + 0x00000064)
 377 /*****************************************************************************/
 378 /*  Reserved                             [31:28] */
 379 #define      FLD_DIF_BPF_COEFF_14                       0x0fff0000
 380 /*  Reserved                             [15:12] */
 381 #define      FLD_DIF_BPF_COEFF_15                       0x00000fff
 382
 383 /*****************************************************************************/
 384 #define      DIF_BPF_COEFF1617        (DIRECT_IF_REVB_BASE + 0x00000068)
 385 /*****************************************************************************/
 386 /*  Reserved                             [31:29] */
 387 #define      FLD_DIF_BPF_COEFF_16                       0x1fff0000
 388 /*  Reserved                             [15:13] */
 389 #define      FLD_DIF_BPF_COEFF_17                       0x00001fff
 390
 391 /*****************************************************************************/
 392 #define      DIF_BPF_COEFF1819        (DIRECT_IF_REVB_BASE + 0x0000006c)
 393 /*****************************************************************************/
 394 /*  Reserved                             [31:29] */
 395 #define      FLD_DIF_BPF_COEFF_18                       0x1fff0000
 396 /*  Reserved                             [15:13] */
 397 #define      FLD_DIF_BPF_COEFF_19                       0x00001fff
 398
 399 /*****************************************************************************/
 400 #define      DIF_BPF_COEFF2021        (DIRECT_IF_REVB_BASE + 0x00000070)
 401 /*****************************************************************************/
 402 /*  Reserved                             [31:29] */
 403 #define      FLD_DIF_BPF_COEFF_20                       0x1fff0000
 404 /*  Reserved                             [15:14] */
 405 #define      FLD_DIF_BPF_COEFF_21                       0x00003fff
 406
 407 /*****************************************************************************/
 408 #define      DIF_BPF_COEFF2223        (DIRECT_IF_REVB_BASE + 0x00000074)
 409 /*****************************************************************************/
 410 /*  Reserved                             [31:30] */
 411 #define      FLD_DIF_BPF_COEFF_22                       0x3fff0000
 412 /*  Reserved                             [15:14] */
 413 #define      FLD_DIF_BPF_COEFF_23                       0x00003fff
 414
 415 /*****************************************************************************/
 416 #define      DIF_BPF_COEFF2425        (DIRECT_IF_REVB_BASE + 0x00000078)
 417 /*****************************************************************************/
 418 /*  Reserved                             [31:30] */
 419 #define      FLD_DIF_BPF_COEFF_24                       0x3fff0000
 420 /*  Reserved                             [15:14] */
 421 #define      FLD_DIF_BPF_COEFF_25                       0x00003fff
 422
 423 /*****************************************************************************/
 424 #define      DIF_BPF_COEFF2627        (DIRECT_IF_REVB_BASE + 0x0000007c)
 425 /*****************************************************************************/
 426 /*  Reserved                             [31:30] */
 427 #define      FLD_DIF_BPF_COEFF_26                       0x3fff0000
 428 /*  Reserved                             [15:14] */
 429 #define      FLD_DIF_BPF_COEFF_27                       0x00003fff
 430
 431 /*****************************************************************************/
 432 #define      DIF_BPF_COEFF2829        (DIRECT_IF_REVB_BASE + 0x00000080)
 433 /*****************************************************************************/
 434 /*  Reserved                             [31:30] */
 435 #define      FLD_DIF_BPF_COEFF_28                       0x3fff0000
 436 /*  Reserved                             [15:14] */
 437 #define      FLD_DIF_BPF_COEFF_29                       0x00003fff
 438
 439 /*****************************************************************************/
 440 #define      DIF_BPF_COEFF3031        (DIRECT_IF_REVB_BASE + 0x00000084)
 441 /*****************************************************************************/
 442 /*  Reserved                             [31:30] */
 443 #define      FLD_DIF_BPF_COEFF_30                       0x3fff0000
 444 /*  Reserved                             [15:14] */
 445 #define      FLD_DIF_BPF_COEFF_31                       0x00003fff
 446
 447 /*****************************************************************************/
 448 #define      DIF_BPF_COEFF3233        (DIRECT_IF_REVB_BASE + 0x00000088)
 449 /*****************************************************************************/
 450 /*  Reserved                             [31:30] */
 451 #define      FLD_DIF_BPF_COEFF_32                       0x3fff0000
 452 /*  Reserved                             [15:14] */
 453 #define      FLD_DIF_BPF_COEFF_33                       0x00003fff
 454
 455 /*****************************************************************************/
 456 #define      DIF_BPF_COEFF3435        (DIRECT_IF_REVB_BASE + 0x0000008c)
 457 /*****************************************************************************/
 458 /*  Reserved                             [31:30] */
 459 #define      FLD_DIF_BPF_COEFF_34                       0x3fff0000
 460 /*  Reserved                             [15:14] */
 461 #define      FLD_DIF_BPF_COEFF_35                       0x00003fff
 462
 463 /*****************************************************************************/
 464 #define      DIF_BPF_COEFF36          (DIRECT_IF_REVB_BASE + 0x00000090)
 465 /*****************************************************************************/
 466 /*  Reserved                             [31:30] */
 467 #define      FLD_DIF_BPF_COEFF_36                       0x3fff0000
 468 /*  Reserved                             [15:0] */
 469
 470 /*****************************************************************************/
 471 #define      DIF_RPT_VARIANCE         (DIRECT_IF_REVB_BASE + 0x00000094)
 472 /*****************************************************************************/
 473 /*  Reserved                             [31:20] */
 474 #define      FLD_DIF_RPT_VARIANCE                       0x000fffff
 475
 476 /*****************************************************************************/
 477 #define      DIF_SOFT_RST_CTRL_REVB       (DIRECT_IF_REVB_BASE + 0x00000098)
 478 /*****************************************************************************/
 479 /*  Reserved                             [31:8] */
 480 #define      FLD_DIF_DIF_SOFT_RST                       0x00000080
 481 #define      FLD_DIF_DIF_REG_RST_MSK                    0x00000040
 482 #define      FLD_DIF_AGC_RST_MSK                        0x00000020
 483 #define      FLD_DIF_CMP_RST_MSK                        0x00000010
 484 #define      FLD_DIF_AVS_RST_MSK                        0x00000008
 485 #define      FLD_DIF_NYQ_RST_MSK                        0x00000004
 486 #define      FLD_DIF_DIF_SRC_RST_MSK                    0x00000002
 487 #define      FLD_DIF_PLL_RST_MSK                        0x00000001
 488
 489 /*****************************************************************************/
 490 #define      DIF_PLL_FREQ_ERR         (DIRECT_IF_REVB_BASE + 0x0000009c)
 491 /*****************************************************************************/
 492 /*  Reserved                             [31:25] */
 493 #define      FLD_DIF_CTL_IP                             0x01ffffff
 494
 495 #endif