Linux 3.11-rc3
[cris-mirror.git] / drivers / mfd / db8500-prcmu.c
blob3c157faee645805f398cc2047d5f7b035555aacc
1 /*
2 * Copyright (C) STMicroelectronics 2009
3 * Copyright (C) ST-Ericsson SA 2010
5 * License Terms: GNU General Public License v2
6 * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
7 * Author: Sundar Iyer <sundar.iyer@stericsson.com>
8 * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
10 * U8500 PRCM Unit interface driver
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/delay.h>
16 #include <linux/errno.h>
17 #include <linux/err.h>
18 #include <linux/spinlock.h>
19 #include <linux/io.h>
20 #include <linux/slab.h>
21 #include <linux/mutex.h>
22 #include <linux/completion.h>
23 #include <linux/irq.h>
24 #include <linux/jiffies.h>
25 #include <linux/bitops.h>
26 #include <linux/fs.h>
27 #include <linux/of.h>
28 #include <linux/platform_device.h>
29 #include <linux/uaccess.h>
30 #include <linux/mfd/core.h>
31 #include <linux/mfd/dbx500-prcmu.h>
32 #include <linux/mfd/abx500/ab8500.h>
33 #include <linux/regulator/db8500-prcmu.h>
34 #include <linux/regulator/machine.h>
35 #include <linux/cpufreq.h>
36 #include <linux/platform_data/ux500_wdt.h>
37 #include <linux/platform_data/db8500_thermal.h>
38 #include "dbx500-prcmu-regs.h"
40 /* Index of different voltages to be used when accessing AVSData */
41 #define PRCM_AVS_BASE 0x2FC
42 #define PRCM_AVS_VBB_RET (PRCM_AVS_BASE + 0x0)
43 #define PRCM_AVS_VBB_MAX_OPP (PRCM_AVS_BASE + 0x1)
44 #define PRCM_AVS_VBB_100_OPP (PRCM_AVS_BASE + 0x2)
45 #define PRCM_AVS_VBB_50_OPP (PRCM_AVS_BASE + 0x3)
46 #define PRCM_AVS_VARM_MAX_OPP (PRCM_AVS_BASE + 0x4)
47 #define PRCM_AVS_VARM_100_OPP (PRCM_AVS_BASE + 0x5)
48 #define PRCM_AVS_VARM_50_OPP (PRCM_AVS_BASE + 0x6)
49 #define PRCM_AVS_VARM_RET (PRCM_AVS_BASE + 0x7)
50 #define PRCM_AVS_VAPE_100_OPP (PRCM_AVS_BASE + 0x8)
51 #define PRCM_AVS_VAPE_50_OPP (PRCM_AVS_BASE + 0x9)
52 #define PRCM_AVS_VMOD_100_OPP (PRCM_AVS_BASE + 0xA)
53 #define PRCM_AVS_VMOD_50_OPP (PRCM_AVS_BASE + 0xB)
54 #define PRCM_AVS_VSAFE (PRCM_AVS_BASE + 0xC)
56 #define PRCM_AVS_VOLTAGE 0
57 #define PRCM_AVS_VOLTAGE_MASK 0x3f
58 #define PRCM_AVS_ISSLOWSTARTUP 6
59 #define PRCM_AVS_ISSLOWSTARTUP_MASK (1 << PRCM_AVS_ISSLOWSTARTUP)
60 #define PRCM_AVS_ISMODEENABLE 7
61 #define PRCM_AVS_ISMODEENABLE_MASK (1 << PRCM_AVS_ISMODEENABLE)
63 #define PRCM_BOOT_STATUS 0xFFF
64 #define PRCM_ROMCODE_A2P 0xFFE
65 #define PRCM_ROMCODE_P2A 0xFFD
66 #define PRCM_XP70_CUR_PWR_STATE 0xFFC /* 4 BYTES */
68 #define PRCM_SW_RST_REASON 0xFF8 /* 2 bytes */
70 #define _PRCM_MBOX_HEADER 0xFE8 /* 16 bytes */
71 #define PRCM_MBOX_HEADER_REQ_MB0 (_PRCM_MBOX_HEADER + 0x0)
72 #define PRCM_MBOX_HEADER_REQ_MB1 (_PRCM_MBOX_HEADER + 0x1)
73 #define PRCM_MBOX_HEADER_REQ_MB2 (_PRCM_MBOX_HEADER + 0x2)
74 #define PRCM_MBOX_HEADER_REQ_MB3 (_PRCM_MBOX_HEADER + 0x3)
75 #define PRCM_MBOX_HEADER_REQ_MB4 (_PRCM_MBOX_HEADER + 0x4)
76 #define PRCM_MBOX_HEADER_REQ_MB5 (_PRCM_MBOX_HEADER + 0x5)
77 #define PRCM_MBOX_HEADER_ACK_MB0 (_PRCM_MBOX_HEADER + 0x8)
79 /* Req Mailboxes */
80 #define PRCM_REQ_MB0 0xFDC /* 12 bytes */
81 #define PRCM_REQ_MB1 0xFD0 /* 12 bytes */
82 #define PRCM_REQ_MB2 0xFC0 /* 16 bytes */
83 #define PRCM_REQ_MB3 0xE4C /* 372 bytes */
84 #define PRCM_REQ_MB4 0xE48 /* 4 bytes */
85 #define PRCM_REQ_MB5 0xE44 /* 4 bytes */
87 /* Ack Mailboxes */
88 #define PRCM_ACK_MB0 0xE08 /* 52 bytes */
89 #define PRCM_ACK_MB1 0xE04 /* 4 bytes */
90 #define PRCM_ACK_MB2 0xE00 /* 4 bytes */
91 #define PRCM_ACK_MB3 0xDFC /* 4 bytes */
92 #define PRCM_ACK_MB4 0xDF8 /* 4 bytes */
93 #define PRCM_ACK_MB5 0xDF4 /* 4 bytes */
95 /* Mailbox 0 headers */
96 #define MB0H_POWER_STATE_TRANS 0
97 #define MB0H_CONFIG_WAKEUPS_EXE 1
98 #define MB0H_READ_WAKEUP_ACK 3
99 #define MB0H_CONFIG_WAKEUPS_SLEEP 4
101 #define MB0H_WAKEUP_EXE 2
102 #define MB0H_WAKEUP_SLEEP 5
104 /* Mailbox 0 REQs */
105 #define PRCM_REQ_MB0_AP_POWER_STATE (PRCM_REQ_MB0 + 0x0)
106 #define PRCM_REQ_MB0_AP_PLL_STATE (PRCM_REQ_MB0 + 0x1)
107 #define PRCM_REQ_MB0_ULP_CLOCK_STATE (PRCM_REQ_MB0 + 0x2)
108 #define PRCM_REQ_MB0_DO_NOT_WFI (PRCM_REQ_MB0 + 0x3)
109 #define PRCM_REQ_MB0_WAKEUP_8500 (PRCM_REQ_MB0 + 0x4)
110 #define PRCM_REQ_MB0_WAKEUP_4500 (PRCM_REQ_MB0 + 0x8)
112 /* Mailbox 0 ACKs */
113 #define PRCM_ACK_MB0_AP_PWRSTTR_STATUS (PRCM_ACK_MB0 + 0x0)
114 #define PRCM_ACK_MB0_READ_POINTER (PRCM_ACK_MB0 + 0x1)
115 #define PRCM_ACK_MB0_WAKEUP_0_8500 (PRCM_ACK_MB0 + 0x4)
116 #define PRCM_ACK_MB0_WAKEUP_0_4500 (PRCM_ACK_MB0 + 0x8)
117 #define PRCM_ACK_MB0_WAKEUP_1_8500 (PRCM_ACK_MB0 + 0x1C)
118 #define PRCM_ACK_MB0_WAKEUP_1_4500 (PRCM_ACK_MB0 + 0x20)
119 #define PRCM_ACK_MB0_EVENT_4500_NUMBERS 20
121 /* Mailbox 1 headers */
122 #define MB1H_ARM_APE_OPP 0x0
123 #define MB1H_RESET_MODEM 0x2
124 #define MB1H_REQUEST_APE_OPP_100_VOLT 0x3
125 #define MB1H_RELEASE_APE_OPP_100_VOLT 0x4
126 #define MB1H_RELEASE_USB_WAKEUP 0x5
127 #define MB1H_PLL_ON_OFF 0x6
129 /* Mailbox 1 Requests */
130 #define PRCM_REQ_MB1_ARM_OPP (PRCM_REQ_MB1 + 0x0)
131 #define PRCM_REQ_MB1_APE_OPP (PRCM_REQ_MB1 + 0x1)
132 #define PRCM_REQ_MB1_PLL_ON_OFF (PRCM_REQ_MB1 + 0x4)
133 #define PLL_SOC0_OFF 0x1
134 #define PLL_SOC0_ON 0x2
135 #define PLL_SOC1_OFF 0x4
136 #define PLL_SOC1_ON 0x8
138 /* Mailbox 1 ACKs */
139 #define PRCM_ACK_MB1_CURRENT_ARM_OPP (PRCM_ACK_MB1 + 0x0)
140 #define PRCM_ACK_MB1_CURRENT_APE_OPP (PRCM_ACK_MB1 + 0x1)
141 #define PRCM_ACK_MB1_APE_VOLTAGE_STATUS (PRCM_ACK_MB1 + 0x2)
142 #define PRCM_ACK_MB1_DVFS_STATUS (PRCM_ACK_MB1 + 0x3)
144 /* Mailbox 2 headers */
145 #define MB2H_DPS 0x0
146 #define MB2H_AUTO_PWR 0x1
148 /* Mailbox 2 REQs */
149 #define PRCM_REQ_MB2_SVA_MMDSP (PRCM_REQ_MB2 + 0x0)
150 #define PRCM_REQ_MB2_SVA_PIPE (PRCM_REQ_MB2 + 0x1)
151 #define PRCM_REQ_MB2_SIA_MMDSP (PRCM_REQ_MB2 + 0x2)
152 #define PRCM_REQ_MB2_SIA_PIPE (PRCM_REQ_MB2 + 0x3)
153 #define PRCM_REQ_MB2_SGA (PRCM_REQ_MB2 + 0x4)
154 #define PRCM_REQ_MB2_B2R2_MCDE (PRCM_REQ_MB2 + 0x5)
155 #define PRCM_REQ_MB2_ESRAM12 (PRCM_REQ_MB2 + 0x6)
156 #define PRCM_REQ_MB2_ESRAM34 (PRCM_REQ_MB2 + 0x7)
157 #define PRCM_REQ_MB2_AUTO_PM_SLEEP (PRCM_REQ_MB2 + 0x8)
158 #define PRCM_REQ_MB2_AUTO_PM_IDLE (PRCM_REQ_MB2 + 0xC)
160 /* Mailbox 2 ACKs */
161 #define PRCM_ACK_MB2_DPS_STATUS (PRCM_ACK_MB2 + 0x0)
162 #define HWACC_PWR_ST_OK 0xFE
164 /* Mailbox 3 headers */
165 #define MB3H_ANC 0x0
166 #define MB3H_SIDETONE 0x1
167 #define MB3H_SYSCLK 0xE
169 /* Mailbox 3 Requests */
170 #define PRCM_REQ_MB3_ANC_FIR_COEFF (PRCM_REQ_MB3 + 0x0)
171 #define PRCM_REQ_MB3_ANC_IIR_COEFF (PRCM_REQ_MB3 + 0x20)
172 #define PRCM_REQ_MB3_ANC_SHIFTER (PRCM_REQ_MB3 + 0x60)
173 #define PRCM_REQ_MB3_ANC_WARP (PRCM_REQ_MB3 + 0x64)
174 #define PRCM_REQ_MB3_SIDETONE_FIR_GAIN (PRCM_REQ_MB3 + 0x68)
175 #define PRCM_REQ_MB3_SIDETONE_FIR_COEFF (PRCM_REQ_MB3 + 0x6C)
176 #define PRCM_REQ_MB3_SYSCLK_MGT (PRCM_REQ_MB3 + 0x16C)
178 /* Mailbox 4 headers */
179 #define MB4H_DDR_INIT 0x0
180 #define MB4H_MEM_ST 0x1
181 #define MB4H_HOTDOG 0x12
182 #define MB4H_HOTMON 0x13
183 #define MB4H_HOT_PERIOD 0x14
184 #define MB4H_A9WDOG_CONF 0x16
185 #define MB4H_A9WDOG_EN 0x17
186 #define MB4H_A9WDOG_DIS 0x18
187 #define MB4H_A9WDOG_LOAD 0x19
188 #define MB4H_A9WDOG_KICK 0x20
190 /* Mailbox 4 Requests */
191 #define PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE (PRCM_REQ_MB4 + 0x0)
192 #define PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE (PRCM_REQ_MB4 + 0x1)
193 #define PRCM_REQ_MB4_ESRAM0_ST (PRCM_REQ_MB4 + 0x3)
194 #define PRCM_REQ_MB4_HOTDOG_THRESHOLD (PRCM_REQ_MB4 + 0x0)
195 #define PRCM_REQ_MB4_HOTMON_LOW (PRCM_REQ_MB4 + 0x0)
196 #define PRCM_REQ_MB4_HOTMON_HIGH (PRCM_REQ_MB4 + 0x1)
197 #define PRCM_REQ_MB4_HOTMON_CONFIG (PRCM_REQ_MB4 + 0x2)
198 #define PRCM_REQ_MB4_HOT_PERIOD (PRCM_REQ_MB4 + 0x0)
199 #define HOTMON_CONFIG_LOW BIT(0)
200 #define HOTMON_CONFIG_HIGH BIT(1)
201 #define PRCM_REQ_MB4_A9WDOG_0 (PRCM_REQ_MB4 + 0x0)
202 #define PRCM_REQ_MB4_A9WDOG_1 (PRCM_REQ_MB4 + 0x1)
203 #define PRCM_REQ_MB4_A9WDOG_2 (PRCM_REQ_MB4 + 0x2)
204 #define PRCM_REQ_MB4_A9WDOG_3 (PRCM_REQ_MB4 + 0x3)
205 #define A9WDOG_AUTO_OFF_EN BIT(7)
206 #define A9WDOG_AUTO_OFF_DIS 0
207 #define A9WDOG_ID_MASK 0xf
209 /* Mailbox 5 Requests */
210 #define PRCM_REQ_MB5_I2C_SLAVE_OP (PRCM_REQ_MB5 + 0x0)
211 #define PRCM_REQ_MB5_I2C_HW_BITS (PRCM_REQ_MB5 + 0x1)
212 #define PRCM_REQ_MB5_I2C_REG (PRCM_REQ_MB5 + 0x2)
213 #define PRCM_REQ_MB5_I2C_VAL (PRCM_REQ_MB5 + 0x3)
214 #define PRCMU_I2C_WRITE(slave) (((slave) << 1) | BIT(6))
215 #define PRCMU_I2C_READ(slave) (((slave) << 1) | BIT(0) | BIT(6))
216 #define PRCMU_I2C_STOP_EN BIT(3)
218 /* Mailbox 5 ACKs */
219 #define PRCM_ACK_MB5_I2C_STATUS (PRCM_ACK_MB5 + 0x1)
220 #define PRCM_ACK_MB5_I2C_VAL (PRCM_ACK_MB5 + 0x3)
221 #define I2C_WR_OK 0x1
222 #define I2C_RD_OK 0x2
224 #define NUM_MB 8
225 #define MBOX_BIT BIT
226 #define ALL_MBOX_BITS (MBOX_BIT(NUM_MB) - 1)
229 * Wakeups/IRQs
232 #define WAKEUP_BIT_RTC BIT(0)
233 #define WAKEUP_BIT_RTT0 BIT(1)
234 #define WAKEUP_BIT_RTT1 BIT(2)
235 #define WAKEUP_BIT_HSI0 BIT(3)
236 #define WAKEUP_BIT_HSI1 BIT(4)
237 #define WAKEUP_BIT_CA_WAKE BIT(5)
238 #define WAKEUP_BIT_USB BIT(6)
239 #define WAKEUP_BIT_ABB BIT(7)
240 #define WAKEUP_BIT_ABB_FIFO BIT(8)
241 #define WAKEUP_BIT_SYSCLK_OK BIT(9)
242 #define WAKEUP_BIT_CA_SLEEP BIT(10)
243 #define WAKEUP_BIT_AC_WAKE_ACK BIT(11)
244 #define WAKEUP_BIT_SIDE_TONE_OK BIT(12)
245 #define WAKEUP_BIT_ANC_OK BIT(13)
246 #define WAKEUP_BIT_SW_ERROR BIT(14)
247 #define WAKEUP_BIT_AC_SLEEP_ACK BIT(15)
248 #define WAKEUP_BIT_ARM BIT(17)
249 #define WAKEUP_BIT_HOTMON_LOW BIT(18)
250 #define WAKEUP_BIT_HOTMON_HIGH BIT(19)
251 #define WAKEUP_BIT_MODEM_SW_RESET_REQ BIT(20)
252 #define WAKEUP_BIT_GPIO0 BIT(23)
253 #define WAKEUP_BIT_GPIO1 BIT(24)
254 #define WAKEUP_BIT_GPIO2 BIT(25)
255 #define WAKEUP_BIT_GPIO3 BIT(26)
256 #define WAKEUP_BIT_GPIO4 BIT(27)
257 #define WAKEUP_BIT_GPIO5 BIT(28)
258 #define WAKEUP_BIT_GPIO6 BIT(29)
259 #define WAKEUP_BIT_GPIO7 BIT(30)
260 #define WAKEUP_BIT_GPIO8 BIT(31)
262 static struct {
263 bool valid;
264 struct prcmu_fw_version version;
265 } fw_info;
267 static struct irq_domain *db8500_irq_domain;
270 * This vector maps irq numbers to the bits in the bit field used in
271 * communication with the PRCMU firmware.
273 * The reason for having this is to keep the irq numbers contiguous even though
274 * the bits in the bit field are not. (The bits also have a tendency to move
275 * around, to further complicate matters.)
277 #define IRQ_INDEX(_name) ((IRQ_PRCMU_##_name))
278 #define IRQ_ENTRY(_name)[IRQ_INDEX(_name)] = (WAKEUP_BIT_##_name)
280 #define IRQ_PRCMU_RTC 0
281 #define IRQ_PRCMU_RTT0 1
282 #define IRQ_PRCMU_RTT1 2
283 #define IRQ_PRCMU_HSI0 3
284 #define IRQ_PRCMU_HSI1 4
285 #define IRQ_PRCMU_CA_WAKE 5
286 #define IRQ_PRCMU_USB 6
287 #define IRQ_PRCMU_ABB 7
288 #define IRQ_PRCMU_ABB_FIFO 8
289 #define IRQ_PRCMU_ARM 9
290 #define IRQ_PRCMU_MODEM_SW_RESET_REQ 10
291 #define IRQ_PRCMU_GPIO0 11
292 #define IRQ_PRCMU_GPIO1 12
293 #define IRQ_PRCMU_GPIO2 13
294 #define IRQ_PRCMU_GPIO3 14
295 #define IRQ_PRCMU_GPIO4 15
296 #define IRQ_PRCMU_GPIO5 16
297 #define IRQ_PRCMU_GPIO6 17
298 #define IRQ_PRCMU_GPIO7 18
299 #define IRQ_PRCMU_GPIO8 19
300 #define IRQ_PRCMU_CA_SLEEP 20
301 #define IRQ_PRCMU_HOTMON_LOW 21
302 #define IRQ_PRCMU_HOTMON_HIGH 22
303 #define NUM_PRCMU_WAKEUPS 23
305 static u32 prcmu_irq_bit[NUM_PRCMU_WAKEUPS] = {
306 IRQ_ENTRY(RTC),
307 IRQ_ENTRY(RTT0),
308 IRQ_ENTRY(RTT1),
309 IRQ_ENTRY(HSI0),
310 IRQ_ENTRY(HSI1),
311 IRQ_ENTRY(CA_WAKE),
312 IRQ_ENTRY(USB),
313 IRQ_ENTRY(ABB),
314 IRQ_ENTRY(ABB_FIFO),
315 IRQ_ENTRY(CA_SLEEP),
316 IRQ_ENTRY(ARM),
317 IRQ_ENTRY(HOTMON_LOW),
318 IRQ_ENTRY(HOTMON_HIGH),
319 IRQ_ENTRY(MODEM_SW_RESET_REQ),
320 IRQ_ENTRY(GPIO0),
321 IRQ_ENTRY(GPIO1),
322 IRQ_ENTRY(GPIO2),
323 IRQ_ENTRY(GPIO3),
324 IRQ_ENTRY(GPIO4),
325 IRQ_ENTRY(GPIO5),
326 IRQ_ENTRY(GPIO6),
327 IRQ_ENTRY(GPIO7),
328 IRQ_ENTRY(GPIO8)
331 #define VALID_WAKEUPS (BIT(NUM_PRCMU_WAKEUP_INDICES) - 1)
332 #define WAKEUP_ENTRY(_name)[PRCMU_WAKEUP_INDEX_##_name] = (WAKEUP_BIT_##_name)
333 static u32 prcmu_wakeup_bit[NUM_PRCMU_WAKEUP_INDICES] = {
334 WAKEUP_ENTRY(RTC),
335 WAKEUP_ENTRY(RTT0),
336 WAKEUP_ENTRY(RTT1),
337 WAKEUP_ENTRY(HSI0),
338 WAKEUP_ENTRY(HSI1),
339 WAKEUP_ENTRY(USB),
340 WAKEUP_ENTRY(ABB),
341 WAKEUP_ENTRY(ABB_FIFO),
342 WAKEUP_ENTRY(ARM)
346 * mb0_transfer - state needed for mailbox 0 communication.
347 * @lock: The transaction lock.
348 * @dbb_events_lock: A lock used to handle concurrent access to (parts of)
349 * the request data.
350 * @mask_work: Work structure used for (un)masking wakeup interrupts.
351 * @req: Request data that need to persist between requests.
353 static struct {
354 spinlock_t lock;
355 spinlock_t dbb_irqs_lock;
356 struct work_struct mask_work;
357 struct mutex ac_wake_lock;
358 struct completion ac_wake_work;
359 struct {
360 u32 dbb_irqs;
361 u32 dbb_wakeups;
362 u32 abb_events;
363 } req;
364 } mb0_transfer;
367 * mb1_transfer - state needed for mailbox 1 communication.
368 * @lock: The transaction lock.
369 * @work: The transaction completion structure.
370 * @ape_opp: The current APE OPP.
371 * @ack: Reply ("acknowledge") data.
373 static struct {
374 struct mutex lock;
375 struct completion work;
376 u8 ape_opp;
377 struct {
378 u8 header;
379 u8 arm_opp;
380 u8 ape_opp;
381 u8 ape_voltage_status;
382 } ack;
383 } mb1_transfer;
386 * mb2_transfer - state needed for mailbox 2 communication.
387 * @lock: The transaction lock.
388 * @work: The transaction completion structure.
389 * @auto_pm_lock: The autonomous power management configuration lock.
390 * @auto_pm_enabled: A flag indicating whether autonomous PM is enabled.
391 * @req: Request data that need to persist between requests.
392 * @ack: Reply ("acknowledge") data.
394 static struct {
395 struct mutex lock;
396 struct completion work;
397 spinlock_t auto_pm_lock;
398 bool auto_pm_enabled;
399 struct {
400 u8 status;
401 } ack;
402 } mb2_transfer;
405 * mb3_transfer - state needed for mailbox 3 communication.
406 * @lock: The request lock.
407 * @sysclk_lock: A lock used to handle concurrent sysclk requests.
408 * @sysclk_work: Work structure used for sysclk requests.
410 static struct {
411 spinlock_t lock;
412 struct mutex sysclk_lock;
413 struct completion sysclk_work;
414 } mb3_transfer;
417 * mb4_transfer - state needed for mailbox 4 communication.
418 * @lock: The transaction lock.
419 * @work: The transaction completion structure.
421 static struct {
422 struct mutex lock;
423 struct completion work;
424 } mb4_transfer;
427 * mb5_transfer - state needed for mailbox 5 communication.
428 * @lock: The transaction lock.
429 * @work: The transaction completion structure.
430 * @ack: Reply ("acknowledge") data.
432 static struct {
433 struct mutex lock;
434 struct completion work;
435 struct {
436 u8 status;
437 u8 value;
438 } ack;
439 } mb5_transfer;
441 static atomic_t ac_wake_req_state = ATOMIC_INIT(0);
443 /* Spinlocks */
444 static DEFINE_SPINLOCK(prcmu_lock);
445 static DEFINE_SPINLOCK(clkout_lock);
447 /* Global var to runtime determine TCDM base for v2 or v1 */
448 static __iomem void *tcdm_base;
449 static __iomem void *prcmu_base;
451 struct clk_mgt {
452 u32 offset;
453 u32 pllsw;
454 int branch;
455 bool clk38div;
458 enum {
459 PLL_RAW,
460 PLL_FIX,
461 PLL_DIV
464 static DEFINE_SPINLOCK(clk_mgt_lock);
466 #define CLK_MGT_ENTRY(_name, _branch, _clk38div)[PRCMU_##_name] = \
467 { (PRCM_##_name##_MGT), 0 , _branch, _clk38div}
468 struct clk_mgt clk_mgt[PRCMU_NUM_REG_CLOCKS] = {
469 CLK_MGT_ENTRY(SGACLK, PLL_DIV, false),
470 CLK_MGT_ENTRY(UARTCLK, PLL_FIX, true),
471 CLK_MGT_ENTRY(MSP02CLK, PLL_FIX, true),
472 CLK_MGT_ENTRY(MSP1CLK, PLL_FIX, true),
473 CLK_MGT_ENTRY(I2CCLK, PLL_FIX, true),
474 CLK_MGT_ENTRY(SDMMCCLK, PLL_DIV, true),
475 CLK_MGT_ENTRY(SLIMCLK, PLL_FIX, true),
476 CLK_MGT_ENTRY(PER1CLK, PLL_DIV, true),
477 CLK_MGT_ENTRY(PER2CLK, PLL_DIV, true),
478 CLK_MGT_ENTRY(PER3CLK, PLL_DIV, true),
479 CLK_MGT_ENTRY(PER5CLK, PLL_DIV, true),
480 CLK_MGT_ENTRY(PER6CLK, PLL_DIV, true),
481 CLK_MGT_ENTRY(PER7CLK, PLL_DIV, true),
482 CLK_MGT_ENTRY(LCDCLK, PLL_FIX, true),
483 CLK_MGT_ENTRY(BML8580CLK, PLL_DIV, true),
484 CLK_MGT_ENTRY(BMLCLK, PLL_DIV, true),
485 CLK_MGT_ENTRY(HSITXCLK, PLL_DIV, true),
486 CLK_MGT_ENTRY(HSIRXCLK, PLL_DIV, true),
487 CLK_MGT_ENTRY(HDMICLK, PLL_FIX, false),
488 CLK_MGT_ENTRY(APEATCLK, PLL_DIV, true),
489 CLK_MGT_ENTRY(APETRACECLK, PLL_DIV, true),
490 CLK_MGT_ENTRY(MCDECLK, PLL_DIV, true),
491 CLK_MGT_ENTRY(IPI2CCLK, PLL_FIX, true),
492 CLK_MGT_ENTRY(DSIALTCLK, PLL_FIX, false),
493 CLK_MGT_ENTRY(DMACLK, PLL_DIV, true),
494 CLK_MGT_ENTRY(B2R2CLK, PLL_DIV, true),
495 CLK_MGT_ENTRY(TVCLK, PLL_FIX, true),
496 CLK_MGT_ENTRY(SSPCLK, PLL_FIX, true),
497 CLK_MGT_ENTRY(RNGCLK, PLL_FIX, true),
498 CLK_MGT_ENTRY(UICCCLK, PLL_FIX, false),
501 struct dsiclk {
502 u32 divsel_mask;
503 u32 divsel_shift;
504 u32 divsel;
507 static struct dsiclk dsiclk[2] = {
509 .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_MASK,
510 .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_SHIFT,
511 .divsel = PRCM_DSI_PLLOUT_SEL_PHI,
514 .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_MASK,
515 .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_SHIFT,
516 .divsel = PRCM_DSI_PLLOUT_SEL_PHI,
520 struct dsiescclk {
521 u32 en;
522 u32 div_mask;
523 u32 div_shift;
526 static struct dsiescclk dsiescclk[3] = {
528 .en = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_EN,
529 .div_mask = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_MASK,
530 .div_shift = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_SHIFT,
533 .en = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_EN,
534 .div_mask = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_MASK,
535 .div_shift = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_SHIFT,
538 .en = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_EN,
539 .div_mask = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_MASK,
540 .div_shift = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_SHIFT,
546 * Used by MCDE to setup all necessary PRCMU registers
548 #define PRCMU_RESET_DSIPLL 0x00004000
549 #define PRCMU_UNCLAMP_DSIPLL 0x00400800
551 #define PRCMU_CLK_PLL_DIV_SHIFT 0
552 #define PRCMU_CLK_PLL_SW_SHIFT 5
553 #define PRCMU_CLK_38 (1 << 9)
554 #define PRCMU_CLK_38_SRC (1 << 10)
555 #define PRCMU_CLK_38_DIV (1 << 11)
557 /* PLLDIV=12, PLLSW=4 (PLLDDR) */
558 #define PRCMU_DSI_CLOCK_SETTING 0x0000008C
560 /* DPI 50000000 Hz */
561 #define PRCMU_DPI_CLOCK_SETTING ((1 << PRCMU_CLK_PLL_SW_SHIFT) | \
562 (16 << PRCMU_CLK_PLL_DIV_SHIFT))
563 #define PRCMU_DSI_LP_CLOCK_SETTING 0x00000E00
565 /* D=101, N=1, R=4, SELDIV2=0 */
566 #define PRCMU_PLLDSI_FREQ_SETTING 0x00040165
568 #define PRCMU_ENABLE_PLLDSI 0x00000001
569 #define PRCMU_DISABLE_PLLDSI 0x00000000
570 #define PRCMU_RELEASE_RESET_DSS 0x0000400C
571 #define PRCMU_DSI_PLLOUT_SEL_SETTING 0x00000202
572 /* ESC clk, div0=1, div1=1, div2=3 */
573 #define PRCMU_ENABLE_ESCAPE_CLOCK_DIV 0x07030101
574 #define PRCMU_DISABLE_ESCAPE_CLOCK_DIV 0x00030101
575 #define PRCMU_DSI_RESET_SW 0x00000007
577 #define PRCMU_PLLDSI_LOCKP_LOCKED 0x3
579 int db8500_prcmu_enable_dsipll(void)
581 int i;
583 /* Clear DSIPLL_RESETN */
584 writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_CLR);
585 /* Unclamp DSIPLL in/out */
586 writel(PRCMU_UNCLAMP_DSIPLL, PRCM_MMIP_LS_CLAMP_CLR);
588 /* Set DSI PLL FREQ */
589 writel(PRCMU_PLLDSI_FREQ_SETTING, PRCM_PLLDSI_FREQ);
590 writel(PRCMU_DSI_PLLOUT_SEL_SETTING, PRCM_DSI_PLLOUT_SEL);
591 /* Enable Escape clocks */
592 writel(PRCMU_ENABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV);
594 /* Start DSI PLL */
595 writel(PRCMU_ENABLE_PLLDSI, PRCM_PLLDSI_ENABLE);
596 /* Reset DSI PLL */
597 writel(PRCMU_DSI_RESET_SW, PRCM_DSI_SW_RESET);
598 for (i = 0; i < 10; i++) {
599 if ((readl(PRCM_PLLDSI_LOCKP) & PRCMU_PLLDSI_LOCKP_LOCKED)
600 == PRCMU_PLLDSI_LOCKP_LOCKED)
601 break;
602 udelay(100);
604 /* Set DSIPLL_RESETN */
605 writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_SET);
606 return 0;
609 int db8500_prcmu_disable_dsipll(void)
611 /* Disable dsi pll */
612 writel(PRCMU_DISABLE_PLLDSI, PRCM_PLLDSI_ENABLE);
613 /* Disable escapeclock */
614 writel(PRCMU_DISABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV);
615 return 0;
618 int db8500_prcmu_set_display_clocks(void)
620 unsigned long flags;
622 spin_lock_irqsave(&clk_mgt_lock, flags);
624 /* Grab the HW semaphore. */
625 while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
626 cpu_relax();
628 writel(PRCMU_DSI_CLOCK_SETTING, prcmu_base + PRCM_HDMICLK_MGT);
629 writel(PRCMU_DSI_LP_CLOCK_SETTING, prcmu_base + PRCM_TVCLK_MGT);
630 writel(PRCMU_DPI_CLOCK_SETTING, prcmu_base + PRCM_LCDCLK_MGT);
632 /* Release the HW semaphore. */
633 writel(0, PRCM_SEM);
635 spin_unlock_irqrestore(&clk_mgt_lock, flags);
637 return 0;
640 u32 db8500_prcmu_read(unsigned int reg)
642 return readl(prcmu_base + reg);
645 void db8500_prcmu_write(unsigned int reg, u32 value)
647 unsigned long flags;
649 spin_lock_irqsave(&prcmu_lock, flags);
650 writel(value, (prcmu_base + reg));
651 spin_unlock_irqrestore(&prcmu_lock, flags);
654 void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value)
656 u32 val;
657 unsigned long flags;
659 spin_lock_irqsave(&prcmu_lock, flags);
660 val = readl(prcmu_base + reg);
661 val = ((val & ~mask) | (value & mask));
662 writel(val, (prcmu_base + reg));
663 spin_unlock_irqrestore(&prcmu_lock, flags);
666 struct prcmu_fw_version *prcmu_get_fw_version(void)
668 return fw_info.valid ? &fw_info.version : NULL;
671 bool prcmu_has_arm_maxopp(void)
673 return (readb(tcdm_base + PRCM_AVS_VARM_MAX_OPP) &
674 PRCM_AVS_ISMODEENABLE_MASK) == PRCM_AVS_ISMODEENABLE_MASK;
678 * prcmu_get_boot_status - PRCMU boot status checking
679 * Returns: the current PRCMU boot status
681 int prcmu_get_boot_status(void)
683 return readb(tcdm_base + PRCM_BOOT_STATUS);
687 * prcmu_set_rc_a2p - This function is used to run few power state sequences
688 * @val: Value to be set, i.e. transition requested
689 * Returns: 0 on success, -EINVAL on invalid argument
691 * This function is used to run the following power state sequences -
692 * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep
694 int prcmu_set_rc_a2p(enum romcode_write val)
696 if (val < RDY_2_DS || val > RDY_2_XP70_RST)
697 return -EINVAL;
698 writeb(val, (tcdm_base + PRCM_ROMCODE_A2P));
699 return 0;
703 * prcmu_get_rc_p2a - This function is used to get power state sequences
704 * Returns: the power transition that has last happened
706 * This function can return the following transitions-
707 * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep
709 enum romcode_read prcmu_get_rc_p2a(void)
711 return readb(tcdm_base + PRCM_ROMCODE_P2A);
715 * prcmu_get_current_mode - Return the current XP70 power mode
716 * Returns: Returns the current AP(ARM) power mode: init,
717 * apBoot, apExecute, apDeepSleep, apSleep, apIdle, apReset
719 enum ap_pwrst prcmu_get_xp70_current_state(void)
721 return readb(tcdm_base + PRCM_XP70_CUR_PWR_STATE);
725 * prcmu_config_clkout - Configure one of the programmable clock outputs.
726 * @clkout: The CLKOUT number (0 or 1).
727 * @source: The clock to be used (one of the PRCMU_CLKSRC_*).
728 * @div: The divider to be applied.
730 * Configures one of the programmable clock outputs (CLKOUTs).
731 * @div should be in the range [1,63] to request a configuration, or 0 to
732 * inform that the configuration is no longer requested.
734 int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
736 static int requests[2];
737 int r = 0;
738 unsigned long flags;
739 u32 val;
740 u32 bits;
741 u32 mask;
742 u32 div_mask;
744 BUG_ON(clkout > 1);
745 BUG_ON(div > 63);
746 BUG_ON((clkout == 0) && (source > PRCMU_CLKSRC_CLK009));
748 if (!div && !requests[clkout])
749 return -EINVAL;
751 switch (clkout) {
752 case 0:
753 div_mask = PRCM_CLKOCR_CLKODIV0_MASK;
754 mask = (PRCM_CLKOCR_CLKODIV0_MASK | PRCM_CLKOCR_CLKOSEL0_MASK);
755 bits = ((source << PRCM_CLKOCR_CLKOSEL0_SHIFT) |
756 (div << PRCM_CLKOCR_CLKODIV0_SHIFT));
757 break;
758 case 1:
759 div_mask = PRCM_CLKOCR_CLKODIV1_MASK;
760 mask = (PRCM_CLKOCR_CLKODIV1_MASK | PRCM_CLKOCR_CLKOSEL1_MASK |
761 PRCM_CLKOCR_CLK1TYPE);
762 bits = ((source << PRCM_CLKOCR_CLKOSEL1_SHIFT) |
763 (div << PRCM_CLKOCR_CLKODIV1_SHIFT));
764 break;
766 bits &= mask;
768 spin_lock_irqsave(&clkout_lock, flags);
770 val = readl(PRCM_CLKOCR);
771 if (val & div_mask) {
772 if (div) {
773 if ((val & mask) != bits) {
774 r = -EBUSY;
775 goto unlock_and_return;
777 } else {
778 if ((val & mask & ~div_mask) != bits) {
779 r = -EINVAL;
780 goto unlock_and_return;
784 writel((bits | (val & ~mask)), PRCM_CLKOCR);
785 requests[clkout] += (div ? 1 : -1);
787 unlock_and_return:
788 spin_unlock_irqrestore(&clkout_lock, flags);
790 return r;
793 int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll)
795 unsigned long flags;
797 BUG_ON((state < PRCMU_AP_SLEEP) || (PRCMU_AP_DEEP_IDLE < state));
799 spin_lock_irqsave(&mb0_transfer.lock, flags);
801 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
802 cpu_relax();
804 writeb(MB0H_POWER_STATE_TRANS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
805 writeb(state, (tcdm_base + PRCM_REQ_MB0_AP_POWER_STATE));
806 writeb((keep_ap_pll ? 1 : 0), (tcdm_base + PRCM_REQ_MB0_AP_PLL_STATE));
807 writeb((keep_ulp_clk ? 1 : 0),
808 (tcdm_base + PRCM_REQ_MB0_ULP_CLOCK_STATE));
809 writeb(0, (tcdm_base + PRCM_REQ_MB0_DO_NOT_WFI));
810 writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
812 spin_unlock_irqrestore(&mb0_transfer.lock, flags);
814 return 0;
817 u8 db8500_prcmu_get_power_state_result(void)
819 return readb(tcdm_base + PRCM_ACK_MB0_AP_PWRSTTR_STATUS);
822 /* This function should only be called while mb0_transfer.lock is held. */
823 static void config_wakeups(void)
825 const u8 header[2] = {
826 MB0H_CONFIG_WAKEUPS_EXE,
827 MB0H_CONFIG_WAKEUPS_SLEEP
829 static u32 last_dbb_events;
830 static u32 last_abb_events;
831 u32 dbb_events;
832 u32 abb_events;
833 unsigned int i;
835 dbb_events = mb0_transfer.req.dbb_irqs | mb0_transfer.req.dbb_wakeups;
836 dbb_events |= (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK);
838 abb_events = mb0_transfer.req.abb_events;
840 if ((dbb_events == last_dbb_events) && (abb_events == last_abb_events))
841 return;
843 for (i = 0; i < 2; i++) {
844 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
845 cpu_relax();
846 writel(dbb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_8500));
847 writel(abb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_4500));
848 writeb(header[i], (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
849 writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
851 last_dbb_events = dbb_events;
852 last_abb_events = abb_events;
855 void db8500_prcmu_enable_wakeups(u32 wakeups)
857 unsigned long flags;
858 u32 bits;
859 int i;
861 BUG_ON(wakeups != (wakeups & VALID_WAKEUPS));
863 for (i = 0, bits = 0; i < NUM_PRCMU_WAKEUP_INDICES; i++) {
864 if (wakeups & BIT(i))
865 bits |= prcmu_wakeup_bit[i];
868 spin_lock_irqsave(&mb0_transfer.lock, flags);
870 mb0_transfer.req.dbb_wakeups = bits;
871 config_wakeups();
873 spin_unlock_irqrestore(&mb0_transfer.lock, flags);
876 void db8500_prcmu_config_abb_event_readout(u32 abb_events)
878 unsigned long flags;
880 spin_lock_irqsave(&mb0_transfer.lock, flags);
882 mb0_transfer.req.abb_events = abb_events;
883 config_wakeups();
885 spin_unlock_irqrestore(&mb0_transfer.lock, flags);
888 void db8500_prcmu_get_abb_event_buffer(void __iomem **buf)
890 if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1)
891 *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_1_4500);
892 else
893 *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_0_4500);
897 * db8500_prcmu_set_arm_opp - set the appropriate ARM OPP
898 * @opp: The new ARM operating point to which transition is to be made
899 * Returns: 0 on success, non-zero on failure
901 * This function sets the the operating point of the ARM.
903 int db8500_prcmu_set_arm_opp(u8 opp)
905 int r;
907 if (opp < ARM_NO_CHANGE || opp > ARM_EXTCLK)
908 return -EINVAL;
910 r = 0;
912 mutex_lock(&mb1_transfer.lock);
914 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
915 cpu_relax();
917 writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
918 writeb(opp, (tcdm_base + PRCM_REQ_MB1_ARM_OPP));
919 writeb(APE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_APE_OPP));
921 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
922 wait_for_completion(&mb1_transfer.work);
924 if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) ||
925 (mb1_transfer.ack.arm_opp != opp))
926 r = -EIO;
928 mutex_unlock(&mb1_transfer.lock);
930 return r;
934 * db8500_prcmu_get_arm_opp - get the current ARM OPP
936 * Returns: the current ARM OPP
938 int db8500_prcmu_get_arm_opp(void)
940 return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_ARM_OPP);
944 * db8500_prcmu_get_ddr_opp - get the current DDR OPP
946 * Returns: the current DDR OPP
948 int db8500_prcmu_get_ddr_opp(void)
950 return readb(PRCM_DDR_SUBSYS_APE_MINBW);
954 * db8500_set_ddr_opp - set the appropriate DDR OPP
955 * @opp: The new DDR operating point to which transition is to be made
956 * Returns: 0 on success, non-zero on failure
958 * This function sets the operating point of the DDR.
960 static bool enable_set_ddr_opp;
961 int db8500_prcmu_set_ddr_opp(u8 opp)
963 if (opp < DDR_100_OPP || opp > DDR_25_OPP)
964 return -EINVAL;
965 /* Changing the DDR OPP can hang the hardware pre-v21 */
966 if (enable_set_ddr_opp)
967 writeb(opp, PRCM_DDR_SUBSYS_APE_MINBW);
969 return 0;
972 /* Divide the frequency of certain clocks by 2 for APE_50_PARTLY_25_OPP. */
973 static void request_even_slower_clocks(bool enable)
975 u32 clock_reg[] = {
976 PRCM_ACLK_MGT,
977 PRCM_DMACLK_MGT
979 unsigned long flags;
980 unsigned int i;
982 spin_lock_irqsave(&clk_mgt_lock, flags);
984 /* Grab the HW semaphore. */
985 while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
986 cpu_relax();
988 for (i = 0; i < ARRAY_SIZE(clock_reg); i++) {
989 u32 val;
990 u32 div;
992 val = readl(prcmu_base + clock_reg[i]);
993 div = (val & PRCM_CLK_MGT_CLKPLLDIV_MASK);
994 if (enable) {
995 if ((div <= 1) || (div > 15)) {
996 pr_err("prcmu: Bad clock divider %d in %s\n",
997 div, __func__);
998 goto unlock_and_return;
1000 div <<= 1;
1001 } else {
1002 if (div <= 2)
1003 goto unlock_and_return;
1004 div >>= 1;
1006 val = ((val & ~PRCM_CLK_MGT_CLKPLLDIV_MASK) |
1007 (div & PRCM_CLK_MGT_CLKPLLDIV_MASK));
1008 writel(val, prcmu_base + clock_reg[i]);
1011 unlock_and_return:
1012 /* Release the HW semaphore. */
1013 writel(0, PRCM_SEM);
1015 spin_unlock_irqrestore(&clk_mgt_lock, flags);
1019 * db8500_set_ape_opp - set the appropriate APE OPP
1020 * @opp: The new APE operating point to which transition is to be made
1021 * Returns: 0 on success, non-zero on failure
1023 * This function sets the operating point of the APE.
1025 int db8500_prcmu_set_ape_opp(u8 opp)
1027 int r = 0;
1029 if (opp == mb1_transfer.ape_opp)
1030 return 0;
1032 mutex_lock(&mb1_transfer.lock);
1034 if (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP)
1035 request_even_slower_clocks(false);
1037 if ((opp != APE_100_OPP) && (mb1_transfer.ape_opp != APE_100_OPP))
1038 goto skip_message;
1040 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1041 cpu_relax();
1043 writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1044 writeb(ARM_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_ARM_OPP));
1045 writeb(((opp == APE_50_PARTLY_25_OPP) ? APE_50_OPP : opp),
1046 (tcdm_base + PRCM_REQ_MB1_APE_OPP));
1048 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1049 wait_for_completion(&mb1_transfer.work);
1051 if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) ||
1052 (mb1_transfer.ack.ape_opp != opp))
1053 r = -EIO;
1055 skip_message:
1056 if ((!r && (opp == APE_50_PARTLY_25_OPP)) ||
1057 (r && (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP)))
1058 request_even_slower_clocks(true);
1059 if (!r)
1060 mb1_transfer.ape_opp = opp;
1062 mutex_unlock(&mb1_transfer.lock);
1064 return r;
1068 * db8500_prcmu_get_ape_opp - get the current APE OPP
1070 * Returns: the current APE OPP
1072 int db8500_prcmu_get_ape_opp(void)
1074 return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_APE_OPP);
1078 * db8500_prcmu_request_ape_opp_100_voltage - Request APE OPP 100% voltage
1079 * @enable: true to request the higher voltage, false to drop a request.
1081 * Calls to this function to enable and disable requests must be balanced.
1083 int db8500_prcmu_request_ape_opp_100_voltage(bool enable)
1085 int r = 0;
1086 u8 header;
1087 static unsigned int requests;
1089 mutex_lock(&mb1_transfer.lock);
1091 if (enable) {
1092 if (0 != requests++)
1093 goto unlock_and_return;
1094 header = MB1H_REQUEST_APE_OPP_100_VOLT;
1095 } else {
1096 if (requests == 0) {
1097 r = -EIO;
1098 goto unlock_and_return;
1099 } else if (1 != requests--) {
1100 goto unlock_and_return;
1102 header = MB1H_RELEASE_APE_OPP_100_VOLT;
1105 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1106 cpu_relax();
1108 writeb(header, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1110 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1111 wait_for_completion(&mb1_transfer.work);
1113 if ((mb1_transfer.ack.header != header) ||
1114 ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0))
1115 r = -EIO;
1117 unlock_and_return:
1118 mutex_unlock(&mb1_transfer.lock);
1120 return r;
1124 * prcmu_release_usb_wakeup_state - release the state required by a USB wakeup
1126 * This function releases the power state requirements of a USB wakeup.
1128 int prcmu_release_usb_wakeup_state(void)
1130 int r = 0;
1132 mutex_lock(&mb1_transfer.lock);
1134 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1135 cpu_relax();
1137 writeb(MB1H_RELEASE_USB_WAKEUP,
1138 (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1140 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1141 wait_for_completion(&mb1_transfer.work);
1143 if ((mb1_transfer.ack.header != MB1H_RELEASE_USB_WAKEUP) ||
1144 ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0))
1145 r = -EIO;
1147 mutex_unlock(&mb1_transfer.lock);
1149 return r;
1152 static int request_pll(u8 clock, bool enable)
1154 int r = 0;
1156 if (clock == PRCMU_PLLSOC0)
1157 clock = (enable ? PLL_SOC0_ON : PLL_SOC0_OFF);
1158 else if (clock == PRCMU_PLLSOC1)
1159 clock = (enable ? PLL_SOC1_ON : PLL_SOC1_OFF);
1160 else
1161 return -EINVAL;
1163 mutex_lock(&mb1_transfer.lock);
1165 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1166 cpu_relax();
1168 writeb(MB1H_PLL_ON_OFF, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1169 writeb(clock, (tcdm_base + PRCM_REQ_MB1_PLL_ON_OFF));
1171 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1172 wait_for_completion(&mb1_transfer.work);
1174 if (mb1_transfer.ack.header != MB1H_PLL_ON_OFF)
1175 r = -EIO;
1177 mutex_unlock(&mb1_transfer.lock);
1179 return r;
1183 * db8500_prcmu_set_epod - set the state of a EPOD (power domain)
1184 * @epod_id: The EPOD to set
1185 * @epod_state: The new EPOD state
1187 * This function sets the state of a EPOD (power domain). It may not be called
1188 * from interrupt context.
1190 int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state)
1192 int r = 0;
1193 bool ram_retention = false;
1194 int i;
1196 /* check argument */
1197 BUG_ON(epod_id >= NUM_EPOD_ID);
1199 /* set flag if retention is possible */
1200 switch (epod_id) {
1201 case EPOD_ID_SVAMMDSP:
1202 case EPOD_ID_SIAMMDSP:
1203 case EPOD_ID_ESRAM12:
1204 case EPOD_ID_ESRAM34:
1205 ram_retention = true;
1206 break;
1209 /* check argument */
1210 BUG_ON(epod_state > EPOD_STATE_ON);
1211 BUG_ON(epod_state == EPOD_STATE_RAMRET && !ram_retention);
1213 /* get lock */
1214 mutex_lock(&mb2_transfer.lock);
1216 /* wait for mailbox */
1217 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(2))
1218 cpu_relax();
1220 /* fill in mailbox */
1221 for (i = 0; i < NUM_EPOD_ID; i++)
1222 writeb(EPOD_STATE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB2 + i));
1223 writeb(epod_state, (tcdm_base + PRCM_REQ_MB2 + epod_id));
1225 writeb(MB2H_DPS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB2));
1227 writel(MBOX_BIT(2), PRCM_MBOX_CPU_SET);
1230 * The current firmware version does not handle errors correctly,
1231 * and we cannot recover if there is an error.
1232 * This is expected to change when the firmware is updated.
1234 if (!wait_for_completion_timeout(&mb2_transfer.work,
1235 msecs_to_jiffies(20000))) {
1236 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
1237 __func__);
1238 r = -EIO;
1239 goto unlock_and_return;
1242 if (mb2_transfer.ack.status != HWACC_PWR_ST_OK)
1243 r = -EIO;
1245 unlock_and_return:
1246 mutex_unlock(&mb2_transfer.lock);
1247 return r;
1251 * prcmu_configure_auto_pm - Configure autonomous power management.
1252 * @sleep: Configuration for ApSleep.
1253 * @idle: Configuration for ApIdle.
1255 void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
1256 struct prcmu_auto_pm_config *idle)
1258 u32 sleep_cfg;
1259 u32 idle_cfg;
1260 unsigned long flags;
1262 BUG_ON((sleep == NULL) || (idle == NULL));
1264 sleep_cfg = (sleep->sva_auto_pm_enable & 0xF);
1265 sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_auto_pm_enable & 0xF));
1266 sleep_cfg = ((sleep_cfg << 8) | (sleep->sva_power_on & 0xFF));
1267 sleep_cfg = ((sleep_cfg << 8) | (sleep->sia_power_on & 0xFF));
1268 sleep_cfg = ((sleep_cfg << 4) | (sleep->sva_policy & 0xF));
1269 sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_policy & 0xF));
1271 idle_cfg = (idle->sva_auto_pm_enable & 0xF);
1272 idle_cfg = ((idle_cfg << 4) | (idle->sia_auto_pm_enable & 0xF));
1273 idle_cfg = ((idle_cfg << 8) | (idle->sva_power_on & 0xFF));
1274 idle_cfg = ((idle_cfg << 8) | (idle->sia_power_on & 0xFF));
1275 idle_cfg = ((idle_cfg << 4) | (idle->sva_policy & 0xF));
1276 idle_cfg = ((idle_cfg << 4) | (idle->sia_policy & 0xF));
1278 spin_lock_irqsave(&mb2_transfer.auto_pm_lock, flags);
1281 * The autonomous power management configuration is done through
1282 * fields in mailbox 2, but these fields are only used as shared
1283 * variables - i.e. there is no need to send a message.
1285 writel(sleep_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_SLEEP));
1286 writel(idle_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_IDLE));
1288 mb2_transfer.auto_pm_enabled =
1289 ((sleep->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1290 (sleep->sia_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1291 (idle->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1292 (idle->sia_auto_pm_enable == PRCMU_AUTO_PM_ON));
1294 spin_unlock_irqrestore(&mb2_transfer.auto_pm_lock, flags);
1296 EXPORT_SYMBOL(prcmu_configure_auto_pm);
1298 bool prcmu_is_auto_pm_enabled(void)
1300 return mb2_transfer.auto_pm_enabled;
1303 static int request_sysclk(bool enable)
1305 int r;
1306 unsigned long flags;
1308 r = 0;
1310 mutex_lock(&mb3_transfer.sysclk_lock);
1312 spin_lock_irqsave(&mb3_transfer.lock, flags);
1314 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(3))
1315 cpu_relax();
1317 writeb((enable ? ON : OFF), (tcdm_base + PRCM_REQ_MB3_SYSCLK_MGT));
1319 writeb(MB3H_SYSCLK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB3));
1320 writel(MBOX_BIT(3), PRCM_MBOX_CPU_SET);
1322 spin_unlock_irqrestore(&mb3_transfer.lock, flags);
1325 * The firmware only sends an ACK if we want to enable the
1326 * SysClk, and it succeeds.
1328 if (enable && !wait_for_completion_timeout(&mb3_transfer.sysclk_work,
1329 msecs_to_jiffies(20000))) {
1330 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
1331 __func__);
1332 r = -EIO;
1335 mutex_unlock(&mb3_transfer.sysclk_lock);
1337 return r;
1340 static int request_timclk(bool enable)
1342 u32 val = (PRCM_TCR_DOZE_MODE | PRCM_TCR_TENSEL_MASK);
1344 if (!enable)
1345 val |= PRCM_TCR_STOP_TIMERS;
1346 writel(val, PRCM_TCR);
1348 return 0;
1351 static int request_clock(u8 clock, bool enable)
1353 u32 val;
1354 unsigned long flags;
1356 spin_lock_irqsave(&clk_mgt_lock, flags);
1358 /* Grab the HW semaphore. */
1359 while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
1360 cpu_relax();
1362 val = readl(prcmu_base + clk_mgt[clock].offset);
1363 if (enable) {
1364 val |= (PRCM_CLK_MGT_CLKEN | clk_mgt[clock].pllsw);
1365 } else {
1366 clk_mgt[clock].pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK);
1367 val &= ~(PRCM_CLK_MGT_CLKEN | PRCM_CLK_MGT_CLKPLLSW_MASK);
1369 writel(val, prcmu_base + clk_mgt[clock].offset);
1371 /* Release the HW semaphore. */
1372 writel(0, PRCM_SEM);
1374 spin_unlock_irqrestore(&clk_mgt_lock, flags);
1376 return 0;
1379 static int request_sga_clock(u8 clock, bool enable)
1381 u32 val;
1382 int ret;
1384 if (enable) {
1385 val = readl(PRCM_CGATING_BYPASS);
1386 writel(val | PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS);
1389 ret = request_clock(clock, enable);
1391 if (!ret && !enable) {
1392 val = readl(PRCM_CGATING_BYPASS);
1393 writel(val & ~PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS);
1396 return ret;
1399 static inline bool plldsi_locked(void)
1401 return (readl(PRCM_PLLDSI_LOCKP) &
1402 (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 |
1403 PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3)) ==
1404 (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 |
1405 PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3);
1408 static int request_plldsi(bool enable)
1410 int r = 0;
1411 u32 val;
1413 writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP |
1414 PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI), (enable ?
1415 PRCM_MMIP_LS_CLAMP_CLR : PRCM_MMIP_LS_CLAMP_SET));
1417 val = readl(PRCM_PLLDSI_ENABLE);
1418 if (enable)
1419 val |= PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1420 else
1421 val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1422 writel(val, PRCM_PLLDSI_ENABLE);
1424 if (enable) {
1425 unsigned int i;
1426 bool locked = plldsi_locked();
1428 for (i = 10; !locked && (i > 0); --i) {
1429 udelay(100);
1430 locked = plldsi_locked();
1432 if (locked) {
1433 writel(PRCM_APE_RESETN_DSIPLL_RESETN,
1434 PRCM_APE_RESETN_SET);
1435 } else {
1436 writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP |
1437 PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI),
1438 PRCM_MMIP_LS_CLAMP_SET);
1439 val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1440 writel(val, PRCM_PLLDSI_ENABLE);
1441 r = -EAGAIN;
1443 } else {
1444 writel(PRCM_APE_RESETN_DSIPLL_RESETN, PRCM_APE_RESETN_CLR);
1446 return r;
1449 static int request_dsiclk(u8 n, bool enable)
1451 u32 val;
1453 val = readl(PRCM_DSI_PLLOUT_SEL);
1454 val &= ~dsiclk[n].divsel_mask;
1455 val |= ((enable ? dsiclk[n].divsel : PRCM_DSI_PLLOUT_SEL_OFF) <<
1456 dsiclk[n].divsel_shift);
1457 writel(val, PRCM_DSI_PLLOUT_SEL);
1458 return 0;
1461 static int request_dsiescclk(u8 n, bool enable)
1463 u32 val;
1465 val = readl(PRCM_DSITVCLK_DIV);
1466 enable ? (val |= dsiescclk[n].en) : (val &= ~dsiescclk[n].en);
1467 writel(val, PRCM_DSITVCLK_DIV);
1468 return 0;
1472 * db8500_prcmu_request_clock() - Request for a clock to be enabled or disabled.
1473 * @clock: The clock for which the request is made.
1474 * @enable: Whether the clock should be enabled (true) or disabled (false).
1476 * This function should only be used by the clock implementation.
1477 * Do not use it from any other place!
1479 int db8500_prcmu_request_clock(u8 clock, bool enable)
1481 if (clock == PRCMU_SGACLK)
1482 return request_sga_clock(clock, enable);
1483 else if (clock < PRCMU_NUM_REG_CLOCKS)
1484 return request_clock(clock, enable);
1485 else if (clock == PRCMU_TIMCLK)
1486 return request_timclk(enable);
1487 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1488 return request_dsiclk((clock - PRCMU_DSI0CLK), enable);
1489 else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1490 return request_dsiescclk((clock - PRCMU_DSI0ESCCLK), enable);
1491 else if (clock == PRCMU_PLLDSI)
1492 return request_plldsi(enable);
1493 else if (clock == PRCMU_SYSCLK)
1494 return request_sysclk(enable);
1495 else if ((clock == PRCMU_PLLSOC0) || (clock == PRCMU_PLLSOC1))
1496 return request_pll(clock, enable);
1497 else
1498 return -EINVAL;
1501 static unsigned long pll_rate(void __iomem *reg, unsigned long src_rate,
1502 int branch)
1504 u64 rate;
1505 u32 val;
1506 u32 d;
1507 u32 div = 1;
1509 val = readl(reg);
1511 rate = src_rate;
1512 rate *= ((val & PRCM_PLL_FREQ_D_MASK) >> PRCM_PLL_FREQ_D_SHIFT);
1514 d = ((val & PRCM_PLL_FREQ_N_MASK) >> PRCM_PLL_FREQ_N_SHIFT);
1515 if (d > 1)
1516 div *= d;
1518 d = ((val & PRCM_PLL_FREQ_R_MASK) >> PRCM_PLL_FREQ_R_SHIFT);
1519 if (d > 1)
1520 div *= d;
1522 if (val & PRCM_PLL_FREQ_SELDIV2)
1523 div *= 2;
1525 if ((branch == PLL_FIX) || ((branch == PLL_DIV) &&
1526 (val & PRCM_PLL_FREQ_DIV2EN) &&
1527 ((reg == PRCM_PLLSOC0_FREQ) ||
1528 (reg == PRCM_PLLARM_FREQ) ||
1529 (reg == PRCM_PLLDDR_FREQ))))
1530 div *= 2;
1532 (void)do_div(rate, div);
1534 return (unsigned long)rate;
1537 #define ROOT_CLOCK_RATE 38400000
1539 static unsigned long clock_rate(u8 clock)
1541 u32 val;
1542 u32 pllsw;
1543 unsigned long rate = ROOT_CLOCK_RATE;
1545 val = readl(prcmu_base + clk_mgt[clock].offset);
1547 if (val & PRCM_CLK_MGT_CLK38) {
1548 if (clk_mgt[clock].clk38div && (val & PRCM_CLK_MGT_CLK38DIV))
1549 rate /= 2;
1550 return rate;
1553 val |= clk_mgt[clock].pllsw;
1554 pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK);
1556 if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC0)
1557 rate = pll_rate(PRCM_PLLSOC0_FREQ, rate, clk_mgt[clock].branch);
1558 else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC1)
1559 rate = pll_rate(PRCM_PLLSOC1_FREQ, rate, clk_mgt[clock].branch);
1560 else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_DDR)
1561 rate = pll_rate(PRCM_PLLDDR_FREQ, rate, clk_mgt[clock].branch);
1562 else
1563 return 0;
1565 if ((clock == PRCMU_SGACLK) &&
1566 (val & PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN)) {
1567 u64 r = (rate * 10);
1569 (void)do_div(r, 25);
1570 return (unsigned long)r;
1572 val &= PRCM_CLK_MGT_CLKPLLDIV_MASK;
1573 if (val)
1574 return rate / val;
1575 else
1576 return 0;
1579 static unsigned long armss_rate(void)
1581 u32 r;
1582 unsigned long rate;
1584 r = readl(PRCM_ARM_CHGCLKREQ);
1586 if (r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ) {
1587 /* External ARMCLKFIX clock */
1589 rate = pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_FIX);
1591 /* Check PRCM_ARM_CHGCLKREQ divider */
1592 if (!(r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_DIVSEL))
1593 rate /= 2;
1595 /* Check PRCM_ARMCLKFIX_MGT divider */
1596 r = readl(PRCM_ARMCLKFIX_MGT);
1597 r &= PRCM_CLK_MGT_CLKPLLDIV_MASK;
1598 rate /= r;
1600 } else {/* ARM PLL */
1601 rate = pll_rate(PRCM_PLLARM_FREQ, ROOT_CLOCK_RATE, PLL_DIV);
1604 return rate;
1607 static unsigned long dsiclk_rate(u8 n)
1609 u32 divsel;
1610 u32 div = 1;
1612 divsel = readl(PRCM_DSI_PLLOUT_SEL);
1613 divsel = ((divsel & dsiclk[n].divsel_mask) >> dsiclk[n].divsel_shift);
1615 if (divsel == PRCM_DSI_PLLOUT_SEL_OFF)
1616 divsel = dsiclk[n].divsel;
1617 else
1618 dsiclk[n].divsel = divsel;
1620 switch (divsel) {
1621 case PRCM_DSI_PLLOUT_SEL_PHI_4:
1622 div *= 2;
1623 case PRCM_DSI_PLLOUT_SEL_PHI_2:
1624 div *= 2;
1625 case PRCM_DSI_PLLOUT_SEL_PHI:
1626 return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
1627 PLL_RAW) / div;
1628 default:
1629 return 0;
1633 static unsigned long dsiescclk_rate(u8 n)
1635 u32 div;
1637 div = readl(PRCM_DSITVCLK_DIV);
1638 div = ((div & dsiescclk[n].div_mask) >> (dsiescclk[n].div_shift));
1639 return clock_rate(PRCMU_TVCLK) / max((u32)1, div);
1642 unsigned long prcmu_clock_rate(u8 clock)
1644 if (clock < PRCMU_NUM_REG_CLOCKS)
1645 return clock_rate(clock);
1646 else if (clock == PRCMU_TIMCLK)
1647 return ROOT_CLOCK_RATE / 16;
1648 else if (clock == PRCMU_SYSCLK)
1649 return ROOT_CLOCK_RATE;
1650 else if (clock == PRCMU_PLLSOC0)
1651 return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
1652 else if (clock == PRCMU_PLLSOC1)
1653 return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
1654 else if (clock == PRCMU_ARMSS)
1655 return armss_rate();
1656 else if (clock == PRCMU_PLLDDR)
1657 return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
1658 else if (clock == PRCMU_PLLDSI)
1659 return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
1660 PLL_RAW);
1661 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1662 return dsiclk_rate(clock - PRCMU_DSI0CLK);
1663 else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1664 return dsiescclk_rate(clock - PRCMU_DSI0ESCCLK);
1665 else
1666 return 0;
1669 static unsigned long clock_source_rate(u32 clk_mgt_val, int branch)
1671 if (clk_mgt_val & PRCM_CLK_MGT_CLK38)
1672 return ROOT_CLOCK_RATE;
1673 clk_mgt_val &= PRCM_CLK_MGT_CLKPLLSW_MASK;
1674 if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC0)
1675 return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, branch);
1676 else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC1)
1677 return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, branch);
1678 else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_DDR)
1679 return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, branch);
1680 else
1681 return 0;
1684 static u32 clock_divider(unsigned long src_rate, unsigned long rate)
1686 u32 div;
1688 div = (src_rate / rate);
1689 if (div == 0)
1690 return 1;
1691 if (rate < (src_rate / div))
1692 div++;
1693 return div;
1696 static long round_clock_rate(u8 clock, unsigned long rate)
1698 u32 val;
1699 u32 div;
1700 unsigned long src_rate;
1701 long rounded_rate;
1703 val = readl(prcmu_base + clk_mgt[clock].offset);
1704 src_rate = clock_source_rate((val | clk_mgt[clock].pllsw),
1705 clk_mgt[clock].branch);
1706 div = clock_divider(src_rate, rate);
1707 if (val & PRCM_CLK_MGT_CLK38) {
1708 if (clk_mgt[clock].clk38div) {
1709 if (div > 2)
1710 div = 2;
1711 } else {
1712 div = 1;
1714 } else if ((clock == PRCMU_SGACLK) && (div == 3)) {
1715 u64 r = (src_rate * 10);
1717 (void)do_div(r, 25);
1718 if (r <= rate)
1719 return (unsigned long)r;
1721 rounded_rate = (src_rate / min(div, (u32)31));
1723 return rounded_rate;
1726 /* CPU FREQ table, may be changed due to if MAX_OPP is supported. */
1727 static struct cpufreq_frequency_table db8500_cpufreq_table[] = {
1728 { .frequency = 200000, .driver_data = ARM_EXTCLK,},
1729 { .frequency = 400000, .driver_data = ARM_50_OPP,},
1730 { .frequency = 800000, .driver_data = ARM_100_OPP,},
1731 { .frequency = CPUFREQ_TABLE_END,}, /* To be used for MAX_OPP. */
1732 { .frequency = CPUFREQ_TABLE_END,},
1735 static long round_armss_rate(unsigned long rate)
1737 long freq = 0;
1738 int i = 0;
1740 /* cpufreq table frequencies is in KHz. */
1741 rate = rate / 1000;
1743 /* Find the corresponding arm opp from the cpufreq table. */
1744 while (db8500_cpufreq_table[i].frequency != CPUFREQ_TABLE_END) {
1745 freq = db8500_cpufreq_table[i].frequency;
1746 if (freq == rate)
1747 break;
1748 i++;
1751 /* Return the last valid value, even if a match was not found. */
1752 return freq * 1000;
1755 #define MIN_PLL_VCO_RATE 600000000ULL
1756 #define MAX_PLL_VCO_RATE 1680640000ULL
1758 static long round_plldsi_rate(unsigned long rate)
1760 long rounded_rate = 0;
1761 unsigned long src_rate;
1762 unsigned long rem;
1763 u32 r;
1765 src_rate = clock_rate(PRCMU_HDMICLK);
1766 rem = rate;
1768 for (r = 7; (rem > 0) && (r > 0); r--) {
1769 u64 d;
1771 d = (r * rate);
1772 (void)do_div(d, src_rate);
1773 if (d < 6)
1774 d = 6;
1775 else if (d > 255)
1776 d = 255;
1777 d *= src_rate;
1778 if (((2 * d) < (r * MIN_PLL_VCO_RATE)) ||
1779 ((r * MAX_PLL_VCO_RATE) < (2 * d)))
1780 continue;
1781 (void)do_div(d, r);
1782 if (rate < d) {
1783 if (rounded_rate == 0)
1784 rounded_rate = (long)d;
1785 break;
1787 if ((rate - d) < rem) {
1788 rem = (rate - d);
1789 rounded_rate = (long)d;
1792 return rounded_rate;
1795 static long round_dsiclk_rate(unsigned long rate)
1797 u32 div;
1798 unsigned long src_rate;
1799 long rounded_rate;
1801 src_rate = pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
1802 PLL_RAW);
1803 div = clock_divider(src_rate, rate);
1804 rounded_rate = (src_rate / ((div > 2) ? 4 : div));
1806 return rounded_rate;
1809 static long round_dsiescclk_rate(unsigned long rate)
1811 u32 div;
1812 unsigned long src_rate;
1813 long rounded_rate;
1815 src_rate = clock_rate(PRCMU_TVCLK);
1816 div = clock_divider(src_rate, rate);
1817 rounded_rate = (src_rate / min(div, (u32)255));
1819 return rounded_rate;
1822 long prcmu_round_clock_rate(u8 clock, unsigned long rate)
1824 if (clock < PRCMU_NUM_REG_CLOCKS)
1825 return round_clock_rate(clock, rate);
1826 else if (clock == PRCMU_ARMSS)
1827 return round_armss_rate(rate);
1828 else if (clock == PRCMU_PLLDSI)
1829 return round_plldsi_rate(rate);
1830 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1831 return round_dsiclk_rate(rate);
1832 else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1833 return round_dsiescclk_rate(rate);
1834 else
1835 return (long)prcmu_clock_rate(clock);
1838 static void set_clock_rate(u8 clock, unsigned long rate)
1840 u32 val;
1841 u32 div;
1842 unsigned long src_rate;
1843 unsigned long flags;
1845 spin_lock_irqsave(&clk_mgt_lock, flags);
1847 /* Grab the HW semaphore. */
1848 while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
1849 cpu_relax();
1851 val = readl(prcmu_base + clk_mgt[clock].offset);
1852 src_rate = clock_source_rate((val | clk_mgt[clock].pllsw),
1853 clk_mgt[clock].branch);
1854 div = clock_divider(src_rate, rate);
1855 if (val & PRCM_CLK_MGT_CLK38) {
1856 if (clk_mgt[clock].clk38div) {
1857 if (div > 1)
1858 val |= PRCM_CLK_MGT_CLK38DIV;
1859 else
1860 val &= ~PRCM_CLK_MGT_CLK38DIV;
1862 } else if (clock == PRCMU_SGACLK) {
1863 val &= ~(PRCM_CLK_MGT_CLKPLLDIV_MASK |
1864 PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN);
1865 if (div == 3) {
1866 u64 r = (src_rate * 10);
1868 (void)do_div(r, 25);
1869 if (r <= rate) {
1870 val |= PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN;
1871 div = 0;
1874 val |= min(div, (u32)31);
1875 } else {
1876 val &= ~PRCM_CLK_MGT_CLKPLLDIV_MASK;
1877 val |= min(div, (u32)31);
1879 writel(val, prcmu_base + clk_mgt[clock].offset);
1881 /* Release the HW semaphore. */
1882 writel(0, PRCM_SEM);
1884 spin_unlock_irqrestore(&clk_mgt_lock, flags);
1887 static int set_armss_rate(unsigned long rate)
1889 int i = 0;
1891 /* cpufreq table frequencies is in KHz. */
1892 rate = rate / 1000;
1894 /* Find the corresponding arm opp from the cpufreq table. */
1895 while (db8500_cpufreq_table[i].frequency != CPUFREQ_TABLE_END) {
1896 if (db8500_cpufreq_table[i].frequency == rate)
1897 break;
1898 i++;
1901 if (db8500_cpufreq_table[i].frequency != rate)
1902 return -EINVAL;
1904 /* Set the new arm opp. */
1905 return db8500_prcmu_set_arm_opp(db8500_cpufreq_table[i].driver_data);
1908 static int set_plldsi_rate(unsigned long rate)
1910 unsigned long src_rate;
1911 unsigned long rem;
1912 u32 pll_freq = 0;
1913 u32 r;
1915 src_rate = clock_rate(PRCMU_HDMICLK);
1916 rem = rate;
1918 for (r = 7; (rem > 0) && (r > 0); r--) {
1919 u64 d;
1920 u64 hwrate;
1922 d = (r * rate);
1923 (void)do_div(d, src_rate);
1924 if (d < 6)
1925 d = 6;
1926 else if (d > 255)
1927 d = 255;
1928 hwrate = (d * src_rate);
1929 if (((2 * hwrate) < (r * MIN_PLL_VCO_RATE)) ||
1930 ((r * MAX_PLL_VCO_RATE) < (2 * hwrate)))
1931 continue;
1932 (void)do_div(hwrate, r);
1933 if (rate < hwrate) {
1934 if (pll_freq == 0)
1935 pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) |
1936 (r << PRCM_PLL_FREQ_R_SHIFT));
1937 break;
1939 if ((rate - hwrate) < rem) {
1940 rem = (rate - hwrate);
1941 pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) |
1942 (r << PRCM_PLL_FREQ_R_SHIFT));
1945 if (pll_freq == 0)
1946 return -EINVAL;
1948 pll_freq |= (1 << PRCM_PLL_FREQ_N_SHIFT);
1949 writel(pll_freq, PRCM_PLLDSI_FREQ);
1951 return 0;
1954 static void set_dsiclk_rate(u8 n, unsigned long rate)
1956 u32 val;
1957 u32 div;
1959 div = clock_divider(pll_rate(PRCM_PLLDSI_FREQ,
1960 clock_rate(PRCMU_HDMICLK), PLL_RAW), rate);
1962 dsiclk[n].divsel = (div == 1) ? PRCM_DSI_PLLOUT_SEL_PHI :
1963 (div == 2) ? PRCM_DSI_PLLOUT_SEL_PHI_2 :
1964 /* else */ PRCM_DSI_PLLOUT_SEL_PHI_4;
1966 val = readl(PRCM_DSI_PLLOUT_SEL);
1967 val &= ~dsiclk[n].divsel_mask;
1968 val |= (dsiclk[n].divsel << dsiclk[n].divsel_shift);
1969 writel(val, PRCM_DSI_PLLOUT_SEL);
1972 static void set_dsiescclk_rate(u8 n, unsigned long rate)
1974 u32 val;
1975 u32 div;
1977 div = clock_divider(clock_rate(PRCMU_TVCLK), rate);
1978 val = readl(PRCM_DSITVCLK_DIV);
1979 val &= ~dsiescclk[n].div_mask;
1980 val |= (min(div, (u32)255) << dsiescclk[n].div_shift);
1981 writel(val, PRCM_DSITVCLK_DIV);
1984 int prcmu_set_clock_rate(u8 clock, unsigned long rate)
1986 if (clock < PRCMU_NUM_REG_CLOCKS)
1987 set_clock_rate(clock, rate);
1988 else if (clock == PRCMU_ARMSS)
1989 return set_armss_rate(rate);
1990 else if (clock == PRCMU_PLLDSI)
1991 return set_plldsi_rate(rate);
1992 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1993 set_dsiclk_rate((clock - PRCMU_DSI0CLK), rate);
1994 else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1995 set_dsiescclk_rate((clock - PRCMU_DSI0ESCCLK), rate);
1996 return 0;
1999 int db8500_prcmu_config_esram0_deep_sleep(u8 state)
2001 if ((state > ESRAM0_DEEP_SLEEP_STATE_RET) ||
2002 (state < ESRAM0_DEEP_SLEEP_STATE_OFF))
2003 return -EINVAL;
2005 mutex_lock(&mb4_transfer.lock);
2007 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2008 cpu_relax();
2010 writeb(MB4H_MEM_ST, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2011 writeb(((DDR_PWR_STATE_OFFHIGHLAT << 4) | DDR_PWR_STATE_ON),
2012 (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE));
2013 writeb(DDR_PWR_STATE_ON,
2014 (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE));
2015 writeb(state, (tcdm_base + PRCM_REQ_MB4_ESRAM0_ST));
2017 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2018 wait_for_completion(&mb4_transfer.work);
2020 mutex_unlock(&mb4_transfer.lock);
2022 return 0;
2025 int db8500_prcmu_config_hotdog(u8 threshold)
2027 mutex_lock(&mb4_transfer.lock);
2029 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2030 cpu_relax();
2032 writeb(threshold, (tcdm_base + PRCM_REQ_MB4_HOTDOG_THRESHOLD));
2033 writeb(MB4H_HOTDOG, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2035 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2036 wait_for_completion(&mb4_transfer.work);
2038 mutex_unlock(&mb4_transfer.lock);
2040 return 0;
2043 int db8500_prcmu_config_hotmon(u8 low, u8 high)
2045 mutex_lock(&mb4_transfer.lock);
2047 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2048 cpu_relax();
2050 writeb(low, (tcdm_base + PRCM_REQ_MB4_HOTMON_LOW));
2051 writeb(high, (tcdm_base + PRCM_REQ_MB4_HOTMON_HIGH));
2052 writeb((HOTMON_CONFIG_LOW | HOTMON_CONFIG_HIGH),
2053 (tcdm_base + PRCM_REQ_MB4_HOTMON_CONFIG));
2054 writeb(MB4H_HOTMON, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2056 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2057 wait_for_completion(&mb4_transfer.work);
2059 mutex_unlock(&mb4_transfer.lock);
2061 return 0;
2064 static int config_hot_period(u16 val)
2066 mutex_lock(&mb4_transfer.lock);
2068 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2069 cpu_relax();
2071 writew(val, (tcdm_base + PRCM_REQ_MB4_HOT_PERIOD));
2072 writeb(MB4H_HOT_PERIOD, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2074 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2075 wait_for_completion(&mb4_transfer.work);
2077 mutex_unlock(&mb4_transfer.lock);
2079 return 0;
2082 int db8500_prcmu_start_temp_sense(u16 cycles32k)
2084 if (cycles32k == 0xFFFF)
2085 return -EINVAL;
2087 return config_hot_period(cycles32k);
2090 int db8500_prcmu_stop_temp_sense(void)
2092 return config_hot_period(0xFFFF);
2095 static int prcmu_a9wdog(u8 cmd, u8 d0, u8 d1, u8 d2, u8 d3)
2098 mutex_lock(&mb4_transfer.lock);
2100 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2101 cpu_relax();
2103 writeb(d0, (tcdm_base + PRCM_REQ_MB4_A9WDOG_0));
2104 writeb(d1, (tcdm_base + PRCM_REQ_MB4_A9WDOG_1));
2105 writeb(d2, (tcdm_base + PRCM_REQ_MB4_A9WDOG_2));
2106 writeb(d3, (tcdm_base + PRCM_REQ_MB4_A9WDOG_3));
2108 writeb(cmd, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2110 writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2111 wait_for_completion(&mb4_transfer.work);
2113 mutex_unlock(&mb4_transfer.lock);
2115 return 0;
2119 int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
2121 BUG_ON(num == 0 || num > 0xf);
2122 return prcmu_a9wdog(MB4H_A9WDOG_CONF, num, 0, 0,
2123 sleep_auto_off ? A9WDOG_AUTO_OFF_EN :
2124 A9WDOG_AUTO_OFF_DIS);
2126 EXPORT_SYMBOL(db8500_prcmu_config_a9wdog);
2128 int db8500_prcmu_enable_a9wdog(u8 id)
2130 return prcmu_a9wdog(MB4H_A9WDOG_EN, id, 0, 0, 0);
2132 EXPORT_SYMBOL(db8500_prcmu_enable_a9wdog);
2134 int db8500_prcmu_disable_a9wdog(u8 id)
2136 return prcmu_a9wdog(MB4H_A9WDOG_DIS, id, 0, 0, 0);
2138 EXPORT_SYMBOL(db8500_prcmu_disable_a9wdog);
2140 int db8500_prcmu_kick_a9wdog(u8 id)
2142 return prcmu_a9wdog(MB4H_A9WDOG_KICK, id, 0, 0, 0);
2144 EXPORT_SYMBOL(db8500_prcmu_kick_a9wdog);
2147 * timeout is 28 bit, in ms.
2149 int db8500_prcmu_load_a9wdog(u8 id, u32 timeout)
2151 return prcmu_a9wdog(MB4H_A9WDOG_LOAD,
2152 (id & A9WDOG_ID_MASK) |
2154 * Put the lowest 28 bits of timeout at
2155 * offset 4. Four first bits are used for id.
2157 (u8)((timeout << 4) & 0xf0),
2158 (u8)((timeout >> 4) & 0xff),
2159 (u8)((timeout >> 12) & 0xff),
2160 (u8)((timeout >> 20) & 0xff));
2162 EXPORT_SYMBOL(db8500_prcmu_load_a9wdog);
2165 * prcmu_abb_read() - Read register value(s) from the ABB.
2166 * @slave: The I2C slave address.
2167 * @reg: The (start) register address.
2168 * @value: The read out value(s).
2169 * @size: The number of registers to read.
2171 * Reads register value(s) from the ABB.
2172 * @size has to be 1 for the current firmware version.
2174 int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
2176 int r;
2178 if (size != 1)
2179 return -EINVAL;
2181 mutex_lock(&mb5_transfer.lock);
2183 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
2184 cpu_relax();
2186 writeb(0, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5));
2187 writeb(PRCMU_I2C_READ(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP));
2188 writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS));
2189 writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG));
2190 writeb(0, (tcdm_base + PRCM_REQ_MB5_I2C_VAL));
2192 writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
2194 if (!wait_for_completion_timeout(&mb5_transfer.work,
2195 msecs_to_jiffies(20000))) {
2196 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
2197 __func__);
2198 r = -EIO;
2199 } else {
2200 r = ((mb5_transfer.ack.status == I2C_RD_OK) ? 0 : -EIO);
2203 if (!r)
2204 *value = mb5_transfer.ack.value;
2206 mutex_unlock(&mb5_transfer.lock);
2208 return r;
2212 * prcmu_abb_write_masked() - Write masked register value(s) to the ABB.
2213 * @slave: The I2C slave address.
2214 * @reg: The (start) register address.
2215 * @value: The value(s) to write.
2216 * @mask: The mask(s) to use.
2217 * @size: The number of registers to write.
2219 * Writes masked register value(s) to the ABB.
2220 * For each @value, only the bits set to 1 in the corresponding @mask
2221 * will be written. The other bits are not changed.
2222 * @size has to be 1 for the current firmware version.
2224 int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size)
2226 int r;
2228 if (size != 1)
2229 return -EINVAL;
2231 mutex_lock(&mb5_transfer.lock);
2233 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
2234 cpu_relax();
2236 writeb(~*mask, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5));
2237 writeb(PRCMU_I2C_WRITE(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP));
2238 writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS));
2239 writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG));
2240 writeb(*value, (tcdm_base + PRCM_REQ_MB5_I2C_VAL));
2242 writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
2244 if (!wait_for_completion_timeout(&mb5_transfer.work,
2245 msecs_to_jiffies(20000))) {
2246 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
2247 __func__);
2248 r = -EIO;
2249 } else {
2250 r = ((mb5_transfer.ack.status == I2C_WR_OK) ? 0 : -EIO);
2253 mutex_unlock(&mb5_transfer.lock);
2255 return r;
2259 * prcmu_abb_write() - Write register value(s) to the ABB.
2260 * @slave: The I2C slave address.
2261 * @reg: The (start) register address.
2262 * @value: The value(s) to write.
2263 * @size: The number of registers to write.
2265 * Writes register value(s) to the ABB.
2266 * @size has to be 1 for the current firmware version.
2268 int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
2270 u8 mask = ~0;
2272 return prcmu_abb_write_masked(slave, reg, value, &mask, size);
2276 * prcmu_ac_wake_req - should be called whenever ARM wants to wakeup Modem
2278 int prcmu_ac_wake_req(void)
2280 u32 val;
2281 int ret = 0;
2283 mutex_lock(&mb0_transfer.ac_wake_lock);
2285 val = readl(PRCM_HOSTACCESS_REQ);
2286 if (val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ)
2287 goto unlock_and_return;
2289 atomic_set(&ac_wake_req_state, 1);
2292 * Force Modem Wake-up before hostaccess_req ping-pong.
2293 * It prevents Modem to enter in Sleep while acking the hostaccess
2294 * request. The 31us delay has been calculated by HWI.
2296 val |= PRCM_HOSTACCESS_REQ_WAKE_REQ;
2297 writel(val, PRCM_HOSTACCESS_REQ);
2299 udelay(31);
2301 val |= PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ;
2302 writel(val, PRCM_HOSTACCESS_REQ);
2304 if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work,
2305 msecs_to_jiffies(5000))) {
2306 #if defined(CONFIG_DBX500_PRCMU_DEBUG)
2307 db8500_prcmu_debug_dump(__func__, true, true);
2308 #endif
2309 pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n",
2310 __func__);
2311 ret = -EFAULT;
2314 unlock_and_return:
2315 mutex_unlock(&mb0_transfer.ac_wake_lock);
2316 return ret;
2320 * prcmu_ac_sleep_req - called when ARM no longer needs to talk to modem
2322 void prcmu_ac_sleep_req()
2324 u32 val;
2326 mutex_lock(&mb0_transfer.ac_wake_lock);
2328 val = readl(PRCM_HOSTACCESS_REQ);
2329 if (!(val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ))
2330 goto unlock_and_return;
2332 writel((val & ~PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ),
2333 PRCM_HOSTACCESS_REQ);
2335 if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work,
2336 msecs_to_jiffies(5000))) {
2337 pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n",
2338 __func__);
2341 atomic_set(&ac_wake_req_state, 0);
2343 unlock_and_return:
2344 mutex_unlock(&mb0_transfer.ac_wake_lock);
2347 bool db8500_prcmu_is_ac_wake_requested(void)
2349 return (atomic_read(&ac_wake_req_state) != 0);
2353 * db8500_prcmu_system_reset - System reset
2355 * Saves the reset reason code and then sets the APE_SOFTRST register which
2356 * fires interrupt to fw
2358 void db8500_prcmu_system_reset(u16 reset_code)
2360 writew(reset_code, (tcdm_base + PRCM_SW_RST_REASON));
2361 writel(1, PRCM_APE_SOFTRST);
2365 * db8500_prcmu_get_reset_code - Retrieve SW reset reason code
2367 * Retrieves the reset reason code stored by prcmu_system_reset() before
2368 * last restart.
2370 u16 db8500_prcmu_get_reset_code(void)
2372 return readw(tcdm_base + PRCM_SW_RST_REASON);
2376 * db8500_prcmu_reset_modem - ask the PRCMU to reset modem
2378 void db8500_prcmu_modem_reset(void)
2380 mutex_lock(&mb1_transfer.lock);
2382 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
2383 cpu_relax();
2385 writeb(MB1H_RESET_MODEM, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
2386 writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
2387 wait_for_completion(&mb1_transfer.work);
2390 * No need to check return from PRCMU as modem should go in reset state
2391 * This state is already managed by upper layer
2394 mutex_unlock(&mb1_transfer.lock);
2397 static void ack_dbb_wakeup(void)
2399 unsigned long flags;
2401 spin_lock_irqsave(&mb0_transfer.lock, flags);
2403 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
2404 cpu_relax();
2406 writeb(MB0H_READ_WAKEUP_ACK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
2407 writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
2409 spin_unlock_irqrestore(&mb0_transfer.lock, flags);
2412 static inline void print_unknown_header_warning(u8 n, u8 header)
2414 pr_warning("prcmu: Unknown message header (%d) in mailbox %d.\n",
2415 header, n);
2418 static bool read_mailbox_0(void)
2420 bool r;
2421 u32 ev;
2422 unsigned int n;
2423 u8 header;
2425 header = readb(tcdm_base + PRCM_MBOX_HEADER_ACK_MB0);
2426 switch (header) {
2427 case MB0H_WAKEUP_EXE:
2428 case MB0H_WAKEUP_SLEEP:
2429 if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1)
2430 ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_1_8500);
2431 else
2432 ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_0_8500);
2434 if (ev & (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK))
2435 complete(&mb0_transfer.ac_wake_work);
2436 if (ev & WAKEUP_BIT_SYSCLK_OK)
2437 complete(&mb3_transfer.sysclk_work);
2439 ev &= mb0_transfer.req.dbb_irqs;
2441 for (n = 0; n < NUM_PRCMU_WAKEUPS; n++) {
2442 if (ev & prcmu_irq_bit[n])
2443 generic_handle_irq(irq_find_mapping(db8500_irq_domain, n));
2445 r = true;
2446 break;
2447 default:
2448 print_unknown_header_warning(0, header);
2449 r = false;
2450 break;
2452 writel(MBOX_BIT(0), PRCM_ARM_IT1_CLR);
2453 return r;
2456 static bool read_mailbox_1(void)
2458 mb1_transfer.ack.header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB1);
2459 mb1_transfer.ack.arm_opp = readb(tcdm_base +
2460 PRCM_ACK_MB1_CURRENT_ARM_OPP);
2461 mb1_transfer.ack.ape_opp = readb(tcdm_base +
2462 PRCM_ACK_MB1_CURRENT_APE_OPP);
2463 mb1_transfer.ack.ape_voltage_status = readb(tcdm_base +
2464 PRCM_ACK_MB1_APE_VOLTAGE_STATUS);
2465 writel(MBOX_BIT(1), PRCM_ARM_IT1_CLR);
2466 complete(&mb1_transfer.work);
2467 return false;
2470 static bool read_mailbox_2(void)
2472 mb2_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB2_DPS_STATUS);
2473 writel(MBOX_BIT(2), PRCM_ARM_IT1_CLR);
2474 complete(&mb2_transfer.work);
2475 return false;
2478 static bool read_mailbox_3(void)
2480 writel(MBOX_BIT(3), PRCM_ARM_IT1_CLR);
2481 return false;
2484 static bool read_mailbox_4(void)
2486 u8 header;
2487 bool do_complete = true;
2489 header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB4);
2490 switch (header) {
2491 case MB4H_MEM_ST:
2492 case MB4H_HOTDOG:
2493 case MB4H_HOTMON:
2494 case MB4H_HOT_PERIOD:
2495 case MB4H_A9WDOG_CONF:
2496 case MB4H_A9WDOG_EN:
2497 case MB4H_A9WDOG_DIS:
2498 case MB4H_A9WDOG_LOAD:
2499 case MB4H_A9WDOG_KICK:
2500 break;
2501 default:
2502 print_unknown_header_warning(4, header);
2503 do_complete = false;
2504 break;
2507 writel(MBOX_BIT(4), PRCM_ARM_IT1_CLR);
2509 if (do_complete)
2510 complete(&mb4_transfer.work);
2512 return false;
2515 static bool read_mailbox_5(void)
2517 mb5_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB5_I2C_STATUS);
2518 mb5_transfer.ack.value = readb(tcdm_base + PRCM_ACK_MB5_I2C_VAL);
2519 writel(MBOX_BIT(5), PRCM_ARM_IT1_CLR);
2520 complete(&mb5_transfer.work);
2521 return false;
2524 static bool read_mailbox_6(void)
2526 writel(MBOX_BIT(6), PRCM_ARM_IT1_CLR);
2527 return false;
2530 static bool read_mailbox_7(void)
2532 writel(MBOX_BIT(7), PRCM_ARM_IT1_CLR);
2533 return false;
2536 static bool (* const read_mailbox[NUM_MB])(void) = {
2537 read_mailbox_0,
2538 read_mailbox_1,
2539 read_mailbox_2,
2540 read_mailbox_3,
2541 read_mailbox_4,
2542 read_mailbox_5,
2543 read_mailbox_6,
2544 read_mailbox_7
2547 static irqreturn_t prcmu_irq_handler(int irq, void *data)
2549 u32 bits;
2550 u8 n;
2551 irqreturn_t r;
2553 bits = (readl(PRCM_ARM_IT1_VAL) & ALL_MBOX_BITS);
2554 if (unlikely(!bits))
2555 return IRQ_NONE;
2557 r = IRQ_HANDLED;
2558 for (n = 0; bits; n++) {
2559 if (bits & MBOX_BIT(n)) {
2560 bits -= MBOX_BIT(n);
2561 if (read_mailbox[n]())
2562 r = IRQ_WAKE_THREAD;
2565 return r;
2568 static irqreturn_t prcmu_irq_thread_fn(int irq, void *data)
2570 ack_dbb_wakeup();
2571 return IRQ_HANDLED;
2574 static void prcmu_mask_work(struct work_struct *work)
2576 unsigned long flags;
2578 spin_lock_irqsave(&mb0_transfer.lock, flags);
2580 config_wakeups();
2582 spin_unlock_irqrestore(&mb0_transfer.lock, flags);
2585 static void prcmu_irq_mask(struct irq_data *d)
2587 unsigned long flags;
2589 spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags);
2591 mb0_transfer.req.dbb_irqs &= ~prcmu_irq_bit[d->hwirq];
2593 spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags);
2595 if (d->irq != IRQ_PRCMU_CA_SLEEP)
2596 schedule_work(&mb0_transfer.mask_work);
2599 static void prcmu_irq_unmask(struct irq_data *d)
2601 unsigned long flags;
2603 spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags);
2605 mb0_transfer.req.dbb_irqs |= prcmu_irq_bit[d->hwirq];
2607 spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags);
2609 if (d->irq != IRQ_PRCMU_CA_SLEEP)
2610 schedule_work(&mb0_transfer.mask_work);
2613 static void noop(struct irq_data *d)
2617 static struct irq_chip prcmu_irq_chip = {
2618 .name = "prcmu",
2619 .irq_disable = prcmu_irq_mask,
2620 .irq_ack = noop,
2621 .irq_mask = prcmu_irq_mask,
2622 .irq_unmask = prcmu_irq_unmask,
2625 static __init char *fw_project_name(u32 project)
2627 switch (project) {
2628 case PRCMU_FW_PROJECT_U8500:
2629 return "U8500";
2630 case PRCMU_FW_PROJECT_U8400:
2631 return "U8400";
2632 case PRCMU_FW_PROJECT_U9500:
2633 return "U9500";
2634 case PRCMU_FW_PROJECT_U8500_MBB:
2635 return "U8500 MBB";
2636 case PRCMU_FW_PROJECT_U8500_C1:
2637 return "U8500 C1";
2638 case PRCMU_FW_PROJECT_U8500_C2:
2639 return "U8500 C2";
2640 case PRCMU_FW_PROJECT_U8500_C3:
2641 return "U8500 C3";
2642 case PRCMU_FW_PROJECT_U8500_C4:
2643 return "U8500 C4";
2644 case PRCMU_FW_PROJECT_U9500_MBL:
2645 return "U9500 MBL";
2646 case PRCMU_FW_PROJECT_U8500_MBL:
2647 return "U8500 MBL";
2648 case PRCMU_FW_PROJECT_U8500_MBL2:
2649 return "U8500 MBL2";
2650 case PRCMU_FW_PROJECT_U8520:
2651 return "U8520 MBL";
2652 case PRCMU_FW_PROJECT_U8420:
2653 return "U8420";
2654 case PRCMU_FW_PROJECT_U9540:
2655 return "U9540";
2656 case PRCMU_FW_PROJECT_A9420:
2657 return "A9420";
2658 case PRCMU_FW_PROJECT_L8540:
2659 return "L8540";
2660 case PRCMU_FW_PROJECT_L8580:
2661 return "L8580";
2662 default:
2663 return "Unknown";
2667 static int db8500_irq_map(struct irq_domain *d, unsigned int virq,
2668 irq_hw_number_t hwirq)
2670 irq_set_chip_and_handler(virq, &prcmu_irq_chip,
2671 handle_simple_irq);
2672 set_irq_flags(virq, IRQF_VALID);
2674 return 0;
2677 static struct irq_domain_ops db8500_irq_ops = {
2678 .map = db8500_irq_map,
2679 .xlate = irq_domain_xlate_twocell,
2682 static int db8500_irq_init(struct device_node *np, int irq_base)
2684 int i;
2686 /* In the device tree case, just take some IRQs */
2687 if (np)
2688 irq_base = 0;
2690 db8500_irq_domain = irq_domain_add_simple(
2691 np, NUM_PRCMU_WAKEUPS, irq_base,
2692 &db8500_irq_ops, NULL);
2694 if (!db8500_irq_domain) {
2695 pr_err("Failed to create irqdomain\n");
2696 return -ENOSYS;
2699 /* All wakeups will be used, so create mappings for all */
2700 for (i = 0; i < NUM_PRCMU_WAKEUPS; i++)
2701 irq_create_mapping(db8500_irq_domain, i);
2703 return 0;
2706 static void dbx500_fw_version_init(struct platform_device *pdev,
2707 u32 version_offset)
2709 struct resource *res;
2710 void __iomem *tcpm_base;
2711 u32 version;
2713 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
2714 "prcmu-tcpm");
2715 if (!res) {
2716 dev_err(&pdev->dev,
2717 "Error: no prcmu tcpm memory region provided\n");
2718 return;
2720 tcpm_base = ioremap(res->start, resource_size(res));
2721 if (!tcpm_base) {
2722 dev_err(&pdev->dev, "no prcmu tcpm mem region provided\n");
2723 return;
2726 version = readl(tcpm_base + version_offset);
2727 fw_info.version.project = (version & 0xFF);
2728 fw_info.version.api_version = (version >> 8) & 0xFF;
2729 fw_info.version.func_version = (version >> 16) & 0xFF;
2730 fw_info.version.errata = (version >> 24) & 0xFF;
2731 strncpy(fw_info.version.project_name,
2732 fw_project_name(fw_info.version.project),
2733 PRCMU_FW_PROJECT_NAME_LEN);
2734 fw_info.valid = true;
2735 pr_info("PRCMU firmware: %s(%d), version %d.%d.%d\n",
2736 fw_info.version.project_name,
2737 fw_info.version.project,
2738 fw_info.version.api_version,
2739 fw_info.version.func_version,
2740 fw_info.version.errata);
2741 iounmap(tcpm_base);
2744 void __init db8500_prcmu_early_init(u32 phy_base, u32 size)
2747 * This is a temporary remap to bring up the clocks. It is
2748 * subsequently replaces with a real remap. After the merge of
2749 * the mailbox subsystem all of this early code goes away, and the
2750 * clock driver can probe independently. An early initcall will
2751 * still be needed, but it can be diverted into drivers/clk/ux500.
2753 prcmu_base = ioremap(phy_base, size);
2754 if (!prcmu_base)
2755 pr_err("%s: ioremap() of prcmu registers failed!\n", __func__);
2757 spin_lock_init(&mb0_transfer.lock);
2758 spin_lock_init(&mb0_transfer.dbb_irqs_lock);
2759 mutex_init(&mb0_transfer.ac_wake_lock);
2760 init_completion(&mb0_transfer.ac_wake_work);
2761 mutex_init(&mb1_transfer.lock);
2762 init_completion(&mb1_transfer.work);
2763 mb1_transfer.ape_opp = APE_NO_CHANGE;
2764 mutex_init(&mb2_transfer.lock);
2765 init_completion(&mb2_transfer.work);
2766 spin_lock_init(&mb2_transfer.auto_pm_lock);
2767 spin_lock_init(&mb3_transfer.lock);
2768 mutex_init(&mb3_transfer.sysclk_lock);
2769 init_completion(&mb3_transfer.sysclk_work);
2770 mutex_init(&mb4_transfer.lock);
2771 init_completion(&mb4_transfer.work);
2772 mutex_init(&mb5_transfer.lock);
2773 init_completion(&mb5_transfer.work);
2775 INIT_WORK(&mb0_transfer.mask_work, prcmu_mask_work);
2778 static void __init init_prcm_registers(void)
2780 u32 val;
2782 val = readl(PRCM_A9PL_FORCE_CLKEN);
2783 val &= ~(PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN |
2784 PRCM_A9PL_FORCE_CLKEN_PRCM_A9AXI_FORCE_CLKEN);
2785 writel(val, (PRCM_A9PL_FORCE_CLKEN));
2789 * Power domain switches (ePODs) modeled as regulators for the DB8500 SoC
2791 static struct regulator_consumer_supply db8500_vape_consumers[] = {
2792 REGULATOR_SUPPLY("v-ape", NULL),
2793 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.0"),
2794 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.1"),
2795 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.2"),
2796 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.3"),
2797 REGULATOR_SUPPLY("v-i2c", "nmk-i2c.4"),
2798 /* "v-mmc" changed to "vcore" in the mainline kernel */
2799 REGULATOR_SUPPLY("vcore", "sdi0"),
2800 REGULATOR_SUPPLY("vcore", "sdi1"),
2801 REGULATOR_SUPPLY("vcore", "sdi2"),
2802 REGULATOR_SUPPLY("vcore", "sdi3"),
2803 REGULATOR_SUPPLY("vcore", "sdi4"),
2804 REGULATOR_SUPPLY("v-dma", "dma40.0"),
2805 REGULATOR_SUPPLY("v-ape", "ab8500-usb.0"),
2806 /* "v-uart" changed to "vcore" in the mainline kernel */
2807 REGULATOR_SUPPLY("vcore", "uart0"),
2808 REGULATOR_SUPPLY("vcore", "uart1"),
2809 REGULATOR_SUPPLY("vcore", "uart2"),
2810 REGULATOR_SUPPLY("v-ape", "nmk-ske-keypad.0"),
2811 REGULATOR_SUPPLY("v-hsi", "ste_hsi.0"),
2812 REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
2815 static struct regulator_consumer_supply db8500_vsmps2_consumers[] = {
2816 REGULATOR_SUPPLY("musb_1v8", "ab8500-usb.0"),
2817 /* AV8100 regulator */
2818 REGULATOR_SUPPLY("hdmi_1v8", "0-0070"),
2821 static struct regulator_consumer_supply db8500_b2r2_mcde_consumers[] = {
2822 REGULATOR_SUPPLY("vsupply", "b2r2_bus"),
2823 REGULATOR_SUPPLY("vsupply", "mcde"),
2826 /* SVA MMDSP regulator switch */
2827 static struct regulator_consumer_supply db8500_svammdsp_consumers[] = {
2828 REGULATOR_SUPPLY("sva-mmdsp", "cm_control"),
2831 /* SVA pipe regulator switch */
2832 static struct regulator_consumer_supply db8500_svapipe_consumers[] = {
2833 REGULATOR_SUPPLY("sva-pipe", "cm_control"),
2836 /* SIA MMDSP regulator switch */
2837 static struct regulator_consumer_supply db8500_siammdsp_consumers[] = {
2838 REGULATOR_SUPPLY("sia-mmdsp", "cm_control"),
2841 /* SIA pipe regulator switch */
2842 static struct regulator_consumer_supply db8500_siapipe_consumers[] = {
2843 REGULATOR_SUPPLY("sia-pipe", "cm_control"),
2846 static struct regulator_consumer_supply db8500_sga_consumers[] = {
2847 REGULATOR_SUPPLY("v-mali", NULL),
2850 /* ESRAM1 and 2 regulator switch */
2851 static struct regulator_consumer_supply db8500_esram12_consumers[] = {
2852 REGULATOR_SUPPLY("esram12", "cm_control"),
2855 /* ESRAM3 and 4 regulator switch */
2856 static struct regulator_consumer_supply db8500_esram34_consumers[] = {
2857 REGULATOR_SUPPLY("v-esram34", "mcde"),
2858 REGULATOR_SUPPLY("esram34", "cm_control"),
2859 REGULATOR_SUPPLY("lcla_esram", "dma40.0"),
2862 static struct regulator_init_data db8500_regulators[DB8500_NUM_REGULATORS] = {
2863 [DB8500_REGULATOR_VAPE] = {
2864 .constraints = {
2865 .name = "db8500-vape",
2866 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2867 .always_on = true,
2869 .consumer_supplies = db8500_vape_consumers,
2870 .num_consumer_supplies = ARRAY_SIZE(db8500_vape_consumers),
2872 [DB8500_REGULATOR_VARM] = {
2873 .constraints = {
2874 .name = "db8500-varm",
2875 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2878 [DB8500_REGULATOR_VMODEM] = {
2879 .constraints = {
2880 .name = "db8500-vmodem",
2881 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2884 [DB8500_REGULATOR_VPLL] = {
2885 .constraints = {
2886 .name = "db8500-vpll",
2887 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2890 [DB8500_REGULATOR_VSMPS1] = {
2891 .constraints = {
2892 .name = "db8500-vsmps1",
2893 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2896 [DB8500_REGULATOR_VSMPS2] = {
2897 .constraints = {
2898 .name = "db8500-vsmps2",
2899 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2901 .consumer_supplies = db8500_vsmps2_consumers,
2902 .num_consumer_supplies = ARRAY_SIZE(db8500_vsmps2_consumers),
2904 [DB8500_REGULATOR_VSMPS3] = {
2905 .constraints = {
2906 .name = "db8500-vsmps3",
2907 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2910 [DB8500_REGULATOR_VRF1] = {
2911 .constraints = {
2912 .name = "db8500-vrf1",
2913 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2916 [DB8500_REGULATOR_SWITCH_SVAMMDSP] = {
2917 /* dependency to u8500-vape is handled outside regulator framework */
2918 .constraints = {
2919 .name = "db8500-sva-mmdsp",
2920 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2922 .consumer_supplies = db8500_svammdsp_consumers,
2923 .num_consumer_supplies = ARRAY_SIZE(db8500_svammdsp_consumers),
2925 [DB8500_REGULATOR_SWITCH_SVAMMDSPRET] = {
2926 .constraints = {
2927 /* "ret" means "retention" */
2928 .name = "db8500-sva-mmdsp-ret",
2929 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2932 [DB8500_REGULATOR_SWITCH_SVAPIPE] = {
2933 /* dependency to u8500-vape is handled outside regulator framework */
2934 .constraints = {
2935 .name = "db8500-sva-pipe",
2936 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2938 .consumer_supplies = db8500_svapipe_consumers,
2939 .num_consumer_supplies = ARRAY_SIZE(db8500_svapipe_consumers),
2941 [DB8500_REGULATOR_SWITCH_SIAMMDSP] = {
2942 /* dependency to u8500-vape is handled outside regulator framework */
2943 .constraints = {
2944 .name = "db8500-sia-mmdsp",
2945 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2947 .consumer_supplies = db8500_siammdsp_consumers,
2948 .num_consumer_supplies = ARRAY_SIZE(db8500_siammdsp_consumers),
2950 [DB8500_REGULATOR_SWITCH_SIAMMDSPRET] = {
2951 .constraints = {
2952 .name = "db8500-sia-mmdsp-ret",
2953 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2956 [DB8500_REGULATOR_SWITCH_SIAPIPE] = {
2957 /* dependency to u8500-vape is handled outside regulator framework */
2958 .constraints = {
2959 .name = "db8500-sia-pipe",
2960 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2962 .consumer_supplies = db8500_siapipe_consumers,
2963 .num_consumer_supplies = ARRAY_SIZE(db8500_siapipe_consumers),
2965 [DB8500_REGULATOR_SWITCH_SGA] = {
2966 .supply_regulator = "db8500-vape",
2967 .constraints = {
2968 .name = "db8500-sga",
2969 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2971 .consumer_supplies = db8500_sga_consumers,
2972 .num_consumer_supplies = ARRAY_SIZE(db8500_sga_consumers),
2975 [DB8500_REGULATOR_SWITCH_B2R2_MCDE] = {
2976 .supply_regulator = "db8500-vape",
2977 .constraints = {
2978 .name = "db8500-b2r2-mcde",
2979 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2981 .consumer_supplies = db8500_b2r2_mcde_consumers,
2982 .num_consumer_supplies = ARRAY_SIZE(db8500_b2r2_mcde_consumers),
2984 [DB8500_REGULATOR_SWITCH_ESRAM12] = {
2986 * esram12 is set in retention and supplied by Vsafe when Vape is off,
2987 * no need to hold Vape
2989 .constraints = {
2990 .name = "db8500-esram12",
2991 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2993 .consumer_supplies = db8500_esram12_consumers,
2994 .num_consumer_supplies = ARRAY_SIZE(db8500_esram12_consumers),
2996 [DB8500_REGULATOR_SWITCH_ESRAM12RET] = {
2997 .constraints = {
2998 .name = "db8500-esram12-ret",
2999 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
3002 [DB8500_REGULATOR_SWITCH_ESRAM34] = {
3004 * esram34 is set in retention and supplied by Vsafe when Vape is off,
3005 * no need to hold Vape
3007 .constraints = {
3008 .name = "db8500-esram34",
3009 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
3011 .consumer_supplies = db8500_esram34_consumers,
3012 .num_consumer_supplies = ARRAY_SIZE(db8500_esram34_consumers),
3014 [DB8500_REGULATOR_SWITCH_ESRAM34RET] = {
3015 .constraints = {
3016 .name = "db8500-esram34-ret",
3017 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
3022 static struct ux500_wdt_data db8500_wdt_pdata = {
3023 .timeout = 600, /* 10 minutes */
3024 .has_28_bits_resolution = true,
3027 * Thermal Sensor
3030 static struct resource db8500_thsens_resources[] = {
3032 .name = "IRQ_HOTMON_LOW",
3033 .start = IRQ_PRCMU_HOTMON_LOW,
3034 .end = IRQ_PRCMU_HOTMON_LOW,
3035 .flags = IORESOURCE_IRQ,
3038 .name = "IRQ_HOTMON_HIGH",
3039 .start = IRQ_PRCMU_HOTMON_HIGH,
3040 .end = IRQ_PRCMU_HOTMON_HIGH,
3041 .flags = IORESOURCE_IRQ,
3045 static struct db8500_thsens_platform_data db8500_thsens_data = {
3046 .trip_points[0] = {
3047 .temp = 70000,
3048 .type = THERMAL_TRIP_ACTIVE,
3049 .cdev_name = {
3050 [0] = "thermal-cpufreq-0",
3053 .trip_points[1] = {
3054 .temp = 75000,
3055 .type = THERMAL_TRIP_ACTIVE,
3056 .cdev_name = {
3057 [0] = "thermal-cpufreq-0",
3060 .trip_points[2] = {
3061 .temp = 80000,
3062 .type = THERMAL_TRIP_ACTIVE,
3063 .cdev_name = {
3064 [0] = "thermal-cpufreq-0",
3067 .trip_points[3] = {
3068 .temp = 85000,
3069 .type = THERMAL_TRIP_CRITICAL,
3071 .num_trips = 4,
3074 static struct mfd_cell common_prcmu_devs[] = {
3076 .name = "ux500_wdt",
3077 .platform_data = &db8500_wdt_pdata,
3078 .pdata_size = sizeof(db8500_wdt_pdata),
3079 .id = -1,
3083 static struct mfd_cell db8500_prcmu_devs[] = {
3085 .name = "db8500-prcmu-regulators",
3086 .of_compatible = "stericsson,db8500-prcmu-regulator",
3087 .platform_data = &db8500_regulators,
3088 .pdata_size = sizeof(db8500_regulators),
3091 .name = "cpufreq-ux500",
3092 .of_compatible = "stericsson,cpufreq-ux500",
3093 .platform_data = &db8500_cpufreq_table,
3094 .pdata_size = sizeof(db8500_cpufreq_table),
3097 .name = "db8500-thermal",
3098 .num_resources = ARRAY_SIZE(db8500_thsens_resources),
3099 .resources = db8500_thsens_resources,
3100 .platform_data = &db8500_thsens_data,
3101 .pdata_size = sizeof(db8500_thsens_data),
3105 static void db8500_prcmu_update_cpufreq(void)
3107 if (prcmu_has_arm_maxopp()) {
3108 db8500_cpufreq_table[3].frequency = 1000000;
3109 db8500_cpufreq_table[3].driver_data = ARM_MAX_OPP;
3113 static int db8500_prcmu_register_ab8500(struct device *parent,
3114 struct ab8500_platform_data *pdata,
3115 int irq)
3117 struct resource ab8500_resource = DEFINE_RES_IRQ(irq);
3118 struct mfd_cell ab8500_cell = {
3119 .name = "ab8500-core",
3120 .of_compatible = "stericsson,ab8500",
3121 .id = AB8500_VERSION_AB8500,
3122 .platform_data = pdata,
3123 .pdata_size = sizeof(struct ab8500_platform_data),
3124 .resources = &ab8500_resource,
3125 .num_resources = 1,
3128 return mfd_add_devices(parent, 0, &ab8500_cell, 1, NULL, 0, NULL);
3132 * prcmu_fw_init - arch init call for the Linux PRCMU fw init logic
3135 static int db8500_prcmu_probe(struct platform_device *pdev)
3137 struct device_node *np = pdev->dev.of_node;
3138 struct prcmu_pdata *pdata = dev_get_platdata(&pdev->dev);
3139 int irq = 0, err = 0;
3140 struct resource *res;
3142 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "prcmu");
3143 if (!res) {
3144 dev_err(&pdev->dev, "no prcmu memory region provided\n");
3145 return -ENOENT;
3147 prcmu_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
3148 if (!prcmu_base) {
3149 dev_err(&pdev->dev,
3150 "failed to ioremap prcmu register memory\n");
3151 return -ENOENT;
3153 init_prcm_registers();
3154 dbx500_fw_version_init(pdev, pdata->version_offset);
3155 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "prcmu-tcdm");
3156 if (!res) {
3157 dev_err(&pdev->dev, "no prcmu tcdm region provided\n");
3158 return -ENOENT;
3160 tcdm_base = devm_ioremap(&pdev->dev, res->start,
3161 resource_size(res));
3163 /* Clean up the mailbox interrupts after pre-kernel code. */
3164 writel(ALL_MBOX_BITS, PRCM_ARM_IT1_CLR);
3166 irq = platform_get_irq(pdev, 0);
3167 if (irq <= 0) {
3168 dev_err(&pdev->dev, "no prcmu irq provided\n");
3169 return -ENOENT;
3172 err = request_threaded_irq(irq, prcmu_irq_handler,
3173 prcmu_irq_thread_fn, IRQF_NO_SUSPEND, "prcmu", NULL);
3174 if (err < 0) {
3175 pr_err("prcmu: Failed to allocate IRQ_DB8500_PRCMU1.\n");
3176 err = -EBUSY;
3177 goto no_irq_return;
3180 db8500_irq_init(np, pdata->irq_base);
3182 prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET);
3184 db8500_prcmu_update_cpufreq();
3186 err = mfd_add_devices(&pdev->dev, 0, common_prcmu_devs,
3187 ARRAY_SIZE(common_prcmu_devs), NULL, 0, db8500_irq_domain);
3188 if (err) {
3189 pr_err("prcmu: Failed to add subdevices\n");
3190 return err;
3193 /* TODO: Remove restriction when clk definitions are available. */
3194 if (!of_machine_is_compatible("st-ericsson,u8540")) {
3195 err = mfd_add_devices(&pdev->dev, 0, db8500_prcmu_devs,
3196 ARRAY_SIZE(db8500_prcmu_devs), NULL, 0,
3197 db8500_irq_domain);
3198 if (err) {
3199 mfd_remove_devices(&pdev->dev);
3200 pr_err("prcmu: Failed to add subdevices\n");
3201 goto no_irq_return;
3205 err = db8500_prcmu_register_ab8500(&pdev->dev, pdata->ab_platdata,
3206 pdata->ab_irq);
3207 if (err) {
3208 mfd_remove_devices(&pdev->dev);
3209 pr_err("prcmu: Failed to add ab8500 subdevice\n");
3210 goto no_irq_return;
3213 pr_info("DB8500 PRCMU initialized\n");
3215 no_irq_return:
3216 return err;
3218 static const struct of_device_id db8500_prcmu_match[] = {
3219 { .compatible = "stericsson,db8500-prcmu"},
3220 { },
3223 static struct platform_driver db8500_prcmu_driver = {
3224 .driver = {
3225 .name = "db8500-prcmu",
3226 .owner = THIS_MODULE,
3227 .of_match_table = db8500_prcmu_match,
3229 .probe = db8500_prcmu_probe,
3232 static int __init db8500_prcmu_init(void)
3234 return platform_driver_register(&db8500_prcmu_driver);
3237 core_initcall(db8500_prcmu_init);
3239 MODULE_AUTHOR("Mattias Nilsson <mattias.i.nilsson@stericsson.com>");
3240 MODULE_DESCRIPTION("DB8500 PRCM Unit driver");
3241 MODULE_LICENSE("GPL v2");