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Linux 3.11-rc3
[cris-mirror.git] / drivers / mmc / host / omap_hsmmc.c
blob1865321465c40471751f16c6a50ba417cd07171c
1 /*
2 * drivers/mmc/host/omap_hsmmc.c
3 *
4 * Driver for OMAP2430/3430 MMC controller.
5 *
6 * Copyright (C) 2007 Texas Instruments.
7 *
8 * Authors:
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
12 *
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
16 */
17
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/kernel.h>
21 #include <linux/debugfs.h>
22 #include <linux/dmaengine.h>
23 #include <linux/seq_file.h>
24 #include <linux/interrupt.h>
25 #include <linux/delay.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/platform_device.h>
28 #include <linux/timer.h>
29 #include <linux/clk.h>
30 #include <linux/of.h>
31 #include <linux/of_gpio.h>
32 #include <linux/of_device.h>
33 #include <linux/omap-dma.h>
34 #include <linux/mmc/host.h>
35 #include <linux/mmc/core.h>
36 #include <linux/mmc/mmc.h>
37 #include <linux/io.h>
38 #include <linux/gpio.h>
39 #include <linux/regulator/consumer.h>
40 #include <linux/pinctrl/consumer.h>
41 #include <linux/pm_runtime.h>
42 #include <linux/platform_data/mmc-omap.h>
43
44 /* OMAP HSMMC Host Controller Registers */
45 #define OMAP_HSMMC_SYSSTATUS 0x0014
46 #define OMAP_HSMMC_CON 0x002C
47 #define OMAP_HSMMC_BLK 0x0104
48 #define OMAP_HSMMC_ARG 0x0108
49 #define OMAP_HSMMC_CMD 0x010C
50 #define OMAP_HSMMC_RSP10 0x0110
51 #define OMAP_HSMMC_RSP32 0x0114
52 #define OMAP_HSMMC_RSP54 0x0118
53 #define OMAP_HSMMC_RSP76 0x011C
54 #define OMAP_HSMMC_DATA 0x0120
55 #define OMAP_HSMMC_HCTL 0x0128
56 #define OMAP_HSMMC_SYSCTL 0x012C
57 #define OMAP_HSMMC_STAT 0x0130
58 #define OMAP_HSMMC_IE 0x0134
59 #define OMAP_HSMMC_ISE 0x0138
60 #define OMAP_HSMMC_CAPA 0x0140
61
62 #define VS18 (1 << 26)
63 #define VS30 (1 << 25)
64 #define HSS (1 << 21)
65 #define SDVS18 (0x5 << 9)
66 #define SDVS30 (0x6 << 9)
67 #define SDVS33 (0x7 << 9)
68 #define SDVS_MASK 0x00000E00
69 #define SDVSCLR 0xFFFFF1FF
70 #define SDVSDET 0x00000400
71 #define AUTOIDLE 0x1
72 #define SDBP (1 << 8)
73 #define DTO 0xe
74 #define ICE 0x1
75 #define ICS 0x2
76 #define CEN (1 << 2)
77 #define CLKD_MASK 0x0000FFC0
78 #define CLKD_SHIFT 6
79 #define DTO_MASK 0x000F0000
80 #define DTO_SHIFT 16
81 #define INIT_STREAM (1 << 1)
82 #define DP_SELECT (1 << 21)
83 #define DDIR (1 << 4)
84 #define DMAE 0x1
85 #define MSBS (1 << 5)
86 #define BCE (1 << 1)
87 #define FOUR_BIT (1 << 1)
88 #define HSPE (1 << 2)
89 #define DDR (1 << 19)
90 #define DW8 (1 << 5)
91 #define OD 0x1
92 #define STAT_CLEAR 0xFFFFFFFF
93 #define INIT_STREAM_CMD 0x00000000
94 #define DUAL_VOLT_OCR_BIT 7
95 #define SRC (1 << 25)
96 #define SRD (1 << 26)
97 #define SOFTRESET (1 << 1)
98 #define RESETDONE (1 << 0)
99
100 /* Interrupt masks for IE and ISE register */
101 #define CC_EN (1 << 0)
102 #define TC_EN (1 << 1)
103 #define BWR_EN (1 << 4)
104 #define BRR_EN (1 << 5)
105 #define ERR_EN (1 << 15)
106 #define CTO_EN (1 << 16)
107 #define CCRC_EN (1 << 17)
108 #define CEB_EN (1 << 18)
109 #define CIE_EN (1 << 19)
110 #define DTO_EN (1 << 20)
111 #define DCRC_EN (1 << 21)
112 #define DEB_EN (1 << 22)
113 #define CERR_EN (1 << 28)
114 #define BADA_EN (1 << 29)
115
116 #define INT_EN_MASK (BADA_EN | CERR_EN | DEB_EN | DCRC_EN |\
117 DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \
118 BRR_EN | BWR_EN | TC_EN | CC_EN)
119
120 #define MMC_AUTOSUSPEND_DELAY 100
121 #define MMC_TIMEOUT_MS 20
122 #define OMAP_MMC_MIN_CLOCK 400000
123 #define OMAP_MMC_MAX_CLOCK 52000000
124 #define DRIVER_NAME "omap_hsmmc"
125
126 /*
127 * One controller can have multiple slots, like on some omap boards using
128 * omap.c controller driver. Luckily this is not currently done on any known
129 * omap_hsmmc.c device.
130 */
131 #define mmc_slot(host) (host->pdata->slots[host->slot_id])
132
133 /*
134 * MMC Host controller read/write API's
135 */
136 #define OMAP_HSMMC_READ(base, reg) \
137 __raw_readl((base) + OMAP_HSMMC_##reg)
138
139 #define OMAP_HSMMC_WRITE(base, reg, val) \
140 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
141
142 struct omap_hsmmc_next {
143 unsigned int dma_len;
144 s32 cookie;
145 };
146
147 struct omap_hsmmc_host {
148 struct device *dev;
149 struct mmc_host *mmc;
150 struct mmc_request *mrq;
151 struct mmc_command *cmd;
152 struct mmc_data *data;
153 struct clk *fclk;
154 struct clk *dbclk;
155 /*
156 * vcc == configured supply
157 * vcc_aux == optional
158 * - MMC1, supply for DAT4..DAT7
159 * - MMC2/MMC2, external level shifter voltage supply, for
160 * chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
161 */
162 struct regulator *vcc;
163 struct regulator *vcc_aux;
164 int pbias_disable;
165 void __iomem *base;
166 resource_size_t mapbase;
167 spinlock_t irq_lock; /* Prevent races with irq handler */
168 unsigned int dma_len;
169 unsigned int dma_sg_idx;
170 unsigned char bus_mode;
171 unsigned char power_mode;
172 int suspended;
173 int irq;
174 int use_dma, dma_ch;
175 struct dma_chan *tx_chan;
176 struct dma_chan *rx_chan;
177 int slot_id;
178 int response_busy;
179 int context_loss;
180 int protect_card;
181 int reqs_blocked;
182 int use_reg;
183 int req_in_progress;
184 struct omap_hsmmc_next next_data;
185
186 struct omap_mmc_platform_data *pdata;
187 };
188
189 static int omap_hsmmc_card_detect(struct device *dev, int slot)
190 {
191 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
192 struct omap_mmc_platform_data *mmc = host->pdata;
193
194 /* NOTE: assumes card detect signal is active-low */
195 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
196 }
197
198 static int omap_hsmmc_get_wp(struct device *dev, int slot)
199 {
200 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
201 struct omap_mmc_platform_data *mmc = host->pdata;
202
203 /* NOTE: assumes write protect signal is active-high */
204 return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
205 }
206
207 static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
208 {
209 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
210 struct omap_mmc_platform_data *mmc = host->pdata;
211
212 /* NOTE: assumes card detect signal is active-low */
213 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
214 }
215
216 #ifdef CONFIG_PM
217
218 static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
219 {
220 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
221 struct omap_mmc_platform_data *mmc = host->pdata;
222
223 disable_irq(mmc->slots[0].card_detect_irq);
224 return 0;
225 }
226
227 static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
228 {
229 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
230 struct omap_mmc_platform_data *mmc = host->pdata;
231
232 enable_irq(mmc->slots[0].card_detect_irq);
233 return 0;
234 }
235
236 #else
237
238 #define omap_hsmmc_suspend_cdirq NULL
239 #define omap_hsmmc_resume_cdirq NULL
240
241 #endif
242
243 #ifdef CONFIG_REGULATOR
244
245 static int omap_hsmmc_set_power(struct device *dev, int slot, int power_on,
246 int vdd)
247 {
248 struct omap_hsmmc_host *host =
249 platform_get_drvdata(to_platform_device(dev));
250 int ret = 0;
251
252 /*
253 * If we don't see a Vcc regulator, assume it's a fixed
254 * voltage always-on regulator.
255 */
256 if (!host->vcc)
257 return 0;
258 /*
259 * With DT, never turn OFF the regulator for MMC1. This is because
260 * the pbias cell programming support is still missing when
261 * booting with Device tree
262 */
263 if (host->pbias_disable && !vdd)
264 return 0;
265
266 if (mmc_slot(host).before_set_reg)
267 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
268
269 /*
270 * Assume Vcc regulator is used only to power the card ... OMAP
271 * VDDS is used to power the pins, optionally with a transceiver to
272 * support cards using voltages other than VDDS (1.8V nominal). When a
273 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
274 *
275 * In some cases this regulator won't support enable/disable;
276 * e.g. it's a fixed rail for a WLAN chip.
277 *
278 * In other cases vcc_aux switches interface power. Example, for
279 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
280 * chips/cards need an interface voltage rail too.
281 */
282 if (power_on) {
283 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
284 /* Enable interface voltage rail, if needed */
285 if (ret == 0 && host->vcc_aux) {
286 ret = regulator_enable(host->vcc_aux);
287 if (ret < 0)
288 ret = mmc_regulator_set_ocr(host->mmc,
289 host->vcc, 0);
290 }
291 } else {
292 /* Shut down the rail */
293 if (host->vcc_aux)
294 ret = regulator_disable(host->vcc_aux);
295 if (!ret) {
296 /* Then proceed to shut down the local regulator */
297 ret = mmc_regulator_set_ocr(host->mmc,
298 host->vcc, 0);
299 }
300 }
301
302 if (mmc_slot(host).after_set_reg)
303 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
304
305 return ret;
306 }
307
308 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
309 {
310 struct regulator *reg;
311 int ocr_value = 0;
312
313 reg = regulator_get(host->dev, "vmmc");
314 if (IS_ERR(reg)) {
315 dev_err(host->dev, "vmmc regulator missing\n");
316 return PTR_ERR(reg);
317 } else {
318 mmc_slot(host).set_power = omap_hsmmc_set_power;
319 host->vcc = reg;
320 ocr_value = mmc_regulator_get_ocrmask(reg);
321 if (!mmc_slot(host).ocr_mask) {
322 mmc_slot(host).ocr_mask = ocr_value;
323 } else {
324 if (!(mmc_slot(host).ocr_mask & ocr_value)) {
325 dev_err(host->dev, "ocrmask %x is not supported\n",
326 mmc_slot(host).ocr_mask);
327 mmc_slot(host).ocr_mask = 0;
328 return -EINVAL;
329 }
330 }
331
332 /* Allow an aux regulator */
333 reg = regulator_get(host->dev, "vmmc_aux");
334 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
335
336 /* For eMMC do not power off when not in sleep state */
337 if (mmc_slot(host).no_regulator_off_init)
338 return 0;
339 /*
340 * UGLY HACK: workaround regulator framework bugs.
341 * When the bootloader leaves a supply active, it's
342 * initialized with zero usecount ... and we can't
343 * disable it without first enabling it. Until the
344 * framework is fixed, we need a workaround like this
345 * (which is safe for MMC, but not in general).
346 */
347 if (regulator_is_enabled(host->vcc) > 0 ||
348 (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) {
349 int vdd = ffs(mmc_slot(host).ocr_mask) - 1;
350
351 mmc_slot(host).set_power(host->dev, host->slot_id,
352 1, vdd);
353 mmc_slot(host).set_power(host->dev, host->slot_id,
354 0, 0);
355 }
356 }
357
358 return 0;
359 }
360
361 static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
362 {
363 regulator_put(host->vcc);
364 regulator_put(host->vcc_aux);
365 mmc_slot(host).set_power = NULL;
366 }
367
368 static inline int omap_hsmmc_have_reg(void)
369 {
370 return 1;
371 }
372
373 #else
374
375 static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
376 {
377 return -EINVAL;
378 }
379
380 static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
381 {
382 }
383
384 static inline int omap_hsmmc_have_reg(void)
385 {
386 return 0;
387 }
388
389 #endif
390
391 static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
392 {
393 int ret;
394
395 if (gpio_is_valid(pdata->slots[0].switch_pin)) {
396 if (pdata->slots[0].cover)
397 pdata->slots[0].get_cover_state =
398 omap_hsmmc_get_cover_state;
399 else
400 pdata->slots[0].card_detect = omap_hsmmc_card_detect;
401 pdata->slots[0].card_detect_irq =
402 gpio_to_irq(pdata->slots[0].switch_pin);
403 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
404 if (ret)
405 return ret;
406 ret = gpio_direction_input(pdata->slots[0].switch_pin);
407 if (ret)
408 goto err_free_sp;
409 } else
410 pdata->slots[0].switch_pin = -EINVAL;
411
412 if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
413 pdata->slots[0].get_ro = omap_hsmmc_get_wp;
414 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
415 if (ret)
416 goto err_free_cd;
417 ret = gpio_direction_input(pdata->slots[0].gpio_wp);
418 if (ret)
419 goto err_free_wp;
420 } else
421 pdata->slots[0].gpio_wp = -EINVAL;
422
423 return 0;
424
425 err_free_wp:
426 gpio_free(pdata->slots[0].gpio_wp);
427 err_free_cd:
428 if (gpio_is_valid(pdata->slots[0].switch_pin))
429 err_free_sp:
430 gpio_free(pdata->slots[0].switch_pin);
431 return ret;
432 }
433
434 static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
435 {
436 if (gpio_is_valid(pdata->slots[0].gpio_wp))
437 gpio_free(pdata->slots[0].gpio_wp);
438 if (gpio_is_valid(pdata->slots[0].switch_pin))
439 gpio_free(pdata->slots[0].switch_pin);
440 }
441
442 /*
443 * Start clock to the card
444 */
445 static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
446 {
447 OMAP_HSMMC_WRITE(host->base, SYSCTL,
448 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
449 }
450
451 /*
452 * Stop clock to the card
453 */
454 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
455 {
456 OMAP_HSMMC_WRITE(host->base, SYSCTL,
457 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
458 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
459 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n");
460 }
461
462 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
463 struct mmc_command *cmd)
464 {
465 unsigned int irq_mask;
466
467 if (host->use_dma)
468 irq_mask = INT_EN_MASK & ~(BRR_EN | BWR_EN);
469 else
470 irq_mask = INT_EN_MASK;
471
472 /* Disable timeout for erases */
473 if (cmd->opcode == MMC_ERASE)
474 irq_mask &= ~DTO_EN;
475
476 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
477 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
478 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
479 }
480
481 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
482 {
483 OMAP_HSMMC_WRITE(host->base, ISE, 0);
484 OMAP_HSMMC_WRITE(host->base, IE, 0);
485 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
486 }
487
488 /* Calculate divisor for the given clock frequency */
489 static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
490 {
491 u16 dsor = 0;
492
493 if (ios->clock) {
494 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
495 if (dsor > 250)
496 dsor = 250;
497 }
498
499 return dsor;
500 }
501
502 static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
503 {
504 struct mmc_ios *ios = &host->mmc->ios;
505 unsigned long regval;
506 unsigned long timeout;
507 unsigned long clkdiv;
508
509 dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
510
511 omap_hsmmc_stop_clock(host);
512
513 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
514 regval = regval & ~(CLKD_MASK | DTO_MASK);
515 clkdiv = calc_divisor(host, ios);
516 regval = regval | (clkdiv << 6) | (DTO << 16);
517 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
518 OMAP_HSMMC_WRITE(host->base, SYSCTL,
519 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
520
521 /* Wait till the ICS bit is set */
522 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
523 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
524 && time_before(jiffies, timeout))
525 cpu_relax();
526
527 /*
528 * Enable High-Speed Support
529 * Pre-Requisites
530 * - Controller should support High-Speed-Enable Bit
531 * - Controller should not be using DDR Mode
532 * - Controller should advertise that it supports High Speed
533 * in capabilities register
534 * - MMC/SD clock coming out of controller > 25MHz
535 */
536 if ((mmc_slot(host).features & HSMMC_HAS_HSPE_SUPPORT) &&
537 (ios->timing != MMC_TIMING_UHS_DDR50) &&
538 ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) {
539 regval = OMAP_HSMMC_READ(host->base, HCTL);
540 if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000)
541 regval |= HSPE;
542 else
543 regval &= ~HSPE;
544
545 OMAP_HSMMC_WRITE(host->base, HCTL, regval);
546 }
547
548 omap_hsmmc_start_clock(host);
549 }
550
551 static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
552 {
553 struct mmc_ios *ios = &host->mmc->ios;
554 u32 con;
555
556 con = OMAP_HSMMC_READ(host->base, CON);
557 if (ios->timing == MMC_TIMING_UHS_DDR50)
558 con |= DDR; /* configure in DDR mode */
559 else
560 con &= ~DDR;
561 switch (ios->bus_width) {
562 case MMC_BUS_WIDTH_8:
563 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
564 break;
565 case MMC_BUS_WIDTH_4:
566 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
567 OMAP_HSMMC_WRITE(host->base, HCTL,
568 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
569 break;
570 case MMC_BUS_WIDTH_1:
571 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
572 OMAP_HSMMC_WRITE(host->base, HCTL,
573 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
574 break;
575 }
576 }
577
578 static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
579 {
580 struct mmc_ios *ios = &host->mmc->ios;
581 u32 con;
582
583 con = OMAP_HSMMC_READ(host->base, CON);
584 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
585 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
586 else
587 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
588 }
589
590 #ifdef CONFIG_PM
591
592 /*
593 * Restore the MMC host context, if it was lost as result of a
594 * power state change.
595 */
596 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
597 {
598 struct mmc_ios *ios = &host->mmc->ios;
599 struct omap_mmc_platform_data *pdata = host->pdata;
600 int context_loss = 0;
601 u32 hctl, capa;
602 unsigned long timeout;
603
604 if (pdata->get_context_loss_count) {
605 context_loss = pdata->get_context_loss_count(host->dev);
606 if (context_loss < 0)
607 return 1;
608 }
609
610 dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
611 context_loss == host->context_loss ? "not " : "");
612 if (host->context_loss == context_loss)
613 return 1;
614
615 if (!OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE)
616 return 1;
617
618 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
619 if (host->power_mode != MMC_POWER_OFF &&
620 (1 << ios->vdd) <= MMC_VDD_23_24)
621 hctl = SDVS18;
622 else
623 hctl = SDVS30;
624 capa = VS30 | VS18;
625 } else {
626 hctl = SDVS18;
627 capa = VS18;
628 }
629
630 OMAP_HSMMC_WRITE(host->base, HCTL,
631 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
632
633 OMAP_HSMMC_WRITE(host->base, CAPA,
634 OMAP_HSMMC_READ(host->base, CAPA) | capa);
635
636 OMAP_HSMMC_WRITE(host->base, HCTL,
637 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
638
639 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
640 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
641 && time_before(jiffies, timeout))
642 ;
643
644 omap_hsmmc_disable_irq(host);
645
646 /* Do not initialize card-specific things if the power is off */
647 if (host->power_mode == MMC_POWER_OFF)
648 goto out;
649
650 omap_hsmmc_set_bus_width(host);
651
652 omap_hsmmc_set_clock(host);
653
654 omap_hsmmc_set_bus_mode(host);
655
656 out:
657 host->context_loss = context_loss;
658
659 dev_dbg(mmc_dev(host->mmc), "context is restored\n");
660 return 0;
661 }
662
663 /*
664 * Save the MMC host context (store the number of power state changes so far).
665 */
666 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
667 {
668 struct omap_mmc_platform_data *pdata = host->pdata;
669 int context_loss;
670
671 if (pdata->get_context_loss_count) {
672 context_loss = pdata->get_context_loss_count(host->dev);
673 if (context_loss < 0)
674 return;
675 host->context_loss = context_loss;
676 }
677 }
678
679 #else
680
681 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
682 {
683 return 0;
684 }
685
686 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
687 {
688 }
689
690 #endif
691
692 /*
693 * Send init stream sequence to card
694 * before sending IDLE command
695 */
696 static void send_init_stream(struct omap_hsmmc_host *host)
697 {
698 int reg = 0;
699 unsigned long timeout;
700
701 if (host->protect_card)
702 return;
703
704 disable_irq(host->irq);
705
706 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
707 OMAP_HSMMC_WRITE(host->base, CON,
708 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
709 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
710
711 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
712 while ((reg != CC_EN) && time_before(jiffies, timeout))
713 reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN;
714
715 OMAP_HSMMC_WRITE(host->base, CON,
716 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
717
718 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
719 OMAP_HSMMC_READ(host->base, STAT);
720
721 enable_irq(host->irq);
722 }
723
724 static inline
725 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
726 {
727 int r = 1;
728
729 if (mmc_slot(host).get_cover_state)
730 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
731 return r;
732 }
733
734 static ssize_t
735 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
736 char *buf)
737 {
738 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
739 struct omap_hsmmc_host *host = mmc_priv(mmc);
740
741 return sprintf(buf, "%s\n",
742 omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
743 }
744
745 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
746
747 static ssize_t
748 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
749 char *buf)
750 {
751 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
752 struct omap_hsmmc_host *host = mmc_priv(mmc);
753
754 return sprintf(buf, "%s\n", mmc_slot(host).name);
755 }
756
757 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
758
759 /*
760 * Configure the response type and send the cmd.
761 */
762 static void
763 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
764 struct mmc_data *data)
765 {
766 int cmdreg = 0, resptype = 0, cmdtype = 0;
767
768 dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
769 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
770 host->cmd = cmd;
771
772 omap_hsmmc_enable_irq(host, cmd);
773
774 host->response_busy = 0;
775 if (cmd->flags & MMC_RSP_PRESENT) {
776 if (cmd->flags & MMC_RSP_136)
777 resptype = 1;
778 else if (cmd->flags & MMC_RSP_BUSY) {
779 resptype = 3;
780 host->response_busy = 1;
781 } else
782 resptype = 2;
783 }
784
785 /*
786 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
787 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
788 * a val of 0x3, rest 0x0.
789 */
790 if (cmd == host->mrq->stop)
791 cmdtype = 0x3;
792
793 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
794
795 if (data) {
796 cmdreg |= DP_SELECT | MSBS | BCE;
797 if (data->flags & MMC_DATA_READ)
798 cmdreg |= DDIR;
799 else
800 cmdreg &= ~(DDIR);
801 }
802
803 if (host->use_dma)
804 cmdreg |= DMAE;
805
806 host->req_in_progress = 1;
807
808 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
809 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
810 }
811
812 static int
813 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
814 {
815 if (data->flags & MMC_DATA_WRITE)
816 return DMA_TO_DEVICE;
817 else
818 return DMA_FROM_DEVICE;
819 }
820
821 static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host,
822 struct mmc_data *data)
823 {
824 return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
825 }
826
827 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
828 {
829 int dma_ch;
830 unsigned long flags;
831
832 spin_lock_irqsave(&host->irq_lock, flags);
833 host->req_in_progress = 0;
834 dma_ch = host->dma_ch;
835 spin_unlock_irqrestore(&host->irq_lock, flags);
836
837 omap_hsmmc_disable_irq(host);
838 /* Do not complete the request if DMA is still in progress */
839 if (mrq->data && host->use_dma && dma_ch != -1)
840 return;
841 host->mrq = NULL;
842 mmc_request_done(host->mmc, mrq);
843 }
844
845 /*
846 * Notify the transfer complete to MMC core
847 */
848 static void
849 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
850 {
851 if (!data) {
852 struct mmc_request *mrq = host->mrq;
853
854 /* TC before CC from CMD6 - don't know why, but it happens */
855 if (host->cmd && host->cmd->opcode == 6 &&
856 host->response_busy) {
857 host->response_busy = 0;
858 return;
859 }
860
861 omap_hsmmc_request_done(host, mrq);
862 return;
863 }
864
865 host->data = NULL;
866
867 if (!data->error)
868 data->bytes_xfered += data->blocks * (data->blksz);
869 else
870 data->bytes_xfered = 0;
871
872 if (!data->stop) {
873 omap_hsmmc_request_done(host, data->mrq);
874 return;
875 }
876 omap_hsmmc_start_command(host, data->stop, NULL);
877 }
878
879 /*
880 * Notify the core about command completion
881 */
882 static void
883 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
884 {
885 host->cmd = NULL;
886
887 if (cmd->flags & MMC_RSP_PRESENT) {
888 if (cmd->flags & MMC_RSP_136) {
889 /* response type 2 */
890 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
891 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
892 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
893 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
894 } else {
895 /* response types 1, 1b, 3, 4, 5, 6 */
896 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
897 }
898 }
899 if ((host->data == NULL && !host->response_busy) || cmd->error)
900 omap_hsmmc_request_done(host, cmd->mrq);
901 }
902
903 /*
904 * DMA clean up for command errors
905 */
906 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
907 {
908 int dma_ch;
909 unsigned long flags;
910
911 host->data->error = errno;
912
913 spin_lock_irqsave(&host->irq_lock, flags);
914 dma_ch = host->dma_ch;
915 host->dma_ch = -1;
916 spin_unlock_irqrestore(&host->irq_lock, flags);
917
918 if (host->use_dma && dma_ch != -1) {
919 struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data);
920
921 dmaengine_terminate_all(chan);
922 dma_unmap_sg(chan->device->dev,
923 host->data->sg, host->data->sg_len,
924 omap_hsmmc_get_dma_dir(host, host->data));
925
926 host->data->host_cookie = 0;
927 }
928 host->data = NULL;
929 }
930
931 /*
932 * Readable error output
933 */
934 #ifdef CONFIG_MMC_DEBUG
935 static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
936 {
937 /* --- means reserved bit without definition at documentation */
938 static const char *omap_hsmmc_status_bits[] = {
939 "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
940 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
941 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
942 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
943 };
944 char res[256];
945 char *buf = res;
946 int len, i;
947
948 len = sprintf(buf, "MMC IRQ 0x%x :", status);
949 buf += len;
950
951 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
952 if (status & (1 << i)) {
953 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
954 buf += len;
955 }
956
957 dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
958 }
959 #else
960 static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
961 u32 status)
962 {
963 }
964 #endif /* CONFIG_MMC_DEBUG */
965
966 /*
967 * MMC controller internal state machines reset
968 *
969 * Used to reset command or data internal state machines, using respectively
970 * SRC or SRD bit of SYSCTL register
971 * Can be called from interrupt context
972 */
973 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
974 unsigned long bit)
975 {
976 unsigned long i = 0;
977 unsigned long limit = (loops_per_jiffy *
978 msecs_to_jiffies(MMC_TIMEOUT_MS));
979
980 OMAP_HSMMC_WRITE(host->base, SYSCTL,
981 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
982
983 /*
984 * OMAP4 ES2 and greater has an updated reset logic.
985 * Monitor a 0->1 transition first
986 */
987 if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
988 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
989 && (i++ < limit))
990 cpu_relax();
991 }
992 i = 0;
993
994 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
995 (i++ < limit))
996 cpu_relax();
997
998 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
999 dev_err(mmc_dev(host->mmc),
1000 "Timeout waiting on controller reset in %s\n",
1001 __func__);
1002 }
1003
1004 static void hsmmc_command_incomplete(struct omap_hsmmc_host *host,
1005 int err, int end_cmd)
1006 {
1007 if (end_cmd) {
1008 omap_hsmmc_reset_controller_fsm(host, SRC);
1009 if (host->cmd)
1010 host->cmd->error = err;
1011 }
1012
1013 if (host->data) {
1014 omap_hsmmc_reset_controller_fsm(host, SRD);
1015 omap_hsmmc_dma_cleanup(host, err);
1016 } else if (host->mrq && host->mrq->cmd)
1017 host->mrq->cmd->error = err;
1018 }
1019
1020 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
1021 {
1022 struct mmc_data *data;
1023 int end_cmd = 0, end_trans = 0;
1024
1025 data = host->data;
1026 dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1027
1028 if (status & ERR_EN) {
1029 omap_hsmmc_dbg_report_irq(host, status);
1030
1031 if (status & (CTO_EN | CCRC_EN))
1032 end_cmd = 1;
1033 if (status & (CTO_EN | DTO_EN))
1034 hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd);
1035 else if (status & (CCRC_EN | DCRC_EN))
1036 hsmmc_command_incomplete(host, -EILSEQ, end_cmd);
1037
1038 if (host->data || host->response_busy) {
1039 end_trans = !end_cmd;
1040 host->response_busy = 0;
1041 }
1042 }
1043
1044 if (end_cmd || ((status & CC_EN) && host->cmd))
1045 omap_hsmmc_cmd_done(host, host->cmd);
1046 if ((end_trans || (status & TC_EN)) && host->mrq)
1047 omap_hsmmc_xfer_done(host, data);
1048 }
1049
1050 /*
1051 * MMC controller IRQ handler
1052 */
1053 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1054 {
1055 struct omap_hsmmc_host *host = dev_id;
1056 int status;
1057
1058 status = OMAP_HSMMC_READ(host->base, STAT);
1059 while (status & INT_EN_MASK && host->req_in_progress) {
1060 omap_hsmmc_do_irq(host, status);
1061
1062 /* Flush posted write */
1063 OMAP_HSMMC_WRITE(host->base, STAT, status);
1064 status = OMAP_HSMMC_READ(host->base, STAT);
1065 }
1066
1067 return IRQ_HANDLED;
1068 }
1069
1070 static void set_sd_bus_power(struct omap_hsmmc_host *host)
1071 {
1072 unsigned long i;
1073
1074 OMAP_HSMMC_WRITE(host->base, HCTL,
1075 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1076 for (i = 0; i < loops_per_jiffy; i++) {
1077 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1078 break;
1079 cpu_relax();
1080 }
1081 }
1082
1083 /*
1084 * Switch MMC interface voltage ... only relevant for MMC1.
1085 *
1086 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1087 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1088 * Some chips, like eMMC ones, use internal transceivers.
1089 */
1090 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1091 {
1092 u32 reg_val = 0;
1093 int ret;
1094
1095 /* Disable the clocks */
1096 pm_runtime_put_sync(host->dev);
1097 if (host->dbclk)
1098 clk_disable_unprepare(host->dbclk);
1099
1100 /* Turn the power off */
1101 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1102
1103 /* Turn the power ON with given VDD 1.8 or 3.0v */
1104 if (!ret)
1105 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1106 vdd);
1107 pm_runtime_get_sync(host->dev);
1108 if (host->dbclk)
1109 clk_prepare_enable(host->dbclk);
1110
1111 if (ret != 0)
1112 goto err;
1113
1114 OMAP_HSMMC_WRITE(host->base, HCTL,
1115 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1116 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1117
1118 /*
1119 * If a MMC dual voltage card is detected, the set_ios fn calls
1120 * this fn with VDD bit set for 1.8V. Upon card removal from the
1121 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1122 *
1123 * Cope with a bit of slop in the range ... per data sheets:
1124 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1125 * but recommended values are 1.71V to 1.89V
1126 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1127 * but recommended values are 2.7V to 3.3V
1128 *
1129 * Board setup code shouldn't permit anything very out-of-range.
1130 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1131 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1132 */
1133 if ((1 << vdd) <= MMC_VDD_23_24)
1134 reg_val |= SDVS18;
1135 else
1136 reg_val |= SDVS30;
1137
1138 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1139 set_sd_bus_power(host);
1140
1141 return 0;
1142 err:
1143 dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1144 return ret;
1145 }
1146
1147 /* Protect the card while the cover is open */
1148 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1149 {
1150 if (!mmc_slot(host).get_cover_state)
1151 return;
1152
1153 host->reqs_blocked = 0;
1154 if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1155 if (host->protect_card) {
1156 dev_info(host->dev, "%s: cover is closed, "
1157 "card is now accessible\n",
1158 mmc_hostname(host->mmc));
1159 host->protect_card = 0;
1160 }
1161 } else {
1162 if (!host->protect_card) {
1163 dev_info(host->dev, "%s: cover is open, "
1164 "card is now inaccessible\n",
1165 mmc_hostname(host->mmc));
1166 host->protect_card = 1;
1167 }
1168 }
1169 }
1170
1171 /*
1172 * irq handler to notify the core about card insertion/removal
1173 */
1174 static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id)
1175 {
1176 struct omap_hsmmc_host *host = dev_id;
1177 struct omap_mmc_slot_data *slot = &mmc_slot(host);
1178 int carddetect;
1179
1180 if (host->suspended)
1181 return IRQ_HANDLED;
1182
1183 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
1184
1185 if (slot->card_detect)
1186 carddetect = slot->card_detect(host->dev, host->slot_id);
1187 else {
1188 omap_hsmmc_protect_card(host);
1189 carddetect = -ENOSYS;
1190 }
1191
1192 if (carddetect)
1193 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
1194 else
1195 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
1196 return IRQ_HANDLED;
1197 }
1198
1199 static void omap_hsmmc_dma_callback(void *param)
1200 {
1201 struct omap_hsmmc_host *host = param;
1202 struct dma_chan *chan;
1203 struct mmc_data *data;
1204 int req_in_progress;
1205
1206 spin_lock_irq(&host->irq_lock);
1207 if (host->dma_ch < 0) {
1208 spin_unlock_irq(&host->irq_lock);
1209 return;
1210 }
1211
1212 data = host->mrq->data;
1213 chan = omap_hsmmc_get_dma_chan(host, data);
1214 if (!data->host_cookie)
1215 dma_unmap_sg(chan->device->dev,
1216 data->sg, data->sg_len,
1217 omap_hsmmc_get_dma_dir(host, data));
1218
1219 req_in_progress = host->req_in_progress;
1220 host->dma_ch = -1;
1221 spin_unlock_irq(&host->irq_lock);
1222
1223 /* If DMA has finished after TC, complete the request */
1224 if (!req_in_progress) {
1225 struct mmc_request *mrq = host->mrq;
1226
1227 host->mrq = NULL;
1228 mmc_request_done(host->mmc, mrq);
1229 }
1230 }
1231
1232 static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1233 struct mmc_data *data,
1234 struct omap_hsmmc_next *next,
1235 struct dma_chan *chan)
1236 {
1237 int dma_len;
1238
1239 if (!next && data->host_cookie &&
1240 data->host_cookie != host->next_data.cookie) {
1241 dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d"
1242 " host->next_data.cookie %d\n",
1243 __func__, data->host_cookie, host->next_data.cookie);
1244 data->host_cookie = 0;
1245 }
1246
1247 /* Check if next job is already prepared */
1248 if (next ||
1249 (!next && data->host_cookie != host->next_data.cookie)) {
1250 dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len,
1251 omap_hsmmc_get_dma_dir(host, data));
1252
1253 } else {
1254 dma_len = host->next_data.dma_len;
1255 host->next_data.dma_len = 0;
1256 }
1257
1258
1259 if (dma_len == 0)
1260 return -EINVAL;
1261
1262 if (next) {
1263 next->dma_len = dma_len;
1264 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1265 } else
1266 host->dma_len = dma_len;
1267
1268 return 0;
1269 }
1270
1271 /*
1272 * Routine to configure and start DMA for the MMC card
1273 */
1274 static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
1275 struct mmc_request *req)
1276 {
1277 struct dma_slave_config cfg;
1278 struct dma_async_tx_descriptor *tx;
1279 int ret = 0, i;
1280 struct mmc_data *data = req->data;
1281 struct dma_chan *chan;
1282
1283 /* Sanity check: all the SG entries must be aligned by block size. */
1284 for (i = 0; i < data->sg_len; i++) {
1285 struct scatterlist *sgl;
1286
1287 sgl = data->sg + i;
1288 if (sgl->length % data->blksz)
1289 return -EINVAL;
1290 }
1291 if ((data->blksz % 4) != 0)
1292 /* REVISIT: The MMC buffer increments only when MSB is written.
1293 * Return error for blksz which is non multiple of four.
1294 */
1295 return -EINVAL;
1296
1297 BUG_ON(host->dma_ch != -1);
1298
1299 chan = omap_hsmmc_get_dma_chan(host, data);
1300
1301 cfg.src_addr = host->mapbase + OMAP_HSMMC_DATA;
1302 cfg.dst_addr = host->mapbase + OMAP_HSMMC_DATA;
1303 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1304 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1305 cfg.src_maxburst = data->blksz / 4;
1306 cfg.dst_maxburst = data->blksz / 4;
1307
1308 ret = dmaengine_slave_config(chan, &cfg);
1309 if (ret)
1310 return ret;
1311
1312 ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan);
1313 if (ret)
1314 return ret;
1315
1316 tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len,
1317 data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
1318 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1319 if (!tx) {
1320 dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n");
1321 /* FIXME: cleanup */
1322 return -1;
1323 }
1324
1325 tx->callback = omap_hsmmc_dma_callback;
1326 tx->callback_param = host;
1327
1328 /* Does not fail */
1329 dmaengine_submit(tx);
1330
1331 host->dma_ch = 1;
1332
1333 dma_async_issue_pending(chan);
1334
1335 return 0;
1336 }
1337
1338 static void set_data_timeout(struct omap_hsmmc_host *host,
1339 unsigned int timeout_ns,
1340 unsigned int timeout_clks)
1341 {
1342 unsigned int timeout, cycle_ns;
1343 uint32_t reg, clkd, dto = 0;
1344
1345 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1346 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1347 if (clkd == 0)
1348 clkd = 1;
1349
1350 cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
1351 timeout = timeout_ns / cycle_ns;
1352 timeout += timeout_clks;
1353 if (timeout) {
1354 while ((timeout & 0x80000000) == 0) {
1355 dto += 1;
1356 timeout <<= 1;
1357 }
1358 dto = 31 - dto;
1359 timeout <<= 1;
1360 if (timeout && dto)
1361 dto += 1;
1362 if (dto >= 13)
1363 dto -= 13;
1364 else
1365 dto = 0;
1366 if (dto > 14)
1367 dto = 14;
1368 }
1369
1370 reg &= ~DTO_MASK;
1371 reg |= dto << DTO_SHIFT;
1372 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1373 }
1374
1375 /*
1376 * Configure block length for MMC/SD cards and initiate the transfer.
1377 */
1378 static int
1379 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1380 {
1381 int ret;
1382 host->data = req->data;
1383
1384 if (req->data == NULL) {
1385 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1386 /*
1387 * Set an arbitrary 100ms data timeout for commands with
1388 * busy signal.
1389 */
1390 if (req->cmd->flags & MMC_RSP_BUSY)
1391 set_data_timeout(host, 100000000U, 0);
1392 return 0;
1393 }
1394
1395 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1396 | (req->data->blocks << 16));
1397 set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
1398
1399 if (host->use_dma) {
1400 ret = omap_hsmmc_start_dma_transfer(host, req);
1401 if (ret != 0) {
1402 dev_err(mmc_dev(host->mmc), "MMC start dma failure\n");
1403 return ret;
1404 }
1405 }
1406 return 0;
1407 }
1408
1409 static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1410 int err)
1411 {
1412 struct omap_hsmmc_host *host = mmc_priv(mmc);
1413 struct mmc_data *data = mrq->data;
1414
1415 if (host->use_dma && data->host_cookie) {
1416 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data);
1417
1418 dma_unmap_sg(c->device->dev, data->sg, data->sg_len,
1419 omap_hsmmc_get_dma_dir(host, data));
1420 data->host_cookie = 0;
1421 }
1422 }
1423
1424 static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1425 bool is_first_req)
1426 {
1427 struct omap_hsmmc_host *host = mmc_priv(mmc);
1428
1429 if (mrq->data->host_cookie) {
1430 mrq->data->host_cookie = 0;
1431 return ;
1432 }
1433
1434 if (host->use_dma) {
1435 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data);
1436
1437 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1438 &host->next_data, c))
1439 mrq->data->host_cookie = 0;
1440 }
1441 }
1442
1443 /*
1444 * Request function. for read/write operation
1445 */
1446 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1447 {
1448 struct omap_hsmmc_host *host = mmc_priv(mmc);
1449 int err;
1450
1451 BUG_ON(host->req_in_progress);
1452 BUG_ON(host->dma_ch != -1);
1453 if (host->protect_card) {
1454 if (host->reqs_blocked < 3) {
1455 /*
1456 * Ensure the controller is left in a consistent
1457 * state by resetting the command and data state
1458 * machines.
1459 */
1460 omap_hsmmc_reset_controller_fsm(host, SRD);
1461 omap_hsmmc_reset_controller_fsm(host, SRC);
1462 host->reqs_blocked += 1;
1463 }
1464 req->cmd->error = -EBADF;
1465 if (req->data)
1466 req->data->error = -EBADF;
1467 req->cmd->retries = 0;
1468 mmc_request_done(mmc, req);
1469 return;
1470 } else if (host->reqs_blocked)
1471 host->reqs_blocked = 0;
1472 WARN_ON(host->mrq != NULL);
1473 host->mrq = req;
1474 err = omap_hsmmc_prepare_data(host, req);
1475 if (err) {
1476 req->cmd->error = err;
1477 if (req->data)
1478 req->data->error = err;
1479 host->mrq = NULL;
1480 mmc_request_done(mmc, req);
1481 return;
1482 }
1483
1484 omap_hsmmc_start_command(host, req->cmd, req->data);
1485 }
1486
1487 /* Routine to configure clock values. Exposed API to core */
1488 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1489 {
1490 struct omap_hsmmc_host *host = mmc_priv(mmc);
1491 int do_send_init_stream = 0;
1492
1493 pm_runtime_get_sync(host->dev);
1494
1495 if (ios->power_mode != host->power_mode) {
1496 switch (ios->power_mode) {
1497 case MMC_POWER_OFF:
1498 mmc_slot(host).set_power(host->dev, host->slot_id,
1499 0, 0);
1500 break;
1501 case MMC_POWER_UP:
1502 mmc_slot(host).set_power(host->dev, host->slot_id,
1503 1, ios->vdd);
1504 break;
1505 case MMC_POWER_ON:
1506 do_send_init_stream = 1;
1507 break;
1508 }
1509 host->power_mode = ios->power_mode;
1510 }
1511
1512 /* FIXME: set registers based only on changes to ios */
1513
1514 omap_hsmmc_set_bus_width(host);
1515
1516 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1517 /* Only MMC1 can interface at 3V without some flavor
1518 * of external transceiver; but they all handle 1.8V.
1519 */
1520 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1521 (ios->vdd == DUAL_VOLT_OCR_BIT) &&
1522 /*
1523 * With pbias cell programming missing, this
1524 * can't be allowed on MMC1 when booting with device
1525 * tree.
1526 */
1527 !host->pbias_disable) {
1528 /*
1529 * The mmc_select_voltage fn of the core does
1530 * not seem to set the power_mode to
1531 * MMC_POWER_UP upon recalculating the voltage.
1532 * vdd 1.8v.
1533 */
1534 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1535 dev_dbg(mmc_dev(host->mmc),
1536 "Switch operation failed\n");
1537 }
1538 }
1539
1540 omap_hsmmc_set_clock(host);
1541
1542 if (do_send_init_stream)
1543 send_init_stream(host);
1544
1545 omap_hsmmc_set_bus_mode(host);
1546
1547 pm_runtime_put_autosuspend(host->dev);
1548 }
1549
1550 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1551 {
1552 struct omap_hsmmc_host *host = mmc_priv(mmc);
1553
1554 if (!mmc_slot(host).card_detect)
1555 return -ENOSYS;
1556 return mmc_slot(host).card_detect(host->dev, host->slot_id);
1557 }
1558
1559 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1560 {
1561 struct omap_hsmmc_host *host = mmc_priv(mmc);
1562
1563 if (!mmc_slot(host).get_ro)
1564 return -ENOSYS;
1565 return mmc_slot(host).get_ro(host->dev, 0);
1566 }
1567
1568 static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1569 {
1570 struct omap_hsmmc_host *host = mmc_priv(mmc);
1571
1572 if (mmc_slot(host).init_card)
1573 mmc_slot(host).init_card(card);
1574 }
1575
1576 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1577 {
1578 u32 hctl, capa, value;
1579
1580 /* Only MMC1 supports 3.0V */
1581 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1582 hctl = SDVS30;
1583 capa = VS30 | VS18;
1584 } else {
1585 hctl = SDVS18;
1586 capa = VS18;
1587 }
1588
1589 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1590 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1591
1592 value = OMAP_HSMMC_READ(host->base, CAPA);
1593 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1594
1595 /* Set SD bus power bit */
1596 set_sd_bus_power(host);
1597 }
1598
1599 static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
1600 {
1601 struct omap_hsmmc_host *host = mmc_priv(mmc);
1602
1603 pm_runtime_get_sync(host->dev);
1604
1605 return 0;
1606 }
1607
1608 static int omap_hsmmc_disable_fclk(struct mmc_host *mmc)
1609 {
1610 struct omap_hsmmc_host *host = mmc_priv(mmc);
1611
1612 pm_runtime_mark_last_busy(host->dev);
1613 pm_runtime_put_autosuspend(host->dev);
1614
1615 return 0;
1616 }
1617
1618 static const struct mmc_host_ops omap_hsmmc_ops = {
1619 .enable = omap_hsmmc_enable_fclk,
1620 .disable = omap_hsmmc_disable_fclk,
1621 .post_req = omap_hsmmc_post_req,
1622 .pre_req = omap_hsmmc_pre_req,
1623 .request = omap_hsmmc_request,
1624 .set_ios = omap_hsmmc_set_ios,
1625 .get_cd = omap_hsmmc_get_cd,
1626 .get_ro = omap_hsmmc_get_ro,
1627 .init_card = omap_hsmmc_init_card,
1628 /* NYET -- enable_sdio_irq */
1629 };
1630
1631 #ifdef CONFIG_DEBUG_FS
1632
1633 static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1634 {
1635 struct mmc_host *mmc = s->private;
1636 struct omap_hsmmc_host *host = mmc_priv(mmc);
1637 int context_loss = 0;
1638
1639 if (host->pdata->get_context_loss_count)
1640 context_loss = host->pdata->get_context_loss_count(host->dev);
1641
1642 seq_printf(s, "mmc%d:\n ctx_loss:\t%d:%d\n\nregs:\n",
1643 mmc->index, host->context_loss, context_loss);
1644
1645 if (host->suspended) {
1646 seq_printf(s, "host suspended, can't read registers\n");
1647 return 0;
1648 }
1649
1650 pm_runtime_get_sync(host->dev);
1651
1652 seq_printf(s, "CON:\t\t0x%08x\n",
1653 OMAP_HSMMC_READ(host->base, CON));
1654 seq_printf(s, "HCTL:\t\t0x%08x\n",
1655 OMAP_HSMMC_READ(host->base, HCTL));
1656 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1657 OMAP_HSMMC_READ(host->base, SYSCTL));
1658 seq_printf(s, "IE:\t\t0x%08x\n",
1659 OMAP_HSMMC_READ(host->base, IE));
1660 seq_printf(s, "ISE:\t\t0x%08x\n",
1661 OMAP_HSMMC_READ(host->base, ISE));
1662 seq_printf(s, "CAPA:\t\t0x%08x\n",
1663 OMAP_HSMMC_READ(host->base, CAPA));
1664
1665 pm_runtime_mark_last_busy(host->dev);
1666 pm_runtime_put_autosuspend(host->dev);
1667
1668 return 0;
1669 }
1670
1671 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
1672 {
1673 return single_open(file, omap_hsmmc_regs_show, inode->i_private);
1674 }
1675
1676 static const struct file_operations mmc_regs_fops = {
1677 .open = omap_hsmmc_regs_open,
1678 .read = seq_read,
1679 .llseek = seq_lseek,
1680 .release = single_release,
1681 };
1682
1683 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1684 {
1685 if (mmc->debugfs_root)
1686 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1687 mmc, &mmc_regs_fops);
1688 }
1689
1690 #else
1691
1692 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1693 {
1694 }
1695
1696 #endif
1697
1698 #ifdef CONFIG_OF
1699 static u16 omap4_reg_offset = 0x100;
1700
1701 static const struct of_device_id omap_mmc_of_match[] = {
1702 {
1703 .compatible = "ti,omap2-hsmmc",
1704 },
1705 {
1706 .compatible = "ti,omap3-hsmmc",
1707 },
1708 {
1709 .compatible = "ti,omap4-hsmmc",
1710 .data = &omap4_reg_offset,
1711 },
1712 {},
1713 };
1714 MODULE_DEVICE_TABLE(of, omap_mmc_of_match);
1715
1716 static struct omap_mmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
1717 {
1718 struct omap_mmc_platform_data *pdata;
1719 struct device_node *np = dev->of_node;
1720 u32 bus_width, max_freq;
1721 int cd_gpio, wp_gpio;
1722
1723 cd_gpio = of_get_named_gpio(np, "cd-gpios", 0);
1724 wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
1725 if (cd_gpio == -EPROBE_DEFER || wp_gpio == -EPROBE_DEFER)
1726 return ERR_PTR(-EPROBE_DEFER);
1727
1728 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1729 if (!pdata)
1730 return NULL; /* out of memory */
1731
1732 if (of_find_property(np, "ti,dual-volt", NULL))
1733 pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1734
1735 /* This driver only supports 1 slot */
1736 pdata->nr_slots = 1;
1737 pdata->slots[0].switch_pin = cd_gpio;
1738 pdata->slots[0].gpio_wp = wp_gpio;
1739
1740 if (of_find_property(np, "ti,non-removable", NULL)) {
1741 pdata->slots[0].nonremovable = true;
1742 pdata->slots[0].no_regulator_off_init = true;
1743 }
1744 of_property_read_u32(np, "bus-width", &bus_width);
1745 if (bus_width == 4)
1746 pdata->slots[0].caps |= MMC_CAP_4_BIT_DATA;
1747 else if (bus_width == 8)
1748 pdata->slots[0].caps |= MMC_CAP_8_BIT_DATA;
1749
1750 if (of_find_property(np, "ti,needs-special-reset", NULL))
1751 pdata->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
1752
1753 if (!of_property_read_u32(np, "max-frequency", &max_freq))
1754 pdata->max_freq = max_freq;
1755
1756 if (of_find_property(np, "ti,needs-special-hs-handling", NULL))
1757 pdata->slots[0].features |= HSMMC_HAS_HSPE_SUPPORT;
1758
1759 return pdata;
1760 }
1761 #else
1762 static inline struct omap_mmc_platform_data
1763 *of_get_hsmmc_pdata(struct device *dev)
1764 {
1765 return NULL;
1766 }
1767 #endif
1768
1769 static int omap_hsmmc_probe(struct platform_device *pdev)
1770 {
1771 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1772 struct mmc_host *mmc;
1773 struct omap_hsmmc_host *host = NULL;
1774 struct resource *res;
1775 int ret, irq;
1776 const struct of_device_id *match;
1777 dma_cap_mask_t mask;
1778 unsigned tx_req, rx_req;
1779 struct pinctrl *pinctrl;
1780
1781 match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev);
1782 if (match) {
1783 pdata = of_get_hsmmc_pdata(&pdev->dev);
1784
1785 if (IS_ERR(pdata))
1786 return PTR_ERR(pdata);
1787
1788 if (match->data) {
1789 const u16 *offsetp = match->data;
1790 pdata->reg_offset = *offsetp;
1791 }
1792 }
1793
1794 if (pdata == NULL) {
1795 dev_err(&pdev->dev, "Platform Data is missing\n");
1796 return -ENXIO;
1797 }
1798
1799 if (pdata->nr_slots == 0) {
1800 dev_err(&pdev->dev, "No Slots\n");
1801 return -ENXIO;
1802 }
1803
1804 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1805 irq = platform_get_irq(pdev, 0);
1806 if (res == NULL || irq < 0)
1807 return -ENXIO;
1808
1809 res = request_mem_region(res->start, resource_size(res), pdev->name);
1810 if (res == NULL)
1811 return -EBUSY;
1812
1813 ret = omap_hsmmc_gpio_init(pdata);
1814 if (ret)
1815 goto err;
1816
1817 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
1818 if (!mmc) {
1819 ret = -ENOMEM;
1820 goto err_alloc;
1821 }
1822
1823 host = mmc_priv(mmc);
1824 host->mmc = mmc;
1825 host->pdata = pdata;
1826 host->dev = &pdev->dev;
1827 host->use_dma = 1;
1828 host->dma_ch = -1;
1829 host->irq = irq;
1830 host->slot_id = 0;
1831 host->mapbase = res->start + pdata->reg_offset;
1832 host->base = ioremap(host->mapbase, SZ_4K);
1833 host->power_mode = MMC_POWER_OFF;
1834 host->next_data.cookie = 1;
1835
1836 platform_set_drvdata(pdev, host);
1837
1838 mmc->ops = &omap_hsmmc_ops;
1839
1840 /*
1841 * If regulator_disable can only put vcc_aux to sleep then there is
1842 * no off state.
1843 */
1844 if (mmc_slot(host).vcc_aux_disable_is_sleep)
1845 mmc_slot(host).no_off = 1;
1846
1847 mmc->f_min = OMAP_MMC_MIN_CLOCK;
1848
1849 if (pdata->max_freq > 0)
1850 mmc->f_max = pdata->max_freq;
1851 else
1852 mmc->f_max = OMAP_MMC_MAX_CLOCK;
1853
1854 spin_lock_init(&host->irq_lock);
1855
1856 host->fclk = clk_get(&pdev->dev, "fck");
1857 if (IS_ERR(host->fclk)) {
1858 ret = PTR_ERR(host->fclk);
1859 host->fclk = NULL;
1860 goto err1;
1861 }
1862
1863 if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
1864 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
1865 mmc->caps2 |= MMC_CAP2_NO_MULTI_READ;
1866 }
1867
1868 pm_runtime_enable(host->dev);
1869 pm_runtime_get_sync(host->dev);
1870 pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
1871 pm_runtime_use_autosuspend(host->dev);
1872
1873 omap_hsmmc_context_save(host);
1874
1875 /* This can be removed once we support PBIAS with DT */
1876 if (host->dev->of_node && host->mapbase == 0x4809c000)
1877 host->pbias_disable = 1;
1878
1879 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1880 /*
1881 * MMC can still work without debounce clock.
1882 */
1883 if (IS_ERR(host->dbclk)) {
1884 host->dbclk = NULL;
1885 } else if (clk_prepare_enable(host->dbclk) != 0) {
1886 dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n");
1887 clk_put(host->dbclk);
1888 host->dbclk = NULL;
1889 }
1890
1891 /* Since we do only SG emulation, we can have as many segs
1892 * as we want. */
1893 mmc->max_segs = 1024;
1894
1895 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
1896 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
1897 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1898 mmc->max_seg_size = mmc->max_req_size;
1899
1900 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
1901 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
1902
1903 mmc->caps |= mmc_slot(host).caps;
1904 if (mmc->caps & MMC_CAP_8_BIT_DATA)
1905 mmc->caps |= MMC_CAP_4_BIT_DATA;
1906
1907 if (mmc_slot(host).nonremovable)
1908 mmc->caps |= MMC_CAP_NONREMOVABLE;
1909
1910 mmc->pm_caps = mmc_slot(host).pm_caps;
1911
1912 omap_hsmmc_conf_bus_power(host);
1913
1914 if (!pdev->dev.of_node) {
1915 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1916 if (!res) {
1917 dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n");
1918 ret = -ENXIO;
1919 goto err_irq;
1920 }
1921 tx_req = res->start;
1922
1923 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1924 if (!res) {
1925 dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n");
1926 ret = -ENXIO;
1927 goto err_irq;
1928 }
1929 rx_req = res->start;
1930 }
1931
1932 dma_cap_zero(mask);
1933 dma_cap_set(DMA_SLAVE, mask);
1934
1935 host->rx_chan =
1936 dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
1937 &rx_req, &pdev->dev, "rx");
1938
1939 if (!host->rx_chan) {
1940 dev_err(mmc_dev(host->mmc), "unable to obtain RX DMA engine channel %u\n", rx_req);
1941 ret = -ENXIO;
1942 goto err_irq;
1943 }
1944
1945 host->tx_chan =
1946 dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
1947 &tx_req, &pdev->dev, "tx");
1948
1949 if (!host->tx_chan) {
1950 dev_err(mmc_dev(host->mmc), "unable to obtain TX DMA engine channel %u\n", tx_req);
1951 ret = -ENXIO;
1952 goto err_irq;
1953 }
1954
1955 /* Request IRQ for MMC operations */
1956 ret = request_irq(host->irq, omap_hsmmc_irq, 0,
1957 mmc_hostname(mmc), host);
1958 if (ret) {
1959 dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1960 goto err_irq;
1961 }
1962
1963 if (pdata->init != NULL) {
1964 if (pdata->init(&pdev->dev) != 0) {
1965 dev_err(mmc_dev(host->mmc),
1966 "Unable to configure MMC IRQs\n");
1967 goto err_irq_cd_init;
1968 }
1969 }
1970
1971 if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
1972 ret = omap_hsmmc_reg_get(host);
1973 if (ret)
1974 goto err_reg;
1975 host->use_reg = 1;
1976 }
1977
1978 mmc->ocr_avail = mmc_slot(host).ocr_mask;
1979
1980 /* Request IRQ for card detect */
1981 if ((mmc_slot(host).card_detect_irq)) {
1982 ret = request_threaded_irq(mmc_slot(host).card_detect_irq,
1983 NULL,
1984 omap_hsmmc_detect,
1985 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
1986 mmc_hostname(mmc), host);
1987 if (ret) {
1988 dev_err(mmc_dev(host->mmc),
1989 "Unable to grab MMC CD IRQ\n");
1990 goto err_irq_cd;
1991 }
1992 pdata->suspend = omap_hsmmc_suspend_cdirq;
1993 pdata->resume = omap_hsmmc_resume_cdirq;
1994 }
1995
1996 omap_hsmmc_disable_irq(host);
1997
1998 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
1999 if (IS_ERR(pinctrl))
2000 dev_warn(&pdev->dev,
2001 "pins are not configured from the driver\n");
2002
2003 omap_hsmmc_protect_card(host);
2004
2005 mmc_add_host(mmc);
2006
2007 if (mmc_slot(host).name != NULL) {
2008 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2009 if (ret < 0)
2010 goto err_slot_name;
2011 }
2012 if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
2013 ret = device_create_file(&mmc->class_dev,
2014 &dev_attr_cover_switch);
2015 if (ret < 0)
2016 goto err_slot_name;
2017 }
2018
2019 omap_hsmmc_debugfs(mmc);
2020 pm_runtime_mark_last_busy(host->dev);
2021 pm_runtime_put_autosuspend(host->dev);
2022
2023 return 0;
2024
2025 err_slot_name:
2026 mmc_remove_host(mmc);
2027 free_irq(mmc_slot(host).card_detect_irq, host);
2028 err_irq_cd:
2029 if (host->use_reg)
2030 omap_hsmmc_reg_put(host);
2031 err_reg:
2032 if (host->pdata->cleanup)
2033 host->pdata->cleanup(&pdev->dev);
2034 err_irq_cd_init:
2035 free_irq(host->irq, host);
2036 err_irq:
2037 if (host->tx_chan)
2038 dma_release_channel(host->tx_chan);
2039 if (host->rx_chan)
2040 dma_release_channel(host->rx_chan);
2041 pm_runtime_put_sync(host->dev);
2042 pm_runtime_disable(host->dev);
2043 clk_put(host->fclk);
2044 if (host->dbclk) {
2045 clk_disable_unprepare(host->dbclk);
2046 clk_put(host->dbclk);
2047 }
2048 err1:
2049 iounmap(host->base);
2050 mmc_free_host(mmc);
2051 err_alloc:
2052 omap_hsmmc_gpio_free(pdata);
2053 err:
2054 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2055 if (res)
2056 release_mem_region(res->start, resource_size(res));
2057 return ret;
2058 }
2059
2060 static int omap_hsmmc_remove(struct platform_device *pdev)
2061 {
2062 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2063 struct resource *res;
2064
2065 pm_runtime_get_sync(host->dev);
2066 mmc_remove_host(host->mmc);
2067 if (host->use_reg)
2068 omap_hsmmc_reg_put(host);
2069 if (host->pdata->cleanup)
2070 host->pdata->cleanup(&pdev->dev);
2071 free_irq(host->irq, host);
2072 if (mmc_slot(host).card_detect_irq)
2073 free_irq(mmc_slot(host).card_detect_irq, host);
2074
2075 if (host->tx_chan)
2076 dma_release_channel(host->tx_chan);
2077 if (host->rx_chan)
2078 dma_release_channel(host->rx_chan);
2079
2080 pm_runtime_put_sync(host->dev);
2081 pm_runtime_disable(host->dev);
2082 clk_put(host->fclk);
2083 if (host->dbclk) {
2084 clk_disable_unprepare(host->dbclk);
2085 clk_put(host->dbclk);
2086 }
2087
2088 omap_hsmmc_gpio_free(host->pdata);
2089 iounmap(host->base);
2090 mmc_free_host(host->mmc);
2091
2092 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2093 if (res)
2094 release_mem_region(res->start, resource_size(res));
2095
2096 return 0;
2097 }
2098
2099 #ifdef CONFIG_PM
2100 static int omap_hsmmc_prepare(struct device *dev)
2101 {
2102 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2103
2104 if (host->pdata->suspend)
2105 return host->pdata->suspend(dev, host->slot_id);
2106
2107 return 0;
2108 }
2109
2110 static void omap_hsmmc_complete(struct device *dev)
2111 {
2112 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2113
2114 if (host->pdata->resume)
2115 host->pdata->resume(dev, host->slot_id);
2116
2117 }
2118
2119 static int omap_hsmmc_suspend(struct device *dev)
2120 {
2121 int ret = 0;
2122 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2123
2124 if (!host)
2125 return 0;
2126
2127 if (host && host->suspended)
2128 return 0;
2129
2130 pm_runtime_get_sync(host->dev);
2131 host->suspended = 1;
2132 ret = mmc_suspend_host(host->mmc);
2133
2134 if (ret) {
2135 host->suspended = 0;
2136 goto err;
2137 }
2138
2139 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
2140 omap_hsmmc_disable_irq(host);
2141 OMAP_HSMMC_WRITE(host->base, HCTL,
2142 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2143 }
2144
2145 if (host->dbclk)
2146 clk_disable_unprepare(host->dbclk);
2147 err:
2148 pm_runtime_put_sync(host->dev);
2149 return ret;
2150 }
2151
2152 /* Routine to resume the MMC device */
2153 static int omap_hsmmc_resume(struct device *dev)
2154 {
2155 int ret = 0;
2156 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2157
2158 if (!host)
2159 return 0;
2160
2161 if (host && !host->suspended)
2162 return 0;
2163
2164 pm_runtime_get_sync(host->dev);
2165
2166 if (host->dbclk)
2167 clk_prepare_enable(host->dbclk);
2168
2169 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
2170 omap_hsmmc_conf_bus_power(host);
2171
2172 omap_hsmmc_protect_card(host);
2173
2174 /* Notify the core to resume the host */
2175 ret = mmc_resume_host(host->mmc);
2176 if (ret == 0)
2177 host->suspended = 0;
2178
2179 pm_runtime_mark_last_busy(host->dev);
2180 pm_runtime_put_autosuspend(host->dev);
2181
2182 return ret;
2183
2184 }
2185
2186 #else
2187 #define omap_hsmmc_prepare NULL
2188 #define omap_hsmmc_complete NULL
2189 #define omap_hsmmc_suspend NULL
2190 #define omap_hsmmc_resume NULL
2191 #endif
2192
2193 static int omap_hsmmc_runtime_suspend(struct device *dev)
2194 {
2195 struct omap_hsmmc_host *host;
2196
2197 host = platform_get_drvdata(to_platform_device(dev));
2198 omap_hsmmc_context_save(host);
2199 dev_dbg(dev, "disabled\n");
2200
2201 return 0;
2202 }
2203
2204 static int omap_hsmmc_runtime_resume(struct device *dev)
2205 {
2206 struct omap_hsmmc_host *host;
2207
2208 host = platform_get_drvdata(to_platform_device(dev));
2209 omap_hsmmc_context_restore(host);
2210 dev_dbg(dev, "enabled\n");
2211
2212 return 0;
2213 }
2214
2215 static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
2216 .suspend = omap_hsmmc_suspend,
2217 .resume = omap_hsmmc_resume,
2218 .prepare = omap_hsmmc_prepare,
2219 .complete = omap_hsmmc_complete,
2220 .runtime_suspend = omap_hsmmc_runtime_suspend,
2221 .runtime_resume = omap_hsmmc_runtime_resume,
2222 };
2223
2224 static struct platform_driver omap_hsmmc_driver = {
2225 .probe = omap_hsmmc_probe,
2226 .remove = omap_hsmmc_remove,
2227 .driver = {
2228 .name = DRIVER_NAME,
2229 .owner = THIS_MODULE,
2230 .pm = &omap_hsmmc_dev_pm_ops,
2231 .of_match_table = of_match_ptr(omap_mmc_of_match),
2232 },
2233 };
2234
2235 module_platform_driver(omap_hsmmc_driver);
2236 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2237 MODULE_LICENSE("GPL");
2238 MODULE_ALIAS("platform:" DRIVER_NAME);
2239 MODULE_AUTHOR("Texas Instruments Inc");
CRIS linux kernel tree