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Linux 3.11-rc3
[cris-mirror.git] / drivers / mtd / devices / m25p80.c
blob2f3d2a5ff349a174dc0f473f07c67f477f0139c4
1 /*
2 * MTD SPI driver for ST M25Pxx (and similar) serial flash chips
3 *
4 * Author: Mike Lavender, mike@steroidmicros.com
5 *
6 * Copyright (c) 2005, Intec Automation Inc.
7 *
8 * Some parts are based on lart.c by Abraham Van Der Merwe
9 *
10 * Cleaned up and generalized based on mtd_dataflash.c
11 *
12 * This code is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 *
16 */
17
18 #include <linux/init.h>
19 #include <linux/err.h>
20 #include <linux/errno.h>
21 #include <linux/module.h>
22 #include <linux/device.h>
23 #include <linux/interrupt.h>
24 #include <linux/mutex.h>
25 #include <linux/math64.h>
26 #include <linux/slab.h>
27 #include <linux/sched.h>
28 #include <linux/mod_devicetable.h>
29
30 #include <linux/mtd/cfi.h>
31 #include <linux/mtd/mtd.h>
32 #include <linux/mtd/partitions.h>
33 #include <linux/of_platform.h>
34
35 #include <linux/spi/spi.h>
36 #include <linux/spi/flash.h>
37
38 /* Flash opcodes. */
39 #define OPCODE_WREN 0x06 /* Write enable */
40 #define OPCODE_RDSR 0x05 /* Read status register */
41 #define OPCODE_WRSR 0x01 /* Write status register 1 byte */
42 #define OPCODE_NORM_READ 0x03 /* Read data bytes (low frequency) */
43 #define OPCODE_FAST_READ 0x0b /* Read data bytes (high frequency) */
44 #define OPCODE_PP 0x02 /* Page program (up to 256 bytes) */
45 #define OPCODE_BE_4K 0x20 /* Erase 4KiB block */
46 #define OPCODE_BE_32K 0x52 /* Erase 32KiB block */
47 #define OPCODE_CHIP_ERASE 0xc7 /* Erase whole flash chip */
48 #define OPCODE_SE 0xd8 /* Sector erase (usually 64KiB) */
49 #define OPCODE_RDID 0x9f /* Read JEDEC ID */
50
51 /* Used for SST flashes only. */
52 #define OPCODE_BP 0x02 /* Byte program */
53 #define OPCODE_WRDI 0x04 /* Write disable */
54 #define OPCODE_AAI_WP 0xad /* Auto address increment word program */
55
56 /* Used for Macronix flashes only. */
57 #define OPCODE_EN4B 0xb7 /* Enter 4-byte mode */
58 #define OPCODE_EX4B 0xe9 /* Exit 4-byte mode */
59
60 /* Used for Spansion flashes only. */
61 #define OPCODE_BRWR 0x17 /* Bank register write */
62
63 /* Status Register bits. */
64 #define SR_WIP 1 /* Write in progress */
65 #define SR_WEL 2 /* Write enable latch */
66 /* meaning of other SR_* bits may differ between vendors */
67 #define SR_BP0 4 /* Block protect 0 */
68 #define SR_BP1 8 /* Block protect 1 */
69 #define SR_BP2 0x10 /* Block protect 2 */
70 #define SR_SRWD 0x80 /* SR write protect */
71
72 /* Define max times to check status register before we give up. */
73 #define MAX_READY_WAIT_JIFFIES (40 * HZ) /* M25P16 specs 40s max chip erase */
74 #define MAX_CMD_SIZE 5
75
76 #define JEDEC_MFR(_jedec_id) ((_jedec_id) >> 16)
77
78 /****************************************************************************/
79
80 struct m25p {
81 struct spi_device *spi;
82 struct mutex lock;
83 struct mtd_info mtd;
84 u16 page_size;
85 u16 addr_width;
86 u8 erase_opcode;
87 u8 *command;
88 bool fast_read;
89 };
90
91 static inline struct m25p *mtd_to_m25p(struct mtd_info *mtd)
92 {
93 return container_of(mtd, struct m25p, mtd);
94 }
95
96 /****************************************************************************/
97
98 /*
99 * Internal helper functions
100 */
101
102 /*
103 * Read the status register, returning its value in the location
104 * Return the status register value.
105 * Returns negative if error occurred.
106 */
107 static int read_sr(struct m25p *flash)
108 {
109 ssize_t retval;
110 u8 code = OPCODE_RDSR;
111 u8 val;
112
113 retval = spi_write_then_read(flash->spi, &code, 1, &val, 1);
114
115 if (retval < 0) {
116 dev_err(&flash->spi->dev, "error %d reading SR\n",
117 (int) retval);
118 return retval;
119 }
120
121 return val;
122 }
123
124 /*
125 * Write status register 1 byte
126 * Returns negative if error occurred.
127 */
128 static int write_sr(struct m25p *flash, u8 val)
129 {
130 flash->command[0] = OPCODE_WRSR;
131 flash->command[1] = val;
132
133 return spi_write(flash->spi, flash->command, 2);
134 }
135
136 /*
137 * Set write enable latch with Write Enable command.
138 * Returns negative if error occurred.
139 */
140 static inline int write_enable(struct m25p *flash)
141 {
142 u8 code = OPCODE_WREN;
143
144 return spi_write_then_read(flash->spi, &code, 1, NULL, 0);
145 }
146
147 /*
148 * Send write disble instruction to the chip.
149 */
150 static inline int write_disable(struct m25p *flash)
151 {
152 u8 code = OPCODE_WRDI;
153
154 return spi_write_then_read(flash->spi, &code, 1, NULL, 0);
155 }
156
157 /*
158 * Enable/disable 4-byte addressing mode.
159 */
160 static inline int set_4byte(struct m25p *flash, u32 jedec_id, int enable)
161 {
162 switch (JEDEC_MFR(jedec_id)) {
163 case CFI_MFR_MACRONIX:
164 case 0xEF /* winbond */:
165 flash->command[0] = enable ? OPCODE_EN4B : OPCODE_EX4B;
166 return spi_write(flash->spi, flash->command, 1);
167 default:
168 /* Spansion style */
169 flash->command[0] = OPCODE_BRWR;
170 flash->command[1] = enable << 7;
171 return spi_write(flash->spi, flash->command, 2);
172 }
173 }
174
175 /*
176 * Service routine to read status register until ready, or timeout occurs.
177 * Returns non-zero if error.
178 */
179 static int wait_till_ready(struct m25p *flash)
180 {
181 unsigned long deadline;
182 int sr;
183
184 deadline = jiffies + MAX_READY_WAIT_JIFFIES;
185
186 do {
187 if ((sr = read_sr(flash)) < 0)
188 break;
189 else if (!(sr & SR_WIP))
190 return 0;
191
192 cond_resched();
193
194 } while (!time_after_eq(jiffies, deadline));
195
196 return 1;
197 }
198
199 /*
200 * Erase the whole flash memory
201 *
202 * Returns 0 if successful, non-zero otherwise.
203 */
204 static int erase_chip(struct m25p *flash)
205 {
206 pr_debug("%s: %s %lldKiB\n", dev_name(&flash->spi->dev), __func__,
207 (long long)(flash->mtd.size >> 10));
208
209 /* Wait until finished previous write command. */
210 if (wait_till_ready(flash))
211 return 1;
212
213 /* Send write enable, then erase commands. */
214 write_enable(flash);
215
216 /* Set up command buffer. */
217 flash->command[0] = OPCODE_CHIP_ERASE;
218
219 spi_write(flash->spi, flash->command, 1);
220
221 return 0;
222 }
223
224 static void m25p_addr2cmd(struct m25p *flash, unsigned int addr, u8 *cmd)
225 {
226 /* opcode is in cmd[0] */
227 cmd[1] = addr >> (flash->addr_width * 8 - 8);
228 cmd[2] = addr >> (flash->addr_width * 8 - 16);
229 cmd[3] = addr >> (flash->addr_width * 8 - 24);
230 cmd[4] = addr >> (flash->addr_width * 8 - 32);
231 }
232
233 static int m25p_cmdsz(struct m25p *flash)
234 {
235 return 1 + flash->addr_width;
236 }
237
238 /*
239 * Erase one sector of flash memory at offset ``offset'' which is any
240 * address within the sector which should be erased.
241 *
242 * Returns 0 if successful, non-zero otherwise.
243 */
244 static int erase_sector(struct m25p *flash, u32 offset)
245 {
246 pr_debug("%s: %s %dKiB at 0x%08x\n", dev_name(&flash->spi->dev),
247 __func__, flash->mtd.erasesize / 1024, offset);
248
249 /* Wait until finished previous write command. */
250 if (wait_till_ready(flash))
251 return 1;
252
253 /* Send write enable, then erase commands. */
254 write_enable(flash);
255
256 /* Set up command buffer. */
257 flash->command[0] = flash->erase_opcode;
258 m25p_addr2cmd(flash, offset, flash->command);
259
260 spi_write(flash->spi, flash->command, m25p_cmdsz(flash));
261
262 return 0;
263 }
264
265 /****************************************************************************/
266
267 /*
268 * MTD implementation
269 */
270
271 /*
272 * Erase an address range on the flash chip. The address range may extend
273 * one or more erase sectors. Return an error is there is a problem erasing.
274 */
275 static int m25p80_erase(struct mtd_info *mtd, struct erase_info *instr)
276 {
277 struct m25p *flash = mtd_to_m25p(mtd);
278 u32 addr,len;
279 uint32_t rem;
280
281 pr_debug("%s: %s at 0x%llx, len %lld\n", dev_name(&flash->spi->dev),
282 __func__, (long long)instr->addr,
283 (long long)instr->len);
284
285 div_u64_rem(instr->len, mtd->erasesize, &rem);
286 if (rem)
287 return -EINVAL;
288
289 addr = instr->addr;
290 len = instr->len;
291
292 mutex_lock(&flash->lock);
293
294 /* whole-chip erase? */
295 if (len == flash->mtd.size) {
296 if (erase_chip(flash)) {
297 instr->state = MTD_ERASE_FAILED;
298 mutex_unlock(&flash->lock);
299 return -EIO;
300 }
301
302 /* REVISIT in some cases we could speed up erasing large regions
303 * by using OPCODE_SE instead of OPCODE_BE_4K. We may have set up
304 * to use "small sector erase", but that's not always optimal.
305 */
306
307 /* "sector"-at-a-time erase */
308 } else {
309 while (len) {
310 if (erase_sector(flash, addr)) {
311 instr->state = MTD_ERASE_FAILED;
312 mutex_unlock(&flash->lock);
313 return -EIO;
314 }
315
316 addr += mtd->erasesize;
317 len -= mtd->erasesize;
318 }
319 }
320
321 mutex_unlock(&flash->lock);
322
323 instr->state = MTD_ERASE_DONE;
324 mtd_erase_callback(instr);
325
326 return 0;
327 }
328
329 /*
330 * Read an address range from the flash chip. The address range
331 * may be any size provided it is within the physical boundaries.
332 */
333 static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len,
334 size_t *retlen, u_char *buf)
335 {
336 struct m25p *flash = mtd_to_m25p(mtd);
337 struct spi_transfer t[2];
338 struct spi_message m;
339 uint8_t opcode;
340
341 pr_debug("%s: %s from 0x%08x, len %zd\n", dev_name(&flash->spi->dev),
342 __func__, (u32)from, len);
343
344 spi_message_init(&m);
345 memset(t, 0, (sizeof t));
346
347 /* NOTE:
348 * OPCODE_FAST_READ (if available) is faster.
349 * Should add 1 byte DUMMY_BYTE.
350 */
351 t[0].tx_buf = flash->command;
352 t[0].len = m25p_cmdsz(flash) + (flash->fast_read ? 1 : 0);
353 spi_message_add_tail(&t[0], &m);
354
355 t[1].rx_buf = buf;
356 t[1].len = len;
357 spi_message_add_tail(&t[1], &m);
358
359 mutex_lock(&flash->lock);
360
361 /* Wait till previous write/erase is done. */
362 if (wait_till_ready(flash)) {
363 /* REVISIT status return?? */
364 mutex_unlock(&flash->lock);
365 return 1;
366 }
367
368 /* FIXME switch to OPCODE_FAST_READ. It's required for higher
369 * clocks; and at this writing, every chip this driver handles
370 * supports that opcode.
371 */
372
373 /* Set up the write data buffer. */
374 opcode = flash->fast_read ? OPCODE_FAST_READ : OPCODE_NORM_READ;
375 flash->command[0] = opcode;
376 m25p_addr2cmd(flash, from, flash->command);
377
378 spi_sync(flash->spi, &m);
379
380 *retlen = m.actual_length - m25p_cmdsz(flash) -
381 (flash->fast_read ? 1 : 0);
382
383 mutex_unlock(&flash->lock);
384
385 return 0;
386 }
387
388 /*
389 * Write an address range to the flash chip. Data must be written in
390 * FLASH_PAGESIZE chunks. The address range may be any size provided
391 * it is within the physical boundaries.
392 */
393 static int m25p80_write(struct mtd_info *mtd, loff_t to, size_t len,
394 size_t *retlen, const u_char *buf)
395 {
396 struct m25p *flash = mtd_to_m25p(mtd);
397 u32 page_offset, page_size;
398 struct spi_transfer t[2];
399 struct spi_message m;
400
401 pr_debug("%s: %s to 0x%08x, len %zd\n", dev_name(&flash->spi->dev),
402 __func__, (u32)to, len);
403
404 spi_message_init(&m);
405 memset(t, 0, (sizeof t));
406
407 t[0].tx_buf = flash->command;
408 t[0].len = m25p_cmdsz(flash);
409 spi_message_add_tail(&t[0], &m);
410
411 t[1].tx_buf = buf;
412 spi_message_add_tail(&t[1], &m);
413
414 mutex_lock(&flash->lock);
415
416 /* Wait until finished previous write command. */
417 if (wait_till_ready(flash)) {
418 mutex_unlock(&flash->lock);
419 return 1;
420 }
421
422 write_enable(flash);
423
424 /* Set up the opcode in the write buffer. */
425 flash->command[0] = OPCODE_PP;
426 m25p_addr2cmd(flash, to, flash->command);
427
428 page_offset = to & (flash->page_size - 1);
429
430 /* do all the bytes fit onto one page? */
431 if (page_offset + len <= flash->page_size) {
432 t[1].len = len;
433
434 spi_sync(flash->spi, &m);
435
436 *retlen = m.actual_length - m25p_cmdsz(flash);
437 } else {
438 u32 i;
439
440 /* the size of data remaining on the first page */
441 page_size = flash->page_size - page_offset;
442
443 t[1].len = page_size;
444 spi_sync(flash->spi, &m);
445
446 *retlen = m.actual_length - m25p_cmdsz(flash);
447
448 /* write everything in flash->page_size chunks */
449 for (i = page_size; i < len; i += page_size) {
450 page_size = len - i;
451 if (page_size > flash->page_size)
452 page_size = flash->page_size;
453
454 /* write the next page to flash */
455 m25p_addr2cmd(flash, to + i, flash->command);
456
457 t[1].tx_buf = buf + i;
458 t[1].len = page_size;
459
460 wait_till_ready(flash);
461
462 write_enable(flash);
463
464 spi_sync(flash->spi, &m);
465
466 *retlen += m.actual_length - m25p_cmdsz(flash);
467 }
468 }
469
470 mutex_unlock(&flash->lock);
471
472 return 0;
473 }
474
475 static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
476 size_t *retlen, const u_char *buf)
477 {
478 struct m25p *flash = mtd_to_m25p(mtd);
479 struct spi_transfer t[2];
480 struct spi_message m;
481 size_t actual;
482 int cmd_sz, ret;
483
484 pr_debug("%s: %s to 0x%08x, len %zd\n", dev_name(&flash->spi->dev),
485 __func__, (u32)to, len);
486
487 spi_message_init(&m);
488 memset(t, 0, (sizeof t));
489
490 t[0].tx_buf = flash->command;
491 t[0].len = m25p_cmdsz(flash);
492 spi_message_add_tail(&t[0], &m);
493
494 t[1].tx_buf = buf;
495 spi_message_add_tail(&t[1], &m);
496
497 mutex_lock(&flash->lock);
498
499 /* Wait until finished previous write command. */
500 ret = wait_till_ready(flash);
501 if (ret)
502 goto time_out;
503
504 write_enable(flash);
505
506 actual = to % 2;
507 /* Start write from odd address. */
508 if (actual) {
509 flash->command[0] = OPCODE_BP;
510 m25p_addr2cmd(flash, to, flash->command);
511
512 /* write one byte. */
513 t[1].len = 1;
514 spi_sync(flash->spi, &m);
515 ret = wait_till_ready(flash);
516 if (ret)
517 goto time_out;
518 *retlen += m.actual_length - m25p_cmdsz(flash);
519 }
520 to += actual;
521
522 flash->command[0] = OPCODE_AAI_WP;
523 m25p_addr2cmd(flash, to, flash->command);
524
525 /* Write out most of the data here. */
526 cmd_sz = m25p_cmdsz(flash);
527 for (; actual < len - 1; actual += 2) {
528 t[0].len = cmd_sz;
529 /* write two bytes. */
530 t[1].len = 2;
531 t[1].tx_buf = buf + actual;
532
533 spi_sync(flash->spi, &m);
534 ret = wait_till_ready(flash);
535 if (ret)
536 goto time_out;
537 *retlen += m.actual_length - cmd_sz;
538 cmd_sz = 1;
539 to += 2;
540 }
541 write_disable(flash);
542 ret = wait_till_ready(flash);
543 if (ret)
544 goto time_out;
545
546 /* Write out trailing byte if it exists. */
547 if (actual != len) {
548 write_enable(flash);
549 flash->command[0] = OPCODE_BP;
550 m25p_addr2cmd(flash, to, flash->command);
551 t[0].len = m25p_cmdsz(flash);
552 t[1].len = 1;
553 t[1].tx_buf = buf + actual;
554
555 spi_sync(flash->spi, &m);
556 ret = wait_till_ready(flash);
557 if (ret)
558 goto time_out;
559 *retlen += m.actual_length - m25p_cmdsz(flash);
560 write_disable(flash);
561 }
562
563 time_out:
564 mutex_unlock(&flash->lock);
565 return ret;
566 }
567
568 static int m25p80_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
569 {
570 struct m25p *flash = mtd_to_m25p(mtd);
571 uint32_t offset = ofs;
572 uint8_t status_old, status_new;
573 int res = 0;
574
575 mutex_lock(&flash->lock);
576 /* Wait until finished previous command */
577 if (wait_till_ready(flash)) {
578 res = 1;
579 goto err;
580 }
581
582 status_old = read_sr(flash);
583
584 if (offset < flash->mtd.size-(flash->mtd.size/2))
585 status_new = status_old | SR_BP2 | SR_BP1 | SR_BP0;
586 else if (offset < flash->mtd.size-(flash->mtd.size/4))
587 status_new = (status_old & ~SR_BP0) | SR_BP2 | SR_BP1;
588 else if (offset < flash->mtd.size-(flash->mtd.size/8))
589 status_new = (status_old & ~SR_BP1) | SR_BP2 | SR_BP0;
590 else if (offset < flash->mtd.size-(flash->mtd.size/16))
591 status_new = (status_old & ~(SR_BP0|SR_BP1)) | SR_BP2;
592 else if (offset < flash->mtd.size-(flash->mtd.size/32))
593 status_new = (status_old & ~SR_BP2) | SR_BP1 | SR_BP0;
594 else if (offset < flash->mtd.size-(flash->mtd.size/64))
595 status_new = (status_old & ~(SR_BP2|SR_BP0)) | SR_BP1;
596 else
597 status_new = (status_old & ~(SR_BP2|SR_BP1)) | SR_BP0;
598
599 /* Only modify protection if it will not unlock other areas */
600 if ((status_new&(SR_BP2|SR_BP1|SR_BP0)) >
601 (status_old&(SR_BP2|SR_BP1|SR_BP0))) {
602 write_enable(flash);
603 if (write_sr(flash, status_new) < 0) {
604 res = 1;
605 goto err;
606 }
607 }
608
609 err: mutex_unlock(&flash->lock);
610 return res;
611 }
612
613 static int m25p80_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
614 {
615 struct m25p *flash = mtd_to_m25p(mtd);
616 uint32_t offset = ofs;
617 uint8_t status_old, status_new;
618 int res = 0;
619
620 mutex_lock(&flash->lock);
621 /* Wait until finished previous command */
622 if (wait_till_ready(flash)) {
623 res = 1;
624 goto err;
625 }
626
627 status_old = read_sr(flash);
628
629 if (offset+len > flash->mtd.size-(flash->mtd.size/64))
630 status_new = status_old & ~(SR_BP2|SR_BP1|SR_BP0);
631 else if (offset+len > flash->mtd.size-(flash->mtd.size/32))
632 status_new = (status_old & ~(SR_BP2|SR_BP1)) | SR_BP0;
633 else if (offset+len > flash->mtd.size-(flash->mtd.size/16))
634 status_new = (status_old & ~(SR_BP2|SR_BP0)) | SR_BP1;
635 else if (offset+len > flash->mtd.size-(flash->mtd.size/8))
636 status_new = (status_old & ~SR_BP2) | SR_BP1 | SR_BP0;
637 else if (offset+len > flash->mtd.size-(flash->mtd.size/4))
638 status_new = (status_old & ~(SR_BP0|SR_BP1)) | SR_BP2;
639 else if (offset+len > flash->mtd.size-(flash->mtd.size/2))
640 status_new = (status_old & ~SR_BP1) | SR_BP2 | SR_BP0;
641 else
642 status_new = (status_old & ~SR_BP0) | SR_BP2 | SR_BP1;
643
644 /* Only modify protection if it will not lock other areas */
645 if ((status_new&(SR_BP2|SR_BP1|SR_BP0)) <
646 (status_old&(SR_BP2|SR_BP1|SR_BP0))) {
647 write_enable(flash);
648 if (write_sr(flash, status_new) < 0) {
649 res = 1;
650 goto err;
651 }
652 }
653
654 err: mutex_unlock(&flash->lock);
655 return res;
656 }
657
658 /****************************************************************************/
659
660 /*
661 * SPI device driver setup and teardown
662 */
663
664 struct flash_info {
665 /* JEDEC id zero means "no ID" (most older chips); otherwise it has
666 * a high byte of zero plus three data bytes: the manufacturer id,
667 * then a two byte device id.
668 */
669 u32 jedec_id;
670 u16 ext_id;
671
672 /* The size listed here is what works with OPCODE_SE, which isn't
673 * necessarily called a "sector" by the vendor.
674 */
675 unsigned sector_size;
676 u16 n_sectors;
677
678 u16 page_size;
679 u16 addr_width;
680
681 u16 flags;
682 #define SECT_4K 0x01 /* OPCODE_BE_4K works uniformly */
683 #define M25P_NO_ERASE 0x02 /* No erase command needed */
684 #define SST_WRITE 0x04 /* use SST byte programming */
685 };
686
687 #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
688 ((kernel_ulong_t)&(struct flash_info) { \
689 .jedec_id = (_jedec_id), \
690 .ext_id = (_ext_id), \
691 .sector_size = (_sector_size), \
692 .n_sectors = (_n_sectors), \
693 .page_size = 256, \
694 .flags = (_flags), \
695 })
696
697 #define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width) \
698 ((kernel_ulong_t)&(struct flash_info) { \
699 .sector_size = (_sector_size), \
700 .n_sectors = (_n_sectors), \
701 .page_size = (_page_size), \
702 .addr_width = (_addr_width), \
703 .flags = M25P_NO_ERASE, \
704 })
705
706 /* NOTE: double check command sets and memory organization when you add
707 * more flash chips. This current list focusses on newer chips, which
708 * have been converging on command sets which including JEDEC ID.
709 */
710 static const struct spi_device_id m25p_ids[] = {
711 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
712 { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) },
713 { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) },
714
715 { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K) },
716 { "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) },
717 { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) },
718
719 { "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K) },
720 { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) },
721 { "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K) },
722 { "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
723
724 { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) },
725
726 /* EON -- en25xxx */
727 { "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) },
728 { "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) },
729 { "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) },
730 { "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) },
731 { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
732 { "en25qh256", INFO(0x1c7019, 0, 64 * 1024, 512, 0) },
733
734 /* Everspin */
735 { "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2) },
736
737 /* GigaDevice */
738 { "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64, SECT_4K) },
739 { "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128, SECT_4K) },
740
741 /* Intel/Numonyx -- xxxs33b */
742 { "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
743 { "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) },
744 { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) },
745
746 /* Macronix */
747 { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) },
748 { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) },
749 { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) },
750 { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) },
751 { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, 0) },
752 { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, 0) },
753 { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
754 { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
755 { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 0) },
756 { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
757 { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, 0) },
758
759 /* Micron */
760 { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, 0) },
761 { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, 0) },
762 { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, 0) },
763 { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K) },
764
765 /* Spansion -- single (large) sector size only, at least
766 * for the chips listed here (without boot sectors).
767 */
768 { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, 0) },
769 { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, 0) },
770 { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) },
771 { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, 0) },
772 { "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, 0) },
773 { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
774 { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
775 { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
776 { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, 0) },
777 { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, 0) },
778 { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
779 { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },
780 { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) },
781 { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) },
782 { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) },
783 { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K) },
784 { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
785
786 /* SST -- large erase sizes are "overlays", "sectors" are 4K */
787 { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
788 { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
789 { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K | SST_WRITE) },
790 { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K | SST_WRITE) },
791 { "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128, SECT_4K) },
792 { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) },
793 { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) },
794 { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) },
795 { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
796
797 /* ST Microelectronics -- newer production may have feature updates */
798 { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) },
799 { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) },
800 { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) },
801 { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) },
802 { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) },
803 { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) },
804 { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) },
805 { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) },
806 { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) },
807 { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, 0) },
808
809 { "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2, 0) },
810 { "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4, 0) },
811 { "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4, 0) },
812 { "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8, 0) },
813 { "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16, 0) },
814 { "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32, 0) },
815 { "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64, 0) },
816 { "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128, 0) },
817 { "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64, 0) },
818
819 { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2, 0) },
820 { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16, 0) },
821 { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32, 0) },
822
823 { "m25pe20", INFO(0x208012, 0, 64 * 1024, 4, 0) },
824 { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16, 0) },
825 { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) },
826
827 { "m25px32", INFO(0x207116, 0, 64 * 1024, 64, SECT_4K) },
828 { "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64, SECT_4K) },
829 { "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64, SECT_4K) },
830 { "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) },
831
832 /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
833 { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) },
834 { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) },
835 { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) },
836 { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) },
837 { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) },
838 { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) },
839 { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) },
840 { "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64, SECT_4K) },
841 { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
842 { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
843 { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) },
844 { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
845 { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
846 { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K) },
847
848 /* Catalyst / On Semiconductor -- non-JEDEC */
849 { "cat25c11", CAT25_INFO( 16, 8, 16, 1) },
850 { "cat25c03", CAT25_INFO( 32, 8, 16, 2) },
851 { "cat25c09", CAT25_INFO( 128, 8, 32, 2) },
852 { "cat25c17", CAT25_INFO( 256, 8, 32, 2) },
853 { "cat25128", CAT25_INFO(2048, 8, 64, 2) },
854 { },
855 };
856 MODULE_DEVICE_TABLE(spi, m25p_ids);
857
858 static const struct spi_device_id *jedec_probe(struct spi_device *spi)
859 {
860 int tmp;
861 u8 code = OPCODE_RDID;
862 u8 id[5];
863 u32 jedec;
864 u16 ext_jedec;
865 struct flash_info *info;
866
867 /* JEDEC also defines an optional "extended device information"
868 * string for after vendor-specific data, after the three bytes
869 * we use here. Supporting some chips might require using it.
870 */
871 tmp = spi_write_then_read(spi, &code, 1, id, 5);
872 if (tmp < 0) {
873 pr_debug("%s: error %d reading JEDEC ID\n",
874 dev_name(&spi->dev), tmp);
875 return ERR_PTR(tmp);
876 }
877 jedec = id[0];
878 jedec = jedec << 8;
879 jedec |= id[1];
880 jedec = jedec << 8;
881 jedec |= id[2];
882
883 ext_jedec = id[3] << 8 | id[4];
884
885 for (tmp = 0; tmp < ARRAY_SIZE(m25p_ids) - 1; tmp++) {
886 info = (void *)m25p_ids[tmp].driver_data;
887 if (info->jedec_id == jedec) {
888 if (info->ext_id != 0 && info->ext_id != ext_jedec)
889 continue;
890 return &m25p_ids[tmp];
891 }
892 }
893 dev_err(&spi->dev, "unrecognized JEDEC id %06x\n", jedec);
894 return ERR_PTR(-ENODEV);
895 }
896
897
898 /*
899 * board specific setup should have ensured the SPI clock used here
900 * matches what the READ command supports, at least until this driver
901 * understands FAST_READ (for clocks over 25 MHz).
902 */
903 static int m25p_probe(struct spi_device *spi)
904 {
905 const struct spi_device_id *id = spi_get_device_id(spi);
906 struct flash_platform_data *data;
907 struct m25p *flash;
908 struct flash_info *info;
909 unsigned i;
910 struct mtd_part_parser_data ppdata;
911 struct device_node __maybe_unused *np = spi->dev.of_node;
912
913 #ifdef CONFIG_MTD_OF_PARTS
914 if (!of_device_is_available(np))
915 return -ENODEV;
916 #endif
917
918 /* Platform data helps sort out which chip type we have, as
919 * well as how this board partitions it. If we don't have
920 * a chip ID, try the JEDEC id commands; they'll work for most
921 * newer chips, even if we don't recognize the particular chip.
922 */
923 data = spi->dev.platform_data;
924 if (data && data->type) {
925 const struct spi_device_id *plat_id;
926
927 for (i = 0; i < ARRAY_SIZE(m25p_ids) - 1; i++) {
928 plat_id = &m25p_ids[i];
929 if (strcmp(data->type, plat_id->name))
930 continue;
931 break;
932 }
933
934 if (i < ARRAY_SIZE(m25p_ids) - 1)
935 id = plat_id;
936 else
937 dev_warn(&spi->dev, "unrecognized id %s\n", data->type);
938 }
939
940 info = (void *)id->driver_data;
941
942 if (info->jedec_id) {
943 const struct spi_device_id *jid;
944
945 jid = jedec_probe(spi);
946 if (IS_ERR(jid)) {
947 return PTR_ERR(jid);
948 } else if (jid != id) {
949 /*
950 * JEDEC knows better, so overwrite platform ID. We
951 * can't trust partitions any longer, but we'll let
952 * mtd apply them anyway, since some partitions may be
953 * marked read-only, and we don't want to lose that
954 * information, even if it's not 100% accurate.
955 */
956 dev_warn(&spi->dev, "found %s, expected %s\n",
957 jid->name, id->name);
958 id = jid;
959 info = (void *)jid->driver_data;
960 }
961 }
962
963 flash = kzalloc(sizeof *flash, GFP_KERNEL);
964 if (!flash)
965 return -ENOMEM;
966 flash->command = kmalloc(MAX_CMD_SIZE + (flash->fast_read ? 1 : 0),
967 GFP_KERNEL);
968 if (!flash->command) {
969 kfree(flash);
970 return -ENOMEM;
971 }
972
973 flash->spi = spi;
974 mutex_init(&flash->lock);
975 dev_set_drvdata(&spi->dev, flash);
976
977 /*
978 * Atmel, SST and Intel/Numonyx serial flash tend to power
979 * up with the software protection bits set
980 */
981
982 if (JEDEC_MFR(info->jedec_id) == CFI_MFR_ATMEL ||
983 JEDEC_MFR(info->jedec_id) == CFI_MFR_INTEL ||
984 JEDEC_MFR(info->jedec_id) == CFI_MFR_SST) {
985 write_enable(flash);
986 write_sr(flash, 0);
987 }
988
989 if (data && data->name)
990 flash->mtd.name = data->name;
991 else
992 flash->mtd.name = dev_name(&spi->dev);
993
994 flash->mtd.type = MTD_NORFLASH;
995 flash->mtd.writesize = 1;
996 flash->mtd.flags = MTD_CAP_NORFLASH;
997 flash->mtd.size = info->sector_size * info->n_sectors;
998 flash->mtd._erase = m25p80_erase;
999 flash->mtd._read = m25p80_read;
1000
1001 /* flash protection support for STmicro chips */
1002 if (JEDEC_MFR(info->jedec_id) == CFI_MFR_ST) {
1003 flash->mtd._lock = m25p80_lock;
1004 flash->mtd._unlock = m25p80_unlock;
1005 }
1006
1007 /* sst flash chips use AAI word program */
1008 if (info->flags & SST_WRITE)
1009 flash->mtd._write = sst_write;
1010 else
1011 flash->mtd._write = m25p80_write;
1012
1013 /* prefer "small sector" erase if possible */
1014 if (info->flags & SECT_4K) {
1015 flash->erase_opcode = OPCODE_BE_4K;
1016 flash->mtd.erasesize = 4096;
1017 } else {
1018 flash->erase_opcode = OPCODE_SE;
1019 flash->mtd.erasesize = info->sector_size;
1020 }
1021
1022 if (info->flags & M25P_NO_ERASE)
1023 flash->mtd.flags |= MTD_NO_ERASE;
1024
1025 ppdata.of_node = spi->dev.of_node;
1026 flash->mtd.dev.parent = &spi->dev;
1027 flash->page_size = info->page_size;
1028 flash->mtd.writebufsize = flash->page_size;
1029
1030 flash->fast_read = false;
1031 #ifdef CONFIG_OF
1032 if (np && of_property_read_bool(np, "m25p,fast-read"))
1033 flash->fast_read = true;
1034 #endif
1035
1036 #ifdef CONFIG_M25PXX_USE_FAST_READ
1037 flash->fast_read = true;
1038 #endif
1039
1040 if (info->addr_width)
1041 flash->addr_width = info->addr_width;
1042 else {
1043 /* enable 4-byte addressing if the device exceeds 16MiB */
1044 if (flash->mtd.size > 0x1000000) {
1045 flash->addr_width = 4;
1046 set_4byte(flash, info->jedec_id, 1);
1047 } else
1048 flash->addr_width = 3;
1049 }
1050
1051 dev_info(&spi->dev, "%s (%lld Kbytes)\n", id->name,
1052 (long long)flash->mtd.size >> 10);
1053
1054 pr_debug("mtd .name = %s, .size = 0x%llx (%lldMiB) "
1055 ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n",
1056 flash->mtd.name,
1057 (long long)flash->mtd.size, (long long)(flash->mtd.size >> 20),
1058 flash->mtd.erasesize, flash->mtd.erasesize / 1024,
1059 flash->mtd.numeraseregions);
1060
1061 if (flash->mtd.numeraseregions)
1062 for (i = 0; i < flash->mtd.numeraseregions; i++)
1063 pr_debug("mtd.eraseregions[%d] = { .offset = 0x%llx, "
1064 ".erasesize = 0x%.8x (%uKiB), "
1065 ".numblocks = %d }\n",
1066 i, (long long)flash->mtd.eraseregions[i].offset,
1067 flash->mtd.eraseregions[i].erasesize,
1068 flash->mtd.eraseregions[i].erasesize / 1024,
1069 flash->mtd.eraseregions[i].numblocks);
1070
1071
1072 /* partitions should match sector boundaries; and it may be good to
1073 * use readonly partitions for writeprotected sectors (BP2..BP0).
1074 */
1075 return mtd_device_parse_register(&flash->mtd, NULL, &ppdata,
1076 data ? data->parts : NULL,
1077 data ? data->nr_parts : 0);
1078 }
1079
1080
1081 static int m25p_remove(struct spi_device *spi)
1082 {
1083 struct m25p *flash = dev_get_drvdata(&spi->dev);
1084 int status;
1085
1086 /* Clean up MTD stuff. */
1087 status = mtd_device_unregister(&flash->mtd);
1088 if (status == 0) {
1089 kfree(flash->command);
1090 kfree(flash);
1091 }
1092 return 0;
1093 }
1094
1095
1096 static struct spi_driver m25p80_driver = {
1097 .driver = {
1098 .name = "m25p80",
1099 .owner = THIS_MODULE,
1100 },
1101 .id_table = m25p_ids,
1102 .probe = m25p_probe,
1103 .remove = m25p_remove,
1104
1105 /* REVISIT: many of these chips have deep power-down modes, which
1106 * should clearly be entered on suspend() to minimize power use.
1107 * And also when they're otherwise idle...
1108 */
1109 };
1110
1111 module_spi_driver(m25p80_driver);
1112
1113 MODULE_LICENSE("GPL");
1114 MODULE_AUTHOR("Mike Lavender");
1115 MODULE_DESCRIPTION("MTD SPI driver for ST M25Pxx flash chips");
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