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Linux 3.11-rc3
[cris-mirror.git] / drivers / mtd / nand / denali.c
blob0c8bb6bf8424732b068f17f4793c3a957e86031a
1 /*
2 * NAND Flash Controller Device Driver
3 * Copyright © 2009-2010, Intel Corporation and its suppliers.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 *
18 */
19 #include <linux/interrupt.h>
20 #include <linux/delay.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/wait.h>
23 #include <linux/mutex.h>
24 #include <linux/slab.h>
25 #include <linux/mtd/mtd.h>
26 #include <linux/module.h>
27
28 #include "denali.h"
29
30 MODULE_LICENSE("GPL");
31
32 /* We define a module parameter that allows the user to override
33 * the hardware and decide what timing mode should be used.
34 */
35 #define NAND_DEFAULT_TIMINGS -1
36
37 static int onfi_timing_mode = NAND_DEFAULT_TIMINGS;
38 module_param(onfi_timing_mode, int, S_IRUGO);
39 MODULE_PARM_DESC(onfi_timing_mode, "Overrides default ONFI setting."
40 " -1 indicates use default timings");
41
42 #define DENALI_NAND_NAME "denali-nand"
43
44 /* We define a macro here that combines all interrupts this driver uses into
45 * a single constant value, for convenience. */
46 #define DENALI_IRQ_ALL (INTR_STATUS__DMA_CMD_COMP | \
47 INTR_STATUS__ECC_TRANSACTION_DONE | \
48 INTR_STATUS__ECC_ERR | \
49 INTR_STATUS__PROGRAM_FAIL | \
50 INTR_STATUS__LOAD_COMP | \
51 INTR_STATUS__PROGRAM_COMP | \
52 INTR_STATUS__TIME_OUT | \
53 INTR_STATUS__ERASE_FAIL | \
54 INTR_STATUS__RST_COMP | \
55 INTR_STATUS__ERASE_COMP)
56
57 /* indicates whether or not the internal value for the flash bank is
58 * valid or not */
59 #define CHIP_SELECT_INVALID -1
60
61 #define SUPPORT_8BITECC 1
62
63 /* This macro divides two integers and rounds fractional values up
64 * to the nearest integer value. */
65 #define CEIL_DIV(X, Y) (((X)%(Y)) ? ((X)/(Y)+1) : ((X)/(Y)))
66
67 /* this macro allows us to convert from an MTD structure to our own
68 * device context (denali) structure.
69 */
70 #define mtd_to_denali(m) container_of(m, struct denali_nand_info, mtd)
71
72 /* These constants are defined by the driver to enable common driver
73 * configuration options. */
74 #define SPARE_ACCESS 0x41
75 #define MAIN_ACCESS 0x42
76 #define MAIN_SPARE_ACCESS 0x43
77
78 #define DENALI_READ 0
79 #define DENALI_WRITE 0x100
80
81 /* types of device accesses. We can issue commands and get status */
82 #define COMMAND_CYCLE 0
83 #define ADDR_CYCLE 1
84 #define STATUS_CYCLE 2
85
86 /* this is a helper macro that allows us to
87 * format the bank into the proper bits for the controller */
88 #define BANK(x) ((x) << 24)
89
90 /* forward declarations */
91 static void clear_interrupts(struct denali_nand_info *denali);
92 static uint32_t wait_for_irq(struct denali_nand_info *denali,
93 uint32_t irq_mask);
94 static void denali_irq_enable(struct denali_nand_info *denali,
95 uint32_t int_mask);
96 static uint32_t read_interrupt_status(struct denali_nand_info *denali);
97
98 /* Certain operations for the denali NAND controller use
99 * an indexed mode to read/write data. The operation is
100 * performed by writing the address value of the command
101 * to the device memory followed by the data. This function
102 * abstracts this common operation.
103 */
104 static void index_addr(struct denali_nand_info *denali,
105 uint32_t address, uint32_t data)
106 {
107 iowrite32(address, denali->flash_mem);
108 iowrite32(data, denali->flash_mem + 0x10);
109 }
110
111 /* Perform an indexed read of the device */
112 static void index_addr_read_data(struct denali_nand_info *denali,
113 uint32_t address, uint32_t *pdata)
114 {
115 iowrite32(address, denali->flash_mem);
116 *pdata = ioread32(denali->flash_mem + 0x10);
117 }
118
119 /* We need to buffer some data for some of the NAND core routines.
120 * The operations manage buffering that data. */
121 static void reset_buf(struct denali_nand_info *denali)
122 {
123 denali->buf.head = denali->buf.tail = 0;
124 }
125
126 static void write_byte_to_buf(struct denali_nand_info *denali, uint8_t byte)
127 {
128 BUG_ON(denali->buf.tail >= sizeof(denali->buf.buf));
129 denali->buf.buf[denali->buf.tail++] = byte;
130 }
131
132 /* reads the status of the device */
133 static void read_status(struct denali_nand_info *denali)
134 {
135 uint32_t cmd = 0x0;
136
137 /* initialize the data buffer to store status */
138 reset_buf(denali);
139
140 cmd = ioread32(denali->flash_reg + WRITE_PROTECT);
141 if (cmd)
142 write_byte_to_buf(denali, NAND_STATUS_WP);
143 else
144 write_byte_to_buf(denali, 0);
145 }
146
147 /* resets a specific device connected to the core */
148 static void reset_bank(struct denali_nand_info *denali)
149 {
150 uint32_t irq_status = 0;
151 uint32_t irq_mask = INTR_STATUS__RST_COMP |
152 INTR_STATUS__TIME_OUT;
153
154 clear_interrupts(denali);
155
156 iowrite32(1 << denali->flash_bank, denali->flash_reg + DEVICE_RESET);
157
158 irq_status = wait_for_irq(denali, irq_mask);
159
160 if (irq_status & INTR_STATUS__TIME_OUT)
161 dev_err(denali->dev, "reset bank failed.\n");
162 }
163
164 /* Reset the flash controller */
165 static uint16_t denali_nand_reset(struct denali_nand_info *denali)
166 {
167 uint32_t i;
168
169 dev_dbg(denali->dev, "%s, Line %d, Function: %s\n",
170 __FILE__, __LINE__, __func__);
171
172 for (i = 0 ; i < denali->max_banks; i++)
173 iowrite32(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT,
174 denali->flash_reg + INTR_STATUS(i));
175
176 for (i = 0 ; i < denali->max_banks; i++) {
177 iowrite32(1 << i, denali->flash_reg + DEVICE_RESET);
178 while (!(ioread32(denali->flash_reg +
179 INTR_STATUS(i)) &
180 (INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT)))
181 cpu_relax();
182 if (ioread32(denali->flash_reg + INTR_STATUS(i)) &
183 INTR_STATUS__TIME_OUT)
184 dev_dbg(denali->dev,
185 "NAND Reset operation timed out on bank %d\n", i);
186 }
187
188 for (i = 0; i < denali->max_banks; i++)
189 iowrite32(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT,
190 denali->flash_reg + INTR_STATUS(i));
191
192 return PASS;
193 }
194
195 /* this routine calculates the ONFI timing values for a given mode and
196 * programs the clocking register accordingly. The mode is determined by
197 * the get_onfi_nand_para routine.
198 */
199 static void nand_onfi_timing_set(struct denali_nand_info *denali,
200 uint16_t mode)
201 {
202 uint16_t Trea[6] = {40, 30, 25, 20, 20, 16};
203 uint16_t Trp[6] = {50, 25, 17, 15, 12, 10};
204 uint16_t Treh[6] = {30, 15, 15, 10, 10, 7};
205 uint16_t Trc[6] = {100, 50, 35, 30, 25, 20};
206 uint16_t Trhoh[6] = {0, 15, 15, 15, 15, 15};
207 uint16_t Trloh[6] = {0, 0, 0, 0, 5, 5};
208 uint16_t Tcea[6] = {100, 45, 30, 25, 25, 25};
209 uint16_t Tadl[6] = {200, 100, 100, 100, 70, 70};
210 uint16_t Trhw[6] = {200, 100, 100, 100, 100, 100};
211 uint16_t Trhz[6] = {200, 100, 100, 100, 100, 100};
212 uint16_t Twhr[6] = {120, 80, 80, 60, 60, 60};
213 uint16_t Tcs[6] = {70, 35, 25, 25, 20, 15};
214
215 uint16_t TclsRising = 1;
216 uint16_t data_invalid_rhoh, data_invalid_rloh, data_invalid;
217 uint16_t dv_window = 0;
218 uint16_t en_lo, en_hi;
219 uint16_t acc_clks;
220 uint16_t addr_2_data, re_2_we, re_2_re, we_2_re, cs_cnt;
221
222 dev_dbg(denali->dev, "%s, Line %d, Function: %s\n",
223 __FILE__, __LINE__, __func__);
224
225 en_lo = CEIL_DIV(Trp[mode], CLK_X);
226 en_hi = CEIL_DIV(Treh[mode], CLK_X);
227 #if ONFI_BLOOM_TIME
228 if ((en_hi * CLK_X) < (Treh[mode] + 2))
229 en_hi++;
230 #endif
231
232 if ((en_lo + en_hi) * CLK_X < Trc[mode])
233 en_lo += CEIL_DIV((Trc[mode] - (en_lo + en_hi) * CLK_X), CLK_X);
234
235 if ((en_lo + en_hi) < CLK_MULTI)
236 en_lo += CLK_MULTI - en_lo - en_hi;
237
238 while (dv_window < 8) {
239 data_invalid_rhoh = en_lo * CLK_X + Trhoh[mode];
240
241 data_invalid_rloh = (en_lo + en_hi) * CLK_X + Trloh[mode];
242
243 data_invalid =
244 data_invalid_rhoh <
245 data_invalid_rloh ? data_invalid_rhoh : data_invalid_rloh;
246
247 dv_window = data_invalid - Trea[mode];
248
249 if (dv_window < 8)
250 en_lo++;
251 }
252
253 acc_clks = CEIL_DIV(Trea[mode], CLK_X);
254
255 while (((acc_clks * CLK_X) - Trea[mode]) < 3)
256 acc_clks++;
257
258 if ((data_invalid - acc_clks * CLK_X) < 2)
259 dev_warn(denali->dev, "%s, Line %d: Warning!\n",
260 __FILE__, __LINE__);
261
262 addr_2_data = CEIL_DIV(Tadl[mode], CLK_X);
263 re_2_we = CEIL_DIV(Trhw[mode], CLK_X);
264 re_2_re = CEIL_DIV(Trhz[mode], CLK_X);
265 we_2_re = CEIL_DIV(Twhr[mode], CLK_X);
266 cs_cnt = CEIL_DIV((Tcs[mode] - Trp[mode]), CLK_X);
267 if (!TclsRising)
268 cs_cnt = CEIL_DIV(Tcs[mode], CLK_X);
269 if (cs_cnt == 0)
270 cs_cnt = 1;
271
272 if (Tcea[mode]) {
273 while (((cs_cnt * CLK_X) + Trea[mode]) < Tcea[mode])
274 cs_cnt++;
275 }
276
277 #if MODE5_WORKAROUND
278 if (mode == 5)
279 acc_clks = 5;
280 #endif
281
282 /* Sighting 3462430: Temporary hack for MT29F128G08CJABAWP:B */
283 if ((ioread32(denali->flash_reg + MANUFACTURER_ID) == 0) &&
284 (ioread32(denali->flash_reg + DEVICE_ID) == 0x88))
285 acc_clks = 6;
286
287 iowrite32(acc_clks, denali->flash_reg + ACC_CLKS);
288 iowrite32(re_2_we, denali->flash_reg + RE_2_WE);
289 iowrite32(re_2_re, denali->flash_reg + RE_2_RE);
290 iowrite32(we_2_re, denali->flash_reg + WE_2_RE);
291 iowrite32(addr_2_data, denali->flash_reg + ADDR_2_DATA);
292 iowrite32(en_lo, denali->flash_reg + RDWR_EN_LO_CNT);
293 iowrite32(en_hi, denali->flash_reg + RDWR_EN_HI_CNT);
294 iowrite32(cs_cnt, denali->flash_reg + CS_SETUP_CNT);
295 }
296
297 /* queries the NAND device to see what ONFI modes it supports. */
298 static uint16_t get_onfi_nand_para(struct denali_nand_info *denali)
299 {
300 int i;
301 /* we needn't to do a reset here because driver has already
302 * reset all the banks before
303 * */
304 if (!(ioread32(denali->flash_reg + ONFI_TIMING_MODE) &
305 ONFI_TIMING_MODE__VALUE))
306 return FAIL;
307
308 for (i = 5; i > 0; i--) {
309 if (ioread32(denali->flash_reg + ONFI_TIMING_MODE) &
310 (0x01 << i))
311 break;
312 }
313
314 nand_onfi_timing_set(denali, i);
315
316 /* By now, all the ONFI devices we know support the page cache */
317 /* rw feature. So here we enable the pipeline_rw_ahead feature */
318 /* iowrite32(1, denali->flash_reg + CACHE_WRITE_ENABLE); */
319 /* iowrite32(1, denali->flash_reg + CACHE_READ_ENABLE); */
320
321 return PASS;
322 }
323
324 static void get_samsung_nand_para(struct denali_nand_info *denali,
325 uint8_t device_id)
326 {
327 if (device_id == 0xd3) { /* Samsung K9WAG08U1A */
328 /* Set timing register values according to datasheet */
329 iowrite32(5, denali->flash_reg + ACC_CLKS);
330 iowrite32(20, denali->flash_reg + RE_2_WE);
331 iowrite32(12, denali->flash_reg + WE_2_RE);
332 iowrite32(14, denali->flash_reg + ADDR_2_DATA);
333 iowrite32(3, denali->flash_reg + RDWR_EN_LO_CNT);
334 iowrite32(2, denali->flash_reg + RDWR_EN_HI_CNT);
335 iowrite32(2, denali->flash_reg + CS_SETUP_CNT);
336 }
337 }
338
339 static void get_toshiba_nand_para(struct denali_nand_info *denali)
340 {
341 uint32_t tmp;
342
343 /* Workaround to fix a controller bug which reports a wrong */
344 /* spare area size for some kind of Toshiba NAND device */
345 if ((ioread32(denali->flash_reg + DEVICE_MAIN_AREA_SIZE) == 4096) &&
346 (ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE) == 64)) {
347 iowrite32(216, denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
348 tmp = ioread32(denali->flash_reg + DEVICES_CONNECTED) *
349 ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
350 iowrite32(tmp,
351 denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE);
352 #if SUPPORT_15BITECC
353 iowrite32(15, denali->flash_reg + ECC_CORRECTION);
354 #elif SUPPORT_8BITECC
355 iowrite32(8, denali->flash_reg + ECC_CORRECTION);
356 #endif
357 }
358 }
359
360 static void get_hynix_nand_para(struct denali_nand_info *denali,
361 uint8_t device_id)
362 {
363 uint32_t main_size, spare_size;
364
365 switch (device_id) {
366 case 0xD5: /* Hynix H27UAG8T2A, H27UBG8U5A or H27UCG8VFA */
367 case 0xD7: /* Hynix H27UDG8VEM, H27UCG8UDM or H27UCG8V5A */
368 iowrite32(128, denali->flash_reg + PAGES_PER_BLOCK);
369 iowrite32(4096, denali->flash_reg + DEVICE_MAIN_AREA_SIZE);
370 iowrite32(224, denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
371 main_size = 4096 *
372 ioread32(denali->flash_reg + DEVICES_CONNECTED);
373 spare_size = 224 *
374 ioread32(denali->flash_reg + DEVICES_CONNECTED);
375 iowrite32(main_size,
376 denali->flash_reg + LOGICAL_PAGE_DATA_SIZE);
377 iowrite32(spare_size,
378 denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE);
379 iowrite32(0, denali->flash_reg + DEVICE_WIDTH);
380 #if SUPPORT_15BITECC
381 iowrite32(15, denali->flash_reg + ECC_CORRECTION);
382 #elif SUPPORT_8BITECC
383 iowrite32(8, denali->flash_reg + ECC_CORRECTION);
384 #endif
385 break;
386 default:
387 dev_warn(denali->dev,
388 "Spectra: Unknown Hynix NAND (Device ID: 0x%x)."
389 "Will use default parameter values instead.\n",
390 device_id);
391 }
392 }
393
394 /* determines how many NAND chips are connected to the controller. Note for
395 * Intel CE4100 devices we don't support more than one device.
396 */
397 static void find_valid_banks(struct denali_nand_info *denali)
398 {
399 uint32_t id[denali->max_banks];
400 int i;
401
402 denali->total_used_banks = 1;
403 for (i = 0; i < denali->max_banks; i++) {
404 index_addr(denali, (uint32_t)(MODE_11 | (i << 24) | 0), 0x90);
405 index_addr(denali, (uint32_t)(MODE_11 | (i << 24) | 1), 0);
406 index_addr_read_data(denali,
407 (uint32_t)(MODE_11 | (i << 24) | 2), &id[i]);
408
409 dev_dbg(denali->dev,
410 "Return 1st ID for bank[%d]: %x\n", i, id[i]);
411
412 if (i == 0) {
413 if (!(id[i] & 0x0ff))
414 break; /* WTF? */
415 } else {
416 if ((id[i] & 0x0ff) == (id[0] & 0x0ff))
417 denali->total_used_banks++;
418 else
419 break;
420 }
421 }
422
423 if (denali->platform == INTEL_CE4100) {
424 /* Platform limitations of the CE4100 device limit
425 * users to a single chip solution for NAND.
426 * Multichip support is not enabled.
427 */
428 if (denali->total_used_banks != 1) {
429 dev_err(denali->dev,
430 "Sorry, Intel CE4100 only supports "
431 "a single NAND device.\n");
432 BUG();
433 }
434 }
435 dev_dbg(denali->dev,
436 "denali->total_used_banks: %d\n", denali->total_used_banks);
437 }
438
439 /*
440 * Use the configuration feature register to determine the maximum number of
441 * banks that the hardware supports.
442 */
443 static void detect_max_banks(struct denali_nand_info *denali)
444 {
445 uint32_t features = ioread32(denali->flash_reg + FEATURES);
446
447 denali->max_banks = 2 << (features & FEATURES__N_BANKS);
448 }
449
450 static void detect_partition_feature(struct denali_nand_info *denali)
451 {
452 /* For MRST platform, denali->fwblks represent the
453 * number of blocks firmware is taken,
454 * FW is in protect partition and MTD driver has no
455 * permission to access it. So let driver know how many
456 * blocks it can't touch.
457 * */
458 if (ioread32(denali->flash_reg + FEATURES) & FEATURES__PARTITION) {
459 if ((ioread32(denali->flash_reg + PERM_SRC_ID(1)) &
460 PERM_SRC_ID__SRCID) == SPECTRA_PARTITION_ID) {
461 denali->fwblks =
462 ((ioread32(denali->flash_reg + MIN_MAX_BANK(1)) &
463 MIN_MAX_BANK__MIN_VALUE) *
464 denali->blksperchip)
465 +
466 (ioread32(denali->flash_reg + MIN_BLK_ADDR(1)) &
467 MIN_BLK_ADDR__VALUE);
468 } else
469 denali->fwblks = SPECTRA_START_BLOCK;
470 } else
471 denali->fwblks = SPECTRA_START_BLOCK;
472 }
473
474 static uint16_t denali_nand_timing_set(struct denali_nand_info *denali)
475 {
476 uint16_t status = PASS;
477 uint32_t id_bytes[5], addr;
478 uint8_t i, maf_id, device_id;
479
480 dev_dbg(denali->dev,
481 "%s, Line %d, Function: %s\n",
482 __FILE__, __LINE__, __func__);
483
484 /* Use read id method to get device ID and other
485 * params. For some NAND chips, controller can't
486 * report the correct device ID by reading from
487 * DEVICE_ID register
488 * */
489 addr = (uint32_t)MODE_11 | BANK(denali->flash_bank);
490 index_addr(denali, (uint32_t)addr | 0, 0x90);
491 index_addr(denali, (uint32_t)addr | 1, 0);
492 for (i = 0; i < 5; i++)
493 index_addr_read_data(denali, addr | 2, &id_bytes[i]);
494 maf_id = id_bytes[0];
495 device_id = id_bytes[1];
496
497 if (ioread32(denali->flash_reg + ONFI_DEVICE_NO_OF_LUNS) &
498 ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE) { /* ONFI 1.0 NAND */
499 if (FAIL == get_onfi_nand_para(denali))
500 return FAIL;
501 } else if (maf_id == 0xEC) { /* Samsung NAND */
502 get_samsung_nand_para(denali, device_id);
503 } else if (maf_id == 0x98) { /* Toshiba NAND */
504 get_toshiba_nand_para(denali);
505 } else if (maf_id == 0xAD) { /* Hynix NAND */
506 get_hynix_nand_para(denali, device_id);
507 }
508
509 dev_info(denali->dev,
510 "Dump timing register values:"
511 "acc_clks: %d, re_2_we: %d, re_2_re: %d\n"
512 "we_2_re: %d, addr_2_data: %d, rdwr_en_lo_cnt: %d\n"
513 "rdwr_en_hi_cnt: %d, cs_setup_cnt: %d\n",
514 ioread32(denali->flash_reg + ACC_CLKS),
515 ioread32(denali->flash_reg + RE_2_WE),
516 ioread32(denali->flash_reg + RE_2_RE),
517 ioread32(denali->flash_reg + WE_2_RE),
518 ioread32(denali->flash_reg + ADDR_2_DATA),
519 ioread32(denali->flash_reg + RDWR_EN_LO_CNT),
520 ioread32(denali->flash_reg + RDWR_EN_HI_CNT),
521 ioread32(denali->flash_reg + CS_SETUP_CNT));
522
523 find_valid_banks(denali);
524
525 detect_partition_feature(denali);
526
527 /* If the user specified to override the default timings
528 * with a specific ONFI mode, we apply those changes here.
529 */
530 if (onfi_timing_mode != NAND_DEFAULT_TIMINGS)
531 nand_onfi_timing_set(denali, onfi_timing_mode);
532
533 return status;
534 }
535
536 static void denali_set_intr_modes(struct denali_nand_info *denali,
537 uint16_t INT_ENABLE)
538 {
539 dev_dbg(denali->dev, "%s, Line %d, Function: %s\n",
540 __FILE__, __LINE__, __func__);
541
542 if (INT_ENABLE)
543 iowrite32(1, denali->flash_reg + GLOBAL_INT_ENABLE);
544 else
545 iowrite32(0, denali->flash_reg + GLOBAL_INT_ENABLE);
546 }
547
548 /* validation function to verify that the controlling software is making
549 * a valid request
550 */
551 static inline bool is_flash_bank_valid(int flash_bank)
552 {
553 return (flash_bank >= 0 && flash_bank < 4);
554 }
555
556 static void denali_irq_init(struct denali_nand_info *denali)
557 {
558 uint32_t int_mask = 0;
559 int i;
560
561 /* Disable global interrupts */
562 denali_set_intr_modes(denali, false);
563
564 int_mask = DENALI_IRQ_ALL;
565
566 /* Clear all status bits */
567 for (i = 0; i < denali->max_banks; ++i)
568 iowrite32(0xFFFF, denali->flash_reg + INTR_STATUS(i));
569
570 denali_irq_enable(denali, int_mask);
571 }
572
573 static void denali_irq_cleanup(int irqnum, struct denali_nand_info *denali)
574 {
575 denali_set_intr_modes(denali, false);
576 free_irq(irqnum, denali);
577 }
578
579 static void denali_irq_enable(struct denali_nand_info *denali,
580 uint32_t int_mask)
581 {
582 int i;
583
584 for (i = 0; i < denali->max_banks; ++i)
585 iowrite32(int_mask, denali->flash_reg + INTR_EN(i));
586 }
587
588 /* This function only returns when an interrupt that this driver cares about
589 * occurs. This is to reduce the overhead of servicing interrupts
590 */
591 static inline uint32_t denali_irq_detected(struct denali_nand_info *denali)
592 {
593 return read_interrupt_status(denali) & DENALI_IRQ_ALL;
594 }
595
596 /* Interrupts are cleared by writing a 1 to the appropriate status bit */
597 static inline void clear_interrupt(struct denali_nand_info *denali,
598 uint32_t irq_mask)
599 {
600 uint32_t intr_status_reg = 0;
601
602 intr_status_reg = INTR_STATUS(denali->flash_bank);
603
604 iowrite32(irq_mask, denali->flash_reg + intr_status_reg);
605 }
606
607 static void clear_interrupts(struct denali_nand_info *denali)
608 {
609 uint32_t status = 0x0;
610 spin_lock_irq(&denali->irq_lock);
611
612 status = read_interrupt_status(denali);
613 clear_interrupt(denali, status);
614
615 denali->irq_status = 0x0;
616 spin_unlock_irq(&denali->irq_lock);
617 }
618
619 static uint32_t read_interrupt_status(struct denali_nand_info *denali)
620 {
621 uint32_t intr_status_reg = 0;
622
623 intr_status_reg = INTR_STATUS(denali->flash_bank);
624
625 return ioread32(denali->flash_reg + intr_status_reg);
626 }
627
628 /* This is the interrupt service routine. It handles all interrupts
629 * sent to this device. Note that on CE4100, this is a shared
630 * interrupt.
631 */
632 static irqreturn_t denali_isr(int irq, void *dev_id)
633 {
634 struct denali_nand_info *denali = dev_id;
635 uint32_t irq_status = 0x0;
636 irqreturn_t result = IRQ_NONE;
637
638 spin_lock(&denali->irq_lock);
639
640 /* check to see if a valid NAND chip has
641 * been selected.
642 */
643 if (is_flash_bank_valid(denali->flash_bank)) {
644 /* check to see if controller generated
645 * the interrupt, since this is a shared interrupt */
646 irq_status = denali_irq_detected(denali);
647 if (irq_status != 0) {
648 /* handle interrupt */
649 /* first acknowledge it */
650 clear_interrupt(denali, irq_status);
651 /* store the status in the device context for someone
652 to read */
653 denali->irq_status |= irq_status;
654 /* notify anyone who cares that it happened */
655 complete(&denali->complete);
656 /* tell the OS that we've handled this */
657 result = IRQ_HANDLED;
658 }
659 }
660 spin_unlock(&denali->irq_lock);
661 return result;
662 }
663 #define BANK(x) ((x) << 24)
664
665 static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask)
666 {
667 unsigned long comp_res = 0;
668 uint32_t intr_status = 0;
669 bool retry = false;
670 unsigned long timeout = msecs_to_jiffies(1000);
671
672 do {
673 comp_res =
674 wait_for_completion_timeout(&denali->complete, timeout);
675 spin_lock_irq(&denali->irq_lock);
676 intr_status = denali->irq_status;
677
678 if (intr_status & irq_mask) {
679 denali->irq_status &= ~irq_mask;
680 spin_unlock_irq(&denali->irq_lock);
681 /* our interrupt was detected */
682 break;
683 } else {
684 /* these are not the interrupts you are looking for -
685 * need to wait again */
686 spin_unlock_irq(&denali->irq_lock);
687 retry = true;
688 }
689 } while (comp_res != 0);
690
691 if (comp_res == 0) {
692 /* timeout */
693 pr_err("timeout occurred, status = 0x%x, mask = 0x%x\n",
694 intr_status, irq_mask);
695
696 intr_status = 0;
697 }
698 return intr_status;
699 }
700
701 /* This helper function setups the registers for ECC and whether or not
702 * the spare area will be transferred. */
703 static void setup_ecc_for_xfer(struct denali_nand_info *denali, bool ecc_en,
704 bool transfer_spare)
705 {
706 int ecc_en_flag = 0, transfer_spare_flag = 0;
707
708 /* set ECC, transfer spare bits if needed */
709 ecc_en_flag = ecc_en ? ECC_ENABLE__FLAG : 0;
710 transfer_spare_flag = transfer_spare ? TRANSFER_SPARE_REG__FLAG : 0;
711
712 /* Enable spare area/ECC per user's request. */
713 iowrite32(ecc_en_flag, denali->flash_reg + ECC_ENABLE);
714 iowrite32(transfer_spare_flag,
715 denali->flash_reg + TRANSFER_SPARE_REG);
716 }
717
718 /* sends a pipeline command operation to the controller. See the Denali NAND
719 * controller's user guide for more information (section 4.2.3.6).
720 */
721 static int denali_send_pipeline_cmd(struct denali_nand_info *denali,
722 bool ecc_en,
723 bool transfer_spare,
724 int access_type,
725 int op)
726 {
727 int status = PASS;
728 uint32_t addr = 0x0, cmd = 0x0, page_count = 1, irq_status = 0,
729 irq_mask = 0;
730
731 if (op == DENALI_READ)
732 irq_mask = INTR_STATUS__LOAD_COMP;
733 else if (op == DENALI_WRITE)
734 irq_mask = 0;
735 else
736 BUG();
737
738 setup_ecc_for_xfer(denali, ecc_en, transfer_spare);
739
740 /* clear interrupts */
741 clear_interrupts(denali);
742
743 addr = BANK(denali->flash_bank) | denali->page;
744
745 if (op == DENALI_WRITE && access_type != SPARE_ACCESS) {
746 cmd = MODE_01 | addr;
747 iowrite32(cmd, denali->flash_mem);
748 } else if (op == DENALI_WRITE && access_type == SPARE_ACCESS) {
749 /* read spare area */
750 cmd = MODE_10 | addr;
751 index_addr(denali, (uint32_t)cmd, access_type);
752
753 cmd = MODE_01 | addr;
754 iowrite32(cmd, denali->flash_mem);
755 } else if (op == DENALI_READ) {
756 /* setup page read request for access type */
757 cmd = MODE_10 | addr;
758 index_addr(denali, (uint32_t)cmd, access_type);
759
760 /* page 33 of the NAND controller spec indicates we should not
761 use the pipeline commands in Spare area only mode. So we
762 don't.
763 */
764 if (access_type == SPARE_ACCESS) {
765 cmd = MODE_01 | addr;
766 iowrite32(cmd, denali->flash_mem);
767 } else {
768 index_addr(denali, (uint32_t)cmd,
769 0x2000 | op | page_count);
770
771 /* wait for command to be accepted
772 * can always use status0 bit as the
773 * mask is identical for each
774 * bank. */
775 irq_status = wait_for_irq(denali, irq_mask);
776
777 if (irq_status == 0) {
778 dev_err(denali->dev,
779 "cmd, page, addr on timeout "
780 "(0x%x, 0x%x, 0x%x)\n",
781 cmd, denali->page, addr);
782 status = FAIL;
783 } else {
784 cmd = MODE_01 | addr;
785 iowrite32(cmd, denali->flash_mem);
786 }
787 }
788 }
789 return status;
790 }
791
792 /* helper function that simply writes a buffer to the flash */
793 static int write_data_to_flash_mem(struct denali_nand_info *denali,
794 const uint8_t *buf,
795 int len)
796 {
797 uint32_t i = 0, *buf32;
798
799 /* verify that the len is a multiple of 4. see comment in
800 * read_data_from_flash_mem() */
801 BUG_ON((len % 4) != 0);
802
803 /* write the data to the flash memory */
804 buf32 = (uint32_t *)buf;
805 for (i = 0; i < len / 4; i++)
806 iowrite32(*buf32++, denali->flash_mem + 0x10);
807 return i*4; /* intent is to return the number of bytes read */
808 }
809
810 /* helper function that simply reads a buffer from the flash */
811 static int read_data_from_flash_mem(struct denali_nand_info *denali,
812 uint8_t *buf,
813 int len)
814 {
815 uint32_t i = 0, *buf32;
816
817 /* we assume that len will be a multiple of 4, if not
818 * it would be nice to know about it ASAP rather than
819 * have random failures...
820 * This assumption is based on the fact that this
821 * function is designed to be used to read flash pages,
822 * which are typically multiples of 4...
823 */
824
825 BUG_ON((len % 4) != 0);
826
827 /* transfer the data from the flash */
828 buf32 = (uint32_t *)buf;
829 for (i = 0; i < len / 4; i++)
830 *buf32++ = ioread32(denali->flash_mem + 0x10);
831 return i*4; /* intent is to return the number of bytes read */
832 }
833
834 /* writes OOB data to the device */
835 static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
836 {
837 struct denali_nand_info *denali = mtd_to_denali(mtd);
838 uint32_t irq_status = 0;
839 uint32_t irq_mask = INTR_STATUS__PROGRAM_COMP |
840 INTR_STATUS__PROGRAM_FAIL;
841 int status = 0;
842
843 denali->page = page;
844
845 if (denali_send_pipeline_cmd(denali, false, false, SPARE_ACCESS,
846 DENALI_WRITE) == PASS) {
847 write_data_to_flash_mem(denali, buf, mtd->oobsize);
848
849 /* wait for operation to complete */
850 irq_status = wait_for_irq(denali, irq_mask);
851
852 if (irq_status == 0) {
853 dev_err(denali->dev, "OOB write failed\n");
854 status = -EIO;
855 }
856 } else {
857 dev_err(denali->dev, "unable to send pipeline command\n");
858 status = -EIO;
859 }
860 return status;
861 }
862
863 /* reads OOB data from the device */
864 static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
865 {
866 struct denali_nand_info *denali = mtd_to_denali(mtd);
867 uint32_t irq_mask = INTR_STATUS__LOAD_COMP,
868 irq_status = 0, addr = 0x0, cmd = 0x0;
869
870 denali->page = page;
871
872 if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS,
873 DENALI_READ) == PASS) {
874 read_data_from_flash_mem(denali, buf, mtd->oobsize);
875
876 /* wait for command to be accepted
877 * can always use status0 bit as the mask is identical for each
878 * bank. */
879 irq_status = wait_for_irq(denali, irq_mask);
880
881 if (irq_status == 0)
882 dev_err(denali->dev, "page on OOB timeout %d\n",
883 denali->page);
884
885 /* We set the device back to MAIN_ACCESS here as I observed
886 * instability with the controller if you do a block erase
887 * and the last transaction was a SPARE_ACCESS. Block erase
888 * is reliable (according to the MTD test infrastructure)
889 * if you are in MAIN_ACCESS.
890 */
891 addr = BANK(denali->flash_bank) | denali->page;
892 cmd = MODE_10 | addr;
893 index_addr(denali, (uint32_t)cmd, MAIN_ACCESS);
894 }
895 }
896
897 /* this function examines buffers to see if they contain data that
898 * indicate that the buffer is part of an erased region of flash.
899 */
900 bool is_erased(uint8_t *buf, int len)
901 {
902 int i = 0;
903 for (i = 0; i < len; i++)
904 if (buf[i] != 0xFF)
905 return false;
906 return true;
907 }
908 #define ECC_SECTOR_SIZE 512
909
910 #define ECC_SECTOR(x) (((x) & ECC_ERROR_ADDRESS__SECTOR_NR) >> 12)
911 #define ECC_BYTE(x) (((x) & ECC_ERROR_ADDRESS__OFFSET))
912 #define ECC_CORRECTION_VALUE(x) ((x) & ERR_CORRECTION_INFO__BYTEMASK)
913 #define ECC_ERROR_CORRECTABLE(x) (!((x) & ERR_CORRECTION_INFO__ERROR_TYPE))
914 #define ECC_ERR_DEVICE(x) (((x) & ERR_CORRECTION_INFO__DEVICE_NR) >> 8)
915 #define ECC_LAST_ERR(x) ((x) & ERR_CORRECTION_INFO__LAST_ERR_INFO)
916
917 static bool handle_ecc(struct denali_nand_info *denali, uint8_t *buf,
918 uint32_t irq_status, unsigned int *max_bitflips)
919 {
920 bool check_erased_page = false;
921 unsigned int bitflips = 0;
922
923 if (irq_status & INTR_STATUS__ECC_ERR) {
924 /* read the ECC errors. we'll ignore them for now */
925 uint32_t err_address = 0, err_correction_info = 0;
926 uint32_t err_byte = 0, err_sector = 0, err_device = 0;
927 uint32_t err_correction_value = 0;
928 denali_set_intr_modes(denali, false);
929
930 do {
931 err_address = ioread32(denali->flash_reg +
932 ECC_ERROR_ADDRESS);
933 err_sector = ECC_SECTOR(err_address);
934 err_byte = ECC_BYTE(err_address);
935
936 err_correction_info = ioread32(denali->flash_reg +
937 ERR_CORRECTION_INFO);
938 err_correction_value =
939 ECC_CORRECTION_VALUE(err_correction_info);
940 err_device = ECC_ERR_DEVICE(err_correction_info);
941
942 if (ECC_ERROR_CORRECTABLE(err_correction_info)) {
943 /* If err_byte is larger than ECC_SECTOR_SIZE,
944 * means error happened in OOB, so we ignore
945 * it. It's no need for us to correct it
946 * err_device is represented the NAND error
947 * bits are happened in if there are more
948 * than one NAND connected.
949 * */
950 if (err_byte < ECC_SECTOR_SIZE) {
951 int offset;
952 offset = (err_sector *
953 ECC_SECTOR_SIZE +
954 err_byte) *
955 denali->devnum +
956 err_device;
957 /* correct the ECC error */
958 buf[offset] ^= err_correction_value;
959 denali->mtd.ecc_stats.corrected++;
960 bitflips++;
961 }
962 } else {
963 /* if the error is not correctable, need to
964 * look at the page to see if it is an erased
965 * page. if so, then it's not a real ECC error
966 * */
967 check_erased_page = true;
968 }
969 } while (!ECC_LAST_ERR(err_correction_info));
970 /* Once handle all ecc errors, controller will triger
971 * a ECC_TRANSACTION_DONE interrupt, so here just wait
972 * for a while for this interrupt
973 * */
974 while (!(read_interrupt_status(denali) &
975 INTR_STATUS__ECC_TRANSACTION_DONE))
976 cpu_relax();
977 clear_interrupts(denali);
978 denali_set_intr_modes(denali, true);
979 }
980 *max_bitflips = bitflips;
981 return check_erased_page;
982 }
983
984 /* programs the controller to either enable/disable DMA transfers */
985 static void denali_enable_dma(struct denali_nand_info *denali, bool en)
986 {
987 uint32_t reg_val = 0x0;
988
989 if (en)
990 reg_val = DMA_ENABLE__FLAG;
991
992 iowrite32(reg_val, denali->flash_reg + DMA_ENABLE);
993 ioread32(denali->flash_reg + DMA_ENABLE);
994 }
995
996 /* setups the HW to perform the data DMA */
997 static void denali_setup_dma(struct denali_nand_info *denali, int op)
998 {
999 uint32_t mode = 0x0;
1000 const int page_count = 1;
1001 dma_addr_t addr = denali->buf.dma_buf;
1002
1003 mode = MODE_10 | BANK(denali->flash_bank);
1004
1005 /* DMA is a four step process */
1006
1007 /* 1. setup transfer type and # of pages */
1008 index_addr(denali, mode | denali->page, 0x2000 | op | page_count);
1009
1010 /* 2. set memory high address bits 23:8 */
1011 index_addr(denali, mode | ((uint16_t)(addr >> 16) << 8), 0x2200);
1012
1013 /* 3. set memory low address bits 23:8 */
1014 index_addr(denali, mode | ((uint16_t)addr << 8), 0x2300);
1015
1016 /* 4. interrupt when complete, burst len = 64 bytes*/
1017 index_addr(denali, mode | 0x14000, 0x2400);
1018 }
1019
1020 /* writes a page. user specifies type, and this function handles the
1021 * configuration details. */
1022 static int write_page(struct mtd_info *mtd, struct nand_chip *chip,
1023 const uint8_t *buf, bool raw_xfer)
1024 {
1025 struct denali_nand_info *denali = mtd_to_denali(mtd);
1026
1027 dma_addr_t addr = denali->buf.dma_buf;
1028 size_t size = denali->mtd.writesize + denali->mtd.oobsize;
1029
1030 uint32_t irq_status = 0;
1031 uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP |
1032 INTR_STATUS__PROGRAM_FAIL;
1033
1034 /* if it is a raw xfer, we want to disable ecc, and send
1035 * the spare area.
1036 * !raw_xfer - enable ecc
1037 * raw_xfer - transfer spare
1038 */
1039 setup_ecc_for_xfer(denali, !raw_xfer, raw_xfer);
1040
1041 /* copy buffer into DMA buffer */
1042 memcpy(denali->buf.buf, buf, mtd->writesize);
1043
1044 if (raw_xfer) {
1045 /* transfer the data to the spare area */
1046 memcpy(denali->buf.buf + mtd->writesize,
1047 chip->oob_poi,
1048 mtd->oobsize);
1049 }
1050
1051 dma_sync_single_for_device(denali->dev, addr, size, DMA_TO_DEVICE);
1052
1053 clear_interrupts(denali);
1054 denali_enable_dma(denali, true);
1055
1056 denali_setup_dma(denali, DENALI_WRITE);
1057
1058 /* wait for operation to complete */
1059 irq_status = wait_for_irq(denali, irq_mask);
1060
1061 if (irq_status == 0) {
1062 dev_err(denali->dev,
1063 "timeout on write_page (type = %d)\n",
1064 raw_xfer);
1065 denali->status =
1066 (irq_status & INTR_STATUS__PROGRAM_FAIL) ?
1067 NAND_STATUS_FAIL : PASS;
1068 }
1069
1070 denali_enable_dma(denali, false);
1071 dma_sync_single_for_cpu(denali->dev, addr, size, DMA_TO_DEVICE);
1072
1073 return 0;
1074 }
1075
1076 /* NAND core entry points */
1077
1078 /* this is the callback that the NAND core calls to write a page. Since
1079 * writing a page with ECC or without is similar, all the work is done
1080 * by write_page above.
1081 * */
1082 static int denali_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1083 const uint8_t *buf, int oob_required)
1084 {
1085 /* for regular page writes, we let HW handle all the ECC
1086 * data written to the device. */
1087 return write_page(mtd, chip, buf, false);
1088 }
1089
1090 /* This is the callback that the NAND core calls to write a page without ECC.
1091 * raw access is similar to ECC page writes, so all the work is done in the
1092 * write_page() function above.
1093 */
1094 static int denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1095 const uint8_t *buf, int oob_required)
1096 {
1097 /* for raw page writes, we want to disable ECC and simply write
1098 whatever data is in the buffer. */
1099 return write_page(mtd, chip, buf, true);
1100 }
1101
1102 static int denali_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
1103 int page)
1104 {
1105 return write_oob_data(mtd, chip->oob_poi, page);
1106 }
1107
1108 static int denali_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
1109 int page)
1110 {
1111 read_oob_data(mtd, chip->oob_poi, page);
1112
1113 return 0;
1114 }
1115
1116 static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1117 uint8_t *buf, int oob_required, int page)
1118 {
1119 unsigned int max_bitflips;
1120 struct denali_nand_info *denali = mtd_to_denali(mtd);
1121
1122 dma_addr_t addr = denali->buf.dma_buf;
1123 size_t size = denali->mtd.writesize + denali->mtd.oobsize;
1124
1125 uint32_t irq_status = 0;
1126 uint32_t irq_mask = INTR_STATUS__ECC_TRANSACTION_DONE |
1127 INTR_STATUS__ECC_ERR;
1128 bool check_erased_page = false;
1129
1130 if (page != denali->page) {
1131 dev_err(denali->dev, "IN %s: page %d is not"
1132 " equal to denali->page %d, investigate!!",
1133 __func__, page, denali->page);
1134 BUG();
1135 }
1136
1137 setup_ecc_for_xfer(denali, true, false);
1138
1139 denali_enable_dma(denali, true);
1140 dma_sync_single_for_device(denali->dev, addr, size, DMA_FROM_DEVICE);
1141
1142 clear_interrupts(denali);
1143 denali_setup_dma(denali, DENALI_READ);
1144
1145 /* wait for operation to complete */
1146 irq_status = wait_for_irq(denali, irq_mask);
1147
1148 dma_sync_single_for_cpu(denali->dev, addr, size, DMA_FROM_DEVICE);
1149
1150 memcpy(buf, denali->buf.buf, mtd->writesize);
1151
1152 check_erased_page = handle_ecc(denali, buf, irq_status, &max_bitflips);
1153 denali_enable_dma(denali, false);
1154
1155 if (check_erased_page) {
1156 read_oob_data(&denali->mtd, chip->oob_poi, denali->page);
1157
1158 /* check ECC failures that may have occurred on erased pages */
1159 if (check_erased_page) {
1160 if (!is_erased(buf, denali->mtd.writesize))
1161 denali->mtd.ecc_stats.failed++;
1162 if (!is_erased(buf, denali->mtd.oobsize))
1163 denali->mtd.ecc_stats.failed++;
1164 }
1165 }
1166 return max_bitflips;
1167 }
1168
1169 static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1170 uint8_t *buf, int oob_required, int page)
1171 {
1172 struct denali_nand_info *denali = mtd_to_denali(mtd);
1173
1174 dma_addr_t addr = denali->buf.dma_buf;
1175 size_t size = denali->mtd.writesize + denali->mtd.oobsize;
1176
1177 uint32_t irq_status = 0;
1178 uint32_t irq_mask = INTR_STATUS__DMA_CMD_COMP;
1179
1180 if (page != denali->page) {
1181 dev_err(denali->dev, "IN %s: page %d is not"
1182 " equal to denali->page %d, investigate!!",
1183 __func__, page, denali->page);
1184 BUG();
1185 }
1186
1187 setup_ecc_for_xfer(denali, false, true);
1188 denali_enable_dma(denali, true);
1189
1190 dma_sync_single_for_device(denali->dev, addr, size, DMA_FROM_DEVICE);
1191
1192 clear_interrupts(denali);
1193 denali_setup_dma(denali, DENALI_READ);
1194
1195 /* wait for operation to complete */
1196 irq_status = wait_for_irq(denali, irq_mask);
1197
1198 dma_sync_single_for_cpu(denali->dev, addr, size, DMA_FROM_DEVICE);
1199
1200 denali_enable_dma(denali, false);
1201
1202 memcpy(buf, denali->buf.buf, mtd->writesize);
1203 memcpy(chip->oob_poi, denali->buf.buf + mtd->writesize, mtd->oobsize);
1204
1205 return 0;
1206 }
1207
1208 static uint8_t denali_read_byte(struct mtd_info *mtd)
1209 {
1210 struct denali_nand_info *denali = mtd_to_denali(mtd);
1211 uint8_t result = 0xff;
1212
1213 if (denali->buf.head < denali->buf.tail)
1214 result = denali->buf.buf[denali->buf.head++];
1215
1216 return result;
1217 }
1218
1219 static void denali_select_chip(struct mtd_info *mtd, int chip)
1220 {
1221 struct denali_nand_info *denali = mtd_to_denali(mtd);
1222
1223 spin_lock_irq(&denali->irq_lock);
1224 denali->flash_bank = chip;
1225 spin_unlock_irq(&denali->irq_lock);
1226 }
1227
1228 static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip)
1229 {
1230 struct denali_nand_info *denali = mtd_to_denali(mtd);
1231 int status = denali->status;
1232 denali->status = 0;
1233
1234 return status;
1235 }
1236
1237 static void denali_erase(struct mtd_info *mtd, int page)
1238 {
1239 struct denali_nand_info *denali = mtd_to_denali(mtd);
1240
1241 uint32_t cmd = 0x0, irq_status = 0;
1242
1243 /* clear interrupts */
1244 clear_interrupts(denali);
1245
1246 /* setup page read request for access type */
1247 cmd = MODE_10 | BANK(denali->flash_bank) | page;
1248 index_addr(denali, (uint32_t)cmd, 0x1);
1249
1250 /* wait for erase to complete or failure to occur */
1251 irq_status = wait_for_irq(denali, INTR_STATUS__ERASE_COMP |
1252 INTR_STATUS__ERASE_FAIL);
1253
1254 denali->status = (irq_status & INTR_STATUS__ERASE_FAIL) ?
1255 NAND_STATUS_FAIL : PASS;
1256 }
1257
1258 static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col,
1259 int page)
1260 {
1261 struct denali_nand_info *denali = mtd_to_denali(mtd);
1262 uint32_t addr, id;
1263 int i;
1264
1265 switch (cmd) {
1266 case NAND_CMD_PAGEPROG:
1267 break;
1268 case NAND_CMD_STATUS:
1269 read_status(denali);
1270 break;
1271 case NAND_CMD_READID:
1272 case NAND_CMD_PARAM:
1273 reset_buf(denali);
1274 /*sometimes ManufactureId read from register is not right
1275 * e.g. some of Micron MT29F32G08QAA MLC NAND chips
1276 * So here we send READID cmd to NAND insteand
1277 * */
1278 addr = (uint32_t)MODE_11 | BANK(denali->flash_bank);
1279 index_addr(denali, (uint32_t)addr | 0, 0x90);
1280 index_addr(denali, (uint32_t)addr | 1, 0);
1281 for (i = 0; i < 5; i++) {
1282 index_addr_read_data(denali,
1283 (uint32_t)addr | 2,
1284 &id);
1285 write_byte_to_buf(denali, id);
1286 }
1287 break;
1288 case NAND_CMD_READ0:
1289 case NAND_CMD_SEQIN:
1290 denali->page = page;
1291 break;
1292 case NAND_CMD_RESET:
1293 reset_bank(denali);
1294 break;
1295 case NAND_CMD_READOOB:
1296 /* TODO: Read OOB data */
1297 break;
1298 default:
1299 pr_err(": unsupported command received 0x%x\n", cmd);
1300 break;
1301 }
1302 }
1303
1304 /* stubs for ECC functions not used by the NAND core */
1305 static int denali_ecc_calculate(struct mtd_info *mtd, const uint8_t *data,
1306 uint8_t *ecc_code)
1307 {
1308 struct denali_nand_info *denali = mtd_to_denali(mtd);
1309 dev_err(denali->dev,
1310 "denali_ecc_calculate called unexpectedly\n");
1311 BUG();
1312 return -EIO;
1313 }
1314
1315 static int denali_ecc_correct(struct mtd_info *mtd, uint8_t *data,
1316 uint8_t *read_ecc, uint8_t *calc_ecc)
1317 {
1318 struct denali_nand_info *denali = mtd_to_denali(mtd);
1319 dev_err(denali->dev,
1320 "denali_ecc_correct called unexpectedly\n");
1321 BUG();
1322 return -EIO;
1323 }
1324
1325 static void denali_ecc_hwctl(struct mtd_info *mtd, int mode)
1326 {
1327 struct denali_nand_info *denali = mtd_to_denali(mtd);
1328 dev_err(denali->dev,
1329 "denali_ecc_hwctl called unexpectedly\n");
1330 BUG();
1331 }
1332 /* end NAND core entry points */
1333
1334 /* Initialization code to bring the device up to a known good state */
1335 static void denali_hw_init(struct denali_nand_info *denali)
1336 {
1337 /* tell driver how many bit controller will skip before
1338 * writing ECC code in OOB, this register may be already
1339 * set by firmware. So we read this value out.
1340 * if this value is 0, just let it be.
1341 * */
1342 denali->bbtskipbytes = ioread32(denali->flash_reg +
1343 SPARE_AREA_SKIP_BYTES);
1344 detect_max_banks(denali);
1345 denali_nand_reset(denali);
1346 iowrite32(0x0F, denali->flash_reg + RB_PIN_ENABLED);
1347 iowrite32(CHIP_EN_DONT_CARE__FLAG,
1348 denali->flash_reg + CHIP_ENABLE_DONT_CARE);
1349
1350 iowrite32(0xffff, denali->flash_reg + SPARE_AREA_MARKER);
1351
1352 /* Should set value for these registers when init */
1353 iowrite32(0, denali->flash_reg + TWO_ROW_ADDR_CYCLES);
1354 iowrite32(1, denali->flash_reg + ECC_ENABLE);
1355 denali_nand_timing_set(denali);
1356 denali_irq_init(denali);
1357 }
1358
1359 /* Althogh controller spec said SLC ECC is forceb to be 4bit,
1360 * but denali controller in MRST only support 15bit and 8bit ECC
1361 * correction
1362 * */
1363 #define ECC_8BITS 14
1364 static struct nand_ecclayout nand_8bit_oob = {
1365 .eccbytes = 14,
1366 };
1367
1368 #define ECC_15BITS 26
1369 static struct nand_ecclayout nand_15bit_oob = {
1370 .eccbytes = 26,
1371 };
1372
1373 static uint8_t bbt_pattern[] = {'B', 'b', 't', '0' };
1374 static uint8_t mirror_pattern[] = {'1', 't', 'b', 'B' };
1375
1376 static struct nand_bbt_descr bbt_main_descr = {
1377 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1378 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1379 .offs = 8,
1380 .len = 4,
1381 .veroffs = 12,
1382 .maxblocks = 4,
1383 .pattern = bbt_pattern,
1384 };
1385
1386 static struct nand_bbt_descr bbt_mirror_descr = {
1387 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1388 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1389 .offs = 8,
1390 .len = 4,
1391 .veroffs = 12,
1392 .maxblocks = 4,
1393 .pattern = mirror_pattern,
1394 };
1395
1396 /* initialize driver data structures */
1397 void denali_drv_init(struct denali_nand_info *denali)
1398 {
1399 denali->idx = 0;
1400
1401 /* setup interrupt handler */
1402 /* the completion object will be used to notify
1403 * the callee that the interrupt is done */
1404 init_completion(&denali->complete);
1405
1406 /* the spinlock will be used to synchronize the ISR
1407 * with any element that might be access shared
1408 * data (interrupt status) */
1409 spin_lock_init(&denali->irq_lock);
1410
1411 /* indicate that MTD has not selected a valid bank yet */
1412 denali->flash_bank = CHIP_SELECT_INVALID;
1413
1414 /* initialize our irq_status variable to indicate no interrupts */
1415 denali->irq_status = 0;
1416 }
1417
1418 int denali_init(struct denali_nand_info *denali)
1419 {
1420 int ret;
1421
1422 if (denali->platform == INTEL_CE4100) {
1423 /* Due to a silicon limitation, we can only support
1424 * ONFI timing mode 1 and below.
1425 */
1426 if (onfi_timing_mode < -1 || onfi_timing_mode > 1) {
1427 pr_err("Intel CE4100 only supports ONFI timing mode 1 or below\n");
1428 return -EINVAL;
1429 }
1430 }
1431
1432 /* Is 32-bit DMA supported? */
1433 ret = dma_set_mask(denali->dev, DMA_BIT_MASK(32));
1434 if (ret) {
1435 pr_err("Spectra: no usable DMA configuration\n");
1436 return ret;
1437 }
1438 denali->buf.dma_buf = dma_map_single(denali->dev, denali->buf.buf,
1439 DENALI_BUF_SIZE,
1440 DMA_BIDIRECTIONAL);
1441
1442 if (dma_mapping_error(denali->dev, denali->buf.dma_buf)) {
1443 dev_err(denali->dev, "Spectra: failed to map DMA buffer\n");
1444 return -EIO;
1445 }
1446 denali->mtd.dev.parent = denali->dev;
1447 denali_hw_init(denali);
1448 denali_drv_init(denali);
1449
1450 /* denali_isr register is done after all the hardware
1451 * initilization is finished*/
1452 if (request_irq(denali->irq, denali_isr, IRQF_SHARED,
1453 DENALI_NAND_NAME, denali)) {
1454 pr_err("Spectra: Unable to allocate IRQ\n");
1455 return -ENODEV;
1456 }
1457
1458 /* now that our ISR is registered, we can enable interrupts */
1459 denali_set_intr_modes(denali, true);
1460 denali->mtd.name = "denali-nand";
1461 denali->mtd.owner = THIS_MODULE;
1462 denali->mtd.priv = &denali->nand;
1463
1464 /* register the driver with the NAND core subsystem */
1465 denali->nand.select_chip = denali_select_chip;
1466 denali->nand.cmdfunc = denali_cmdfunc;
1467 denali->nand.read_byte = denali_read_byte;
1468 denali->nand.waitfunc = denali_waitfunc;
1469
1470 /* scan for NAND devices attached to the controller
1471 * this is the first stage in a two step process to register
1472 * with the nand subsystem */
1473 if (nand_scan_ident(&denali->mtd, denali->max_banks, NULL)) {
1474 ret = -ENXIO;
1475 goto failed_req_irq;
1476 }
1477
1478 /* MTD supported page sizes vary by kernel. We validate our
1479 * kernel supports the device here.
1480 */
1481 if (denali->mtd.writesize > NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE) {
1482 ret = -ENODEV;
1483 pr_err("Spectra: device size not supported by this version of MTD.");
1484 goto failed_req_irq;
1485 }
1486
1487 /* support for multi nand
1488 * MTD known nothing about multi nand,
1489 * so we should tell it the real pagesize
1490 * and anything necessery
1491 */
1492 denali->devnum = ioread32(denali->flash_reg + DEVICES_CONNECTED);
1493 denali->nand.chipsize <<= (denali->devnum - 1);
1494 denali->nand.page_shift += (denali->devnum - 1);
1495 denali->nand.pagemask = (denali->nand.chipsize >>
1496 denali->nand.page_shift) - 1;
1497 denali->nand.bbt_erase_shift += (denali->devnum - 1);
1498 denali->nand.phys_erase_shift = denali->nand.bbt_erase_shift;
1499 denali->nand.chip_shift += (denali->devnum - 1);
1500 denali->mtd.writesize <<= (denali->devnum - 1);
1501 denali->mtd.oobsize <<= (denali->devnum - 1);
1502 denali->mtd.erasesize <<= (denali->devnum - 1);
1503 denali->mtd.size = denali->nand.numchips * denali->nand.chipsize;
1504 denali->bbtskipbytes *= denali->devnum;
1505
1506 /* second stage of the NAND scan
1507 * this stage requires information regarding ECC and
1508 * bad block management. */
1509
1510 /* Bad block management */
1511 denali->nand.bbt_td = &bbt_main_descr;
1512 denali->nand.bbt_md = &bbt_mirror_descr;
1513
1514 /* skip the scan for now until we have OOB read and write support */
1515 denali->nand.bbt_options |= NAND_BBT_USE_FLASH;
1516 denali->nand.options |= NAND_SKIP_BBTSCAN;
1517 denali->nand.ecc.mode = NAND_ECC_HW_SYNDROME;
1518
1519 /* Denali Controller only support 15bit and 8bit ECC in MRST,
1520 * so just let controller do 15bit ECC for MLC and 8bit ECC for
1521 * SLC if possible.
1522 * */
1523 if (denali->nand.cellinfo & 0xc &&
1524 (denali->mtd.oobsize > (denali->bbtskipbytes +
1525 ECC_15BITS * (denali->mtd.writesize /
1526 ECC_SECTOR_SIZE)))) {
1527 /* if MLC OOB size is large enough, use 15bit ECC*/
1528 denali->nand.ecc.strength = 15;
1529 denali->nand.ecc.layout = &nand_15bit_oob;
1530 denali->nand.ecc.bytes = ECC_15BITS;
1531 iowrite32(15, denali->flash_reg + ECC_CORRECTION);
1532 } else if (denali->mtd.oobsize < (denali->bbtskipbytes +
1533 ECC_8BITS * (denali->mtd.writesize /
1534 ECC_SECTOR_SIZE))) {
1535 pr_err("Your NAND chip OOB is not large enough to \
1536 contain 8bit ECC correction codes");
1537 goto failed_req_irq;
1538 } else {
1539 denali->nand.ecc.strength = 8;
1540 denali->nand.ecc.layout = &nand_8bit_oob;
1541 denali->nand.ecc.bytes = ECC_8BITS;
1542 iowrite32(8, denali->flash_reg + ECC_CORRECTION);
1543 }
1544
1545 denali->nand.ecc.bytes *= denali->devnum;
1546 denali->nand.ecc.strength *= denali->devnum;
1547 denali->nand.ecc.layout->eccbytes *=
1548 denali->mtd.writesize / ECC_SECTOR_SIZE;
1549 denali->nand.ecc.layout->oobfree[0].offset =
1550 denali->bbtskipbytes + denali->nand.ecc.layout->eccbytes;
1551 denali->nand.ecc.layout->oobfree[0].length =
1552 denali->mtd.oobsize - denali->nand.ecc.layout->eccbytes -
1553 denali->bbtskipbytes;
1554
1555 /* Let driver know the total blocks number and
1556 * how many blocks contained by each nand chip.
1557 * blksperchip will help driver to know how many
1558 * blocks is taken by FW.
1559 * */
1560 denali->totalblks = denali->mtd.size >>
1561 denali->nand.phys_erase_shift;
1562 denali->blksperchip = denali->totalblks / denali->nand.numchips;
1563
1564 /* These functions are required by the NAND core framework, otherwise,
1565 * the NAND core will assert. However, we don't need them, so we'll stub
1566 * them out. */
1567 denali->nand.ecc.calculate = denali_ecc_calculate;
1568 denali->nand.ecc.correct = denali_ecc_correct;
1569 denali->nand.ecc.hwctl = denali_ecc_hwctl;
1570
1571 /* override the default read operations */
1572 denali->nand.ecc.size = ECC_SECTOR_SIZE * denali->devnum;
1573 denali->nand.ecc.read_page = denali_read_page;
1574 denali->nand.ecc.read_page_raw = denali_read_page_raw;
1575 denali->nand.ecc.write_page = denali_write_page;
1576 denali->nand.ecc.write_page_raw = denali_write_page_raw;
1577 denali->nand.ecc.read_oob = denali_read_oob;
1578 denali->nand.ecc.write_oob = denali_write_oob;
1579 denali->nand.erase_cmd = denali_erase;
1580
1581 if (nand_scan_tail(&denali->mtd)) {
1582 ret = -ENXIO;
1583 goto failed_req_irq;
1584 }
1585
1586 ret = mtd_device_register(&denali->mtd, NULL, 0);
1587 if (ret) {
1588 dev_err(denali->dev, "Spectra: Failed to register MTD: %d\n",
1589 ret);
1590 goto failed_req_irq;
1591 }
1592 return 0;
1593
1594 failed_req_irq:
1595 denali_irq_cleanup(denali->irq, denali);
1596
1597 return ret;
1598 }
1599 EXPORT_SYMBOL(denali_init);
1600
1601 /* driver exit point */
1602 void denali_remove(struct denali_nand_info *denali)
1603 {
1604 denali_irq_cleanup(denali->irq, denali);
1605 dma_unmap_single(denali->dev, denali->buf.dma_buf, DENALI_BUF_SIZE,
1606 DMA_BIDIRECTIONAL);
1607 }
1608 EXPORT_SYMBOL(denali_remove);
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