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Linux 3.11-rc3
[cris-mirror.git] / drivers / net / can / mcp251x.c
blob8cda23bf0614a1ebe383660300e3ec0cd34d20e2
1 /*
2 * CAN bus driver for Microchip 251x CAN Controller with SPI Interface
3 *
4 * MCP2510 support and bug fixes by Christian Pellegrin
5 * <chripell@evolware.org>
6 *
7 * Copyright 2009 Christian Pellegrin EVOL S.r.l.
8 *
9 * Copyright 2007 Raymarine UK, Ltd. All Rights Reserved.
10 * Written under contract by:
11 * Chris Elston, Katalix Systems, Ltd.
12 *
13 * Based on Microchip MCP251x CAN controller driver written by
14 * David Vrabel, Copyright 2006 Arcom Control Systems Ltd.
15 *
16 * Based on CAN bus driver for the CCAN controller written by
17 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix
18 * - Simon Kallweit, intefo AG
19 * Copyright 2007
20 *
21 * This program is free software; you can redistribute it and/or modify
22 * it under the terms of the version 2 of the GNU General Public License
23 * as published by the Free Software Foundation
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
33 *
34 *
35 *
36 * Your platform definition file should specify something like:
37 *
38 * static struct mcp251x_platform_data mcp251x_info = {
39 * .oscillator_frequency = 8000000,
40 * .board_specific_setup = &mcp251x_setup,
41 * .power_enable = mcp251x_power_enable,
42 * .transceiver_enable = NULL,
43 * };
44 *
45 * static struct spi_board_info spi_board_info[] = {
46 * {
47 * .modalias = "mcp2510",
48 * // or "mcp2515" depending on your controller
49 * .platform_data = &mcp251x_info,
50 * .irq = IRQ_EINT13,
51 * .max_speed_hz = 2*1000*1000,
52 * .chip_select = 2,
53 * },
54 * };
55 *
56 * Please see mcp251x.h for a description of the fields in
57 * struct mcp251x_platform_data.
58 *
59 */
60
61 #include <linux/can/core.h>
62 #include <linux/can/dev.h>
63 #include <linux/can/led.h>
64 #include <linux/can/platform/mcp251x.h>
65 #include <linux/completion.h>
66 #include <linux/delay.h>
67 #include <linux/device.h>
68 #include <linux/dma-mapping.h>
69 #include <linux/freezer.h>
70 #include <linux/interrupt.h>
71 #include <linux/io.h>
72 #include <linux/kernel.h>
73 #include <linux/module.h>
74 #include <linux/netdevice.h>
75 #include <linux/platform_device.h>
76 #include <linux/slab.h>
77 #include <linux/spi/spi.h>
78 #include <linux/uaccess.h>
79
80 /* SPI interface instruction set */
81 #define INSTRUCTION_WRITE 0x02
82 #define INSTRUCTION_READ 0x03
83 #define INSTRUCTION_BIT_MODIFY 0x05
84 #define INSTRUCTION_LOAD_TXB(n) (0x40 + 2 * (n))
85 #define INSTRUCTION_READ_RXB(n) (((n) == 0) ? 0x90 : 0x94)
86 #define INSTRUCTION_RESET 0xC0
87 #define RTS_TXB0 0x01
88 #define RTS_TXB1 0x02
89 #define RTS_TXB2 0x04
90 #define INSTRUCTION_RTS(n) (0x80 | ((n) & 0x07))
91
92
93 /* MPC251x registers */
94 #define CANSTAT 0x0e
95 #define CANCTRL 0x0f
96 # define CANCTRL_REQOP_MASK 0xe0
97 # define CANCTRL_REQOP_CONF 0x80
98 # define CANCTRL_REQOP_LISTEN_ONLY 0x60
99 # define CANCTRL_REQOP_LOOPBACK 0x40
100 # define CANCTRL_REQOP_SLEEP 0x20
101 # define CANCTRL_REQOP_NORMAL 0x00
102 # define CANCTRL_OSM 0x08
103 # define CANCTRL_ABAT 0x10
104 #define TEC 0x1c
105 #define REC 0x1d
106 #define CNF1 0x2a
107 # define CNF1_SJW_SHIFT 6
108 #define CNF2 0x29
109 # define CNF2_BTLMODE 0x80
110 # define CNF2_SAM 0x40
111 # define CNF2_PS1_SHIFT 3
112 #define CNF3 0x28
113 # define CNF3_SOF 0x08
114 # define CNF3_WAKFIL 0x04
115 # define CNF3_PHSEG2_MASK 0x07
116 #define CANINTE 0x2b
117 # define CANINTE_MERRE 0x80
118 # define CANINTE_WAKIE 0x40
119 # define CANINTE_ERRIE 0x20
120 # define CANINTE_TX2IE 0x10
121 # define CANINTE_TX1IE 0x08
122 # define CANINTE_TX0IE 0x04
123 # define CANINTE_RX1IE 0x02
124 # define CANINTE_RX0IE 0x01
125 #define CANINTF 0x2c
126 # define CANINTF_MERRF 0x80
127 # define CANINTF_WAKIF 0x40
128 # define CANINTF_ERRIF 0x20
129 # define CANINTF_TX2IF 0x10
130 # define CANINTF_TX1IF 0x08
131 # define CANINTF_TX0IF 0x04
132 # define CANINTF_RX1IF 0x02
133 # define CANINTF_RX0IF 0x01
134 # define CANINTF_RX (CANINTF_RX0IF | CANINTF_RX1IF)
135 # define CANINTF_TX (CANINTF_TX2IF | CANINTF_TX1IF | CANINTF_TX0IF)
136 # define CANINTF_ERR (CANINTF_ERRIF)
137 #define EFLG 0x2d
138 # define EFLG_EWARN 0x01
139 # define EFLG_RXWAR 0x02
140 # define EFLG_TXWAR 0x04
141 # define EFLG_RXEP 0x08
142 # define EFLG_TXEP 0x10
143 # define EFLG_TXBO 0x20
144 # define EFLG_RX0OVR 0x40
145 # define EFLG_RX1OVR 0x80
146 #define TXBCTRL(n) (((n) * 0x10) + 0x30 + TXBCTRL_OFF)
147 # define TXBCTRL_ABTF 0x40
148 # define TXBCTRL_MLOA 0x20
149 # define TXBCTRL_TXERR 0x10
150 # define TXBCTRL_TXREQ 0x08
151 #define TXBSIDH(n) (((n) * 0x10) + 0x30 + TXBSIDH_OFF)
152 # define SIDH_SHIFT 3
153 #define TXBSIDL(n) (((n) * 0x10) + 0x30 + TXBSIDL_OFF)
154 # define SIDL_SID_MASK 7
155 # define SIDL_SID_SHIFT 5
156 # define SIDL_EXIDE_SHIFT 3
157 # define SIDL_EID_SHIFT 16
158 # define SIDL_EID_MASK 3
159 #define TXBEID8(n) (((n) * 0x10) + 0x30 + TXBEID8_OFF)
160 #define TXBEID0(n) (((n) * 0x10) + 0x30 + TXBEID0_OFF)
161 #define TXBDLC(n) (((n) * 0x10) + 0x30 + TXBDLC_OFF)
162 # define DLC_RTR_SHIFT 6
163 #define TXBCTRL_OFF 0
164 #define TXBSIDH_OFF 1
165 #define TXBSIDL_OFF 2
166 #define TXBEID8_OFF 3
167 #define TXBEID0_OFF 4
168 #define TXBDLC_OFF 5
169 #define TXBDAT_OFF 6
170 #define RXBCTRL(n) (((n) * 0x10) + 0x60 + RXBCTRL_OFF)
171 # define RXBCTRL_BUKT 0x04
172 # define RXBCTRL_RXM0 0x20
173 # define RXBCTRL_RXM1 0x40
174 #define RXBSIDH(n) (((n) * 0x10) + 0x60 + RXBSIDH_OFF)
175 # define RXBSIDH_SHIFT 3
176 #define RXBSIDL(n) (((n) * 0x10) + 0x60 + RXBSIDL_OFF)
177 # define RXBSIDL_IDE 0x08
178 # define RXBSIDL_SRR 0x10
179 # define RXBSIDL_EID 3
180 # define RXBSIDL_SHIFT 5
181 #define RXBEID8(n) (((n) * 0x10) + 0x60 + RXBEID8_OFF)
182 #define RXBEID0(n) (((n) * 0x10) + 0x60 + RXBEID0_OFF)
183 #define RXBDLC(n) (((n) * 0x10) + 0x60 + RXBDLC_OFF)
184 # define RXBDLC_LEN_MASK 0x0f
185 # define RXBDLC_RTR 0x40
186 #define RXBCTRL_OFF 0
187 #define RXBSIDH_OFF 1
188 #define RXBSIDL_OFF 2
189 #define RXBEID8_OFF 3
190 #define RXBEID0_OFF 4
191 #define RXBDLC_OFF 5
192 #define RXBDAT_OFF 6
193 #define RXFSIDH(n) ((n) * 4)
194 #define RXFSIDL(n) ((n) * 4 + 1)
195 #define RXFEID8(n) ((n) * 4 + 2)
196 #define RXFEID0(n) ((n) * 4 + 3)
197 #define RXMSIDH(n) ((n) * 4 + 0x20)
198 #define RXMSIDL(n) ((n) * 4 + 0x21)
199 #define RXMEID8(n) ((n) * 4 + 0x22)
200 #define RXMEID0(n) ((n) * 4 + 0x23)
201
202 #define GET_BYTE(val, byte) \
203 (((val) >> ((byte) * 8)) & 0xff)
204 #define SET_BYTE(val, byte) \
205 (((val) & 0xff) << ((byte) * 8))
206
207 /*
208 * Buffer size required for the largest SPI transfer (i.e., reading a
209 * frame)
210 */
211 #define CAN_FRAME_MAX_DATA_LEN 8
212 #define SPI_TRANSFER_BUF_LEN (6 + CAN_FRAME_MAX_DATA_LEN)
213 #define CAN_FRAME_MAX_BITS 128
214
215 #define TX_ECHO_SKB_MAX 1
216
217 #define DEVICE_NAME "mcp251x"
218
219 static int mcp251x_enable_dma; /* Enable SPI DMA. Default: 0 (Off) */
220 module_param(mcp251x_enable_dma, int, S_IRUGO);
221 MODULE_PARM_DESC(mcp251x_enable_dma, "Enable SPI DMA. Default: 0 (Off)");
222
223 static const struct can_bittiming_const mcp251x_bittiming_const = {
224 .name = DEVICE_NAME,
225 .tseg1_min = 3,
226 .tseg1_max = 16,
227 .tseg2_min = 2,
228 .tseg2_max = 8,
229 .sjw_max = 4,
230 .brp_min = 1,
231 .brp_max = 64,
232 .brp_inc = 1,
233 };
234
235 enum mcp251x_model {
236 CAN_MCP251X_MCP2510 = 0x2510,
237 CAN_MCP251X_MCP2515 = 0x2515,
238 };
239
240 struct mcp251x_priv {
241 struct can_priv can;
242 struct net_device *net;
243 struct spi_device *spi;
244 enum mcp251x_model model;
245
246 struct mutex mcp_lock; /* SPI device lock */
247
248 u8 *spi_tx_buf;
249 u8 *spi_rx_buf;
250 dma_addr_t spi_tx_dma;
251 dma_addr_t spi_rx_dma;
252
253 struct sk_buff *tx_skb;
254 int tx_len;
255
256 struct workqueue_struct *wq;
257 struct work_struct tx_work;
258 struct work_struct restart_work;
259
260 int force_quit;
261 int after_suspend;
262 #define AFTER_SUSPEND_UP 1
263 #define AFTER_SUSPEND_DOWN 2
264 #define AFTER_SUSPEND_POWER 4
265 #define AFTER_SUSPEND_RESTART 8
266 int restart_tx;
267 };
268
269 #define MCP251X_IS(_model) \
270 static inline int mcp251x_is_##_model(struct spi_device *spi) \
271 { \
272 struct mcp251x_priv *priv = spi_get_drvdata(spi); \
273 return priv->model == CAN_MCP251X_MCP##_model; \
274 }
275
276 MCP251X_IS(2510);
277 MCP251X_IS(2515);
278
279 static void mcp251x_clean(struct net_device *net)
280 {
281 struct mcp251x_priv *priv = netdev_priv(net);
282
283 if (priv->tx_skb || priv->tx_len)
284 net->stats.tx_errors++;
285 if (priv->tx_skb)
286 dev_kfree_skb(priv->tx_skb);
287 if (priv->tx_len)
288 can_free_echo_skb(priv->net, 0);
289 priv->tx_skb = NULL;
290 priv->tx_len = 0;
291 }
292
293 /*
294 * Note about handling of error return of mcp251x_spi_trans: accessing
295 * registers via SPI is not really different conceptually than using
296 * normal I/O assembler instructions, although it's much more
297 * complicated from a practical POV. So it's not advisable to always
298 * check the return value of this function. Imagine that every
299 * read{b,l}, write{b,l} and friends would be bracketed in "if ( < 0)
300 * error();", it would be a great mess (well there are some situation
301 * when exception handling C++ like could be useful after all). So we
302 * just check that transfers are OK at the beginning of our
303 * conversation with the chip and to avoid doing really nasty things
304 * (like injecting bogus packets in the network stack).
305 */
306 static int mcp251x_spi_trans(struct spi_device *spi, int len)
307 {
308 struct mcp251x_priv *priv = spi_get_drvdata(spi);
309 struct spi_transfer t = {
310 .tx_buf = priv->spi_tx_buf,
311 .rx_buf = priv->spi_rx_buf,
312 .len = len,
313 .cs_change = 0,
314 };
315 struct spi_message m;
316 int ret;
317
318 spi_message_init(&m);
319
320 if (mcp251x_enable_dma) {
321 t.tx_dma = priv->spi_tx_dma;
322 t.rx_dma = priv->spi_rx_dma;
323 m.is_dma_mapped = 1;
324 }
325
326 spi_message_add_tail(&t, &m);
327
328 ret = spi_sync(spi, &m);
329 if (ret)
330 dev_err(&spi->dev, "spi transfer failed: ret = %d\n", ret);
331 return ret;
332 }
333
334 static u8 mcp251x_read_reg(struct spi_device *spi, uint8_t reg)
335 {
336 struct mcp251x_priv *priv = spi_get_drvdata(spi);
337 u8 val = 0;
338
339 priv->spi_tx_buf[0] = INSTRUCTION_READ;
340 priv->spi_tx_buf[1] = reg;
341
342 mcp251x_spi_trans(spi, 3);
343 val = priv->spi_rx_buf[2];
344
345 return val;
346 }
347
348 static void mcp251x_read_2regs(struct spi_device *spi, uint8_t reg,
349 uint8_t *v1, uint8_t *v2)
350 {
351 struct mcp251x_priv *priv = spi_get_drvdata(spi);
352
353 priv->spi_tx_buf[0] = INSTRUCTION_READ;
354 priv->spi_tx_buf[1] = reg;
355
356 mcp251x_spi_trans(spi, 4);
357
358 *v1 = priv->spi_rx_buf[2];
359 *v2 = priv->spi_rx_buf[3];
360 }
361
362 static void mcp251x_write_reg(struct spi_device *spi, u8 reg, uint8_t val)
363 {
364 struct mcp251x_priv *priv = spi_get_drvdata(spi);
365
366 priv->spi_tx_buf[0] = INSTRUCTION_WRITE;
367 priv->spi_tx_buf[1] = reg;
368 priv->spi_tx_buf[2] = val;
369
370 mcp251x_spi_trans(spi, 3);
371 }
372
373 static void mcp251x_write_bits(struct spi_device *spi, u8 reg,
374 u8 mask, uint8_t val)
375 {
376 struct mcp251x_priv *priv = spi_get_drvdata(spi);
377
378 priv->spi_tx_buf[0] = INSTRUCTION_BIT_MODIFY;
379 priv->spi_tx_buf[1] = reg;
380 priv->spi_tx_buf[2] = mask;
381 priv->spi_tx_buf[3] = val;
382
383 mcp251x_spi_trans(spi, 4);
384 }
385
386 static void mcp251x_hw_tx_frame(struct spi_device *spi, u8 *buf,
387 int len, int tx_buf_idx)
388 {
389 struct mcp251x_priv *priv = spi_get_drvdata(spi);
390
391 if (mcp251x_is_2510(spi)) {
392 int i;
393
394 for (i = 1; i < TXBDAT_OFF + len; i++)
395 mcp251x_write_reg(spi, TXBCTRL(tx_buf_idx) + i,
396 buf[i]);
397 } else {
398 memcpy(priv->spi_tx_buf, buf, TXBDAT_OFF + len);
399 mcp251x_spi_trans(spi, TXBDAT_OFF + len);
400 }
401 }
402
403 static void mcp251x_hw_tx(struct spi_device *spi, struct can_frame *frame,
404 int tx_buf_idx)
405 {
406 struct mcp251x_priv *priv = spi_get_drvdata(spi);
407 u32 sid, eid, exide, rtr;
408 u8 buf[SPI_TRANSFER_BUF_LEN];
409
410 exide = (frame->can_id & CAN_EFF_FLAG) ? 1 : 0; /* Extended ID Enable */
411 if (exide)
412 sid = (frame->can_id & CAN_EFF_MASK) >> 18;
413 else
414 sid = frame->can_id & CAN_SFF_MASK; /* Standard ID */
415 eid = frame->can_id & CAN_EFF_MASK; /* Extended ID */
416 rtr = (frame->can_id & CAN_RTR_FLAG) ? 1 : 0; /* Remote transmission */
417
418 buf[TXBCTRL_OFF] = INSTRUCTION_LOAD_TXB(tx_buf_idx);
419 buf[TXBSIDH_OFF] = sid >> SIDH_SHIFT;
420 buf[TXBSIDL_OFF] = ((sid & SIDL_SID_MASK) << SIDL_SID_SHIFT) |
421 (exide << SIDL_EXIDE_SHIFT) |
422 ((eid >> SIDL_EID_SHIFT) & SIDL_EID_MASK);
423 buf[TXBEID8_OFF] = GET_BYTE(eid, 1);
424 buf[TXBEID0_OFF] = GET_BYTE(eid, 0);
425 buf[TXBDLC_OFF] = (rtr << DLC_RTR_SHIFT) | frame->can_dlc;
426 memcpy(buf + TXBDAT_OFF, frame->data, frame->can_dlc);
427 mcp251x_hw_tx_frame(spi, buf, frame->can_dlc, tx_buf_idx);
428
429 /* use INSTRUCTION_RTS, to avoid "repeated frame problem" */
430 priv->spi_tx_buf[0] = INSTRUCTION_RTS(1 << tx_buf_idx);
431 mcp251x_spi_trans(priv->spi, 1);
432 }
433
434 static void mcp251x_hw_rx_frame(struct spi_device *spi, u8 *buf,
435 int buf_idx)
436 {
437 struct mcp251x_priv *priv = spi_get_drvdata(spi);
438
439 if (mcp251x_is_2510(spi)) {
440 int i, len;
441
442 for (i = 1; i < RXBDAT_OFF; i++)
443 buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i);
444
445 len = get_can_dlc(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK);
446 for (; i < (RXBDAT_OFF + len); i++)
447 buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i);
448 } else {
449 priv->spi_tx_buf[RXBCTRL_OFF] = INSTRUCTION_READ_RXB(buf_idx);
450 mcp251x_spi_trans(spi, SPI_TRANSFER_BUF_LEN);
451 memcpy(buf, priv->spi_rx_buf, SPI_TRANSFER_BUF_LEN);
452 }
453 }
454
455 static void mcp251x_hw_rx(struct spi_device *spi, int buf_idx)
456 {
457 struct mcp251x_priv *priv = spi_get_drvdata(spi);
458 struct sk_buff *skb;
459 struct can_frame *frame;
460 u8 buf[SPI_TRANSFER_BUF_LEN];
461
462 skb = alloc_can_skb(priv->net, &frame);
463 if (!skb) {
464 dev_err(&spi->dev, "cannot allocate RX skb\n");
465 priv->net->stats.rx_dropped++;
466 return;
467 }
468
469 mcp251x_hw_rx_frame(spi, buf, buf_idx);
470 if (buf[RXBSIDL_OFF] & RXBSIDL_IDE) {
471 /* Extended ID format */
472 frame->can_id = CAN_EFF_FLAG;
473 frame->can_id |=
474 /* Extended ID part */
475 SET_BYTE(buf[RXBSIDL_OFF] & RXBSIDL_EID, 2) |
476 SET_BYTE(buf[RXBEID8_OFF], 1) |
477 SET_BYTE(buf[RXBEID0_OFF], 0) |
478 /* Standard ID part */
479 (((buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) |
480 (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT)) << 18);
481 /* Remote transmission request */
482 if (buf[RXBDLC_OFF] & RXBDLC_RTR)
483 frame->can_id |= CAN_RTR_FLAG;
484 } else {
485 /* Standard ID format */
486 frame->can_id =
487 (buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) |
488 (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT);
489 if (buf[RXBSIDL_OFF] & RXBSIDL_SRR)
490 frame->can_id |= CAN_RTR_FLAG;
491 }
492 /* Data length */
493 frame->can_dlc = get_can_dlc(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK);
494 memcpy(frame->data, buf + RXBDAT_OFF, frame->can_dlc);
495
496 priv->net->stats.rx_packets++;
497 priv->net->stats.rx_bytes += frame->can_dlc;
498
499 can_led_event(priv->net, CAN_LED_EVENT_RX);
500
501 netif_rx_ni(skb);
502 }
503
504 static void mcp251x_hw_sleep(struct spi_device *spi)
505 {
506 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_SLEEP);
507 }
508
509 static netdev_tx_t mcp251x_hard_start_xmit(struct sk_buff *skb,
510 struct net_device *net)
511 {
512 struct mcp251x_priv *priv = netdev_priv(net);
513 struct spi_device *spi = priv->spi;
514
515 if (priv->tx_skb || priv->tx_len) {
516 dev_warn(&spi->dev, "hard_xmit called while tx busy\n");
517 return NETDEV_TX_BUSY;
518 }
519
520 if (can_dropped_invalid_skb(net, skb))
521 return NETDEV_TX_OK;
522
523 netif_stop_queue(net);
524 priv->tx_skb = skb;
525 queue_work(priv->wq, &priv->tx_work);
526
527 return NETDEV_TX_OK;
528 }
529
530 static int mcp251x_do_set_mode(struct net_device *net, enum can_mode mode)
531 {
532 struct mcp251x_priv *priv = netdev_priv(net);
533
534 switch (mode) {
535 case CAN_MODE_START:
536 mcp251x_clean(net);
537 /* We have to delay work since SPI I/O may sleep */
538 priv->can.state = CAN_STATE_ERROR_ACTIVE;
539 priv->restart_tx = 1;
540 if (priv->can.restart_ms == 0)
541 priv->after_suspend = AFTER_SUSPEND_RESTART;
542 queue_work(priv->wq, &priv->restart_work);
543 break;
544 default:
545 return -EOPNOTSUPP;
546 }
547
548 return 0;
549 }
550
551 static int mcp251x_set_normal_mode(struct spi_device *spi)
552 {
553 struct mcp251x_priv *priv = spi_get_drvdata(spi);
554 unsigned long timeout;
555
556 /* Enable interrupts */
557 mcp251x_write_reg(spi, CANINTE,
558 CANINTE_ERRIE | CANINTE_TX2IE | CANINTE_TX1IE |
559 CANINTE_TX0IE | CANINTE_RX1IE | CANINTE_RX0IE);
560
561 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
562 /* Put device into loopback mode */
563 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LOOPBACK);
564 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) {
565 /* Put device into listen-only mode */
566 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LISTEN_ONLY);
567 } else {
568 /* Put device into normal mode */
569 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_NORMAL);
570
571 /* Wait for the device to enter normal mode */
572 timeout = jiffies + HZ;
573 while (mcp251x_read_reg(spi, CANSTAT) & CANCTRL_REQOP_MASK) {
574 schedule();
575 if (time_after(jiffies, timeout)) {
576 dev_err(&spi->dev, "MCP251x didn't"
577 " enter in normal mode\n");
578 return -EBUSY;
579 }
580 }
581 }
582 priv->can.state = CAN_STATE_ERROR_ACTIVE;
583 return 0;
584 }
585
586 static int mcp251x_do_set_bittiming(struct net_device *net)
587 {
588 struct mcp251x_priv *priv = netdev_priv(net);
589 struct can_bittiming *bt = &priv->can.bittiming;
590 struct spi_device *spi = priv->spi;
591
592 mcp251x_write_reg(spi, CNF1, ((bt->sjw - 1) << CNF1_SJW_SHIFT) |
593 (bt->brp - 1));
594 mcp251x_write_reg(spi, CNF2, CNF2_BTLMODE |
595 (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES ?
596 CNF2_SAM : 0) |
597 ((bt->phase_seg1 - 1) << CNF2_PS1_SHIFT) |
598 (bt->prop_seg - 1));
599 mcp251x_write_bits(spi, CNF3, CNF3_PHSEG2_MASK,
600 (bt->phase_seg2 - 1));
601 dev_info(&spi->dev, "CNF: 0x%02x 0x%02x 0x%02x\n",
602 mcp251x_read_reg(spi, CNF1),
603 mcp251x_read_reg(spi, CNF2),
604 mcp251x_read_reg(spi, CNF3));
605
606 return 0;
607 }
608
609 static int mcp251x_setup(struct net_device *net, struct mcp251x_priv *priv,
610 struct spi_device *spi)
611 {
612 mcp251x_do_set_bittiming(net);
613
614 mcp251x_write_reg(spi, RXBCTRL(0),
615 RXBCTRL_BUKT | RXBCTRL_RXM0 | RXBCTRL_RXM1);
616 mcp251x_write_reg(spi, RXBCTRL(1),
617 RXBCTRL_RXM0 | RXBCTRL_RXM1);
618 return 0;
619 }
620
621 static int mcp251x_hw_reset(struct spi_device *spi)
622 {
623 struct mcp251x_priv *priv = spi_get_drvdata(spi);
624 int ret;
625 unsigned long timeout;
626
627 priv->spi_tx_buf[0] = INSTRUCTION_RESET;
628 ret = spi_write(spi, priv->spi_tx_buf, 1);
629 if (ret) {
630 dev_err(&spi->dev, "reset failed: ret = %d\n", ret);
631 return -EIO;
632 }
633
634 /* Wait for reset to finish */
635 timeout = jiffies + HZ;
636 mdelay(10);
637 while ((mcp251x_read_reg(spi, CANSTAT) & CANCTRL_REQOP_MASK)
638 != CANCTRL_REQOP_CONF) {
639 schedule();
640 if (time_after(jiffies, timeout)) {
641 dev_err(&spi->dev, "MCP251x didn't"
642 " enter in conf mode after reset\n");
643 return -EBUSY;
644 }
645 }
646 return 0;
647 }
648
649 static int mcp251x_hw_probe(struct spi_device *spi)
650 {
651 int st1, st2;
652
653 mcp251x_hw_reset(spi);
654
655 /*
656 * Please note that these are "magic values" based on after
657 * reset defaults taken from data sheet which allows us to see
658 * if we really have a chip on the bus (we avoid common all
659 * zeroes or all ones situations)
660 */
661 st1 = mcp251x_read_reg(spi, CANSTAT) & 0xEE;
662 st2 = mcp251x_read_reg(spi, CANCTRL) & 0x17;
663
664 dev_dbg(&spi->dev, "CANSTAT 0x%02x CANCTRL 0x%02x\n", st1, st2);
665
666 /* Check for power up default values */
667 return (st1 == 0x80 && st2 == 0x07) ? 1 : 0;
668 }
669
670 static void mcp251x_open_clean(struct net_device *net)
671 {
672 struct mcp251x_priv *priv = netdev_priv(net);
673 struct spi_device *spi = priv->spi;
674 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
675
676 free_irq(spi->irq, priv);
677 mcp251x_hw_sleep(spi);
678 if (pdata->transceiver_enable)
679 pdata->transceiver_enable(0);
680 close_candev(net);
681 }
682
683 static int mcp251x_stop(struct net_device *net)
684 {
685 struct mcp251x_priv *priv = netdev_priv(net);
686 struct spi_device *spi = priv->spi;
687 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
688
689 close_candev(net);
690
691 priv->force_quit = 1;
692 free_irq(spi->irq, priv);
693 destroy_workqueue(priv->wq);
694 priv->wq = NULL;
695
696 mutex_lock(&priv->mcp_lock);
697
698 /* Disable and clear pending interrupts */
699 mcp251x_write_reg(spi, CANINTE, 0x00);
700 mcp251x_write_reg(spi, CANINTF, 0x00);
701
702 mcp251x_write_reg(spi, TXBCTRL(0), 0);
703 mcp251x_clean(net);
704
705 mcp251x_hw_sleep(spi);
706
707 if (pdata->transceiver_enable)
708 pdata->transceiver_enable(0);
709
710 priv->can.state = CAN_STATE_STOPPED;
711
712 mutex_unlock(&priv->mcp_lock);
713
714 can_led_event(net, CAN_LED_EVENT_STOP);
715
716 return 0;
717 }
718
719 static void mcp251x_error_skb(struct net_device *net, int can_id, int data1)
720 {
721 struct sk_buff *skb;
722 struct can_frame *frame;
723
724 skb = alloc_can_err_skb(net, &frame);
725 if (skb) {
726 frame->can_id |= can_id;
727 frame->data[1] = data1;
728 netif_rx_ni(skb);
729 } else {
730 netdev_err(net, "cannot allocate error skb\n");
731 }
732 }
733
734 static void mcp251x_tx_work_handler(struct work_struct *ws)
735 {
736 struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv,
737 tx_work);
738 struct spi_device *spi = priv->spi;
739 struct net_device *net = priv->net;
740 struct can_frame *frame;
741
742 mutex_lock(&priv->mcp_lock);
743 if (priv->tx_skb) {
744 if (priv->can.state == CAN_STATE_BUS_OFF) {
745 mcp251x_clean(net);
746 } else {
747 frame = (struct can_frame *)priv->tx_skb->data;
748
749 if (frame->can_dlc > CAN_FRAME_MAX_DATA_LEN)
750 frame->can_dlc = CAN_FRAME_MAX_DATA_LEN;
751 mcp251x_hw_tx(spi, frame, 0);
752 priv->tx_len = 1 + frame->can_dlc;
753 can_put_echo_skb(priv->tx_skb, net, 0);
754 priv->tx_skb = NULL;
755 }
756 }
757 mutex_unlock(&priv->mcp_lock);
758 }
759
760 static void mcp251x_restart_work_handler(struct work_struct *ws)
761 {
762 struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv,
763 restart_work);
764 struct spi_device *spi = priv->spi;
765 struct net_device *net = priv->net;
766
767 mutex_lock(&priv->mcp_lock);
768 if (priv->after_suspend) {
769 mdelay(10);
770 mcp251x_hw_reset(spi);
771 mcp251x_setup(net, priv, spi);
772 if (priv->after_suspend & AFTER_SUSPEND_RESTART) {
773 mcp251x_set_normal_mode(spi);
774 } else if (priv->after_suspend & AFTER_SUSPEND_UP) {
775 netif_device_attach(net);
776 mcp251x_clean(net);
777 mcp251x_set_normal_mode(spi);
778 netif_wake_queue(net);
779 } else {
780 mcp251x_hw_sleep(spi);
781 }
782 priv->after_suspend = 0;
783 priv->force_quit = 0;
784 }
785
786 if (priv->restart_tx) {
787 priv->restart_tx = 0;
788 mcp251x_write_reg(spi, TXBCTRL(0), 0);
789 mcp251x_clean(net);
790 netif_wake_queue(net);
791 mcp251x_error_skb(net, CAN_ERR_RESTARTED, 0);
792 }
793 mutex_unlock(&priv->mcp_lock);
794 }
795
796 static irqreturn_t mcp251x_can_ist(int irq, void *dev_id)
797 {
798 struct mcp251x_priv *priv = dev_id;
799 struct spi_device *spi = priv->spi;
800 struct net_device *net = priv->net;
801
802 mutex_lock(&priv->mcp_lock);
803 while (!priv->force_quit) {
804 enum can_state new_state;
805 u8 intf, eflag;
806 u8 clear_intf = 0;
807 int can_id = 0, data1 = 0;
808
809 mcp251x_read_2regs(spi, CANINTF, &intf, &eflag);
810
811 /* mask out flags we don't care about */
812 intf &= CANINTF_RX | CANINTF_TX | CANINTF_ERR;
813
814 /* receive buffer 0 */
815 if (intf & CANINTF_RX0IF) {
816 mcp251x_hw_rx(spi, 0);
817 /*
818 * Free one buffer ASAP
819 * (The MCP2515 does this automatically.)
820 */
821 if (mcp251x_is_2510(spi))
822 mcp251x_write_bits(spi, CANINTF, CANINTF_RX0IF, 0x00);
823 }
824
825 /* receive buffer 1 */
826 if (intf & CANINTF_RX1IF) {
827 mcp251x_hw_rx(spi, 1);
828 /* the MCP2515 does this automatically */
829 if (mcp251x_is_2510(spi))
830 clear_intf |= CANINTF_RX1IF;
831 }
832
833 /* any error or tx interrupt we need to clear? */
834 if (intf & (CANINTF_ERR | CANINTF_TX))
835 clear_intf |= intf & (CANINTF_ERR | CANINTF_TX);
836 if (clear_intf)
837 mcp251x_write_bits(spi, CANINTF, clear_intf, 0x00);
838
839 if (eflag)
840 mcp251x_write_bits(spi, EFLG, eflag, 0x00);
841
842 /* Update can state */
843 if (eflag & EFLG_TXBO) {
844 new_state = CAN_STATE_BUS_OFF;
845 can_id |= CAN_ERR_BUSOFF;
846 } else if (eflag & EFLG_TXEP) {
847 new_state = CAN_STATE_ERROR_PASSIVE;
848 can_id |= CAN_ERR_CRTL;
849 data1 |= CAN_ERR_CRTL_TX_PASSIVE;
850 } else if (eflag & EFLG_RXEP) {
851 new_state = CAN_STATE_ERROR_PASSIVE;
852 can_id |= CAN_ERR_CRTL;
853 data1 |= CAN_ERR_CRTL_RX_PASSIVE;
854 } else if (eflag & EFLG_TXWAR) {
855 new_state = CAN_STATE_ERROR_WARNING;
856 can_id |= CAN_ERR_CRTL;
857 data1 |= CAN_ERR_CRTL_TX_WARNING;
858 } else if (eflag & EFLG_RXWAR) {
859 new_state = CAN_STATE_ERROR_WARNING;
860 can_id |= CAN_ERR_CRTL;
861 data1 |= CAN_ERR_CRTL_RX_WARNING;
862 } else {
863 new_state = CAN_STATE_ERROR_ACTIVE;
864 }
865
866 /* Update can state statistics */
867 switch (priv->can.state) {
868 case CAN_STATE_ERROR_ACTIVE:
869 if (new_state >= CAN_STATE_ERROR_WARNING &&
870 new_state <= CAN_STATE_BUS_OFF)
871 priv->can.can_stats.error_warning++;
872 case CAN_STATE_ERROR_WARNING: /* fallthrough */
873 if (new_state >= CAN_STATE_ERROR_PASSIVE &&
874 new_state <= CAN_STATE_BUS_OFF)
875 priv->can.can_stats.error_passive++;
876 break;
877 default:
878 break;
879 }
880 priv->can.state = new_state;
881
882 if (intf & CANINTF_ERRIF) {
883 /* Handle overflow counters */
884 if (eflag & (EFLG_RX0OVR | EFLG_RX1OVR)) {
885 if (eflag & EFLG_RX0OVR) {
886 net->stats.rx_over_errors++;
887 net->stats.rx_errors++;
888 }
889 if (eflag & EFLG_RX1OVR) {
890 net->stats.rx_over_errors++;
891 net->stats.rx_errors++;
892 }
893 can_id |= CAN_ERR_CRTL;
894 data1 |= CAN_ERR_CRTL_RX_OVERFLOW;
895 }
896 mcp251x_error_skb(net, can_id, data1);
897 }
898
899 if (priv->can.state == CAN_STATE_BUS_OFF) {
900 if (priv->can.restart_ms == 0) {
901 priv->force_quit = 1;
902 can_bus_off(net);
903 mcp251x_hw_sleep(spi);
904 break;
905 }
906 }
907
908 if (intf == 0)
909 break;
910
911 if (intf & CANINTF_TX) {
912 net->stats.tx_packets++;
913 net->stats.tx_bytes += priv->tx_len - 1;
914 can_led_event(net, CAN_LED_EVENT_TX);
915 if (priv->tx_len) {
916 can_get_echo_skb(net, 0);
917 priv->tx_len = 0;
918 }
919 netif_wake_queue(net);
920 }
921
922 }
923 mutex_unlock(&priv->mcp_lock);
924 return IRQ_HANDLED;
925 }
926
927 static int mcp251x_open(struct net_device *net)
928 {
929 struct mcp251x_priv *priv = netdev_priv(net);
930 struct spi_device *spi = priv->spi;
931 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
932 unsigned long flags;
933 int ret;
934
935 ret = open_candev(net);
936 if (ret) {
937 dev_err(&spi->dev, "unable to set initial baudrate!\n");
938 return ret;
939 }
940
941 mutex_lock(&priv->mcp_lock);
942 if (pdata->transceiver_enable)
943 pdata->transceiver_enable(1);
944
945 priv->force_quit = 0;
946 priv->tx_skb = NULL;
947 priv->tx_len = 0;
948
949 flags = IRQF_ONESHOT;
950 if (pdata->irq_flags)
951 flags |= pdata->irq_flags;
952 else
953 flags |= IRQF_TRIGGER_FALLING;
954
955 ret = request_threaded_irq(spi->irq, NULL, mcp251x_can_ist,
956 flags, DEVICE_NAME, priv);
957 if (ret) {
958 dev_err(&spi->dev, "failed to acquire irq %d\n", spi->irq);
959 if (pdata->transceiver_enable)
960 pdata->transceiver_enable(0);
961 close_candev(net);
962 goto open_unlock;
963 }
964
965 priv->wq = create_freezable_workqueue("mcp251x_wq");
966 INIT_WORK(&priv->tx_work, mcp251x_tx_work_handler);
967 INIT_WORK(&priv->restart_work, mcp251x_restart_work_handler);
968
969 ret = mcp251x_hw_reset(spi);
970 if (ret) {
971 mcp251x_open_clean(net);
972 goto open_unlock;
973 }
974 ret = mcp251x_setup(net, priv, spi);
975 if (ret) {
976 mcp251x_open_clean(net);
977 goto open_unlock;
978 }
979 ret = mcp251x_set_normal_mode(spi);
980 if (ret) {
981 mcp251x_open_clean(net);
982 goto open_unlock;
983 }
984
985 can_led_event(net, CAN_LED_EVENT_OPEN);
986
987 netif_wake_queue(net);
988
989 open_unlock:
990 mutex_unlock(&priv->mcp_lock);
991 return ret;
992 }
993
994 static const struct net_device_ops mcp251x_netdev_ops = {
995 .ndo_open = mcp251x_open,
996 .ndo_stop = mcp251x_stop,
997 .ndo_start_xmit = mcp251x_hard_start_xmit,
998 };
999
1000 static int mcp251x_can_probe(struct spi_device *spi)
1001 {
1002 struct net_device *net;
1003 struct mcp251x_priv *priv;
1004 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
1005 int ret = -ENODEV;
1006
1007 if (!pdata)
1008 /* Platform data is required for osc freq */
1009 goto error_out;
1010
1011 /* Allocate can/net device */
1012 net = alloc_candev(sizeof(struct mcp251x_priv), TX_ECHO_SKB_MAX);
1013 if (!net) {
1014 ret = -ENOMEM;
1015 goto error_alloc;
1016 }
1017
1018 net->netdev_ops = &mcp251x_netdev_ops;
1019 net->flags |= IFF_ECHO;
1020
1021 priv = netdev_priv(net);
1022 priv->can.bittiming_const = &mcp251x_bittiming_const;
1023 priv->can.do_set_mode = mcp251x_do_set_mode;
1024 priv->can.clock.freq = pdata->oscillator_frequency / 2;
1025 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES |
1026 CAN_CTRLMODE_LOOPBACK | CAN_CTRLMODE_LISTENONLY;
1027 priv->model = spi_get_device_id(spi)->driver_data;
1028 priv->net = net;
1029 spi_set_drvdata(spi, priv);
1030
1031 priv->spi = spi;
1032 mutex_init(&priv->mcp_lock);
1033
1034 /* If requested, allocate DMA buffers */
1035 if (mcp251x_enable_dma) {
1036 spi->dev.coherent_dma_mask = ~0;
1037
1038 /*
1039 * Minimum coherent DMA allocation is PAGE_SIZE, so allocate
1040 * that much and share it between Tx and Rx DMA buffers.
1041 */
1042 priv->spi_tx_buf = dma_alloc_coherent(&spi->dev,
1043 PAGE_SIZE,
1044 &priv->spi_tx_dma,
1045 GFP_DMA);
1046
1047 if (priv->spi_tx_buf) {
1048 priv->spi_rx_buf = (priv->spi_tx_buf + (PAGE_SIZE / 2));
1049 priv->spi_rx_dma = (dma_addr_t)(priv->spi_tx_dma +
1050 (PAGE_SIZE / 2));
1051 } else {
1052 /* Fall back to non-DMA */
1053 mcp251x_enable_dma = 0;
1054 }
1055 }
1056
1057 /* Allocate non-DMA buffers */
1058 if (!mcp251x_enable_dma) {
1059 priv->spi_tx_buf = kmalloc(SPI_TRANSFER_BUF_LEN, GFP_KERNEL);
1060 if (!priv->spi_tx_buf) {
1061 ret = -ENOMEM;
1062 goto error_tx_buf;
1063 }
1064 priv->spi_rx_buf = kmalloc(SPI_TRANSFER_BUF_LEN, GFP_KERNEL);
1065 if (!priv->spi_rx_buf) {
1066 ret = -ENOMEM;
1067 goto error_rx_buf;
1068 }
1069 }
1070
1071 if (pdata->power_enable)
1072 pdata->power_enable(1);
1073
1074 /* Call out to platform specific setup */
1075 if (pdata->board_specific_setup)
1076 pdata->board_specific_setup(spi);
1077
1078 SET_NETDEV_DEV(net, &spi->dev);
1079
1080 /* Configure the SPI bus */
1081 spi->mode = SPI_MODE_0;
1082 spi->bits_per_word = 8;
1083 spi_setup(spi);
1084
1085 /* Here is OK to not lock the MCP, no one knows about it yet */
1086 if (!mcp251x_hw_probe(spi)) {
1087 dev_info(&spi->dev, "Probe failed\n");
1088 goto error_probe;
1089 }
1090 mcp251x_hw_sleep(spi);
1091
1092 if (pdata->transceiver_enable)
1093 pdata->transceiver_enable(0);
1094
1095 ret = register_candev(net);
1096 if (ret)
1097 goto error_probe;
1098
1099 devm_can_led_init(net);
1100
1101 dev_info(&spi->dev, "probed\n");
1102
1103 return ret;
1104
1105 error_probe:
1106 if (!mcp251x_enable_dma)
1107 kfree(priv->spi_rx_buf);
1108 error_rx_buf:
1109 if (!mcp251x_enable_dma)
1110 kfree(priv->spi_tx_buf);
1111 error_tx_buf:
1112 free_candev(net);
1113 if (mcp251x_enable_dma)
1114 dma_free_coherent(&spi->dev, PAGE_SIZE,
1115 priv->spi_tx_buf, priv->spi_tx_dma);
1116 error_alloc:
1117 if (pdata->power_enable)
1118 pdata->power_enable(0);
1119 dev_err(&spi->dev, "probe failed\n");
1120 error_out:
1121 return ret;
1122 }
1123
1124 static int mcp251x_can_remove(struct spi_device *spi)
1125 {
1126 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
1127 struct mcp251x_priv *priv = spi_get_drvdata(spi);
1128 struct net_device *net = priv->net;
1129
1130 unregister_candev(net);
1131 free_candev(net);
1132
1133 if (mcp251x_enable_dma) {
1134 dma_free_coherent(&spi->dev, PAGE_SIZE,
1135 priv->spi_tx_buf, priv->spi_tx_dma);
1136 } else {
1137 kfree(priv->spi_tx_buf);
1138 kfree(priv->spi_rx_buf);
1139 }
1140
1141 if (pdata->power_enable)
1142 pdata->power_enable(0);
1143
1144 return 0;
1145 }
1146
1147 #ifdef CONFIG_PM_SLEEP
1148
1149 static int mcp251x_can_suspend(struct device *dev)
1150 {
1151 struct spi_device *spi = to_spi_device(dev);
1152 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
1153 struct mcp251x_priv *priv = spi_get_drvdata(spi);
1154 struct net_device *net = priv->net;
1155
1156 priv->force_quit = 1;
1157 disable_irq(spi->irq);
1158 /*
1159 * Note: at this point neither IST nor workqueues are running.
1160 * open/stop cannot be called anyway so locking is not needed
1161 */
1162 if (netif_running(net)) {
1163 netif_device_detach(net);
1164
1165 mcp251x_hw_sleep(spi);
1166 if (pdata->transceiver_enable)
1167 pdata->transceiver_enable(0);
1168 priv->after_suspend = AFTER_SUSPEND_UP;
1169 } else {
1170 priv->after_suspend = AFTER_SUSPEND_DOWN;
1171 }
1172
1173 if (pdata->power_enable) {
1174 pdata->power_enable(0);
1175 priv->after_suspend |= AFTER_SUSPEND_POWER;
1176 }
1177
1178 return 0;
1179 }
1180
1181 static int mcp251x_can_resume(struct device *dev)
1182 {
1183 struct spi_device *spi = to_spi_device(dev);
1184 struct mcp251x_platform_data *pdata = spi->dev.platform_data;
1185 struct mcp251x_priv *priv = spi_get_drvdata(spi);
1186
1187 if (priv->after_suspend & AFTER_SUSPEND_POWER) {
1188 pdata->power_enable(1);
1189 queue_work(priv->wq, &priv->restart_work);
1190 } else {
1191 if (priv->after_suspend & AFTER_SUSPEND_UP) {
1192 if (pdata->transceiver_enable)
1193 pdata->transceiver_enable(1);
1194 queue_work(priv->wq, &priv->restart_work);
1195 } else {
1196 priv->after_suspend = 0;
1197 }
1198 }
1199 priv->force_quit = 0;
1200 enable_irq(spi->irq);
1201 return 0;
1202 }
1203 #endif
1204
1205 static SIMPLE_DEV_PM_OPS(mcp251x_can_pm_ops, mcp251x_can_suspend,
1206 mcp251x_can_resume);
1207
1208 static const struct spi_device_id mcp251x_id_table[] = {
1209 { "mcp2510", CAN_MCP251X_MCP2510 },
1210 { "mcp2515", CAN_MCP251X_MCP2515 },
1211 { },
1212 };
1213
1214 MODULE_DEVICE_TABLE(spi, mcp251x_id_table);
1215
1216 static struct spi_driver mcp251x_can_driver = {
1217 .driver = {
1218 .name = DEVICE_NAME,
1219 .owner = THIS_MODULE,
1220 .pm = &mcp251x_can_pm_ops,
1221 },
1222
1223 .id_table = mcp251x_id_table,
1224 .probe = mcp251x_can_probe,
1225 .remove = mcp251x_can_remove,
1226 };
1227 module_spi_driver(mcp251x_can_driver);
1228
1229 MODULE_AUTHOR("Chris Elston <celston@katalix.com>, "
1230 "Christian Pellegrin <chripell@evolware.org>");
1231 MODULE_DESCRIPTION("Microchip 251x CAN driver");
1232 MODULE_LICENSE("GPL v2");
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