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Linux 3.11-rc3
[cris-mirror.git] / drivers / net / can / ti_hecc.c
blob3a349a22d5bc46eed31bdc32e12d27c25df3bd13
1 /*
2 * TI HECC (CAN) device driver
3 *
4 * This driver supports TI's HECC (High End CAN Controller module) and the
5 * specs for the same is available at <http://www.ti.com>
6 *
7 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation version 2.
12 *
13 * This program is distributed as is WITHOUT ANY WARRANTY of any
14 * kind, whether express or implied; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20 /*
21 * Your platform definitions should specify module ram offsets and interrupt
22 * number to use as follows:
23 *
24 * static struct ti_hecc_platform_data am3517_evm_hecc_pdata = {
25 * .scc_hecc_offset = 0,
26 * .scc_ram_offset = 0x3000,
27 * .hecc_ram_offset = 0x3000,
28 * .mbx_offset = 0x2000,
29 * .int_line = 0,
30 * .revision = 1,
31 * .transceiver_switch = hecc_phy_control,
32 * };
33 *
34 * Please see include/linux/can/platform/ti_hecc.h for description of
35 * above fields.
36 *
37 */
38
39 #include <linux/module.h>
40 #include <linux/init.h>
41 #include <linux/kernel.h>
42 #include <linux/types.h>
43 #include <linux/interrupt.h>
44 #include <linux/errno.h>
45 #include <linux/netdevice.h>
46 #include <linux/skbuff.h>
47 #include <linux/platform_device.h>
48 #include <linux/clk.h>
49 #include <linux/io.h>
50
51 #include <linux/can/dev.h>
52 #include <linux/can/error.h>
53 #include <linux/can/led.h>
54 #include <linux/can/platform/ti_hecc.h>
55
56 #define DRV_NAME "ti_hecc"
57 #define HECC_MODULE_VERSION "0.7"
58 MODULE_VERSION(HECC_MODULE_VERSION);
59 #define DRV_DESC "TI High End CAN Controller Driver " HECC_MODULE_VERSION
60
61 /* TX / RX Mailbox Configuration */
62 #define HECC_MAX_MAILBOXES 32 /* hardware mailboxes - do not change */
63 #define MAX_TX_PRIO 0x3F /* hardware value - do not change */
64
65 /*
66 * Important Note: TX mailbox configuration
67 * TX mailboxes should be restricted to the number of SKB buffers to avoid
68 * maintaining SKB buffers separately. TX mailboxes should be a power of 2
69 * for the mailbox logic to work. Top mailbox numbers are reserved for RX
70 * and lower mailboxes for TX.
71 *
72 * HECC_MAX_TX_MBOX HECC_MB_TX_SHIFT
73 * 4 (default) 2
74 * 8 3
75 * 16 4
76 */
77 #define HECC_MB_TX_SHIFT 2 /* as per table above */
78 #define HECC_MAX_TX_MBOX BIT(HECC_MB_TX_SHIFT)
79
80 #define HECC_TX_PRIO_SHIFT (HECC_MB_TX_SHIFT)
81 #define HECC_TX_PRIO_MASK (MAX_TX_PRIO << HECC_MB_TX_SHIFT)
82 #define HECC_TX_MB_MASK (HECC_MAX_TX_MBOX - 1)
83 #define HECC_TX_MASK ((HECC_MAX_TX_MBOX - 1) | HECC_TX_PRIO_MASK)
84 #define HECC_TX_MBOX_MASK (~(BIT(HECC_MAX_TX_MBOX) - 1))
85 #define HECC_DEF_NAPI_WEIGHT HECC_MAX_RX_MBOX
86
87 /*
88 * Important Note: RX mailbox configuration
89 * RX mailboxes are further logically split into two - main and buffer
90 * mailboxes. The goal is to get all packets into main mailboxes as
91 * driven by mailbox number and receive priority (higher to lower) and
92 * buffer mailboxes are used to receive pkts while main mailboxes are being
93 * processed. This ensures in-order packet reception.
94 *
95 * Here are the recommended values for buffer mailbox. Note that RX mailboxes
96 * start after TX mailboxes:
97 *
98 * HECC_MAX_RX_MBOX HECC_RX_BUFFER_MBOX No of buffer mailboxes
99 * 28 12 8
100 * 16 20 4
101 */
102
103 #define HECC_MAX_RX_MBOX (HECC_MAX_MAILBOXES - HECC_MAX_TX_MBOX)
104 #define HECC_RX_BUFFER_MBOX 12 /* as per table above */
105 #define HECC_RX_FIRST_MBOX (HECC_MAX_MAILBOXES - 1)
106 #define HECC_RX_HIGH_MBOX_MASK (~(BIT(HECC_RX_BUFFER_MBOX) - 1))
107
108 /* TI HECC module registers */
109 #define HECC_CANME 0x0 /* Mailbox enable */
110 #define HECC_CANMD 0x4 /* Mailbox direction */
111 #define HECC_CANTRS 0x8 /* Transmit request set */
112 #define HECC_CANTRR 0xC /* Transmit request */
113 #define HECC_CANTA 0x10 /* Transmission acknowledge */
114 #define HECC_CANAA 0x14 /* Abort acknowledge */
115 #define HECC_CANRMP 0x18 /* Receive message pending */
116 #define HECC_CANRML 0x1C /* Remote message lost */
117 #define HECC_CANRFP 0x20 /* Remote frame pending */
118 #define HECC_CANGAM 0x24 /* SECC only:Global acceptance mask */
119 #define HECC_CANMC 0x28 /* Master control */
120 #define HECC_CANBTC 0x2C /* Bit timing configuration */
121 #define HECC_CANES 0x30 /* Error and status */
122 #define HECC_CANTEC 0x34 /* Transmit error counter */
123 #define HECC_CANREC 0x38 /* Receive error counter */
124 #define HECC_CANGIF0 0x3C /* Global interrupt flag 0 */
125 #define HECC_CANGIM 0x40 /* Global interrupt mask */
126 #define HECC_CANGIF1 0x44 /* Global interrupt flag 1 */
127 #define HECC_CANMIM 0x48 /* Mailbox interrupt mask */
128 #define HECC_CANMIL 0x4C /* Mailbox interrupt level */
129 #define HECC_CANOPC 0x50 /* Overwrite protection control */
130 #define HECC_CANTIOC 0x54 /* Transmit I/O control */
131 #define HECC_CANRIOC 0x58 /* Receive I/O control */
132 #define HECC_CANLNT 0x5C /* HECC only: Local network time */
133 #define HECC_CANTOC 0x60 /* HECC only: Time-out control */
134 #define HECC_CANTOS 0x64 /* HECC only: Time-out status */
135 #define HECC_CANTIOCE 0x68 /* SCC only:Enhanced TX I/O control */
136 #define HECC_CANRIOCE 0x6C /* SCC only:Enhanced RX I/O control */
137
138 /* Mailbox registers */
139 #define HECC_CANMID 0x0
140 #define HECC_CANMCF 0x4
141 #define HECC_CANMDL 0x8
142 #define HECC_CANMDH 0xC
143
144 #define HECC_SET_REG 0xFFFFFFFF
145 #define HECC_CANID_MASK 0x3FF /* 18 bits mask for extended id's */
146 #define HECC_CCE_WAIT_COUNT 100 /* Wait for ~1 sec for CCE bit */
147
148 #define HECC_CANMC_SCM BIT(13) /* SCC compat mode */
149 #define HECC_CANMC_CCR BIT(12) /* Change config request */
150 #define HECC_CANMC_PDR BIT(11) /* Local Power down - for sleep mode */
151 #define HECC_CANMC_ABO BIT(7) /* Auto Bus On */
152 #define HECC_CANMC_STM BIT(6) /* Self test mode - loopback */
153 #define HECC_CANMC_SRES BIT(5) /* Software reset */
154
155 #define HECC_CANTIOC_EN BIT(3) /* Enable CAN TX I/O pin */
156 #define HECC_CANRIOC_EN BIT(3) /* Enable CAN RX I/O pin */
157
158 #define HECC_CANMID_IDE BIT(31) /* Extended frame format */
159 #define HECC_CANMID_AME BIT(30) /* Acceptance mask enable */
160 #define HECC_CANMID_AAM BIT(29) /* Auto answer mode */
161
162 #define HECC_CANES_FE BIT(24) /* form error */
163 #define HECC_CANES_BE BIT(23) /* bit error */
164 #define HECC_CANES_SA1 BIT(22) /* stuck at dominant error */
165 #define HECC_CANES_CRCE BIT(21) /* CRC error */
166 #define HECC_CANES_SE BIT(20) /* stuff bit error */
167 #define HECC_CANES_ACKE BIT(19) /* ack error */
168 #define HECC_CANES_BO BIT(18) /* Bus off status */
169 #define HECC_CANES_EP BIT(17) /* Error passive status */
170 #define HECC_CANES_EW BIT(16) /* Error warning status */
171 #define HECC_CANES_SMA BIT(5) /* suspend mode ack */
172 #define HECC_CANES_CCE BIT(4) /* Change config enabled */
173 #define HECC_CANES_PDA BIT(3) /* Power down mode ack */
174
175 #define HECC_CANBTC_SAM BIT(7) /* sample points */
176
177 #define HECC_BUS_ERROR (HECC_CANES_FE | HECC_CANES_BE |\
178 HECC_CANES_CRCE | HECC_CANES_SE |\
179 HECC_CANES_ACKE)
180
181 #define HECC_CANMCF_RTR BIT(4) /* Remote transmit request */
182
183 #define HECC_CANGIF_MAIF BIT(17) /* Message alarm interrupt */
184 #define HECC_CANGIF_TCOIF BIT(16) /* Timer counter overflow int */
185 #define HECC_CANGIF_GMIF BIT(15) /* Global mailbox interrupt */
186 #define HECC_CANGIF_AAIF BIT(14) /* Abort ack interrupt */
187 #define HECC_CANGIF_WDIF BIT(13) /* Write denied interrupt */
188 #define HECC_CANGIF_WUIF BIT(12) /* Wake up interrupt */
189 #define HECC_CANGIF_RMLIF BIT(11) /* Receive message lost interrupt */
190 #define HECC_CANGIF_BOIF BIT(10) /* Bus off interrupt */
191 #define HECC_CANGIF_EPIF BIT(9) /* Error passive interrupt */
192 #define HECC_CANGIF_WLIF BIT(8) /* Warning level interrupt */
193 #define HECC_CANGIF_MBOX_MASK 0x1F /* Mailbox number mask */
194 #define HECC_CANGIM_I1EN BIT(1) /* Int line 1 enable */
195 #define HECC_CANGIM_I0EN BIT(0) /* Int line 0 enable */
196 #define HECC_CANGIM_DEF_MASK 0x700 /* only busoff/warning/passive */
197 #define HECC_CANGIM_SIL BIT(2) /* system interrupts to int line 1 */
198
199 /* CAN Bittiming constants as per HECC specs */
200 static const struct can_bittiming_const ti_hecc_bittiming_const = {
201 .name = DRV_NAME,
202 .tseg1_min = 1,
203 .tseg1_max = 16,
204 .tseg2_min = 1,
205 .tseg2_max = 8,
206 .sjw_max = 4,
207 .brp_min = 1,
208 .brp_max = 256,
209 .brp_inc = 1,
210 };
211
212 struct ti_hecc_priv {
213 struct can_priv can; /* MUST be first member/field */
214 struct napi_struct napi;
215 struct net_device *ndev;
216 struct clk *clk;
217 void __iomem *base;
218 u32 scc_ram_offset;
219 u32 hecc_ram_offset;
220 u32 mbx_offset;
221 u32 int_line;
222 spinlock_t mbx_lock; /* CANME register needs protection */
223 u32 tx_head;
224 u32 tx_tail;
225 u32 rx_next;
226 void (*transceiver_switch)(int);
227 };
228
229 static inline int get_tx_head_mb(struct ti_hecc_priv *priv)
230 {
231 return priv->tx_head & HECC_TX_MB_MASK;
232 }
233
234 static inline int get_tx_tail_mb(struct ti_hecc_priv *priv)
235 {
236 return priv->tx_tail & HECC_TX_MB_MASK;
237 }
238
239 static inline int get_tx_head_prio(struct ti_hecc_priv *priv)
240 {
241 return (priv->tx_head >> HECC_TX_PRIO_SHIFT) & MAX_TX_PRIO;
242 }
243
244 static inline void hecc_write_lam(struct ti_hecc_priv *priv, u32 mbxno, u32 val)
245 {
246 __raw_writel(val, priv->base + priv->hecc_ram_offset + mbxno * 4);
247 }
248
249 static inline void hecc_write_mbx(struct ti_hecc_priv *priv, u32 mbxno,
250 u32 reg, u32 val)
251 {
252 __raw_writel(val, priv->base + priv->mbx_offset + mbxno * 0x10 +
253 reg);
254 }
255
256 static inline u32 hecc_read_mbx(struct ti_hecc_priv *priv, u32 mbxno, u32 reg)
257 {
258 return __raw_readl(priv->base + priv->mbx_offset + mbxno * 0x10 +
259 reg);
260 }
261
262 static inline void hecc_write(struct ti_hecc_priv *priv, u32 reg, u32 val)
263 {
264 __raw_writel(val, priv->base + reg);
265 }
266
267 static inline u32 hecc_read(struct ti_hecc_priv *priv, int reg)
268 {
269 return __raw_readl(priv->base + reg);
270 }
271
272 static inline void hecc_set_bit(struct ti_hecc_priv *priv, int reg,
273 u32 bit_mask)
274 {
275 hecc_write(priv, reg, hecc_read(priv, reg) | bit_mask);
276 }
277
278 static inline void hecc_clear_bit(struct ti_hecc_priv *priv, int reg,
279 u32 bit_mask)
280 {
281 hecc_write(priv, reg, hecc_read(priv, reg) & ~bit_mask);
282 }
283
284 static inline u32 hecc_get_bit(struct ti_hecc_priv *priv, int reg, u32 bit_mask)
285 {
286 return (hecc_read(priv, reg) & bit_mask) ? 1 : 0;
287 }
288
289 static int ti_hecc_get_state(const struct net_device *ndev,
290 enum can_state *state)
291 {
292 struct ti_hecc_priv *priv = netdev_priv(ndev);
293
294 *state = priv->can.state;
295 return 0;
296 }
297
298 static int ti_hecc_set_btc(struct ti_hecc_priv *priv)
299 {
300 struct can_bittiming *bit_timing = &priv->can.bittiming;
301 u32 can_btc;
302
303 can_btc = (bit_timing->phase_seg2 - 1) & 0x7;
304 can_btc |= ((bit_timing->phase_seg1 + bit_timing->prop_seg - 1)
305 & 0xF) << 3;
306 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) {
307 if (bit_timing->brp > 4)
308 can_btc |= HECC_CANBTC_SAM;
309 else
310 netdev_warn(priv->ndev, "WARN: Triple"
311 "sampling not set due to h/w limitations");
312 }
313 can_btc |= ((bit_timing->sjw - 1) & 0x3) << 8;
314 can_btc |= ((bit_timing->brp - 1) & 0xFF) << 16;
315
316 /* ERM being set to 0 by default meaning resync at falling edge */
317
318 hecc_write(priv, HECC_CANBTC, can_btc);
319 netdev_info(priv->ndev, "setting CANBTC=%#x\n", can_btc);
320
321 return 0;
322 }
323
324 static void ti_hecc_transceiver_switch(const struct ti_hecc_priv *priv,
325 int on)
326 {
327 if (priv->transceiver_switch)
328 priv->transceiver_switch(on);
329 }
330
331 static void ti_hecc_reset(struct net_device *ndev)
332 {
333 u32 cnt;
334 struct ti_hecc_priv *priv = netdev_priv(ndev);
335
336 netdev_dbg(ndev, "resetting hecc ...\n");
337 hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_SRES);
338
339 /* Set change control request and wait till enabled */
340 hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_CCR);
341
342 /*
343 * INFO: It has been observed that at times CCE bit may not be
344 * set and hw seems to be ok even if this bit is not set so
345 * timing out with a timing of 1ms to respect the specs
346 */
347 cnt = HECC_CCE_WAIT_COUNT;
348 while (!hecc_get_bit(priv, HECC_CANES, HECC_CANES_CCE) && cnt != 0) {
349 --cnt;
350 udelay(10);
351 }
352
353 /*
354 * Note: On HECC, BTC can be programmed only in initialization mode, so
355 * it is expected that the can bittiming parameters are set via ip
356 * utility before the device is opened
357 */
358 ti_hecc_set_btc(priv);
359
360 /* Clear CCR (and CANMC register) and wait for CCE = 0 enable */
361 hecc_write(priv, HECC_CANMC, 0);
362
363 /*
364 * INFO: CAN net stack handles bus off and hence disabling auto-bus-on
365 * hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_ABO);
366 */
367
368 /*
369 * INFO: It has been observed that at times CCE bit may not be
370 * set and hw seems to be ok even if this bit is not set so
371 */
372 cnt = HECC_CCE_WAIT_COUNT;
373 while (hecc_get_bit(priv, HECC_CANES, HECC_CANES_CCE) && cnt != 0) {
374 --cnt;
375 udelay(10);
376 }
377
378 /* Enable TX and RX I/O Control pins */
379 hecc_write(priv, HECC_CANTIOC, HECC_CANTIOC_EN);
380 hecc_write(priv, HECC_CANRIOC, HECC_CANRIOC_EN);
381
382 /* Clear registers for clean operation */
383 hecc_write(priv, HECC_CANTA, HECC_SET_REG);
384 hecc_write(priv, HECC_CANRMP, HECC_SET_REG);
385 hecc_write(priv, HECC_CANGIF0, HECC_SET_REG);
386 hecc_write(priv, HECC_CANGIF1, HECC_SET_REG);
387 hecc_write(priv, HECC_CANME, 0);
388 hecc_write(priv, HECC_CANMD, 0);
389
390 /* SCC compat mode NOT supported (and not needed too) */
391 hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_SCM);
392 }
393
394 static void ti_hecc_start(struct net_device *ndev)
395 {
396 struct ti_hecc_priv *priv = netdev_priv(ndev);
397 u32 cnt, mbxno, mbx_mask;
398
399 /* put HECC in initialization mode and set btc */
400 ti_hecc_reset(ndev);
401
402 priv->tx_head = priv->tx_tail = HECC_TX_MASK;
403 priv->rx_next = HECC_RX_FIRST_MBOX;
404
405 /* Enable local and global acceptance mask registers */
406 hecc_write(priv, HECC_CANGAM, HECC_SET_REG);
407
408 /* Prepare configured mailboxes to receive messages */
409 for (cnt = 0; cnt < HECC_MAX_RX_MBOX; cnt++) {
410 mbxno = HECC_MAX_MAILBOXES - 1 - cnt;
411 mbx_mask = BIT(mbxno);
412 hecc_clear_bit(priv, HECC_CANME, mbx_mask);
413 hecc_write_mbx(priv, mbxno, HECC_CANMID, HECC_CANMID_AME);
414 hecc_write_lam(priv, mbxno, HECC_SET_REG);
415 hecc_set_bit(priv, HECC_CANMD, mbx_mask);
416 hecc_set_bit(priv, HECC_CANME, mbx_mask);
417 hecc_set_bit(priv, HECC_CANMIM, mbx_mask);
418 }
419
420 /* Prevent message over-write & Enable interrupts */
421 hecc_write(priv, HECC_CANOPC, HECC_SET_REG);
422 if (priv->int_line) {
423 hecc_write(priv, HECC_CANMIL, HECC_SET_REG);
424 hecc_write(priv, HECC_CANGIM, HECC_CANGIM_DEF_MASK |
425 HECC_CANGIM_I1EN | HECC_CANGIM_SIL);
426 } else {
427 hecc_write(priv, HECC_CANMIL, 0);
428 hecc_write(priv, HECC_CANGIM,
429 HECC_CANGIM_DEF_MASK | HECC_CANGIM_I0EN);
430 }
431 priv->can.state = CAN_STATE_ERROR_ACTIVE;
432 }
433
434 static void ti_hecc_stop(struct net_device *ndev)
435 {
436 struct ti_hecc_priv *priv = netdev_priv(ndev);
437
438 /* Disable interrupts and disable mailboxes */
439 hecc_write(priv, HECC_CANGIM, 0);
440 hecc_write(priv, HECC_CANMIM, 0);
441 hecc_write(priv, HECC_CANME, 0);
442 priv->can.state = CAN_STATE_STOPPED;
443 }
444
445 static int ti_hecc_do_set_mode(struct net_device *ndev, enum can_mode mode)
446 {
447 int ret = 0;
448
449 switch (mode) {
450 case CAN_MODE_START:
451 ti_hecc_start(ndev);
452 netif_wake_queue(ndev);
453 break;
454 default:
455 ret = -EOPNOTSUPP;
456 break;
457 }
458
459 return ret;
460 }
461
462 static int ti_hecc_get_berr_counter(const struct net_device *ndev,
463 struct can_berr_counter *bec)
464 {
465 struct ti_hecc_priv *priv = netdev_priv(ndev);
466
467 bec->txerr = hecc_read(priv, HECC_CANTEC);
468 bec->rxerr = hecc_read(priv, HECC_CANREC);
469
470 return 0;
471 }
472
473 /*
474 * ti_hecc_xmit: HECC Transmit
475 *
476 * The transmit mailboxes start from 0 to HECC_MAX_TX_MBOX. In HECC the
477 * priority of the mailbox for tranmission is dependent upon priority setting
478 * field in mailbox registers. The mailbox with highest value in priority field
479 * is transmitted first. Only when two mailboxes have the same value in
480 * priority field the highest numbered mailbox is transmitted first.
481 *
482 * To utilize the HECC priority feature as described above we start with the
483 * highest numbered mailbox with highest priority level and move on to the next
484 * mailbox with the same priority level and so on. Once we loop through all the
485 * transmit mailboxes we choose the next priority level (lower) and so on
486 * until we reach the lowest priority level on the lowest numbered mailbox
487 * when we stop transmission until all mailboxes are transmitted and then
488 * restart at highest numbered mailbox with highest priority.
489 *
490 * Two counters (head and tail) are used to track the next mailbox to transmit
491 * and to track the echo buffer for already transmitted mailbox. The queue
492 * is stopped when all the mailboxes are busy or when there is a priority
493 * value roll-over happens.
494 */
495 static netdev_tx_t ti_hecc_xmit(struct sk_buff *skb, struct net_device *ndev)
496 {
497 struct ti_hecc_priv *priv = netdev_priv(ndev);
498 struct can_frame *cf = (struct can_frame *)skb->data;
499 u32 mbxno, mbx_mask, data;
500 unsigned long flags;
501
502 if (can_dropped_invalid_skb(ndev, skb))
503 return NETDEV_TX_OK;
504
505 mbxno = get_tx_head_mb(priv);
506 mbx_mask = BIT(mbxno);
507 spin_lock_irqsave(&priv->mbx_lock, flags);
508 if (unlikely(hecc_read(priv, HECC_CANME) & mbx_mask)) {
509 spin_unlock_irqrestore(&priv->mbx_lock, flags);
510 netif_stop_queue(ndev);
511 netdev_err(priv->ndev,
512 "BUG: TX mbx not ready tx_head=%08X, tx_tail=%08X\n",
513 priv->tx_head, priv->tx_tail);
514 return NETDEV_TX_BUSY;
515 }
516 spin_unlock_irqrestore(&priv->mbx_lock, flags);
517
518 /* Prepare mailbox for transmission */
519 data = cf->can_dlc | (get_tx_head_prio(priv) << 8);
520 if (cf->can_id & CAN_RTR_FLAG) /* Remote transmission request */
521 data |= HECC_CANMCF_RTR;
522 hecc_write_mbx(priv, mbxno, HECC_CANMCF, data);
523
524 if (cf->can_id & CAN_EFF_FLAG) /* Extended frame format */
525 data = (cf->can_id & CAN_EFF_MASK) | HECC_CANMID_IDE;
526 else /* Standard frame format */
527 data = (cf->can_id & CAN_SFF_MASK) << 18;
528 hecc_write_mbx(priv, mbxno, HECC_CANMID, data);
529 hecc_write_mbx(priv, mbxno, HECC_CANMDL,
530 be32_to_cpu(*(u32 *)(cf->data)));
531 if (cf->can_dlc > 4)
532 hecc_write_mbx(priv, mbxno, HECC_CANMDH,
533 be32_to_cpu(*(u32 *)(cf->data + 4)));
534 else
535 *(u32 *)(cf->data + 4) = 0;
536 can_put_echo_skb(skb, ndev, mbxno);
537
538 spin_lock_irqsave(&priv->mbx_lock, flags);
539 --priv->tx_head;
540 if ((hecc_read(priv, HECC_CANME) & BIT(get_tx_head_mb(priv))) ||
541 (priv->tx_head & HECC_TX_MASK) == HECC_TX_MASK) {
542 netif_stop_queue(ndev);
543 }
544 hecc_set_bit(priv, HECC_CANME, mbx_mask);
545 spin_unlock_irqrestore(&priv->mbx_lock, flags);
546
547 hecc_clear_bit(priv, HECC_CANMD, mbx_mask);
548 hecc_set_bit(priv, HECC_CANMIM, mbx_mask);
549 hecc_write(priv, HECC_CANTRS, mbx_mask);
550
551 return NETDEV_TX_OK;
552 }
553
554 static int ti_hecc_rx_pkt(struct ti_hecc_priv *priv, int mbxno)
555 {
556 struct net_device_stats *stats = &priv->ndev->stats;
557 struct can_frame *cf;
558 struct sk_buff *skb;
559 u32 data, mbx_mask;
560 unsigned long flags;
561
562 skb = alloc_can_skb(priv->ndev, &cf);
563 if (!skb) {
564 if (printk_ratelimit())
565 netdev_err(priv->ndev,
566 "ti_hecc_rx_pkt: alloc_can_skb() failed\n");
567 return -ENOMEM;
568 }
569
570 mbx_mask = BIT(mbxno);
571 data = hecc_read_mbx(priv, mbxno, HECC_CANMID);
572 if (data & HECC_CANMID_IDE)
573 cf->can_id = (data & CAN_EFF_MASK) | CAN_EFF_FLAG;
574 else
575 cf->can_id = (data >> 18) & CAN_SFF_MASK;
576 data = hecc_read_mbx(priv, mbxno, HECC_CANMCF);
577 if (data & HECC_CANMCF_RTR)
578 cf->can_id |= CAN_RTR_FLAG;
579 cf->can_dlc = get_can_dlc(data & 0xF);
580 data = hecc_read_mbx(priv, mbxno, HECC_CANMDL);
581 *(u32 *)(cf->data) = cpu_to_be32(data);
582 if (cf->can_dlc > 4) {
583 data = hecc_read_mbx(priv, mbxno, HECC_CANMDH);
584 *(u32 *)(cf->data + 4) = cpu_to_be32(data);
585 } else {
586 *(u32 *)(cf->data + 4) = 0;
587 }
588 spin_lock_irqsave(&priv->mbx_lock, flags);
589 hecc_clear_bit(priv, HECC_CANME, mbx_mask);
590 hecc_write(priv, HECC_CANRMP, mbx_mask);
591 /* enable mailbox only if it is part of rx buffer mailboxes */
592 if (priv->rx_next < HECC_RX_BUFFER_MBOX)
593 hecc_set_bit(priv, HECC_CANME, mbx_mask);
594 spin_unlock_irqrestore(&priv->mbx_lock, flags);
595
596 stats->rx_bytes += cf->can_dlc;
597 can_led_event(priv->ndev, CAN_LED_EVENT_RX);
598 netif_receive_skb(skb);
599 stats->rx_packets++;
600
601 return 0;
602 }
603
604 /*
605 * ti_hecc_rx_poll - HECC receive pkts
606 *
607 * The receive mailboxes start from highest numbered mailbox till last xmit
608 * mailbox. On CAN frame reception the hardware places the data into highest
609 * numbered mailbox that matches the CAN ID filter. Since all receive mailboxes
610 * have same filtering (ALL CAN frames) packets will arrive in the highest
611 * available RX mailbox and we need to ensure in-order packet reception.
612 *
613 * To ensure the packets are received in the right order we logically divide
614 * the RX mailboxes into main and buffer mailboxes. Packets are received as per
615 * mailbox priotity (higher to lower) in the main bank and once it is full we
616 * disable further reception into main mailboxes. While the main mailboxes are
617 * processed in NAPI, further packets are received in buffer mailboxes.
618 *
619 * We maintain a RX next mailbox counter to process packets and once all main
620 * mailboxe packets are passed to the upper stack we enable all of them but
621 * continue to process packets received in buffer mailboxes. With each packet
622 * received from buffer mailbox we enable it immediately so as to handle the
623 * overflow from higher mailboxes.
624 */
625 static int ti_hecc_rx_poll(struct napi_struct *napi, int quota)
626 {
627 struct net_device *ndev = napi->dev;
628 struct ti_hecc_priv *priv = netdev_priv(ndev);
629 u32 num_pkts = 0;
630 u32 mbx_mask;
631 unsigned long pending_pkts, flags;
632
633 if (!netif_running(ndev))
634 return 0;
635
636 while ((pending_pkts = hecc_read(priv, HECC_CANRMP)) &&
637 num_pkts < quota) {
638 mbx_mask = BIT(priv->rx_next); /* next rx mailbox to process */
639 if (mbx_mask & pending_pkts) {
640 if (ti_hecc_rx_pkt(priv, priv->rx_next) < 0)
641 return num_pkts;
642 ++num_pkts;
643 } else if (priv->rx_next > HECC_RX_BUFFER_MBOX) {
644 break; /* pkt not received yet */
645 }
646 --priv->rx_next;
647 if (priv->rx_next == HECC_RX_BUFFER_MBOX) {
648 /* enable high bank mailboxes */
649 spin_lock_irqsave(&priv->mbx_lock, flags);
650 mbx_mask = hecc_read(priv, HECC_CANME);
651 mbx_mask |= HECC_RX_HIGH_MBOX_MASK;
652 hecc_write(priv, HECC_CANME, mbx_mask);
653 spin_unlock_irqrestore(&priv->mbx_lock, flags);
654 } else if (priv->rx_next == HECC_MAX_TX_MBOX - 1) {
655 priv->rx_next = HECC_RX_FIRST_MBOX;
656 break;
657 }
658 }
659
660 /* Enable packet interrupt if all pkts are handled */
661 if (hecc_read(priv, HECC_CANRMP) == 0) {
662 napi_complete(napi);
663 /* Re-enable RX mailbox interrupts */
664 mbx_mask = hecc_read(priv, HECC_CANMIM);
665 mbx_mask |= HECC_TX_MBOX_MASK;
666 hecc_write(priv, HECC_CANMIM, mbx_mask);
667 }
668
669 return num_pkts;
670 }
671
672 static int ti_hecc_error(struct net_device *ndev, int int_status,
673 int err_status)
674 {
675 struct ti_hecc_priv *priv = netdev_priv(ndev);
676 struct net_device_stats *stats = &ndev->stats;
677 struct can_frame *cf;
678 struct sk_buff *skb;
679
680 /* propagate the error condition to the can stack */
681 skb = alloc_can_err_skb(ndev, &cf);
682 if (!skb) {
683 if (printk_ratelimit())
684 netdev_err(priv->ndev,
685 "ti_hecc_error: alloc_can_err_skb() failed\n");
686 return -ENOMEM;
687 }
688
689 if (int_status & HECC_CANGIF_WLIF) { /* warning level int */
690 if ((int_status & HECC_CANGIF_BOIF) == 0) {
691 priv->can.state = CAN_STATE_ERROR_WARNING;
692 ++priv->can.can_stats.error_warning;
693 cf->can_id |= CAN_ERR_CRTL;
694 if (hecc_read(priv, HECC_CANTEC) > 96)
695 cf->data[1] |= CAN_ERR_CRTL_TX_WARNING;
696 if (hecc_read(priv, HECC_CANREC) > 96)
697 cf->data[1] |= CAN_ERR_CRTL_RX_WARNING;
698 }
699 hecc_set_bit(priv, HECC_CANES, HECC_CANES_EW);
700 netdev_dbg(priv->ndev, "Error Warning interrupt\n");
701 hecc_clear_bit(priv, HECC_CANMC, HECC_CANMC_CCR);
702 }
703
704 if (int_status & HECC_CANGIF_EPIF) { /* error passive int */
705 if ((int_status & HECC_CANGIF_BOIF) == 0) {
706 priv->can.state = CAN_STATE_ERROR_PASSIVE;
707 ++priv->can.can_stats.error_passive;
708 cf->can_id |= CAN_ERR_CRTL;
709 if (hecc_read(priv, HECC_CANTEC) > 127)
710 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
711 if (hecc_read(priv, HECC_CANREC) > 127)
712 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
713 }
714 hecc_set_bit(priv, HECC_CANES, HECC_CANES_EP);
715 netdev_dbg(priv->ndev, "Error passive interrupt\n");
716 hecc_clear_bit(priv, HECC_CANMC, HECC_CANMC_CCR);
717 }
718
719 /*
720 * Need to check busoff condition in error status register too to
721 * ensure warning interrupts don't hog the system
722 */
723 if ((int_status & HECC_CANGIF_BOIF) || (err_status & HECC_CANES_BO)) {
724 priv->can.state = CAN_STATE_BUS_OFF;
725 cf->can_id |= CAN_ERR_BUSOFF;
726 hecc_set_bit(priv, HECC_CANES, HECC_CANES_BO);
727 hecc_clear_bit(priv, HECC_CANMC, HECC_CANMC_CCR);
728 /* Disable all interrupts in bus-off to avoid int hog */
729 hecc_write(priv, HECC_CANGIM, 0);
730 can_bus_off(ndev);
731 }
732
733 if (err_status & HECC_BUS_ERROR) {
734 ++priv->can.can_stats.bus_error;
735 cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT;
736 cf->data[2] |= CAN_ERR_PROT_UNSPEC;
737 if (err_status & HECC_CANES_FE) {
738 hecc_set_bit(priv, HECC_CANES, HECC_CANES_FE);
739 cf->data[2] |= CAN_ERR_PROT_FORM;
740 }
741 if (err_status & HECC_CANES_BE) {
742 hecc_set_bit(priv, HECC_CANES, HECC_CANES_BE);
743 cf->data[2] |= CAN_ERR_PROT_BIT;
744 }
745 if (err_status & HECC_CANES_SE) {
746 hecc_set_bit(priv, HECC_CANES, HECC_CANES_SE);
747 cf->data[2] |= CAN_ERR_PROT_STUFF;
748 }
749 if (err_status & HECC_CANES_CRCE) {
750 hecc_set_bit(priv, HECC_CANES, HECC_CANES_CRCE);
751 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ |
752 CAN_ERR_PROT_LOC_CRC_DEL;
753 }
754 if (err_status & HECC_CANES_ACKE) {
755 hecc_set_bit(priv, HECC_CANES, HECC_CANES_ACKE);
756 cf->data[3] |= CAN_ERR_PROT_LOC_ACK |
757 CAN_ERR_PROT_LOC_ACK_DEL;
758 }
759 }
760
761 netif_rx(skb);
762 stats->rx_packets++;
763 stats->rx_bytes += cf->can_dlc;
764
765 return 0;
766 }
767
768 static irqreturn_t ti_hecc_interrupt(int irq, void *dev_id)
769 {
770 struct net_device *ndev = (struct net_device *)dev_id;
771 struct ti_hecc_priv *priv = netdev_priv(ndev);
772 struct net_device_stats *stats = &ndev->stats;
773 u32 mbxno, mbx_mask, int_status, err_status;
774 unsigned long ack, flags;
775
776 int_status = hecc_read(priv,
777 (priv->int_line) ? HECC_CANGIF1 : HECC_CANGIF0);
778
779 if (!int_status)
780 return IRQ_NONE;
781
782 err_status = hecc_read(priv, HECC_CANES);
783 if (err_status & (HECC_BUS_ERROR | HECC_CANES_BO |
784 HECC_CANES_EP | HECC_CANES_EW))
785 ti_hecc_error(ndev, int_status, err_status);
786
787 if (int_status & HECC_CANGIF_GMIF) {
788 while (priv->tx_tail - priv->tx_head > 0) {
789 mbxno = get_tx_tail_mb(priv);
790 mbx_mask = BIT(mbxno);
791 if (!(mbx_mask & hecc_read(priv, HECC_CANTA)))
792 break;
793 hecc_clear_bit(priv, HECC_CANMIM, mbx_mask);
794 hecc_write(priv, HECC_CANTA, mbx_mask);
795 spin_lock_irqsave(&priv->mbx_lock, flags);
796 hecc_clear_bit(priv, HECC_CANME, mbx_mask);
797 spin_unlock_irqrestore(&priv->mbx_lock, flags);
798 stats->tx_bytes += hecc_read_mbx(priv, mbxno,
799 HECC_CANMCF) & 0xF;
800 stats->tx_packets++;
801 can_led_event(ndev, CAN_LED_EVENT_TX);
802 can_get_echo_skb(ndev, mbxno);
803 --priv->tx_tail;
804 }
805
806 /* restart queue if wrap-up or if queue stalled on last pkt */
807 if (((priv->tx_head == priv->tx_tail) &&
808 ((priv->tx_head & HECC_TX_MASK) != HECC_TX_MASK)) ||
809 (((priv->tx_tail & HECC_TX_MASK) == HECC_TX_MASK) &&
810 ((priv->tx_head & HECC_TX_MASK) == HECC_TX_MASK)))
811 netif_wake_queue(ndev);
812
813 /* Disable RX mailbox interrupts and let NAPI reenable them */
814 if (hecc_read(priv, HECC_CANRMP)) {
815 ack = hecc_read(priv, HECC_CANMIM);
816 ack &= BIT(HECC_MAX_TX_MBOX) - 1;
817 hecc_write(priv, HECC_CANMIM, ack);
818 napi_schedule(&priv->napi);
819 }
820 }
821
822 /* clear all interrupt conditions - read back to avoid spurious ints */
823 if (priv->int_line) {
824 hecc_write(priv, HECC_CANGIF1, HECC_SET_REG);
825 int_status = hecc_read(priv, HECC_CANGIF1);
826 } else {
827 hecc_write(priv, HECC_CANGIF0, HECC_SET_REG);
828 int_status = hecc_read(priv, HECC_CANGIF0);
829 }
830
831 return IRQ_HANDLED;
832 }
833
834 static int ti_hecc_open(struct net_device *ndev)
835 {
836 struct ti_hecc_priv *priv = netdev_priv(ndev);
837 int err;
838
839 err = request_irq(ndev->irq, ti_hecc_interrupt, IRQF_SHARED,
840 ndev->name, ndev);
841 if (err) {
842 netdev_err(ndev, "error requesting interrupt\n");
843 return err;
844 }
845
846 ti_hecc_transceiver_switch(priv, 1);
847
848 /* Open common can device */
849 err = open_candev(ndev);
850 if (err) {
851 netdev_err(ndev, "open_candev() failed %d\n", err);
852 ti_hecc_transceiver_switch(priv, 0);
853 free_irq(ndev->irq, ndev);
854 return err;
855 }
856
857 can_led_event(ndev, CAN_LED_EVENT_OPEN);
858
859 ti_hecc_start(ndev);
860 napi_enable(&priv->napi);
861 netif_start_queue(ndev);
862
863 return 0;
864 }
865
866 static int ti_hecc_close(struct net_device *ndev)
867 {
868 struct ti_hecc_priv *priv = netdev_priv(ndev);
869
870 netif_stop_queue(ndev);
871 napi_disable(&priv->napi);
872 ti_hecc_stop(ndev);
873 free_irq(ndev->irq, ndev);
874 close_candev(ndev);
875 ti_hecc_transceiver_switch(priv, 0);
876
877 can_led_event(ndev, CAN_LED_EVENT_STOP);
878
879 return 0;
880 }
881
882 static const struct net_device_ops ti_hecc_netdev_ops = {
883 .ndo_open = ti_hecc_open,
884 .ndo_stop = ti_hecc_close,
885 .ndo_start_xmit = ti_hecc_xmit,
886 };
887
888 static int ti_hecc_probe(struct platform_device *pdev)
889 {
890 struct net_device *ndev = (struct net_device *)0;
891 struct ti_hecc_priv *priv;
892 struct ti_hecc_platform_data *pdata;
893 struct resource *mem, *irq;
894 void __iomem *addr;
895 int err = -ENODEV;
896
897 pdata = pdev->dev.platform_data;
898 if (!pdata) {
899 dev_err(&pdev->dev, "No platform data\n");
900 goto probe_exit;
901 }
902
903 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
904 if (!mem) {
905 dev_err(&pdev->dev, "No mem resources\n");
906 goto probe_exit;
907 }
908 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
909 if (!irq) {
910 dev_err(&pdev->dev, "No irq resource\n");
911 goto probe_exit;
912 }
913 if (!request_mem_region(mem->start, resource_size(mem), pdev->name)) {
914 dev_err(&pdev->dev, "HECC region already claimed\n");
915 err = -EBUSY;
916 goto probe_exit;
917 }
918 addr = ioremap(mem->start, resource_size(mem));
919 if (!addr) {
920 dev_err(&pdev->dev, "ioremap failed\n");
921 err = -ENOMEM;
922 goto probe_exit_free_region;
923 }
924
925 ndev = alloc_candev(sizeof(struct ti_hecc_priv), HECC_MAX_TX_MBOX);
926 if (!ndev) {
927 dev_err(&pdev->dev, "alloc_candev failed\n");
928 err = -ENOMEM;
929 goto probe_exit_iounmap;
930 }
931
932 priv = netdev_priv(ndev);
933 priv->ndev = ndev;
934 priv->base = addr;
935 priv->scc_ram_offset = pdata->scc_ram_offset;
936 priv->hecc_ram_offset = pdata->hecc_ram_offset;
937 priv->mbx_offset = pdata->mbx_offset;
938 priv->int_line = pdata->int_line;
939 priv->transceiver_switch = pdata->transceiver_switch;
940
941 priv->can.bittiming_const = &ti_hecc_bittiming_const;
942 priv->can.do_set_mode = ti_hecc_do_set_mode;
943 priv->can.do_get_state = ti_hecc_get_state;
944 priv->can.do_get_berr_counter = ti_hecc_get_berr_counter;
945 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES;
946
947 spin_lock_init(&priv->mbx_lock);
948 ndev->irq = irq->start;
949 ndev->flags |= IFF_ECHO;
950 platform_set_drvdata(pdev, ndev);
951 SET_NETDEV_DEV(ndev, &pdev->dev);
952 ndev->netdev_ops = &ti_hecc_netdev_ops;
953
954 priv->clk = clk_get(&pdev->dev, "hecc_ck");
955 if (IS_ERR(priv->clk)) {
956 dev_err(&pdev->dev, "No clock available\n");
957 err = PTR_ERR(priv->clk);
958 priv->clk = NULL;
959 goto probe_exit_candev;
960 }
961 priv->can.clock.freq = clk_get_rate(priv->clk);
962 netif_napi_add(ndev, &priv->napi, ti_hecc_rx_poll,
963 HECC_DEF_NAPI_WEIGHT);
964
965 clk_enable(priv->clk);
966 err = register_candev(ndev);
967 if (err) {
968 dev_err(&pdev->dev, "register_candev() failed\n");
969 goto probe_exit_clk;
970 }
971
972 devm_can_led_init(ndev);
973
974 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%u)\n",
975 priv->base, (u32) ndev->irq);
976
977 return 0;
978
979 probe_exit_clk:
980 clk_put(priv->clk);
981 probe_exit_candev:
982 free_candev(ndev);
983 probe_exit_iounmap:
984 iounmap(addr);
985 probe_exit_free_region:
986 release_mem_region(mem->start, resource_size(mem));
987 probe_exit:
988 return err;
989 }
990
991 static int ti_hecc_remove(struct platform_device *pdev)
992 {
993 struct resource *res;
994 struct net_device *ndev = platform_get_drvdata(pdev);
995 struct ti_hecc_priv *priv = netdev_priv(ndev);
996
997 unregister_candev(ndev);
998 clk_disable(priv->clk);
999 clk_put(priv->clk);
1000 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1001 iounmap(priv->base);
1002 release_mem_region(res->start, resource_size(res));
1003 free_candev(ndev);
1004
1005 return 0;
1006 }
1007
1008
1009 #ifdef CONFIG_PM
1010 static int ti_hecc_suspend(struct platform_device *pdev, pm_message_t state)
1011 {
1012 struct net_device *dev = platform_get_drvdata(pdev);
1013 struct ti_hecc_priv *priv = netdev_priv(dev);
1014
1015 if (netif_running(dev)) {
1016 netif_stop_queue(dev);
1017 netif_device_detach(dev);
1018 }
1019
1020 hecc_set_bit(priv, HECC_CANMC, HECC_CANMC_PDR);
1021 priv->can.state = CAN_STATE_SLEEPING;
1022
1023 clk_disable(priv->clk);
1024
1025 return 0;
1026 }
1027
1028 static int ti_hecc_resume(struct platform_device *pdev)
1029 {
1030 struct net_device *dev = platform_get_drvdata(pdev);
1031 struct ti_hecc_priv *priv = netdev_priv(dev);
1032
1033 clk_enable(priv->clk);
1034
1035 hecc_clear_bit(priv, HECC_CANMC, HECC_CANMC_PDR);
1036 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1037
1038 if (netif_running(dev)) {
1039 netif_device_attach(dev);
1040 netif_start_queue(dev);
1041 }
1042
1043 return 0;
1044 }
1045 #else
1046 #define ti_hecc_suspend NULL
1047 #define ti_hecc_resume NULL
1048 #endif
1049
1050 /* TI HECC netdevice driver: platform driver structure */
1051 static struct platform_driver ti_hecc_driver = {
1052 .driver = {
1053 .name = DRV_NAME,
1054 .owner = THIS_MODULE,
1055 },
1056 .probe = ti_hecc_probe,
1057 .remove = ti_hecc_remove,
1058 .suspend = ti_hecc_suspend,
1059 .resume = ti_hecc_resume,
1060 };
1061
1062 module_platform_driver(ti_hecc_driver);
1063
1064 MODULE_AUTHOR("Anant Gole <anantgole@ti.com>");
1065 MODULE_LICENSE("GPL v2");
1066 MODULE_DESCRIPTION(DRV_DESC);
1067 MODULE_ALIAS("platform:" DRV_NAME);
CRIS linux kernel tree