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Linux 3.11-rc3
[cris-mirror.git] / drivers / pinctrl / pinctrl-coh901.c
blobf22a2193d949a1915a9759a6466a94a2ecfed2f7
1 /*
2 * U300 GPIO module.
3 *
4 * Copyright (C) 2007-2012 ST-Ericsson AB
5 * License terms: GNU General Public License (GPL) version 2
6 * COH 901 571/3 - Used in DB3210 (U365 2.0) and DB3350 (U335 1.0)
7 * Author: Linus Walleij <linus.walleij@linaro.org>
8 * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
9 */
10 #include <linux/module.h>
11 #include <linux/irq.h>
12 #include <linux/interrupt.h>
13 #include <linux/delay.h>
14 #include <linux/errno.h>
15 #include <linux/io.h>
16 #include <linux/irqdomain.h>
17 #include <linux/clk.h>
18 #include <linux/err.h>
19 #include <linux/platform_device.h>
20 #include <linux/gpio.h>
21 #include <linux/list.h>
22 #include <linux/slab.h>
23 #include <linux/pinctrl/consumer.h>
24 #include <linux/pinctrl/pinconf-generic.h>
25 #include "pinctrl-coh901.h"
26
27 #define U300_GPIO_PORT_STRIDE (0x30)
28 /*
29 * Control Register 32bit (R/W)
30 * bit 15-9 (mask 0x0000FE00) contains the number of cores. 8*cores
31 * gives the number of GPIO pins.
32 * bit 8-2 (mask 0x000001FC) contains the core version ID.
33 */
34 #define U300_GPIO_CR (0x00)
35 #define U300_GPIO_CR_SYNC_SEL_ENABLE (0x00000002UL)
36 #define U300_GPIO_CR_BLOCK_CLKRQ_ENABLE (0x00000001UL)
37 #define U300_GPIO_PXPDIR (0x04)
38 #define U300_GPIO_PXPDOR (0x08)
39 #define U300_GPIO_PXPCR (0x0C)
40 #define U300_GPIO_PXPCR_ALL_PINS_MODE_MASK (0x0000FFFFUL)
41 #define U300_GPIO_PXPCR_PIN_MODE_MASK (0x00000003UL)
42 #define U300_GPIO_PXPCR_PIN_MODE_SHIFT (0x00000002UL)
43 #define U300_GPIO_PXPCR_PIN_MODE_INPUT (0x00000000UL)
44 #define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL (0x00000001UL)
45 #define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN (0x00000002UL)
46 #define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE (0x00000003UL)
47 #define U300_GPIO_PXPER (0x10)
48 #define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK (0x000000FFUL)
49 #define U300_GPIO_PXPER_PULL_UP_DISABLE (0x00000001UL)
50 #define U300_GPIO_PXIEV (0x14)
51 #define U300_GPIO_PXIEN (0x18)
52 #define U300_GPIO_PXIFR (0x1C)
53 #define U300_GPIO_PXICR (0x20)
54 #define U300_GPIO_PXICR_ALL_IRQ_CONFIG_MASK (0x000000FFUL)
55 #define U300_GPIO_PXICR_IRQ_CONFIG_MASK (0x00000001UL)
56 #define U300_GPIO_PXICR_IRQ_CONFIG_FALLING_EDGE (0x00000000UL)
57 #define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE (0x00000001UL)
58
59 /* 8 bits per port, no version has more than 7 ports */
60 #define U300_GPIO_NUM_PORTS 7
61 #define U300_GPIO_PINS_PER_PORT 8
62 #define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * U300_GPIO_NUM_PORTS)
63
64 struct u300_gpio {
65 struct gpio_chip chip;
66 struct list_head port_list;
67 struct clk *clk;
68 void __iomem *base;
69 struct device *dev;
70 u32 stride;
71 /* Register offsets */
72 u32 pcr;
73 u32 dor;
74 u32 dir;
75 u32 per;
76 u32 icr;
77 u32 ien;
78 u32 iev;
79 };
80
81 struct u300_gpio_port {
82 struct list_head node;
83 struct u300_gpio *gpio;
84 char name[8];
85 struct irq_domain *domain;
86 int irq;
87 int number;
88 u8 toggle_edge_mode;
89 };
90
91 /*
92 * Macro to expand to read a specific register found in the "gpio"
93 * struct. It requires the struct u300_gpio *gpio variable to exist in
94 * its context. It calculates the port offset from the given pin
95 * offset, muliplies by the port stride and adds the register offset
96 * so it provides a pointer to the desired register.
97 */
98 #define U300_PIN_REG(pin, reg) \
99 (gpio->base + (pin >> 3) * gpio->stride + gpio->reg)
100
101 /*
102 * Provides a bitmask for a specific gpio pin inside an 8-bit GPIO
103 * register.
104 */
105 #define U300_PIN_BIT(pin) \
106 (1 << (pin & 0x07))
107
108 struct u300_gpio_confdata {
109 u16 bias_mode;
110 bool output;
111 int outval;
112 };
113
114 #define U300_FLOATING_INPUT { \
115 .bias_mode = PIN_CONFIG_BIAS_HIGH_IMPEDANCE, \
116 .output = false, \
117 }
118
119 #define U300_PULL_UP_INPUT { \
120 .bias_mode = PIN_CONFIG_BIAS_PULL_UP, \
121 .output = false, \
122 }
123
124 #define U300_OUTPUT_LOW { \
125 .output = true, \
126 .outval = 0, \
127 }
128
129 #define U300_OUTPUT_HIGH { \
130 .output = true, \
131 .outval = 1, \
132 }
133
134 /* Initial configuration */
135 static const struct __initconst u300_gpio_confdata
136 bs335_gpio_config[U300_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
137 /* Port 0, pins 0-7 */
138 {
139 U300_FLOATING_INPUT,
140 U300_OUTPUT_HIGH,
141 U300_FLOATING_INPUT,
142 U300_OUTPUT_LOW,
143 U300_OUTPUT_LOW,
144 U300_OUTPUT_LOW,
145 U300_OUTPUT_LOW,
146 U300_OUTPUT_LOW,
147 },
148 /* Port 1, pins 0-7 */
149 {
150 U300_OUTPUT_LOW,
151 U300_OUTPUT_LOW,
152 U300_OUTPUT_LOW,
153 U300_PULL_UP_INPUT,
154 U300_FLOATING_INPUT,
155 U300_OUTPUT_HIGH,
156 U300_OUTPUT_LOW,
157 U300_OUTPUT_LOW,
158 },
159 /* Port 2, pins 0-7 */
160 {
161 U300_FLOATING_INPUT,
162 U300_FLOATING_INPUT,
163 U300_FLOATING_INPUT,
164 U300_FLOATING_INPUT,
165 U300_OUTPUT_LOW,
166 U300_PULL_UP_INPUT,
167 U300_OUTPUT_LOW,
168 U300_PULL_UP_INPUT,
169 },
170 /* Port 3, pins 0-7 */
171 {
172 U300_PULL_UP_INPUT,
173 U300_OUTPUT_LOW,
174 U300_FLOATING_INPUT,
175 U300_FLOATING_INPUT,
176 U300_FLOATING_INPUT,
177 U300_FLOATING_INPUT,
178 U300_FLOATING_INPUT,
179 U300_FLOATING_INPUT,
180 },
181 /* Port 4, pins 0-7 */
182 {
183 U300_FLOATING_INPUT,
184 U300_FLOATING_INPUT,
185 U300_FLOATING_INPUT,
186 U300_FLOATING_INPUT,
187 U300_FLOATING_INPUT,
188 U300_FLOATING_INPUT,
189 U300_FLOATING_INPUT,
190 U300_FLOATING_INPUT,
191 },
192 /* Port 5, pins 0-7 */
193 {
194 U300_FLOATING_INPUT,
195 U300_FLOATING_INPUT,
196 U300_FLOATING_INPUT,
197 U300_FLOATING_INPUT,
198 U300_FLOATING_INPUT,
199 U300_FLOATING_INPUT,
200 U300_FLOATING_INPUT,
201 U300_FLOATING_INPUT,
202 },
203 /* Port 6, pind 0-7 */
204 {
205 U300_FLOATING_INPUT,
206 U300_FLOATING_INPUT,
207 U300_FLOATING_INPUT,
208 U300_FLOATING_INPUT,
209 U300_FLOATING_INPUT,
210 U300_FLOATING_INPUT,
211 U300_FLOATING_INPUT,
212 U300_FLOATING_INPUT,
213 }
214 };
215
216 /**
217 * to_u300_gpio() - get the pointer to u300_gpio
218 * @chip: the gpio chip member of the structure u300_gpio
219 */
220 static inline struct u300_gpio *to_u300_gpio(struct gpio_chip *chip)
221 {
222 return container_of(chip, struct u300_gpio, chip);
223 }
224
225 static int u300_gpio_request(struct gpio_chip *chip, unsigned offset)
226 {
227 /*
228 * Map back to global GPIO space and request muxing, the direction
229 * parameter does not matter for this controller.
230 */
231 int gpio = chip->base + offset;
232
233 return pinctrl_request_gpio(gpio);
234 }
235
236 static void u300_gpio_free(struct gpio_chip *chip, unsigned offset)
237 {
238 int gpio = chip->base + offset;
239
240 pinctrl_free_gpio(gpio);
241 }
242
243 static int u300_gpio_get(struct gpio_chip *chip, unsigned offset)
244 {
245 struct u300_gpio *gpio = to_u300_gpio(chip);
246
247 return readl(U300_PIN_REG(offset, dir)) & U300_PIN_BIT(offset);
248 }
249
250 static void u300_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
251 {
252 struct u300_gpio *gpio = to_u300_gpio(chip);
253 unsigned long flags;
254 u32 val;
255
256 local_irq_save(flags);
257
258 val = readl(U300_PIN_REG(offset, dor));
259 if (value)
260 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, dor));
261 else
262 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, dor));
263
264 local_irq_restore(flags);
265 }
266
267 static int u300_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
268 {
269 struct u300_gpio *gpio = to_u300_gpio(chip);
270 unsigned long flags;
271 u32 val;
272
273 local_irq_save(flags);
274 val = readl(U300_PIN_REG(offset, pcr));
275 /* Mask out this pin, note 2 bits per setting */
276 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1));
277 writel(val, U300_PIN_REG(offset, pcr));
278 local_irq_restore(flags);
279 return 0;
280 }
281
282 static int u300_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
283 int value)
284 {
285 struct u300_gpio *gpio = to_u300_gpio(chip);
286 unsigned long flags;
287 u32 oldmode;
288 u32 val;
289
290 local_irq_save(flags);
291 val = readl(U300_PIN_REG(offset, pcr));
292 /*
293 * Drive mode must be set by the special mode set function, set
294 * push/pull mode by default if no mode has been selected.
295 */
296 oldmode = val & (U300_GPIO_PXPCR_PIN_MODE_MASK <<
297 ((offset & 0x07) << 1));
298 /* mode = 0 means input, else some mode is already set */
299 if (oldmode == 0) {
300 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK <<
301 ((offset & 0x07) << 1));
302 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL
303 << ((offset & 0x07) << 1));
304 writel(val, U300_PIN_REG(offset, pcr));
305 }
306 u300_gpio_set(chip, offset, value);
307 local_irq_restore(flags);
308 return 0;
309 }
310
311 static int u300_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
312 {
313 struct u300_gpio *gpio = to_u300_gpio(chip);
314 int portno = offset >> 3;
315 struct u300_gpio_port *port = NULL;
316 struct list_head *p;
317 int retirq;
318 bool found = false;
319
320 list_for_each(p, &gpio->port_list) {
321 port = list_entry(p, struct u300_gpio_port, node);
322 if (port->number == portno) {
323 found = true;
324 break;
325 }
326 }
327 if (!found) {
328 dev_err(gpio->dev, "could not locate port for GPIO %d IRQ\n",
329 offset);
330 return -EINVAL;
331 }
332
333 /*
334 * The local hwirqs on the port are the lower three bits, there
335 * are exactly 8 IRQs per port since they are 8-bit
336 */
337 retirq = irq_find_mapping(port->domain, (offset & 0x7));
338
339 dev_dbg(gpio->dev, "request IRQ for GPIO %d, return %d from port %d\n",
340 offset, retirq, port->number);
341 return retirq;
342 }
343
344 /* Returning -EINVAL means "supported but not available" */
345 int u300_gpio_config_get(struct gpio_chip *chip,
346 unsigned offset,
347 unsigned long *config)
348 {
349 struct u300_gpio *gpio = to_u300_gpio(chip);
350 enum pin_config_param param = (enum pin_config_param) *config;
351 bool biasmode;
352 u32 drmode;
353
354 /* One bit per pin, clamp to bool range */
355 biasmode = !!(readl(U300_PIN_REG(offset, per)) & U300_PIN_BIT(offset));
356
357 /* Mask out the two bits for this pin and shift to bits 0,1 */
358 drmode = readl(U300_PIN_REG(offset, pcr));
359 drmode &= (U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1));
360 drmode >>= ((offset & 0x07) << 1);
361
362 switch (param) {
363 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
364 *config = 0;
365 if (biasmode)
366 return 0;
367 else
368 return -EINVAL;
369 break;
370 case PIN_CONFIG_BIAS_PULL_UP:
371 *config = 0;
372 if (!biasmode)
373 return 0;
374 else
375 return -EINVAL;
376 break;
377 case PIN_CONFIG_DRIVE_PUSH_PULL:
378 *config = 0;
379 if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL)
380 return 0;
381 else
382 return -EINVAL;
383 break;
384 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
385 *config = 0;
386 if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN)
387 return 0;
388 else
389 return -EINVAL;
390 break;
391 case PIN_CONFIG_DRIVE_OPEN_SOURCE:
392 *config = 0;
393 if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE)
394 return 0;
395 else
396 return -EINVAL;
397 break;
398 default:
399 break;
400 }
401 return -ENOTSUPP;
402 }
403
404 int u300_gpio_config_set(struct gpio_chip *chip, unsigned offset,
405 enum pin_config_param param)
406 {
407 struct u300_gpio *gpio = to_u300_gpio(chip);
408 unsigned long flags;
409 u32 val;
410
411 local_irq_save(flags);
412 switch (param) {
413 case PIN_CONFIG_BIAS_DISABLE:
414 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
415 val = readl(U300_PIN_REG(offset, per));
416 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, per));
417 break;
418 case PIN_CONFIG_BIAS_PULL_UP:
419 val = readl(U300_PIN_REG(offset, per));
420 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, per));
421 break;
422 case PIN_CONFIG_DRIVE_PUSH_PULL:
423 val = readl(U300_PIN_REG(offset, pcr));
424 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
425 << ((offset & 0x07) << 1));
426 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL
427 << ((offset & 0x07) << 1));
428 writel(val, U300_PIN_REG(offset, pcr));
429 break;
430 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
431 val = readl(U300_PIN_REG(offset, pcr));
432 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
433 << ((offset & 0x07) << 1));
434 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN
435 << ((offset & 0x07) << 1));
436 writel(val, U300_PIN_REG(offset, pcr));
437 break;
438 case PIN_CONFIG_DRIVE_OPEN_SOURCE:
439 val = readl(U300_PIN_REG(offset, pcr));
440 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
441 << ((offset & 0x07) << 1));
442 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE
443 << ((offset & 0x07) << 1));
444 writel(val, U300_PIN_REG(offset, pcr));
445 break;
446 default:
447 local_irq_restore(flags);
448 dev_err(gpio->dev, "illegal configuration requested\n");
449 return -EINVAL;
450 }
451 local_irq_restore(flags);
452 return 0;
453 }
454
455 static struct gpio_chip u300_gpio_chip = {
456 .label = "u300-gpio-chip",
457 .owner = THIS_MODULE,
458 .request = u300_gpio_request,
459 .free = u300_gpio_free,
460 .get = u300_gpio_get,
461 .set = u300_gpio_set,
462 .direction_input = u300_gpio_direction_input,
463 .direction_output = u300_gpio_direction_output,
464 .to_irq = u300_gpio_to_irq,
465 };
466
467 static void u300_toggle_trigger(struct u300_gpio *gpio, unsigned offset)
468 {
469 u32 val;
470
471 val = readl(U300_PIN_REG(offset, icr));
472 /* Set mode depending on state */
473 if (u300_gpio_get(&gpio->chip, offset)) {
474 /* High now, let's trigger on falling edge next then */
475 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
476 dev_dbg(gpio->dev, "next IRQ on falling edge on pin %d\n",
477 offset);
478 } else {
479 /* Low now, let's trigger on rising edge next then */
480 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
481 dev_dbg(gpio->dev, "next IRQ on rising edge on pin %d\n",
482 offset);
483 }
484 }
485
486 static int u300_gpio_irq_type(struct irq_data *d, unsigned trigger)
487 {
488 struct u300_gpio_port *port = irq_data_get_irq_chip_data(d);
489 struct u300_gpio *gpio = port->gpio;
490 int offset = (port->number << 3) + d->hwirq;
491 u32 val;
492
493 if ((trigger & IRQF_TRIGGER_RISING) &&
494 (trigger & IRQF_TRIGGER_FALLING)) {
495 /*
496 * The GPIO block can only trigger on falling OR rising edges,
497 * not both. So we need to toggle the mode whenever the pin
498 * goes from one state to the other with a special state flag
499 */
500 dev_dbg(gpio->dev,
501 "trigger on both rising and falling edge on pin %d\n",
502 offset);
503 port->toggle_edge_mode |= U300_PIN_BIT(offset);
504 u300_toggle_trigger(gpio, offset);
505 } else if (trigger & IRQF_TRIGGER_RISING) {
506 dev_dbg(gpio->dev, "trigger on rising edge on pin %d\n",
507 offset);
508 val = readl(U300_PIN_REG(offset, icr));
509 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
510 port->toggle_edge_mode &= ~U300_PIN_BIT(offset);
511 } else if (trigger & IRQF_TRIGGER_FALLING) {
512 dev_dbg(gpio->dev, "trigger on falling edge on pin %d\n",
513 offset);
514 val = readl(U300_PIN_REG(offset, icr));
515 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
516 port->toggle_edge_mode &= ~U300_PIN_BIT(offset);
517 }
518
519 return 0;
520 }
521
522 static void u300_gpio_irq_enable(struct irq_data *d)
523 {
524 struct u300_gpio_port *port = irq_data_get_irq_chip_data(d);
525 struct u300_gpio *gpio = port->gpio;
526 int offset = (port->number << 3) + d->hwirq;
527 u32 val;
528 unsigned long flags;
529
530 dev_dbg(gpio->dev, "enable IRQ for hwirq %lu on port %s, offset %d\n",
531 d->hwirq, port->name, offset);
532 local_irq_save(flags);
533 val = readl(U300_PIN_REG(offset, ien));
534 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, ien));
535 local_irq_restore(flags);
536 }
537
538 static void u300_gpio_irq_disable(struct irq_data *d)
539 {
540 struct u300_gpio_port *port = irq_data_get_irq_chip_data(d);
541 struct u300_gpio *gpio = port->gpio;
542 int offset = (port->number << 3) + d->hwirq;
543 u32 val;
544 unsigned long flags;
545
546 local_irq_save(flags);
547 val = readl(U300_PIN_REG(offset, ien));
548 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, ien));
549 local_irq_restore(flags);
550 }
551
552 static struct irq_chip u300_gpio_irqchip = {
553 .name = "u300-gpio-irqchip",
554 .irq_enable = u300_gpio_irq_enable,
555 .irq_disable = u300_gpio_irq_disable,
556 .irq_set_type = u300_gpio_irq_type,
557
558 };
559
560 static void u300_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
561 {
562 struct u300_gpio_port *port = irq_get_handler_data(irq);
563 struct u300_gpio *gpio = port->gpio;
564 int pinoffset = port->number << 3; /* get the right stride */
565 unsigned long val;
566
567 desc->irq_data.chip->irq_ack(&desc->irq_data);
568 /* Read event register */
569 val = readl(U300_PIN_REG(pinoffset, iev));
570 /* Mask relevant bits */
571 val &= 0xFFU; /* 8 bits per port */
572 /* ACK IRQ (clear event) */
573 writel(val, U300_PIN_REG(pinoffset, iev));
574
575 /* Call IRQ handler */
576 if (val != 0) {
577 int irqoffset;
578
579 for_each_set_bit(irqoffset, &val, U300_GPIO_PINS_PER_PORT) {
580 int pin_irq = irq_find_mapping(port->domain, irqoffset);
581 int offset = pinoffset + irqoffset;
582
583 dev_dbg(gpio->dev, "GPIO IRQ %d on pin %d\n",
584 pin_irq, offset);
585 generic_handle_irq(pin_irq);
586 /*
587 * Triggering IRQ on both rising and falling edge
588 * needs mockery
589 */
590 if (port->toggle_edge_mode & U300_PIN_BIT(offset))
591 u300_toggle_trigger(gpio, offset);
592 }
593 }
594
595 desc->irq_data.chip->irq_unmask(&desc->irq_data);
596 }
597
598 static void __init u300_gpio_init_pin(struct u300_gpio *gpio,
599 int offset,
600 const struct u300_gpio_confdata *conf)
601 {
602 /* Set mode: input or output */
603 if (conf->output) {
604 u300_gpio_direction_output(&gpio->chip, offset, conf->outval);
605
606 /* Deactivate bias mode for output */
607 u300_gpio_config_set(&gpio->chip, offset,
608 PIN_CONFIG_BIAS_HIGH_IMPEDANCE);
609
610 /* Set drive mode for output */
611 u300_gpio_config_set(&gpio->chip, offset,
612 PIN_CONFIG_DRIVE_PUSH_PULL);
613
614 dev_dbg(gpio->dev, "set up pin %d as output, value: %d\n",
615 offset, conf->outval);
616 } else {
617 u300_gpio_direction_input(&gpio->chip, offset);
618
619 /* Always set output low on input pins */
620 u300_gpio_set(&gpio->chip, offset, 0);
621
622 /* Set bias mode for input */
623 u300_gpio_config_set(&gpio->chip, offset, conf->bias_mode);
624
625 dev_dbg(gpio->dev, "set up pin %d as input, bias: %04x\n",
626 offset, conf->bias_mode);
627 }
628 }
629
630 static void __init u300_gpio_init_coh901571(struct u300_gpio *gpio)
631 {
632 int i, j;
633
634 /* Write default config and values to all pins */
635 for (i = 0; i < U300_GPIO_NUM_PORTS; i++) {
636 for (j = 0; j < 8; j++) {
637 const struct u300_gpio_confdata *conf;
638 int offset = (i*8) + j;
639
640 conf = &bs335_gpio_config[i][j];
641 u300_gpio_init_pin(gpio, offset, conf);
642 }
643 }
644 }
645
646 static inline void u300_gpio_free_ports(struct u300_gpio *gpio)
647 {
648 struct u300_gpio_port *port;
649 struct list_head *p, *n;
650
651 list_for_each_safe(p, n, &gpio->port_list) {
652 port = list_entry(p, struct u300_gpio_port, node);
653 list_del(&port->node);
654 if (port->domain)
655 irq_domain_remove(port->domain);
656 kfree(port);
657 }
658 }
659
660 /*
661 * Here we map a GPIO in the local gpio_chip pin space to a pin in
662 * the local pinctrl pin space. The pin controller used is
663 * pinctrl-u300.
664 */
665 struct coh901_pinpair {
666 unsigned int offset;
667 unsigned int pin_base;
668 };
669
670 #define COH901_PINRANGE(a, b) { .offset = a, .pin_base = b }
671
672 static struct coh901_pinpair coh901_pintable[] = {
673 COH901_PINRANGE(10, 426),
674 COH901_PINRANGE(11, 180),
675 COH901_PINRANGE(12, 165), /* MS/MMC card insertion */
676 COH901_PINRANGE(13, 179),
677 COH901_PINRANGE(14, 178),
678 COH901_PINRANGE(16, 194),
679 COH901_PINRANGE(17, 193),
680 COH901_PINRANGE(18, 192),
681 COH901_PINRANGE(19, 191),
682 COH901_PINRANGE(20, 186),
683 COH901_PINRANGE(21, 185),
684 COH901_PINRANGE(22, 184),
685 COH901_PINRANGE(23, 183),
686 COH901_PINRANGE(24, 182),
687 COH901_PINRANGE(25, 181),
688 };
689
690 static int __init u300_gpio_probe(struct platform_device *pdev)
691 {
692 struct u300_gpio *gpio;
693 struct resource *memres;
694 int err = 0;
695 int portno;
696 u32 val;
697 u32 ifr;
698 int i;
699
700 gpio = devm_kzalloc(&pdev->dev, sizeof(struct u300_gpio), GFP_KERNEL);
701 if (gpio == NULL)
702 return -ENOMEM;
703
704 gpio->chip = u300_gpio_chip;
705 gpio->chip.ngpio = U300_GPIO_NUM_PORTS * U300_GPIO_PINS_PER_PORT;
706 gpio->chip.dev = &pdev->dev;
707 gpio->chip.base = 0;
708 gpio->dev = &pdev->dev;
709
710 memres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
711 gpio->base = devm_ioremap_resource(&pdev->dev, memres);
712 if (IS_ERR(gpio->base))
713 return PTR_ERR(gpio->base);
714
715 gpio->clk = devm_clk_get(gpio->dev, NULL);
716 if (IS_ERR(gpio->clk)) {
717 err = PTR_ERR(gpio->clk);
718 dev_err(gpio->dev, "could not get GPIO clock\n");
719 return err;
720 }
721
722 err = clk_prepare_enable(gpio->clk);
723 if (err) {
724 dev_err(gpio->dev, "could not enable GPIO clock\n");
725 return err;
726 }
727
728 dev_info(gpio->dev,
729 "initializing GPIO Controller COH 901 571/3\n");
730 gpio->stride = U300_GPIO_PORT_STRIDE;
731 gpio->pcr = U300_GPIO_PXPCR;
732 gpio->dor = U300_GPIO_PXPDOR;
733 gpio->dir = U300_GPIO_PXPDIR;
734 gpio->per = U300_GPIO_PXPER;
735 gpio->icr = U300_GPIO_PXICR;
736 gpio->ien = U300_GPIO_PXIEN;
737 gpio->iev = U300_GPIO_PXIEV;
738 ifr = U300_GPIO_PXIFR;
739
740 val = readl(gpio->base + U300_GPIO_CR);
741 dev_info(gpio->dev, "COH901571/3 block version: %d, " \
742 "number of cores: %d totalling %d pins\n",
743 ((val & 0x000001FC) >> 2),
744 ((val & 0x0000FE00) >> 9),
745 ((val & 0x0000FE00) >> 9) * 8);
746 writel(U300_GPIO_CR_BLOCK_CLKRQ_ENABLE,
747 gpio->base + U300_GPIO_CR);
748 u300_gpio_init_coh901571(gpio);
749
750 /* Add each port with its IRQ separately */
751 INIT_LIST_HEAD(&gpio->port_list);
752 for (portno = 0 ; portno < U300_GPIO_NUM_PORTS; portno++) {
753 struct u300_gpio_port *port =
754 kmalloc(sizeof(struct u300_gpio_port), GFP_KERNEL);
755
756 if (!port) {
757 dev_err(gpio->dev, "out of memory\n");
758 err = -ENOMEM;
759 goto err_no_port;
760 }
761
762 snprintf(port->name, 8, "gpio%d", portno);
763 port->number = portno;
764 port->gpio = gpio;
765
766 port->irq = platform_get_irq(pdev, portno);
767
768 dev_dbg(gpio->dev, "register IRQ %d for port %s\n", port->irq,
769 port->name);
770
771 port->domain = irq_domain_add_linear(pdev->dev.of_node,
772 U300_GPIO_PINS_PER_PORT,
773 &irq_domain_simple_ops,
774 port);
775 if (!port->domain) {
776 err = -ENOMEM;
777 goto err_no_domain;
778 }
779
780 irq_set_chained_handler(port->irq, u300_gpio_irq_handler);
781 irq_set_handler_data(port->irq, port);
782
783 /* For each GPIO pin set the unique IRQ handler */
784 for (i = 0; i < U300_GPIO_PINS_PER_PORT; i++) {
785 int irqno = irq_create_mapping(port->domain, i);
786
787 dev_dbg(gpio->dev, "GPIO%d on port %s gets IRQ %d\n",
788 gpio->chip.base + (port->number << 3) + i,
789 port->name, irqno);
790 irq_set_chip_and_handler(irqno, &u300_gpio_irqchip,
791 handle_simple_irq);
792 set_irq_flags(irqno, IRQF_VALID);
793 irq_set_chip_data(irqno, port);
794 }
795
796 /* Turns off irq force (test register) for this port */
797 writel(0x0, gpio->base + portno * gpio->stride + ifr);
798
799 list_add_tail(&port->node, &gpio->port_list);
800 }
801 dev_dbg(gpio->dev, "initialized %d GPIO ports\n", portno);
802
803 #ifdef CONFIG_OF_GPIO
804 gpio->chip.of_node = pdev->dev.of_node;
805 #endif
806 err = gpiochip_add(&gpio->chip);
807 if (err) {
808 dev_err(gpio->dev, "unable to add gpiochip: %d\n", err);
809 goto err_no_chip;
810 }
811
812 /*
813 * Add pinctrl pin ranges, the pin controller must be registered
814 * at this point
815 */
816 for (i = 0; i < ARRAY_SIZE(coh901_pintable); i++) {
817 struct coh901_pinpair *p = &coh901_pintable[i];
818
819 err = gpiochip_add_pin_range(&gpio->chip, "pinctrl-u300",
820 p->offset, p->pin_base, 1);
821 if (err)
822 goto err_no_range;
823 }
824
825 platform_set_drvdata(pdev, gpio);
826
827 return 0;
828
829 err_no_range:
830 if (gpiochip_remove(&gpio->chip))
831 dev_err(&pdev->dev, "failed to remove gpio chip\n");
832 err_no_chip:
833 err_no_domain:
834 err_no_port:
835 u300_gpio_free_ports(gpio);
836 clk_disable_unprepare(gpio->clk);
837 dev_err(&pdev->dev, "module ERROR:%d\n", err);
838 return err;
839 }
840
841 static int __exit u300_gpio_remove(struct platform_device *pdev)
842 {
843 struct u300_gpio *gpio = platform_get_drvdata(pdev);
844 int err;
845
846 /* Turn off the GPIO block */
847 writel(0x00000000U, gpio->base + U300_GPIO_CR);
848
849 err = gpiochip_remove(&gpio->chip);
850 if (err < 0) {
851 dev_err(gpio->dev, "unable to remove gpiochip: %d\n", err);
852 return err;
853 }
854 u300_gpio_free_ports(gpio);
855 clk_disable_unprepare(gpio->clk);
856 return 0;
857 }
858
859 static const struct of_device_id u300_gpio_match[] = {
860 { .compatible = "stericsson,gpio-coh901" },
861 {},
862 };
863
864 static struct platform_driver u300_gpio_driver = {
865 .driver = {
866 .name = "u300-gpio",
867 .of_match_table = u300_gpio_match,
868 },
869 .remove = __exit_p(u300_gpio_remove),
870 };
871
872 static int __init u300_gpio_init(void)
873 {
874 return platform_driver_probe(&u300_gpio_driver, u300_gpio_probe);
875 }
876
877 static void __exit u300_gpio_exit(void)
878 {
879 platform_driver_unregister(&u300_gpio_driver);
880 }
881
882 arch_initcall(u300_gpio_init);
883 module_exit(u300_gpio_exit);
884
885 MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
886 MODULE_DESCRIPTION("ST-Ericsson AB COH 901 335/COH 901 571/3 GPIO driver");
887 MODULE_LICENSE("GPL");
CRIS linux kernel tree