?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Linux 3.11-rc3
[cris-mirror.git] / drivers / pinctrl / pinctrl-xway.c
blobe92132c76a6b56cf02415f18b890c259f377c404
1 /*
2 * linux/drivers/pinctrl/pinmux-xway.c
3 * based on linux/drivers/pinctrl/pinmux-pxa910.c
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 *
9 * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
10 */
11
12 #include <linux/err.h>
13 #include <linux/slab.h>
14 #include <linux/module.h>
15 #include <linux/of_platform.h>
16 #include <linux/of_address.h>
17 #include <linux/of_gpio.h>
18 #include <linux/ioport.h>
19 #include <linux/io.h>
20 #include <linux/device.h>
21 #include <linux/platform_device.h>
22
23 #include "pinctrl-lantiq.h"
24
25 #include <lantiq_soc.h>
26
27 /* we have 3 1/2 banks of 16 bit each */
28 #define PINS 16
29 #define PORT3 3
30 #define PORT(x) (x / PINS)
31 #define PORT_PIN(x) (x % PINS)
32
33 /* we have 2 mux bits that can be set for each pin */
34 #define MUX_ALT0 0x1
35 #define MUX_ALT1 0x2
36
37 /*
38 * each bank has this offset apart from the 1/2 bank that is mixed into the
39 * other 3 ranges
40 */
41 #define REG_OFF 0x30
42
43 /* these are the offsets to our registers */
44 #define GPIO_BASE(p) (REG_OFF * PORT(p))
45 #define GPIO_OUT(p) GPIO_BASE(p)
46 #define GPIO_IN(p) (GPIO_BASE(p) + 0x04)
47 #define GPIO_DIR(p) (GPIO_BASE(p) + 0x08)
48 #define GPIO_ALT0(p) (GPIO_BASE(p) + 0x0C)
49 #define GPIO_ALT1(p) (GPIO_BASE(p) + 0x10)
50 #define GPIO_OD(p) (GPIO_BASE(p) + 0x14)
51 #define GPIO_PUDSEL(p) (GPIO_BASE(p) + 0x1c)
52 #define GPIO_PUDEN(p) (GPIO_BASE(p) + 0x20)
53
54 /* the 1/2 port needs special offsets for some registers */
55 #define GPIO3_OD (GPIO_BASE(0) + 0x24)
56 #define GPIO3_PUDSEL (GPIO_BASE(0) + 0x28)
57 #define GPIO3_PUDEN (GPIO_BASE(0) + 0x2C)
58 #define GPIO3_ALT1 (GPIO_BASE(PINS) + 0x24)
59
60 /* macros to help us access the registers */
61 #define gpio_getbit(m, r, p) (!!(ltq_r32(m + r) & BIT(p)))
62 #define gpio_setbit(m, r, p) ltq_w32_mask(0, BIT(p), m + r)
63 #define gpio_clearbit(m, r, p) ltq_w32_mask(BIT(p), 0, m + r)
64
65 #define MFP_XWAY(a, f0, f1, f2, f3) \
66 { \
67 .name = #a, \
68 .pin = a, \
69 .func = { \
70 XWAY_MUX_##f0, \
71 XWAY_MUX_##f1, \
72 XWAY_MUX_##f2, \
73 XWAY_MUX_##f3, \
74 }, \
75 }
76
77 #define GRP_MUX(a, m, p) \
78 { .name = a, .mux = XWAY_MUX_##m, .pins = p, .npins = ARRAY_SIZE(p), }
79
80 #define FUNC_MUX(f, m) \
81 { .func = f, .mux = XWAY_MUX_##m, }
82
83 #define XWAY_MAX_PIN 32
84 #define XR9_MAX_PIN 56
85
86 enum xway_mux {
87 XWAY_MUX_GPIO = 0,
88 XWAY_MUX_SPI,
89 XWAY_MUX_ASC,
90 XWAY_MUX_PCI,
91 XWAY_MUX_CGU,
92 XWAY_MUX_EBU,
93 XWAY_MUX_JTAG,
94 XWAY_MUX_EXIN,
95 XWAY_MUX_TDM,
96 XWAY_MUX_STP,
97 XWAY_MUX_SIN,
98 XWAY_MUX_GPT,
99 XWAY_MUX_NMI,
100 XWAY_MUX_MDIO,
101 XWAY_MUX_MII,
102 XWAY_MUX_EPHY,
103 XWAY_MUX_DFE,
104 XWAY_MUX_SDIO,
105 XWAY_MUX_NONE = 0xffff,
106 };
107
108 static const struct ltq_mfp_pin xway_mfp[] = {
109 /* pin f0 f1 f2 f3 */
110 MFP_XWAY(GPIO0, GPIO, EXIN, NONE, TDM),
111 MFP_XWAY(GPIO1, GPIO, EXIN, NONE, NONE),
112 MFP_XWAY(GPIO2, GPIO, CGU, EXIN, NONE),
113 MFP_XWAY(GPIO3, GPIO, CGU, NONE, PCI),
114 MFP_XWAY(GPIO4, GPIO, STP, NONE, ASC),
115 MFP_XWAY(GPIO5, GPIO, STP, NONE, NONE),
116 MFP_XWAY(GPIO6, GPIO, STP, GPT, ASC),
117 MFP_XWAY(GPIO7, GPIO, CGU, PCI, NONE),
118 MFP_XWAY(GPIO8, GPIO, CGU, NMI, NONE),
119 MFP_XWAY(GPIO9, GPIO, ASC, SPI, EXIN),
120 MFP_XWAY(GPIO10, GPIO, ASC, SPI, NONE),
121 MFP_XWAY(GPIO11, GPIO, ASC, PCI, SPI),
122 MFP_XWAY(GPIO12, GPIO, ASC, NONE, NONE),
123 MFP_XWAY(GPIO13, GPIO, EBU, SPI, NONE),
124 MFP_XWAY(GPIO14, GPIO, CGU, PCI, NONE),
125 MFP_XWAY(GPIO15, GPIO, SPI, JTAG, NONE),
126 MFP_XWAY(GPIO16, GPIO, SPI, NONE, JTAG),
127 MFP_XWAY(GPIO17, GPIO, SPI, NONE, JTAG),
128 MFP_XWAY(GPIO18, GPIO, SPI, NONE, JTAG),
129 MFP_XWAY(GPIO19, GPIO, PCI, NONE, NONE),
130 MFP_XWAY(GPIO20, GPIO, JTAG, NONE, NONE),
131 MFP_XWAY(GPIO21, GPIO, PCI, EBU, GPT),
132 MFP_XWAY(GPIO22, GPIO, SPI, NONE, NONE),
133 MFP_XWAY(GPIO23, GPIO, EBU, PCI, STP),
134 MFP_XWAY(GPIO24, GPIO, EBU, TDM, PCI),
135 MFP_XWAY(GPIO25, GPIO, TDM, NONE, ASC),
136 MFP_XWAY(GPIO26, GPIO, EBU, NONE, TDM),
137 MFP_XWAY(GPIO27, GPIO, TDM, NONE, ASC),
138 MFP_XWAY(GPIO28, GPIO, GPT, NONE, NONE),
139 MFP_XWAY(GPIO29, GPIO, PCI, NONE, NONE),
140 MFP_XWAY(GPIO30, GPIO, PCI, NONE, NONE),
141 MFP_XWAY(GPIO31, GPIO, EBU, PCI, NONE),
142 MFP_XWAY(GPIO32, GPIO, NONE, NONE, EBU),
143 MFP_XWAY(GPIO33, GPIO, NONE, NONE, EBU),
144 MFP_XWAY(GPIO34, GPIO, NONE, NONE, EBU),
145 MFP_XWAY(GPIO35, GPIO, NONE, NONE, EBU),
146 MFP_XWAY(GPIO36, GPIO, SIN, NONE, EBU),
147 MFP_XWAY(GPIO37, GPIO, PCI, NONE, NONE),
148 MFP_XWAY(GPIO38, GPIO, PCI, NONE, NONE),
149 MFP_XWAY(GPIO39, GPIO, EXIN, NONE, NONE),
150 MFP_XWAY(GPIO40, GPIO, NONE, NONE, NONE),
151 MFP_XWAY(GPIO41, GPIO, NONE, NONE, NONE),
152 MFP_XWAY(GPIO42, GPIO, MDIO, NONE, NONE),
153 MFP_XWAY(GPIO43, GPIO, MDIO, NONE, NONE),
154 MFP_XWAY(GPIO44, GPIO, NONE, NONE, SIN),
155 MFP_XWAY(GPIO45, GPIO, NONE, NONE, SIN),
156 MFP_XWAY(GPIO46, GPIO, NONE, NONE, EXIN),
157 MFP_XWAY(GPIO47, GPIO, NONE, NONE, SIN),
158 MFP_XWAY(GPIO48, GPIO, EBU, NONE, NONE),
159 MFP_XWAY(GPIO49, GPIO, EBU, NONE, NONE),
160 MFP_XWAY(GPIO50, GPIO, NONE, NONE, NONE),
161 MFP_XWAY(GPIO51, GPIO, NONE, NONE, NONE),
162 MFP_XWAY(GPIO52, GPIO, NONE, NONE, NONE),
163 MFP_XWAY(GPIO53, GPIO, NONE, NONE, NONE),
164 MFP_XWAY(GPIO54, GPIO, NONE, NONE, NONE),
165 MFP_XWAY(GPIO55, GPIO, NONE, NONE, NONE),
166 };
167
168 static const struct ltq_mfp_pin ase_mfp[] = {
169 /* pin f0 f1 f2 f3 */
170 MFP_XWAY(GPIO0, GPIO, EXIN, MII, TDM),
171 MFP_XWAY(GPIO1, GPIO, STP, DFE, EBU),
172 MFP_XWAY(GPIO2, GPIO, STP, DFE, EPHY),
173 MFP_XWAY(GPIO3, GPIO, STP, EPHY, EBU),
174 MFP_XWAY(GPIO4, GPIO, GPT, EPHY, MII),
175 MFP_XWAY(GPIO5, GPIO, MII, ASC, GPT),
176 MFP_XWAY(GPIO6, GPIO, MII, ASC, EXIN),
177 MFP_XWAY(GPIO7, GPIO, SPI, MII, JTAG),
178 MFP_XWAY(GPIO8, GPIO, SPI, MII, JTAG),
179 MFP_XWAY(GPIO9, GPIO, SPI, MII, JTAG),
180 MFP_XWAY(GPIO10, GPIO, SPI, MII, JTAG),
181 MFP_XWAY(GPIO11, GPIO, EBU, CGU, JTAG),
182 MFP_XWAY(GPIO12, GPIO, EBU, MII, SDIO),
183 MFP_XWAY(GPIO13, GPIO, EBU, MII, CGU),
184 MFP_XWAY(GPIO14, GPIO, EBU, SPI, CGU),
185 MFP_XWAY(GPIO15, GPIO, EBU, SPI, SDIO),
186 MFP_XWAY(GPIO16, GPIO, NONE, NONE, NONE),
187 MFP_XWAY(GPIO17, GPIO, NONE, NONE, NONE),
188 MFP_XWAY(GPIO18, GPIO, NONE, NONE, NONE),
189 MFP_XWAY(GPIO19, GPIO, EBU, MII, SDIO),
190 MFP_XWAY(GPIO20, GPIO, EBU, MII, SDIO),
191 MFP_XWAY(GPIO21, GPIO, EBU, MII, SDIO),
192 MFP_XWAY(GPIO22, GPIO, EBU, MII, CGU),
193 MFP_XWAY(GPIO23, GPIO, EBU, MII, CGU),
194 MFP_XWAY(GPIO24, GPIO, EBU, NONE, MII),
195 MFP_XWAY(GPIO25, GPIO, EBU, MII, GPT),
196 MFP_XWAY(GPIO26, GPIO, EBU, MII, SDIO),
197 MFP_XWAY(GPIO27, GPIO, EBU, NONE, MII),
198 MFP_XWAY(GPIO28, GPIO, MII, EBU, SDIO),
199 MFP_XWAY(GPIO29, GPIO, EBU, MII, EXIN),
200 MFP_XWAY(GPIO30, GPIO, NONE, NONE, NONE),
201 MFP_XWAY(GPIO31, GPIO, NONE, NONE, NONE),
202 };
203
204 static const unsigned pins_jtag[] = {GPIO15, GPIO16, GPIO17, GPIO19, GPIO35};
205 static const unsigned pins_asc0[] = {GPIO11, GPIO12};
206 static const unsigned pins_asc0_cts_rts[] = {GPIO9, GPIO10};
207 static const unsigned pins_stp[] = {GPIO4, GPIO5, GPIO6};
208 static const unsigned pins_nmi[] = {GPIO8};
209 static const unsigned pins_mdio[] = {GPIO42, GPIO43};
210
211 static const unsigned pins_ebu_a24[] = {GPIO13};
212 static const unsigned pins_ebu_clk[] = {GPIO21};
213 static const unsigned pins_ebu_cs1[] = {GPIO23};
214 static const unsigned pins_ebu_a23[] = {GPIO24};
215 static const unsigned pins_ebu_wait[] = {GPIO26};
216 static const unsigned pins_ebu_a25[] = {GPIO31};
217 static const unsigned pins_ebu_rdy[] = {GPIO48};
218 static const unsigned pins_ebu_rd[] = {GPIO49};
219
220 static const unsigned pins_nand_ale[] = {GPIO13};
221 static const unsigned pins_nand_cs1[] = {GPIO23};
222 static const unsigned pins_nand_cle[] = {GPIO24};
223 static const unsigned pins_nand_rdy[] = {GPIO48};
224 static const unsigned pins_nand_rd[] = {GPIO49};
225
226 static const unsigned pins_exin0[] = {GPIO0};
227 static const unsigned pins_exin1[] = {GPIO1};
228 static const unsigned pins_exin2[] = {GPIO2};
229 static const unsigned pins_exin3[] = {GPIO39};
230 static const unsigned pins_exin4[] = {GPIO46};
231 static const unsigned pins_exin5[] = {GPIO9};
232
233 static const unsigned pins_spi[] = {GPIO16, GPIO17, GPIO18};
234 static const unsigned pins_spi_cs1[] = {GPIO15};
235 static const unsigned pins_spi_cs2[] = {GPIO21};
236 static const unsigned pins_spi_cs3[] = {GPIO13};
237 static const unsigned pins_spi_cs4[] = {GPIO10};
238 static const unsigned pins_spi_cs5[] = {GPIO9};
239 static const unsigned pins_spi_cs6[] = {GPIO11};
240
241 static const unsigned pins_gpt1[] = {GPIO28};
242 static const unsigned pins_gpt2[] = {GPIO21};
243 static const unsigned pins_gpt3[] = {GPIO6};
244
245 static const unsigned pins_clkout0[] = {GPIO8};
246 static const unsigned pins_clkout1[] = {GPIO7};
247 static const unsigned pins_clkout2[] = {GPIO3};
248 static const unsigned pins_clkout3[] = {GPIO2};
249
250 static const unsigned pins_pci_gnt1[] = {GPIO30};
251 static const unsigned pins_pci_gnt2[] = {GPIO23};
252 static const unsigned pins_pci_gnt3[] = {GPIO19};
253 static const unsigned pins_pci_gnt4[] = {GPIO38};
254 static const unsigned pins_pci_req1[] = {GPIO29};
255 static const unsigned pins_pci_req2[] = {GPIO31};
256 static const unsigned pins_pci_req3[] = {GPIO3};
257 static const unsigned pins_pci_req4[] = {GPIO37};
258
259 static const unsigned ase_pins_jtag[] = {GPIO7, GPIO8, GPIO9, GPIO10, GPIO11};
260 static const unsigned ase_pins_asc[] = {GPIO5, GPIO6};
261 static const unsigned ase_pins_stp[] = {GPIO1, GPIO2, GPIO3};
262 static const unsigned ase_pins_ephy[] = {GPIO2, GPIO3, GPIO4};
263 static const unsigned ase_pins_dfe[] = {GPIO1, GPIO2};
264
265 static const unsigned ase_pins_spi[] = {GPIO8, GPIO9, GPIO10};
266 static const unsigned ase_pins_spi_cs1[] = {GPIO7};
267 static const unsigned ase_pins_spi_cs2[] = {GPIO15};
268 static const unsigned ase_pins_spi_cs3[] = {GPIO14};
269
270 static const unsigned ase_pins_exin0[] = {GPIO6};
271 static const unsigned ase_pins_exin1[] = {GPIO29};
272 static const unsigned ase_pins_exin2[] = {GPIO0};
273
274 static const unsigned ase_pins_gpt1[] = {GPIO5};
275 static const unsigned ase_pins_gpt2[] = {GPIO4};
276 static const unsigned ase_pins_gpt3[] = {GPIO25};
277
278 static const struct ltq_pin_group xway_grps[] = {
279 GRP_MUX("exin0", EXIN, pins_exin0),
280 GRP_MUX("exin1", EXIN, pins_exin1),
281 GRP_MUX("exin2", EXIN, pins_exin2),
282 GRP_MUX("jtag", JTAG, pins_jtag),
283 GRP_MUX("ebu a23", EBU, pins_ebu_a23),
284 GRP_MUX("ebu a24", EBU, pins_ebu_a24),
285 GRP_MUX("ebu a25", EBU, pins_ebu_a25),
286 GRP_MUX("ebu clk", EBU, pins_ebu_clk),
287 GRP_MUX("ebu cs1", EBU, pins_ebu_cs1),
288 GRP_MUX("ebu wait", EBU, pins_ebu_wait),
289 GRP_MUX("nand ale", EBU, pins_nand_ale),
290 GRP_MUX("nand cs1", EBU, pins_nand_cs1),
291 GRP_MUX("nand cle", EBU, pins_nand_cle),
292 GRP_MUX("spi", SPI, pins_spi),
293 GRP_MUX("spi_cs1", SPI, pins_spi_cs1),
294 GRP_MUX("spi_cs2", SPI, pins_spi_cs2),
295 GRP_MUX("spi_cs3", SPI, pins_spi_cs3),
296 GRP_MUX("spi_cs4", SPI, pins_spi_cs4),
297 GRP_MUX("spi_cs5", SPI, pins_spi_cs5),
298 GRP_MUX("spi_cs6", SPI, pins_spi_cs6),
299 GRP_MUX("asc0", ASC, pins_asc0),
300 GRP_MUX("asc0 cts rts", ASC, pins_asc0_cts_rts),
301 GRP_MUX("stp", STP, pins_stp),
302 GRP_MUX("nmi", NMI, pins_nmi),
303 GRP_MUX("gpt1", GPT, pins_gpt1),
304 GRP_MUX("gpt2", GPT, pins_gpt2),
305 GRP_MUX("gpt3", GPT, pins_gpt3),
306 GRP_MUX("clkout0", CGU, pins_clkout0),
307 GRP_MUX("clkout1", CGU, pins_clkout1),
308 GRP_MUX("clkout2", CGU, pins_clkout2),
309 GRP_MUX("clkout3", CGU, pins_clkout3),
310 GRP_MUX("gnt1", PCI, pins_pci_gnt1),
311 GRP_MUX("gnt2", PCI, pins_pci_gnt2),
312 GRP_MUX("gnt3", PCI, pins_pci_gnt3),
313 GRP_MUX("req1", PCI, pins_pci_req1),
314 GRP_MUX("req2", PCI, pins_pci_req2),
315 GRP_MUX("req3", PCI, pins_pci_req3),
316 /* xrx only */
317 GRP_MUX("nand rdy", EBU, pins_nand_rdy),
318 GRP_MUX("nand rd", EBU, pins_nand_rd),
319 GRP_MUX("exin3", EXIN, pins_exin3),
320 GRP_MUX("exin4", EXIN, pins_exin4),
321 GRP_MUX("exin5", EXIN, pins_exin5),
322 GRP_MUX("gnt4", PCI, pins_pci_gnt4),
323 GRP_MUX("req4", PCI, pins_pci_gnt4),
324 GRP_MUX("mdio", MDIO, pins_mdio),
325 };
326
327 static const struct ltq_pin_group ase_grps[] = {
328 GRP_MUX("exin0", EXIN, ase_pins_exin0),
329 GRP_MUX("exin1", EXIN, ase_pins_exin1),
330 GRP_MUX("exin2", EXIN, ase_pins_exin2),
331 GRP_MUX("jtag", JTAG, ase_pins_jtag),
332 GRP_MUX("stp", STP, ase_pins_stp),
333 GRP_MUX("asc", ASC, ase_pins_asc),
334 GRP_MUX("gpt1", GPT, ase_pins_gpt1),
335 GRP_MUX("gpt2", GPT, ase_pins_gpt2),
336 GRP_MUX("gpt3", GPT, ase_pins_gpt3),
337 GRP_MUX("ephy", EPHY, ase_pins_ephy),
338 GRP_MUX("dfe", DFE, ase_pins_dfe),
339 GRP_MUX("spi", SPI, ase_pins_spi),
340 GRP_MUX("spi_cs1", SPI, ase_pins_spi_cs1),
341 GRP_MUX("spi_cs2", SPI, ase_pins_spi_cs2),
342 GRP_MUX("spi_cs3", SPI, ase_pins_spi_cs3),
343 };
344
345 static const char * const xway_pci_grps[] = {"gnt1", "gnt2",
346 "gnt3", "req1",
347 "req2", "req3"};
348 static const char * const xway_spi_grps[] = {"spi", "spi_cs1",
349 "spi_cs2", "spi_cs3",
350 "spi_cs4", "spi_cs5",
351 "spi_cs6"};
352 static const char * const xway_cgu_grps[] = {"clkout0", "clkout1",
353 "clkout2", "clkout3"};
354 static const char * const xway_ebu_grps[] = {"ebu a23", "ebu a24",
355 "ebu a25", "ebu cs1",
356 "ebu wait", "ebu clk",
357 "nand ale", "nand cs1",
358 "nand cle"};
359 static const char * const xway_exin_grps[] = {"exin0", "exin1", "exin2"};
360 static const char * const xway_gpt_grps[] = {"gpt1", "gpt2", "gpt3"};
361 static const char * const xway_asc_grps[] = {"asc0", "asc0 cts rts"};
362 static const char * const xway_jtag_grps[] = {"jtag"};
363 static const char * const xway_stp_grps[] = {"stp"};
364 static const char * const xway_nmi_grps[] = {"nmi"};
365
366 /* ar9/vr9/gr9 */
367 static const char * const xrx_mdio_grps[] = {"mdio"};
368 static const char * const xrx_ebu_grps[] = {"ebu a23", "ebu a24",
369 "ebu a25", "ebu cs1",
370 "ebu wait", "ebu clk",
371 "nand ale", "nand cs1",
372 "nand cle", "nand rdy",
373 "nand rd"};
374 static const char * const xrx_exin_grps[] = {"exin0", "exin1", "exin2",
375 "exin3", "exin4", "exin5"};
376 static const char * const xrx_pci_grps[] = {"gnt1", "gnt2",
377 "gnt3", "gnt4",
378 "req1", "req2",
379 "req3", "req4"};
380
381 /* ase */
382 static const char * const ase_exin_grps[] = {"exin0", "exin1", "exin2"};
383 static const char * const ase_gpt_grps[] = {"gpt1", "gpt2", "gpt3"};
384 static const char * const ase_dfe_grps[] = {"dfe"};
385 static const char * const ase_ephy_grps[] = {"ephy"};
386 static const char * const ase_asc_grps[] = {"asc"};
387 static const char * const ase_jtag_grps[] = {"jtag"};
388 static const char * const ase_stp_grps[] = {"stp"};
389 static const char * const ase_spi_grps[] = {"spi", "spi_cs1",
390 "spi_cs2", "spi_cs3"};
391
392 static const struct ltq_pmx_func danube_funcs[] = {
393 {"spi", ARRAY_AND_SIZE(xway_spi_grps)},
394 {"asc", ARRAY_AND_SIZE(xway_asc_grps)},
395 {"cgu", ARRAY_AND_SIZE(xway_cgu_grps)},
396 {"jtag", ARRAY_AND_SIZE(xway_jtag_grps)},
397 {"exin", ARRAY_AND_SIZE(xway_exin_grps)},
398 {"stp", ARRAY_AND_SIZE(xway_stp_grps)},
399 {"gpt", ARRAY_AND_SIZE(xway_gpt_grps)},
400 {"nmi", ARRAY_AND_SIZE(xway_nmi_grps)},
401 {"pci", ARRAY_AND_SIZE(xway_pci_grps)},
402 {"ebu", ARRAY_AND_SIZE(xway_ebu_grps)},
403 };
404
405 static const struct ltq_pmx_func xrx_funcs[] = {
406 {"spi", ARRAY_AND_SIZE(xway_spi_grps)},
407 {"asc", ARRAY_AND_SIZE(xway_asc_grps)},
408 {"cgu", ARRAY_AND_SIZE(xway_cgu_grps)},
409 {"jtag", ARRAY_AND_SIZE(xway_jtag_grps)},
410 {"exin", ARRAY_AND_SIZE(xrx_exin_grps)},
411 {"stp", ARRAY_AND_SIZE(xway_stp_grps)},
412 {"gpt", ARRAY_AND_SIZE(xway_gpt_grps)},
413 {"nmi", ARRAY_AND_SIZE(xway_nmi_grps)},
414 {"pci", ARRAY_AND_SIZE(xrx_pci_grps)},
415 {"ebu", ARRAY_AND_SIZE(xrx_ebu_grps)},
416 {"mdio", ARRAY_AND_SIZE(xrx_mdio_grps)},
417 };
418
419 static const struct ltq_pmx_func ase_funcs[] = {
420 {"spi", ARRAY_AND_SIZE(ase_spi_grps)},
421 {"asc", ARRAY_AND_SIZE(ase_asc_grps)},
422 {"jtag", ARRAY_AND_SIZE(ase_jtag_grps)},
423 {"exin", ARRAY_AND_SIZE(ase_exin_grps)},
424 {"stp", ARRAY_AND_SIZE(ase_stp_grps)},
425 {"gpt", ARRAY_AND_SIZE(ase_gpt_grps)},
426 {"ephy", ARRAY_AND_SIZE(ase_ephy_grps)},
427 {"dfe", ARRAY_AND_SIZE(ase_dfe_grps)},
428 };
429
430 /* --------- pinconf related code --------- */
431 static int xway_pinconf_get(struct pinctrl_dev *pctldev,
432 unsigned pin,
433 unsigned long *config)
434 {
435 struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev);
436 enum ltq_pinconf_param param = LTQ_PINCONF_UNPACK_PARAM(*config);
437 int port = PORT(pin);
438 u32 reg;
439
440 switch (param) {
441 case LTQ_PINCONF_PARAM_OPEN_DRAIN:
442 if (port == PORT3)
443 reg = GPIO3_OD;
444 else
445 reg = GPIO_OD(pin);
446 *config = LTQ_PINCONF_PACK(param,
447 !gpio_getbit(info->membase[0], reg, PORT_PIN(pin)));
448 break;
449
450 case LTQ_PINCONF_PARAM_PULL:
451 if (port == PORT3)
452 reg = GPIO3_PUDEN;
453 else
454 reg = GPIO_PUDEN(pin);
455 if (!gpio_getbit(info->membase[0], reg, PORT_PIN(pin))) {
456 *config = LTQ_PINCONF_PACK(param, 0);
457 break;
458 }
459
460 if (port == PORT3)
461 reg = GPIO3_PUDSEL;
462 else
463 reg = GPIO_PUDSEL(pin);
464 if (!gpio_getbit(info->membase[0], reg, PORT_PIN(pin)))
465 *config = LTQ_PINCONF_PACK(param, 2);
466 else
467 *config = LTQ_PINCONF_PACK(param, 1);
468 break;
469
470 case LTQ_PINCONF_PARAM_OUTPUT:
471 reg = GPIO_DIR(pin);
472 *config = LTQ_PINCONF_PACK(param,
473 gpio_getbit(info->membase[0], reg, PORT_PIN(pin)));
474 break;
475 default:
476 dev_err(pctldev->dev, "Invalid config param %04x\n", param);
477 return -ENOTSUPP;
478 }
479 return 0;
480 }
481
482 static int xway_pinconf_set(struct pinctrl_dev *pctldev,
483 unsigned pin,
484 unsigned long config)
485 {
486 struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev);
487 enum ltq_pinconf_param param = LTQ_PINCONF_UNPACK_PARAM(config);
488 int arg = LTQ_PINCONF_UNPACK_ARG(config);
489 int port = PORT(pin);
490 u32 reg;
491
492 switch (param) {
493 case LTQ_PINCONF_PARAM_OPEN_DRAIN:
494 if (port == PORT3)
495 reg = GPIO3_OD;
496 else
497 reg = GPIO_OD(pin);
498 if (arg == 0)
499 gpio_setbit(info->membase[0], reg, PORT_PIN(pin));
500 else
501 gpio_clearbit(info->membase[0], reg, PORT_PIN(pin));
502 break;
503
504 case LTQ_PINCONF_PARAM_PULL:
505 if (port == PORT3)
506 reg = GPIO3_PUDEN;
507 else
508 reg = GPIO_PUDEN(pin);
509 if (arg == 0) {
510 gpio_clearbit(info->membase[0], reg, PORT_PIN(pin));
511 break;
512 }
513 gpio_setbit(info->membase[0], reg, PORT_PIN(pin));
514
515 if (port == PORT3)
516 reg = GPIO3_PUDSEL;
517 else
518 reg = GPIO_PUDSEL(pin);
519 if (arg == 1)
520 gpio_clearbit(info->membase[0], reg, PORT_PIN(pin));
521 else if (arg == 2)
522 gpio_setbit(info->membase[0], reg, PORT_PIN(pin));
523 else
524 dev_err(pctldev->dev, "Invalid pull value %d\n", arg);
525 break;
526
527 case LTQ_PINCONF_PARAM_OUTPUT:
528 reg = GPIO_DIR(pin);
529 if (arg == 0)
530 gpio_clearbit(info->membase[0], reg, PORT_PIN(pin));
531 else
532 gpio_setbit(info->membase[0], reg, PORT_PIN(pin));
533 break;
534
535 default:
536 dev_err(pctldev->dev, "Invalid config param %04x\n", param);
537 return -ENOTSUPP;
538 }
539 return 0;
540 }
541
542 int xway_pinconf_group_set(struct pinctrl_dev *pctldev,
543 unsigned selector,
544 unsigned long config)
545 {
546 struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev);
547 int i, ret = 0;
548
549 for (i = 0; i < info->grps[selector].npins && !ret; i++)
550 ret = xway_pinconf_set(pctldev,
551 info->grps[selector].pins[i], config);
552
553 return ret;
554 }
555
556 static const struct pinconf_ops xway_pinconf_ops = {
557 .pin_config_get = xway_pinconf_get,
558 .pin_config_set = xway_pinconf_set,
559 .pin_config_group_set = xway_pinconf_group_set,
560 };
561
562 static struct pinctrl_desc xway_pctrl_desc = {
563 .owner = THIS_MODULE,
564 .confops = &xway_pinconf_ops,
565 };
566
567 static inline int xway_mux_apply(struct pinctrl_dev *pctrldev,
568 int pin, int mux)
569 {
570 struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
571 int port = PORT(pin);
572 u32 alt1_reg = GPIO_ALT1(pin);
573
574 if (port == PORT3)
575 alt1_reg = GPIO3_ALT1;
576
577 if (mux & MUX_ALT0)
578 gpio_setbit(info->membase[0], GPIO_ALT0(pin), PORT_PIN(pin));
579 else
580 gpio_clearbit(info->membase[0], GPIO_ALT0(pin), PORT_PIN(pin));
581
582 if (mux & MUX_ALT1)
583 gpio_setbit(info->membase[0], alt1_reg, PORT_PIN(pin));
584 else
585 gpio_clearbit(info->membase[0], alt1_reg, PORT_PIN(pin));
586
587 return 0;
588 }
589
590 static const struct ltq_cfg_param xway_cfg_params[] = {
591 {"lantiq,pull", LTQ_PINCONF_PARAM_PULL},
592 {"lantiq,open-drain", LTQ_PINCONF_PARAM_OPEN_DRAIN},
593 {"lantiq,output", LTQ_PINCONF_PARAM_OUTPUT},
594 };
595
596 static struct ltq_pinmux_info xway_info = {
597 .desc = &xway_pctrl_desc,
598 .apply_mux = xway_mux_apply,
599 .params = xway_cfg_params,
600 .num_params = ARRAY_SIZE(xway_cfg_params),
601 };
602
603 /* --------- gpio_chip related code --------- */
604 static void xway_gpio_set(struct gpio_chip *chip, unsigned int pin, int val)
605 {
606 struct ltq_pinmux_info *info = dev_get_drvdata(chip->dev);
607
608 if (val)
609 gpio_setbit(info->membase[0], GPIO_OUT(pin), PORT_PIN(pin));
610 else
611 gpio_clearbit(info->membase[0], GPIO_OUT(pin), PORT_PIN(pin));
612 }
613
614 static int xway_gpio_get(struct gpio_chip *chip, unsigned int pin)
615 {
616 struct ltq_pinmux_info *info = dev_get_drvdata(chip->dev);
617
618 return gpio_getbit(info->membase[0], GPIO_IN(pin), PORT_PIN(pin));
619 }
620
621 static int xway_gpio_dir_in(struct gpio_chip *chip, unsigned int pin)
622 {
623 struct ltq_pinmux_info *info = dev_get_drvdata(chip->dev);
624
625 gpio_clearbit(info->membase[0], GPIO_DIR(pin), PORT_PIN(pin));
626
627 return 0;
628 }
629
630 static int xway_gpio_dir_out(struct gpio_chip *chip, unsigned int pin, int val)
631 {
632 struct ltq_pinmux_info *info = dev_get_drvdata(chip->dev);
633
634 gpio_setbit(info->membase[0], GPIO_DIR(pin), PORT_PIN(pin));
635 xway_gpio_set(chip, pin, val);
636
637 return 0;
638 }
639
640 static int xway_gpio_req(struct gpio_chip *chip, unsigned offset)
641 {
642 int gpio = chip->base + offset;
643
644 return pinctrl_request_gpio(gpio);
645 }
646
647 static void xway_gpio_free(struct gpio_chip *chip, unsigned offset)
648 {
649 int gpio = chip->base + offset;
650
651 pinctrl_free_gpio(gpio);
652 }
653
654 static struct gpio_chip xway_chip = {
655 .label = "gpio-xway",
656 .direction_input = xway_gpio_dir_in,
657 .direction_output = xway_gpio_dir_out,
658 .get = xway_gpio_get,
659 .set = xway_gpio_set,
660 .request = xway_gpio_req,
661 .free = xway_gpio_free,
662 .base = -1,
663 };
664
665
666 /* --------- register the pinctrl layer --------- */
667 static const unsigned xway_exin_pin_map[] = {GPIO0, GPIO1, GPIO2, GPIO39, GPIO46, GPIO9};
668 static const unsigned ase_exin_pins_map[] = {GPIO6, GPIO29, GPIO0};
669
670 static struct pinctrl_xway_soc {
671 int pin_count;
672 const struct ltq_mfp_pin *mfp;
673 const struct ltq_pin_group *grps;
674 unsigned int num_grps;
675 const struct ltq_pmx_func *funcs;
676 unsigned int num_funcs;
677 const unsigned *exin;
678 unsigned int num_exin;
679 } soc_cfg[] = {
680 /* legacy xway */
681 {XWAY_MAX_PIN, xway_mfp,
682 xway_grps, ARRAY_SIZE(xway_grps),
683 danube_funcs, ARRAY_SIZE(danube_funcs),
684 xway_exin_pin_map, 3},
685 /* xway xr9 series */
686 {XR9_MAX_PIN, xway_mfp,
687 xway_grps, ARRAY_SIZE(xway_grps),
688 xrx_funcs, ARRAY_SIZE(xrx_funcs),
689 xway_exin_pin_map, 6},
690 /* xway ase series */
691 {XWAY_MAX_PIN, ase_mfp,
692 ase_grps, ARRAY_SIZE(ase_grps),
693 ase_funcs, ARRAY_SIZE(ase_funcs),
694 ase_exin_pins_map, 3},
695 };
696
697 static struct pinctrl_gpio_range xway_gpio_range = {
698 .name = "XWAY GPIO",
699 .gc = &xway_chip,
700 };
701
702 static const struct of_device_id xway_match[] = {
703 { .compatible = "lantiq,pinctrl-xway", .data = &soc_cfg[0]},
704 { .compatible = "lantiq,pinctrl-xr9", .data = &soc_cfg[1]},
705 { .compatible = "lantiq,pinctrl-ase", .data = &soc_cfg[2]},
706 {},
707 };
708 MODULE_DEVICE_TABLE(of, xway_match);
709
710 static int pinmux_xway_probe(struct platform_device *pdev)
711 {
712 const struct of_device_id *match;
713 const struct pinctrl_xway_soc *xway_soc;
714 struct resource *res;
715 int ret, i;
716
717 /* get and remap our register range */
718 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
719 xway_info.membase[0] = devm_ioremap_resource(&pdev->dev, res);
720 if (IS_ERR(xway_info.membase[0]))
721 return PTR_ERR(xway_info.membase[0]);
722
723 match = of_match_device(xway_match, &pdev->dev);
724 if (match)
725 xway_soc = (const struct pinctrl_xway_soc *) match->data;
726 else
727 xway_soc = &soc_cfg[0];
728
729 /* find out how many pads we have */
730 xway_chip.ngpio = xway_soc->pin_count;
731
732 /* load our pad descriptors */
733 xway_info.pads = devm_kzalloc(&pdev->dev,
734 sizeof(struct pinctrl_pin_desc) * xway_chip.ngpio,
735 GFP_KERNEL);
736 if (!xway_info.pads) {
737 dev_err(&pdev->dev, "Failed to allocate pads\n");
738 return -ENOMEM;
739 }
740 for (i = 0; i < xway_chip.ngpio; i++) {
741 /* strlen("ioXY") + 1 = 5 */
742 char *name = devm_kzalloc(&pdev->dev, 5, GFP_KERNEL);
743
744 if (!name) {
745 dev_err(&pdev->dev, "Failed to allocate pad name\n");
746 return -ENOMEM;
747 }
748 snprintf(name, 5, "io%d", i);
749 xway_info.pads[i].number = GPIO0 + i;
750 xway_info.pads[i].name = name;
751 }
752 xway_pctrl_desc.pins = xway_info.pads;
753
754 /* load the gpio chip */
755 xway_chip.dev = &pdev->dev;
756 of_gpiochip_add(&xway_chip);
757 ret = gpiochip_add(&xway_chip);
758 if (ret) {
759 dev_err(&pdev->dev, "Failed to register gpio chip\n");
760 return ret;
761 }
762
763 /* setup the data needed by pinctrl */
764 xway_pctrl_desc.name = dev_name(&pdev->dev);
765 xway_pctrl_desc.npins = xway_chip.ngpio;
766
767 xway_info.num_pads = xway_chip.ngpio;
768 xway_info.num_mfp = xway_chip.ngpio;
769 xway_info.mfp = xway_soc->mfp;
770 xway_info.grps = xway_soc->grps;
771 xway_info.num_grps = xway_soc->num_grps;
772 xway_info.funcs = xway_soc->funcs;
773 xway_info.num_funcs = xway_soc->num_funcs;
774 xway_info.exin = xway_soc->exin;
775 xway_info.num_exin = xway_soc->num_exin;
776
777 /* register with the generic lantiq layer */
778 ret = ltq_pinctrl_register(pdev, &xway_info);
779 if (ret) {
780 dev_err(&pdev->dev, "Failed to register pinctrl driver\n");
781 return ret;
782 }
783
784 /* finish with registering the gpio range in pinctrl */
785 xway_gpio_range.npins = xway_chip.ngpio;
786 xway_gpio_range.base = xway_chip.base;
787 pinctrl_add_gpio_range(xway_info.pctrl, &xway_gpio_range);
788 dev_info(&pdev->dev, "Init done\n");
789 return 0;
790 }
791
792 static struct platform_driver pinmux_xway_driver = {
793 .probe = pinmux_xway_probe,
794 .driver = {
795 .name = "pinctrl-xway",
796 .owner = THIS_MODULE,
797 .of_match_table = xway_match,
798 },
799 };
800
801 static int __init pinmux_xway_init(void)
802 {
803 return platform_driver_register(&pinmux_xway_driver);
804 }
805
806 core_initcall_sync(pinmux_xway_init);
CRIS linux kernel tree