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Linux 3.11-rc3
[cris-mirror.git] / drivers / pinctrl / sh-pfc / core.c
blobf3fc66b243701acc55faa8659e702dc69157ff34
1 /*
2 * SuperH Pin Function Controller support.
3 *
4 * Copyright (C) 2008 Magnus Damm
5 * Copyright (C) 2009 - 2012 Paul Mundt
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11
12 #define DRV_NAME "sh-pfc"
13
14 #include <linux/bitops.h>
15 #include <linux/err.h>
16 #include <linux/errno.h>
17 #include <linux/io.h>
18 #include <linux/ioport.h>
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/of.h>
22 #include <linux/of_device.h>
23 #include <linux/pinctrl/machine.h>
24 #include <linux/platform_device.h>
25 #include <linux/slab.h>
26
27 #include "core.h"
28
29 static int sh_pfc_ioremap(struct sh_pfc *pfc, struct platform_device *pdev)
30 {
31 struct resource *res;
32 int k;
33
34 if (pdev->num_resources == 0)
35 return -EINVAL;
36
37 pfc->window = devm_kzalloc(pfc->dev, pdev->num_resources *
38 sizeof(*pfc->window), GFP_NOWAIT);
39 if (!pfc->window)
40 return -ENOMEM;
41
42 pfc->num_windows = pdev->num_resources;
43
44 for (k = 0, res = pdev->resource; k < pdev->num_resources; k++, res++) {
45 WARN_ON(resource_type(res) != IORESOURCE_MEM);
46 pfc->window[k].phys = res->start;
47 pfc->window[k].size = resource_size(res);
48 pfc->window[k].virt = devm_ioremap_nocache(pfc->dev, res->start,
49 resource_size(res));
50 if (!pfc->window[k].virt)
51 return -ENOMEM;
52 }
53
54 return 0;
55 }
56
57 static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc,
58 unsigned long address)
59 {
60 struct sh_pfc_window *window;
61 unsigned int i;
62
63 /* scan through physical windows and convert address */
64 for (i = 0; i < pfc->num_windows; i++) {
65 window = pfc->window + i;
66
67 if (address < window->phys)
68 continue;
69
70 if (address >= (window->phys + window->size))
71 continue;
72
73 return window->virt + (address - window->phys);
74 }
75
76 BUG();
77 return NULL;
78 }
79
80 int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
81 {
82 unsigned int offset;
83 unsigned int i;
84
85 if (pfc->info->ranges == NULL)
86 return pin;
87
88 for (i = 0, offset = 0; i < pfc->info->nr_ranges; ++i) {
89 const struct pinmux_range *range = &pfc->info->ranges[i];
90
91 if (pin <= range->end)
92 return pin >= range->begin
93 ? offset + pin - range->begin : -1;
94
95 offset += range->end - range->begin + 1;
96 }
97
98 return -EINVAL;
99 }
100
101 static int sh_pfc_enum_in_range(pinmux_enum_t enum_id,
102 const struct pinmux_range *r)
103 {
104 if (enum_id < r->begin)
105 return 0;
106
107 if (enum_id > r->end)
108 return 0;
109
110 return 1;
111 }
112
113 unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg,
114 unsigned long reg_width)
115 {
116 switch (reg_width) {
117 case 8:
118 return ioread8(mapped_reg);
119 case 16:
120 return ioread16(mapped_reg);
121 case 32:
122 return ioread32(mapped_reg);
123 }
124
125 BUG();
126 return 0;
127 }
128
129 void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned long reg_width,
130 unsigned long data)
131 {
132 switch (reg_width) {
133 case 8:
134 iowrite8(data, mapped_reg);
135 return;
136 case 16:
137 iowrite16(data, mapped_reg);
138 return;
139 case 32:
140 iowrite32(data, mapped_reg);
141 return;
142 }
143
144 BUG();
145 }
146
147 static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
148 const struct pinmux_cfg_reg *crp,
149 unsigned long in_pos,
150 void __iomem **mapped_regp,
151 unsigned long *maskp,
152 unsigned long *posp)
153 {
154 int k;
155
156 *mapped_regp = sh_pfc_phys_to_virt(pfc, crp->reg);
157
158 if (crp->field_width) {
159 *maskp = (1 << crp->field_width) - 1;
160 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
161 } else {
162 *maskp = (1 << crp->var_field_width[in_pos]) - 1;
163 *posp = crp->reg_width;
164 for (k = 0; k <= in_pos; k++)
165 *posp -= crp->var_field_width[k];
166 }
167 }
168
169 static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
170 const struct pinmux_cfg_reg *crp,
171 unsigned long field, unsigned long value)
172 {
173 void __iomem *mapped_reg;
174 unsigned long mask, pos, data;
175
176 sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
177
178 dev_dbg(pfc->dev, "write_reg addr = %lx, value = %ld, field = %ld, "
179 "r_width = %ld, f_width = %ld\n",
180 crp->reg, value, field, crp->reg_width, crp->field_width);
181
182 mask = ~(mask << pos);
183 value = value << pos;
184
185 data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
186 data &= mask;
187 data |= value;
188
189 if (pfc->info->unlock_reg)
190 sh_pfc_write_raw_reg(
191 sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,
192 ~data);
193
194 sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
195 }
196
197 static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id,
198 const struct pinmux_cfg_reg **crp, int *fieldp,
199 int *valuep)
200 {
201 const struct pinmux_cfg_reg *config_reg;
202 unsigned long r_width, f_width, curr_width, ncomb;
203 int k, m, n, pos, bit_pos;
204
205 k = 0;
206 while (1) {
207 config_reg = pfc->info->cfg_regs + k;
208
209 r_width = config_reg->reg_width;
210 f_width = config_reg->field_width;
211
212 if (!r_width)
213 break;
214
215 pos = 0;
216 m = 0;
217 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
218 if (f_width)
219 curr_width = f_width;
220 else
221 curr_width = config_reg->var_field_width[m];
222
223 ncomb = 1 << curr_width;
224 for (n = 0; n < ncomb; n++) {
225 if (config_reg->enum_ids[pos + n] == enum_id) {
226 *crp = config_reg;
227 *fieldp = m;
228 *valuep = n;
229 return 0;
230 }
231 }
232 pos += ncomb;
233 m++;
234 }
235 k++;
236 }
237
238 return -EINVAL;
239 }
240
241 static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, pinmux_enum_t mark, int pos,
242 pinmux_enum_t *enum_idp)
243 {
244 const pinmux_enum_t *data = pfc->info->gpio_data;
245 int k;
246
247 if (pos) {
248 *enum_idp = data[pos + 1];
249 return pos + 1;
250 }
251
252 for (k = 0; k < pfc->info->gpio_data_size; k++) {
253 if (data[k] == mark) {
254 *enum_idp = data[k + 1];
255 return k + 1;
256 }
257 }
258
259 dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
260 mark);
261 return -EINVAL;
262 }
263
264 int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
265 {
266 const struct pinmux_cfg_reg *cr = NULL;
267 pinmux_enum_t enum_id;
268 const struct pinmux_range *range;
269 int in_range, pos, field, value;
270 int ret;
271
272 switch (pinmux_type) {
273 case PINMUX_TYPE_GPIO:
274 case PINMUX_TYPE_FUNCTION:
275 range = NULL;
276 break;
277
278 case PINMUX_TYPE_OUTPUT:
279 range = &pfc->info->output;
280 break;
281
282 case PINMUX_TYPE_INPUT:
283 range = &pfc->info->input;
284 break;
285
286 case PINMUX_TYPE_INPUT_PULLUP:
287 range = &pfc->info->input_pu;
288 break;
289
290 case PINMUX_TYPE_INPUT_PULLDOWN:
291 range = &pfc->info->input_pd;
292 break;
293
294 default:
295 return -EINVAL;
296 }
297
298 pos = 0;
299 enum_id = 0;
300 field = 0;
301 value = 0;
302
303 /* Iterate over all the configuration fields we need to update. */
304 while (1) {
305 pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
306 if (pos < 0)
307 return pos;
308
309 if (!enum_id)
310 break;
311
312 /* Check if the configuration field selects a function. If it
313 * doesn't, skip the field if it's not applicable to the
314 * requested pinmux type.
315 */
316 in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
317 if (!in_range) {
318 if (pinmux_type == PINMUX_TYPE_FUNCTION) {
319 /* Functions are allowed to modify all
320 * fields.
321 */
322 in_range = 1;
323 } else if (pinmux_type != PINMUX_TYPE_GPIO) {
324 /* Input/output types can only modify fields
325 * that correspond to their respective ranges.
326 */
327 in_range = sh_pfc_enum_in_range(enum_id, range);
328
329 /*
330 * special case pass through for fixed
331 * input-only or output-only pins without
332 * function enum register association.
333 */
334 if (in_range && enum_id == range->force)
335 continue;
336 }
337 /* GPIOs are only allowed to modify function fields. */
338 }
339
340 if (!in_range)
341 continue;
342
343 ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
344 if (ret < 0)
345 return ret;
346
347 sh_pfc_write_config_reg(pfc, cr, field, value);
348 }
349
350 return 0;
351 }
352
353 #ifdef CONFIG_OF
354 static const struct of_device_id sh_pfc_of_table[] = {
355 #ifdef CONFIG_PINCTRL_PFC_R8A73A4
356 {
357 .compatible = "renesas,pfc-r8a73a4",
358 .data = &r8a73a4_pinmux_info,
359 },
360 #endif
361 #ifdef CONFIG_PINCTRL_PFC_R8A7740
362 {
363 .compatible = "renesas,pfc-r8a7740",
364 .data = &r8a7740_pinmux_info,
365 },
366 #endif
367 #ifdef CONFIG_PINCTRL_PFC_R8A7778
368 {
369 .compatible = "renesas,pfc-r8a7778",
370 .data = &r8a7778_pinmux_info,
371 },
372 #endif
373 #ifdef CONFIG_PINCTRL_PFC_R8A7779
374 {
375 .compatible = "renesas,pfc-r8a7779",
376 .data = &r8a7779_pinmux_info,
377 },
378 #endif
379 #ifdef CONFIG_PINCTRL_PFC_R8A7790
380 {
381 .compatible = "renesas,pfc-r8a7790",
382 .data = &r8a7790_pinmux_info,
383 },
384 #endif
385 #ifdef CONFIG_PINCTRL_PFC_SH7372
386 {
387 .compatible = "renesas,pfc-sh7372",
388 .data = &sh7372_pinmux_info,
389 },
390 #endif
391 #ifdef CONFIG_PINCTRL_PFC_SH73A0
392 {
393 .compatible = "renesas,pfc-sh73a0",
394 .data = &sh73a0_pinmux_info,
395 },
396 #endif
397 { },
398 };
399 MODULE_DEVICE_TABLE(of, sh_pfc_of_table);
400 #endif
401
402 static int sh_pfc_probe(struct platform_device *pdev)
403 {
404 const struct platform_device_id *platid = platform_get_device_id(pdev);
405 #ifdef CONFIG_OF
406 struct device_node *np = pdev->dev.of_node;
407 #endif
408 const struct sh_pfc_soc_info *info;
409 struct sh_pfc *pfc;
410 int ret;
411
412 #ifdef CONFIG_OF
413 if (np)
414 info = of_match_device(sh_pfc_of_table, &pdev->dev)->data;
415 else
416 #endif
417 info = platid ? (const void *)platid->driver_data : NULL;
418
419 if (info == NULL)
420 return -ENODEV;
421
422 pfc = devm_kzalloc(&pdev->dev, sizeof(*pfc), GFP_KERNEL);
423 if (pfc == NULL)
424 return -ENOMEM;
425
426 pfc->info = info;
427 pfc->dev = &pdev->dev;
428
429 ret = sh_pfc_ioremap(pfc, pdev);
430 if (unlikely(ret < 0))
431 return ret;
432
433 spin_lock_init(&pfc->lock);
434
435 if (info->ops && info->ops->init) {
436 ret = info->ops->init(pfc);
437 if (ret < 0)
438 return ret;
439 }
440
441 pinctrl_provide_dummies();
442
443 /*
444 * Initialize pinctrl bindings first
445 */
446 ret = sh_pfc_register_pinctrl(pfc);
447 if (unlikely(ret != 0))
448 goto error;
449
450 #ifdef CONFIG_GPIO_SH_PFC
451 /*
452 * Then the GPIO chip
453 */
454 ret = sh_pfc_register_gpiochip(pfc);
455 if (unlikely(ret != 0)) {
456 /*
457 * If the GPIO chip fails to come up we still leave the
458 * PFC state as it is, given that there are already
459 * extant users of it that have succeeded by this point.
460 */
461 dev_notice(pfc->dev, "failed to init GPIO chip, ignoring...\n");
462 }
463 #endif
464
465 platform_set_drvdata(pdev, pfc);
466
467 dev_info(pfc->dev, "%s support registered\n", info->name);
468
469 return 0;
470
471 error:
472 if (info->ops && info->ops->exit)
473 info->ops->exit(pfc);
474 return ret;
475 }
476
477 static int sh_pfc_remove(struct platform_device *pdev)
478 {
479 struct sh_pfc *pfc = platform_get_drvdata(pdev);
480
481 #ifdef CONFIG_GPIO_SH_PFC
482 sh_pfc_unregister_gpiochip(pfc);
483 #endif
484 sh_pfc_unregister_pinctrl(pfc);
485
486 if (pfc->info->ops && pfc->info->ops->exit)
487 pfc->info->ops->exit(pfc);
488
489 platform_set_drvdata(pdev, NULL);
490
491 return 0;
492 }
493
494 static const struct platform_device_id sh_pfc_id_table[] = {
495 #ifdef CONFIG_PINCTRL_PFC_R8A73A4
496 { "pfc-r8a73a4", (kernel_ulong_t)&r8a73a4_pinmux_info },
497 #endif
498 #ifdef CONFIG_PINCTRL_PFC_R8A7740
499 { "pfc-r8a7740", (kernel_ulong_t)&r8a7740_pinmux_info },
500 #endif
501 #ifdef CONFIG_PINCTRL_PFC_R8A7778
502 { "pfc-r8a7778", (kernel_ulong_t)&r8a7778_pinmux_info },
503 #endif
504 #ifdef CONFIG_PINCTRL_PFC_R8A7779
505 { "pfc-r8a7779", (kernel_ulong_t)&r8a7779_pinmux_info },
506 #endif
507 #ifdef CONFIG_PINCTRL_PFC_R8A7790
508 { "pfc-r8a7790", (kernel_ulong_t)&r8a7790_pinmux_info },
509 #endif
510 #ifdef CONFIG_PINCTRL_PFC_SH7203
511 { "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info },
512 #endif
513 #ifdef CONFIG_PINCTRL_PFC_SH7264
514 { "pfc-sh7264", (kernel_ulong_t)&sh7264_pinmux_info },
515 #endif
516 #ifdef CONFIG_PINCTRL_PFC_SH7269
517 { "pfc-sh7269", (kernel_ulong_t)&sh7269_pinmux_info },
518 #endif
519 #ifdef CONFIG_PINCTRL_PFC_SH7372
520 { "pfc-sh7372", (kernel_ulong_t)&sh7372_pinmux_info },
521 #endif
522 #ifdef CONFIG_PINCTRL_PFC_SH73A0
523 { "pfc-sh73a0", (kernel_ulong_t)&sh73a0_pinmux_info },
524 #endif
525 #ifdef CONFIG_PINCTRL_PFC_SH7720
526 { "pfc-sh7720", (kernel_ulong_t)&sh7720_pinmux_info },
527 #endif
528 #ifdef CONFIG_PINCTRL_PFC_SH7722
529 { "pfc-sh7722", (kernel_ulong_t)&sh7722_pinmux_info },
530 #endif
531 #ifdef CONFIG_PINCTRL_PFC_SH7723
532 { "pfc-sh7723", (kernel_ulong_t)&sh7723_pinmux_info },
533 #endif
534 #ifdef CONFIG_PINCTRL_PFC_SH7724
535 { "pfc-sh7724", (kernel_ulong_t)&sh7724_pinmux_info },
536 #endif
537 #ifdef CONFIG_PINCTRL_PFC_SH7734
538 { "pfc-sh7734", (kernel_ulong_t)&sh7734_pinmux_info },
539 #endif
540 #ifdef CONFIG_PINCTRL_PFC_SH7757
541 { "pfc-sh7757", (kernel_ulong_t)&sh7757_pinmux_info },
542 #endif
543 #ifdef CONFIG_PINCTRL_PFC_SH7785
544 { "pfc-sh7785", (kernel_ulong_t)&sh7785_pinmux_info },
545 #endif
546 #ifdef CONFIG_PINCTRL_PFC_SH7786
547 { "pfc-sh7786", (kernel_ulong_t)&sh7786_pinmux_info },
548 #endif
549 #ifdef CONFIG_PINCTRL_PFC_SHX3
550 { "pfc-shx3", (kernel_ulong_t)&shx3_pinmux_info },
551 #endif
552 { "sh-pfc", 0 },
553 { },
554 };
555 MODULE_DEVICE_TABLE(platform, sh_pfc_id_table);
556
557 static struct platform_driver sh_pfc_driver = {
558 .probe = sh_pfc_probe,
559 .remove = sh_pfc_remove,
560 .id_table = sh_pfc_id_table,
561 .driver = {
562 .name = DRV_NAME,
563 .owner = THIS_MODULE,
564 .of_match_table = of_match_ptr(sh_pfc_of_table),
565 },
566 };
567
568 static int __init sh_pfc_init(void)
569 {
570 return platform_driver_register(&sh_pfc_driver);
571 }
572 postcore_initcall(sh_pfc_init);
573
574 static void __exit sh_pfc_exit(void)
575 {
576 platform_driver_unregister(&sh_pfc_driver);
577 }
578 module_exit(sh_pfc_exit);
579
580 MODULE_AUTHOR("Magnus Damm, Paul Mundt, Laurent Pinchart");
581 MODULE_DESCRIPTION("Pin Control and GPIO driver for SuperH pin function controller");
582 MODULE_LICENSE("GPL v2");
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