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Linux 3.11-rc3
[cris-mirror.git] / drivers / pinctrl / sh-pfc / pfc-r8a73a4.c
blob82bf6aba00743730716a02dd7d66bfd95cf8c178
1 /*
2 * Copyright (C) 2012-2013 Renesas Solutions Corp.
3 * Copyright (C) 2013 Magnus Damm
4 * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of the
9 * License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20 #include <linux/io.h>
21 #include <linux/kernel.h>
22 #include <linux/pinctrl/pinconf-generic.h>
23 #include <mach/irqs.h>
24 #include <mach/r8a73a4.h>
25
26 #include "core.h"
27 #include "sh_pfc.h"
28
29 #define CPU_ALL_PORT(fn, pfx, sfx) \
30 /* Port0 - Port30 */ \
31 PORT_10(fn, pfx, sfx), \
32 PORT_10(fn, pfx##1, sfx), \
33 PORT_10(fn, pfx##2, sfx), \
34 PORT_1(fn, pfx##30, sfx), \
35 /* Port32 - Port40 */ \
36 PORT_1(fn, pfx##32, sfx), PORT_1(fn, pfx##33, sfx), \
37 PORT_1(fn, pfx##34, sfx), PORT_1(fn, pfx##35, sfx), \
38 PORT_1(fn, pfx##36, sfx), PORT_1(fn, pfx##37, sfx), \
39 PORT_1(fn, pfx##38, sfx), PORT_1(fn, pfx##39, sfx), \
40 PORT_1(fn, pfx##40, sfx), \
41 /* Port64 - Port85 */ \
42 PORT_1(fn, pfx##64, sfx), PORT_1(fn, pfx##65, sfx), \
43 PORT_1(fn, pfx##66, sfx), PORT_1(fn, pfx##67, sfx), \
44 PORT_1(fn, pfx##68, sfx), PORT_1(fn, pfx##69, sfx), \
45 PORT_10(fn, pfx##7, sfx), \
46 PORT_1(fn, pfx##80, sfx), PORT_1(fn, pfx##81, sfx), \
47 PORT_1(fn, pfx##82, sfx), PORT_1(fn, pfx##83, sfx), \
48 PORT_1(fn, pfx##84, sfx), PORT_1(fn, pfx##85, sfx), \
49 /* Port96 - Port126 */ \
50 PORT_1(fn, pfx##96, sfx), PORT_1(fn, pfx##97, sfx), \
51 PORT_1(fn, pfx##98, sfx), PORT_1(fn, pfx##99, sfx), \
52 PORT_10(fn, pfx##10, sfx), \
53 PORT_10(fn, pfx##11, sfx), \
54 PORT_1(fn, pfx##120, sfx), PORT_1(fn, pfx##121, sfx), \
55 PORT_1(fn, pfx##122, sfx), PORT_1(fn, pfx##123, sfx), \
56 PORT_1(fn, pfx##124, sfx), PORT_1(fn, pfx##125, sfx), \
57 PORT_1(fn, pfx##126, sfx), \
58 /* Port128 - Port134 */ \
59 PORT_1(fn, pfx##128, sfx), PORT_1(fn, pfx##129, sfx), \
60 PORT_1(fn, pfx##130, sfx), PORT_1(fn, pfx##131, sfx), \
61 PORT_1(fn, pfx##132, sfx), PORT_1(fn, pfx##133, sfx), \
62 PORT_1(fn, pfx##134, sfx), \
63 /* Port160 - Port178 */ \
64 PORT_10(fn, pfx##16, sfx), \
65 PORT_1(fn, pfx##170, sfx), PORT_1(fn, pfx##171, sfx), \
66 PORT_1(fn, pfx##172, sfx), PORT_1(fn, pfx##173, sfx), \
67 PORT_1(fn, pfx##174, sfx), PORT_1(fn, pfx##175, sfx), \
68 PORT_1(fn, pfx##176, sfx), PORT_1(fn, pfx##177, sfx), \
69 PORT_1(fn, pfx##178, sfx), \
70 /* Port192 - Port222 */ \
71 PORT_1(fn, pfx##192, sfx), PORT_1(fn, pfx##193, sfx), \
72 PORT_1(fn, pfx##194, sfx), PORT_1(fn, pfx##195, sfx), \
73 PORT_1(fn, pfx##196, sfx), PORT_1(fn, pfx##197, sfx), \
74 PORT_1(fn, pfx##198, sfx), PORT_1(fn, pfx##199, sfx), \
75 PORT_10(fn, pfx##20, sfx), \
76 PORT_10(fn, pfx##21, sfx), \
77 PORT_1(fn, pfx##220, sfx), PORT_1(fn, pfx##221, sfx), \
78 PORT_1(fn, pfx##222, sfx), \
79 /* Port224 - Port250 */ \
80 PORT_1(fn, pfx##224, sfx), PORT_1(fn, pfx##225, sfx), \
81 PORT_1(fn, pfx##226, sfx), PORT_1(fn, pfx##227, sfx), \
82 PORT_1(fn, pfx##228, sfx), PORT_1(fn, pfx##229, sfx), \
83 PORT_10(fn, pfx##23, sfx), \
84 PORT_10(fn, pfx##24, sfx), \
85 PORT_1(fn, pfx##250, sfx), \
86 /* Port256 - Port283 */ \
87 PORT_1(fn, pfx##256, sfx), PORT_1(fn, pfx##257, sfx), \
88 PORT_1(fn, pfx##258, sfx), PORT_1(fn, pfx##259, sfx), \
89 PORT_10(fn, pfx##26, sfx), \
90 PORT_10(fn, pfx##27, sfx), \
91 PORT_1(fn, pfx##280, sfx), PORT_1(fn, pfx##281, sfx), \
92 PORT_1(fn, pfx##282, sfx), PORT_1(fn, pfx##283, sfx), \
93 /* Port288 - Port308 */ \
94 PORT_1(fn, pfx##288, sfx), PORT_1(fn, pfx##289, sfx), \
95 PORT_10(fn, pfx##29, sfx), \
96 PORT_1(fn, pfx##300, sfx), PORT_1(fn, pfx##301, sfx), \
97 PORT_1(fn, pfx##302, sfx), PORT_1(fn, pfx##303, sfx), \
98 PORT_1(fn, pfx##304, sfx), PORT_1(fn, pfx##305, sfx), \
99 PORT_1(fn, pfx##306, sfx), PORT_1(fn, pfx##307, sfx), \
100 PORT_1(fn, pfx##308, sfx), \
101 /* Port320 - Port329 */ \
102 PORT_10(fn, pfx##32, sfx)
103
104
105 enum {
106 PINMUX_RESERVED = 0,
107
108 /* PORT0_DATA -> PORT329_DATA */
109 PINMUX_DATA_BEGIN,
110 PORT_ALL(DATA),
111 PINMUX_DATA_END,
112
113 /* PORT0_IN -> PORT329_IN */
114 PINMUX_INPUT_BEGIN,
115 PORT_ALL(IN),
116 PINMUX_INPUT_END,
117
118 /* PORT0_OUT -> PORT329_OUT */
119 PINMUX_OUTPUT_BEGIN,
120 PORT_ALL(OUT),
121 PINMUX_OUTPUT_END,
122
123 PINMUX_FUNCTION_BEGIN,
124 PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT329_FN_IN */
125 PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT329_FN_OUT */
126 PORT_ALL(FN0), /* PORT0_FN0 -> PORT329_FN0 */
127 PORT_ALL(FN1), /* PORT0_FN1 -> PORT329_FN1 */
128 PORT_ALL(FN2), /* PORT0_FN2 -> PORT329_FN2 */
129 PORT_ALL(FN3), /* PORT0_FN3 -> PORT329_FN3 */
130 PORT_ALL(FN4), /* PORT0_FN4 -> PORT329_FN4 */
131 PORT_ALL(FN5), /* PORT0_FN5 -> PORT329_FN5 */
132 PORT_ALL(FN6), /* PORT0_FN6 -> PORT329_FN6 */
133 PORT_ALL(FN7), /* PORT0_FN7 -> PORT329_FN7 */
134
135 MSEL1CR_31_0, MSEL1CR_31_1,
136 MSEL1CR_27_0, MSEL1CR_27_1,
137 MSEL1CR_25_0, MSEL1CR_25_1,
138 MSEL1CR_24_0, MSEL1CR_24_1,
139 MSEL1CR_22_0, MSEL1CR_22_1,
140 MSEL1CR_21_0, MSEL1CR_21_1,
141 MSEL1CR_20_0, MSEL1CR_20_1,
142 MSEL1CR_19_0, MSEL1CR_19_1,
143 MSEL1CR_18_0, MSEL1CR_18_1,
144 MSEL1CR_17_0, MSEL1CR_17_1,
145 MSEL1CR_16_0, MSEL1CR_16_1,
146 MSEL1CR_15_0, MSEL1CR_15_1,
147 MSEL1CR_14_0, MSEL1CR_14_1,
148 MSEL1CR_13_0, MSEL1CR_13_1,
149 MSEL1CR_12_0, MSEL1CR_12_1,
150 MSEL1CR_11_0, MSEL1CR_11_1,
151 MSEL1CR_10_0, MSEL1CR_10_1,
152 MSEL1CR_09_0, MSEL1CR_09_1,
153 MSEL1CR_08_0, MSEL1CR_08_1,
154 MSEL1CR_07_0, MSEL1CR_07_1,
155 MSEL1CR_06_0, MSEL1CR_06_1,
156 MSEL1CR_05_0, MSEL1CR_05_1,
157 MSEL1CR_04_0, MSEL1CR_04_1,
158 MSEL1CR_03_0, MSEL1CR_03_1,
159 MSEL1CR_02_0, MSEL1CR_02_1,
160 MSEL1CR_01_0, MSEL1CR_01_1,
161 MSEL1CR_00_0, MSEL1CR_00_1,
162
163 MSEL3CR_31_0, MSEL3CR_31_1,
164 MSEL3CR_28_0, MSEL3CR_28_1,
165 MSEL3CR_27_0, MSEL3CR_27_1,
166 MSEL3CR_26_0, MSEL3CR_26_1,
167 MSEL3CR_23_0, MSEL3CR_23_1,
168 MSEL3CR_22_0, MSEL3CR_22_1,
169 MSEL3CR_21_0, MSEL3CR_21_1,
170 MSEL3CR_20_0, MSEL3CR_20_1,
171 MSEL3CR_19_0, MSEL3CR_19_1,
172 MSEL3CR_18_0, MSEL3CR_18_1,
173 MSEL3CR_17_0, MSEL3CR_17_1,
174 MSEL3CR_16_0, MSEL3CR_16_1,
175 MSEL3CR_15_0, MSEL3CR_15_1,
176 MSEL3CR_12_0, MSEL3CR_12_1,
177 MSEL3CR_11_0, MSEL3CR_11_1,
178 MSEL3CR_10_0, MSEL3CR_10_1,
179 MSEL3CR_09_0, MSEL3CR_09_1,
180 MSEL3CR_06_0, MSEL3CR_06_1,
181 MSEL3CR_03_0, MSEL3CR_03_1,
182 MSEL3CR_01_0, MSEL3CR_01_1,
183 MSEL3CR_00_0, MSEL3CR_00_1,
184
185 MSEL4CR_30_0, MSEL4CR_30_1,
186 MSEL4CR_29_0, MSEL4CR_29_1,
187 MSEL4CR_28_0, MSEL4CR_28_1,
188 MSEL4CR_27_0, MSEL4CR_27_1,
189 MSEL4CR_26_0, MSEL4CR_26_1,
190 MSEL4CR_25_0, MSEL4CR_25_1,
191 MSEL4CR_24_0, MSEL4CR_24_1,
192 MSEL4CR_23_0, MSEL4CR_23_1,
193 MSEL4CR_22_0, MSEL4CR_22_1,
194 MSEL4CR_21_0, MSEL4CR_21_1,
195 MSEL4CR_20_0, MSEL4CR_20_1,
196 MSEL4CR_19_0, MSEL4CR_19_1,
197 MSEL4CR_18_0, MSEL4CR_18_1,
198 MSEL4CR_17_0, MSEL4CR_17_1,
199 MSEL4CR_16_0, MSEL4CR_16_1,
200 MSEL4CR_15_0, MSEL4CR_15_1,
201 MSEL4CR_14_0, MSEL4CR_14_1,
202 MSEL4CR_13_0, MSEL4CR_13_1,
203 MSEL4CR_12_0, MSEL4CR_12_1,
204 MSEL4CR_11_0, MSEL4CR_11_1,
205 MSEL4CR_10_0, MSEL4CR_10_1,
206 MSEL4CR_09_0, MSEL4CR_09_1,
207 MSEL4CR_07_0, MSEL4CR_07_1,
208 MSEL4CR_04_0, MSEL4CR_04_1,
209 MSEL4CR_01_0, MSEL4CR_01_1,
210
211 MSEL5CR_31_0, MSEL5CR_31_1,
212 MSEL5CR_30_0, MSEL5CR_30_1,
213 MSEL5CR_29_0, MSEL5CR_29_1,
214 MSEL5CR_28_0, MSEL5CR_28_1,
215 MSEL5CR_27_0, MSEL5CR_27_1,
216 MSEL5CR_26_0, MSEL5CR_26_1,
217 MSEL5CR_25_0, MSEL5CR_25_1,
218 MSEL5CR_24_0, MSEL5CR_24_1,
219 MSEL5CR_23_0, MSEL5CR_23_1,
220 MSEL5CR_22_0, MSEL5CR_22_1,
221 MSEL5CR_21_0, MSEL5CR_21_1,
222 MSEL5CR_20_0, MSEL5CR_20_1,
223 MSEL5CR_19_0, MSEL5CR_19_1,
224 MSEL5CR_18_0, MSEL5CR_18_1,
225 MSEL5CR_17_0, MSEL5CR_17_1,
226 MSEL5CR_16_0, MSEL5CR_16_1,
227 MSEL5CR_15_0, MSEL5CR_15_1,
228 MSEL5CR_14_0, MSEL5CR_14_1,
229 MSEL5CR_13_0, MSEL5CR_13_1,
230 MSEL5CR_12_0, MSEL5CR_12_1,
231 MSEL5CR_11_0, MSEL5CR_11_1,
232 MSEL5CR_10_0, MSEL5CR_10_1,
233 MSEL5CR_09_0, MSEL5CR_09_1,
234 MSEL5CR_08_0, MSEL5CR_08_1,
235 MSEL5CR_07_0, MSEL5CR_07_1,
236 MSEL5CR_06_0, MSEL5CR_06_1,
237
238 MSEL8CR_16_0, MSEL8CR_16_1,
239 MSEL8CR_01_0, MSEL8CR_01_1,
240 MSEL8CR_00_0, MSEL8CR_00_1,
241
242 PINMUX_FUNCTION_END,
243
244 PINMUX_MARK_BEGIN,
245
246
247 #define F1(a) a##_MARK
248 #define F2(a) a##_MARK
249 #define F3(a) a##_MARK
250 #define F4(a) a##_MARK
251 #define F5(a) a##_MARK
252 #define F6(a) a##_MARK
253 #define F7(a) a##_MARK
254 #define IRQ(a) IRQ##a##_MARK
255
256 F1(LCDD0), F3(PDM2_CLK_0), F7(DU0_DR0), IRQ(0), /* Port0 */
257 F1(LCDD1), F3(PDM2_DATA_1), F7(DU0_DR19), IRQ(1),
258 F1(LCDD2), F3(PDM3_CLK_2), F7(DU0_DR2), IRQ(2),
259 F1(LCDD3), F3(PDM3_DATA_3), F7(DU0_DR3), IRQ(3),
260 F1(LCDD4), F3(PDM4_CLK_4), F7(DU0_DR4), IRQ(4),
261 F1(LCDD5), F3(PDM4_DATA_5), F7(DU0_DR5), IRQ(5),
262 F1(LCDD6), F3(PDM0_OUTCLK_6), F7(DU0_DR6), IRQ(6),
263 F1(LCDD7), F3(PDM0_OUTDATA_7), F7(DU0_DR7), IRQ(7),
264 F1(LCDD8), F3(PDM1_OUTCLK_8), F7(DU0_DG0), IRQ(8),
265 F1(LCDD9), F3(PDM1_OUTDATA_9), F7(DU0_DG1), IRQ(9),
266 F1(LCDD10), F3(FSICCK), F7(DU0_DG2), IRQ(10), /* Port10 */
267 F1(LCDD11), F3(FSICISLD), F7(DU0_DG3), IRQ(11),
268 F1(LCDD12), F3(FSICOMC), F7(DU0_DG4), IRQ(12),
269 F1(LCDD13), F3(FSICOLR), F4(FSICILR), F7(DU0_DG5), IRQ(13),
270 F1(LCDD14), F3(FSICOBT), F4(FSICIBT), F7(DU0_DG6), IRQ(14),
271 F1(LCDD15), F3(FSICOSLD), F7(DU0_DG7), IRQ(15),
272 F1(LCDD16), F4(TPU1TO1), F7(DU0_DB0),
273 F1(LCDD17), F4(SF_IRQ_00), F7(DU0_DB1),
274 F1(LCDD18), F4(SF_IRQ_01), F7(DU0_DB2),
275 F1(LCDD19), F3(SCIFB3_RTS_19), F7(DU0_DB3),
276 F1(LCDD20), F3(SCIFB3_CTS_20), F7(DU0_DB4), /* Port20 */
277 F1(LCDD21), F3(SCIFB3_TXD_21), F7(DU0_DB5),
278 F1(LCDD22), F3(SCIFB3_RXD_22), F7(DU0_DB6),
279 F1(LCDD23), F3(SCIFB3_SCK_23), F7(DU0_DB7),
280 F1(LCDHSYN), F2(LCDCS), F3(SCIFB1_RTS_24),
281 F7(DU0_EXHSYNC_N_CSYNC_N_HSYNC_N),
282 F1(LCDVSYN), F3(SCIFB1_CTS_25), F7(DU0_EXVSYNC_N_VSYNC_N_CSYNC_N),
283 F1(LCDDCK), F2(LCDWR), F3(SCIFB1_TXD_26), F7(DU0_DOTCLKIN),
284 F1(LCDDISP), F2(LCDRS), F3(SCIFB1_RXD_27), F7(DU0_DOTCLKOUT),
285 F1(LCDRD_N), F3(SCIFB1_SCK_28), F7(DU0_DOTCLKOUTB),
286 F1(LCDLCLK), F4(SF_IRQ_02), F7(DU0_DISP_CSYNC_N_DE),
287 F1(LCDDON), F4(SF_IRQ_03), F7(DU0_ODDF_N_CLAMP), /* Port30 */
288
289 F1(SCIFA0_RTS), F5(SIM0_DET), F7(CSCIF0_RTS), /* Port32 */
290 F1(SCIFA0_CTS), F5(SIM1_DET), F7(CSCIF0_CTS),
291 F1(SCIFA0_SCK), F5(SIM0_PWRON), F7(CSCIF0_SCK),
292 F1(SCIFA1_RTS), F7(CSCIF1_RTS),
293 F1(SCIFA1_CTS), F7(CSCIF1_CTS),
294 F1(SCIFA1_SCK), F7(CSCIF1_SCK),
295 F1(SCIFB0_RTS), F3(TPU0TO1), F4(SCIFB3_RTS_38), F7(CHSCIF0_HRTS),
296 F1(SCIFB0_CTS), F3(TPU0TO2), F4(SCIFB3_CTS_39), F7(CHSCIF0_HCTS),
297 F1(SCIFB0_SCK), F3(TPU0TO3), F4(SCIFB3_SCK_40),
298 F7(CHSCIF0_HSCK), /* Port40 */
299
300 F1(PDM0_DATA), /* Port64 */
301 F1(PDM1_DATA),
302 F1(HSI_RX_WAKE), F2(SCIFB2_CTS_66), F3(MSIOF3_SYNC), F5(GenIO4),
303 IRQ(40),
304 F1(HSI_RX_READY), F2(SCIFB1_TXD_67), F5(GIO_OUT3_67), F7(CHSCIF1_HTX),
305 F1(HSI_RX_FLAG), F2(SCIFB2_TXD_68), F3(MSIOF3_TXD), F5(GIO_OUT4_68),
306 F1(HSI_RX_DATA), F2(SCIFB2_RXD_69), F3(MSIOF3_RXD), F5(GIO_OUT5_69),
307 F1(HSI_TX_FLAG), F2(SCIFB1_RTS_70), F5(GIO_OUT1_70), F6(HSIC_TSTCLK0),
308 F7(CHSCIF1_HRTS), /* Port70 */
309 F1(HSI_TX_DATA), F2(SCIFB1_CTS_71), F5(GIO_OUT2_71), F6(HSIC_TSTCLK1),
310 F7(CHSCIF1_HCTS),
311 F1(HSI_TX_WAKE), F2(SCIFB1_RXD_72), F5(GenIO8), F7(CHSCIF1_HRX),
312 F1(HSI_TX_READY), F2(SCIFB2_RTS_73), F3(MSIOF3_SCK), F5(GIO_OUT0_73),
313 F1(IRDA_OUT), F1(IRDA_IN), F1(IRDA_FIRSEL), F1(TPU0TO0),
314 F1(DIGRFEN), F1(GPS_TIMESTAMP), F1(TXP), /* Port80 */
315 F1(TXP2), F1(COEX_0), F1(COEX_1), IRQ(19), IRQ(18), /* Port85 */
316
317 F1(KEYIN0), /* Port96 */
318 F1(KEYIN1), F1(KEYIN2), F1(KEYIN3), F1(KEYIN4), /* Port100 */
319 F1(KEYIN5), F1(KEYIN6), IRQ(41), F1(KEYIN7), IRQ(42),
320 F2(KEYOUT0), F2(KEYOUT1), F2(KEYOUT2), F2(KEYOUT3),
321 F2(KEYOUT4), F2(KEYOUT5), IRQ(43), F2(KEYOUT6), IRQ(44), /* Port110 */
322 F2(KEYOUT7), F5(RFANAEN), IRQ(45),
323 F1(KEYIN8), F2(KEYOUT8), F4(SF_IRQ_04), IRQ(46),
324 F1(KEYIN9), F2(KEYOUT9), F4(SF_IRQ_05), IRQ(47),
325 F1(KEYIN10), F2(KEYOUT10), F4(SF_IRQ_06), IRQ(48),
326 F1(KEYIN11), F2(KEYOUT11), F4(SF_IRQ_07), IRQ(49),
327 F1(SCIFA0_TXD), F7(CSCIF0_TX), F1(SCIFA0_RXD), F7(CSCIF0_RX),
328 F1(SCIFA1_TXD), F7(CSCIF1_TX), F1(SCIFA1_RXD), F7(CSCIF1_RX),
329 F3(SF_PORT_1_120), F4(SCIFB3_RXD_120), F7(DU0_CDE), /* Port120 */
330 F3(SF_PORT_0_121), F4(SCIFB3_TXD_121),
331 F1(SCIFB0_TXD), F7(CHSCIF0_HTX),
332 F1(SCIFB0_RXD), F7(CHSCIF0_HRX), F3(ISP_STROBE_124),
333 F1(STP_ISD_0), F2(PDM4_CLK_125), F3(MSIOF2_TXD), F5(SIM0_VOLTSEL0),
334 F1(TS_SDEN), F2(MSIOF7_SYNC), F3(STP_ISEN_1),
335 F1(STP_ISEN_0), F2(PDM1_OUTDATA_128), F3(MSIOF2_SYNC),
336 F5(SIM1_VOLTSEL1), F1(TS_SPSYNC), F2(MSIOF7_RXD), F3(STP_ISSYNC_1),
337 F1(STP_ISSYNC_0), F2(PDM4_DATA_130), F3(MSIOF2_RXD),
338 F5(SIM0_VOLTSEL1), /* Port130 */
339 F1(STP_OPWM_0), F5(SIM1_PWRON), F1(TS_SCK), F2(MSIOF7_SCK),
340 F3(STP_ISCLK_1), F1(STP_ISCLK_0), F2(PDM1_OUTCLK_133), F3(MSIOF2_SCK),
341 F5(SIM1_VOLTSEL0), F1(TS_SDAT), F2(MSIOF7_TXD), F3(STP_ISD_1),
342 IRQ(20), /* Port160 */
343 IRQ(21), IRQ(22), IRQ(23),
344 F1(MMCD0_0), F1(MMCD0_1), F1(MMCD0_2), F1(MMCD0_3),
345 F1(MMCD0_4), F1(MMCD0_5), F1(MMCD0_6), /* Port170 */
346 F1(MMCD0_7), F1(MMCCMD0), F1(MMCCLK0), F1(MMCRST),
347 IRQ(24), IRQ(25), IRQ(26), IRQ(27),
348 F1(A10), F2(MMCD1_7), IRQ(31), /* Port192 */
349 F1(A9), F2(MMCD1_6), IRQ(32),
350 F1(A8), F2(MMCD1_5), IRQ(33),
351 F1(A7), F2(MMCD1_4), IRQ(34),
352 F1(A6), F2(MMCD1_3), IRQ(35),
353 F1(A5), F2(MMCD1_2), IRQ(36),
354 F1(A4), F2(MMCD1_1), IRQ(37),
355 F1(A3), F2(MMCD1_0), IRQ(38),
356 F1(A2), F2(MMCCMD1), IRQ(39), /* Port200 */
357 F1(A1),
358 F1(A0), F2(BS),
359 F1(CKO), F2(MMCCLK1),
360 F1(CS0_N), F5(SIM0_GPO1),
361 F1(CS2_N), F5(SIM0_GPO2),
362 F1(CS4_N), F2(VIO_VD), F5(SIM1_GPO0),
363 F1(D15), F5(GIO_OUT15),
364 F1(D14), F5(GIO_OUT14),
365 F1(D13), F5(GIO_OUT13),
366 F1(D12), F5(GIO_OUT12), /* Port210 */
367 F1(D11), F5(WGM_TXP2),
368 F1(D10), F5(WGM_GPS_TIMEM_ASK_RFCLK),
369 F1(D9), F2(VIO_D9), F5(GIO_OUT9),
370 F1(D8), F2(VIO_D8), F5(GIO_OUT8),
371 F1(D7), F2(VIO_D7), F5(GIO_OUT7),
372 F1(D6), F2(VIO_D6), F5(GIO_OUT6),
373 F1(D5), F2(VIO_D5), F5(GIO_OUT5_217),
374 F1(D4), F2(VIO_D4), F5(GIO_OUT4_218),
375 F1(D3), F2(VIO_D3), F5(GIO_OUT3_219),
376 F1(D2), F2(VIO_D2), F5(GIO_OUT2_220), /* Port220 */
377 F1(D1), F2(VIO_D1), F5(GIO_OUT1_221),
378 F1(D0), F2(VIO_D0), F5(GIO_OUT0_222),
379 F1(RDWR_224), F2(VIO_HD), F5(SIM1_GPO2),
380 F1(RD_N), F1(WAIT_N), F2(VIO_CLK), F5(SIM1_GPO1),
381 F1(WE0_N), F2(RDWR_227),
382 F1(WE1_N), F5(SIM0_GPO0),
383 F1(PWMO), F2(VIO_CKO1_229),
384 F1(SLIM_CLK), F2(VIO_CKO4_230), /* Port230 */
385 F1(SLIM_DATA), F2(VIO_CKO5_231), F2(VIO_CKO2_232), F4(SF_PORT_0_232),
386 F2(VIO_CKO3_233), F4(SF_PORT_1_233),
387 F1(FSIACK), F2(PDM3_CLK_234), F3(ISP_IRIS1_234),
388 F1(FSIAISLD), F2(PDM3_DATA_235),
389 F1(FSIAOMC), F2(PDM0_OUTCLK_236), F3(ISP_IRIS0_236),
390 F1(FSIAOLR), F2(FSIAILR), F1(FSIAOBT), F2(FSIAIBT),
391 F1(FSIAOSLD), F2(PDM0_OUTDATA_239),
392 F1(FSIBISLD), /* Port240 */
393 F1(FSIBOLR), F2(FSIBILR), F1(FSIBOMC), F3(ISP_SHUTTER1_242),
394 F1(FSIBOBT), F2(FSIBIBT), F1(FSIBOSLD), F2(FSIASPDIF),
395 F1(FSIBCK), F3(ISP_SHUTTER0_245),
396 F1(ISP_IRIS1_246), F1(ISP_IRIS0_247), F1(ISP_SHUTTER1_248),
397 F1(ISP_SHUTTER0_249), F1(ISP_STROBE_250), /* Port250 */
398 F1(MSIOF0_SYNC), F1(MSIOF0_RXD), F1(MSIOF0_SCK), F1(MSIOF0_SS2),
399 F3(VIO_CKO3_259), F1(MSIOF0_TXD), /* Port260 */
400 F2(SCIFB1_SCK_261), F7(CHSCIF1_HSCK), F2(SCIFB2_SCK_262),
401 F1(MSIOF1_SS2), F4(MSIOF5_SS2), F1(MSIOF1_TXD), F4(MSIOF5_TXD),
402 F1(MSIOF1_RXD), F4(MSIOF5_RXD), F1(MSIOF1_SS1), F4(MSIOF5_SS1),
403 F1(MSIOF0_SS1), F1(MSIOF1_SCK), F4(MSIOF5_SCK),
404 F1(MSIOF1_SYNC), F4(MSIOF5_SYNC),
405 F1(MSIOF2_SS1), F3(VIO_CKO5_270), /* Port270 */
406 F1(MSIOF2_SS2), F3(VIO_CKO2_271), F1(MSIOF3_SS2), F3(VIO_CKO1_272),
407 F1(MSIOF3_SS1), F3(VIO_CKO4_273), F1(MSIOF4_SS2), F4(TPU1TO0),
408 F1(IC_DP), F1(SIM0_RST), F1(IC_DM), F1(SIM0_BSICOMP),
409 F1(SIM0_CLK), F1(SIM0_IO), /* Port280 */
410 F1(SIM1_IO), F2(PDM2_DATA_281), F1(SIM1_CLK), F2(PDM2_CLK_282),
411 F1(SIM1_RST), F1(SDHID1_0), F3(STMDATA0_2),
412 F1(SDHID1_1), F3(STMDATA1_2), IRQ(51), /* Port290 */
413 F1(SDHID1_2), F3(STMDATA2_2), F1(SDHID1_3), F3(STMDATA3_2),
414 F1(SDHICLK1), F3(STMCLK_2), F1(SDHICMD1), F3(STMSIDI_2),
415 F1(SDHID2_0), F2(MSIOF4_TXD), F3(SCIFB2_TXD_295), F4(MSIOF6_TXD),
416 F1(SDHID2_1), F4(MSIOF6_SS2), IRQ(52),
417 F1(SDHID2_2), F2(MSIOF4_RXD), F3(SCIFB2_RXD_297), F4(MSIOF6_RXD),
418 F1(SDHID2_3), F2(MSIOF4_SYNC), F3(SCIFB2_CTS_298), F4(MSIOF6_SYNC),
419 F1(SDHICLK2), F2(MSIOF4_SCK), F3(SCIFB2_SCK_299), F4(MSIOF6_SCK),
420 F1(SDHICMD2), F2(MSIOF4_SS1), F3(SCIFB2_RTS_300),
421 F4(MSIOF6_SS1), /* Port300 */
422 F1(SDHICD0), IRQ(50), F1(SDHID0_0), F3(STMDATA0_1),
423 F1(SDHID0_1), F3(STMDATA1_1), F1(SDHID0_2), F3(STMDATA2_1),
424 F1(SDHID0_3), F3(STMDATA3_1), F1(SDHICMD0), F3(STMSIDI_1),
425 F1(SDHIWP0), F1(SDHICLK0), F3(STMCLK_1), IRQ(16), /* Port320 */
426 IRQ(17), IRQ(28), IRQ(29), IRQ(30), IRQ(53), IRQ(54),
427 IRQ(55), IRQ(56), IRQ(57),
428 PINMUX_MARK_END,
429 };
430
431 #define _PORT_DATA(pfx, sfx) PORT_DATA_IO(pfx)
432 #define PINMUX_DATA_ALL() CPU_ALL_PORT(_PORT_DATA, , unused)
433
434 static const pinmux_enum_t pinmux_data[] = {
435 /* specify valid pin states for each pin in GPIO mode */
436 PINMUX_DATA_ALL(),
437
438 /* Port0 */
439 PINMUX_DATA(LCDD0_MARK, PORT0_FN1),
440 PINMUX_DATA(PDM2_CLK_0_MARK, PORT0_FN3),
441 PINMUX_DATA(DU0_DR0_MARK, PORT0_FN7),
442 PINMUX_DATA(IRQ0_MARK, PORT0_FN0),
443
444 /* Port1 */
445 PINMUX_DATA(LCDD1_MARK, PORT1_FN1),
446 PINMUX_DATA(PDM2_DATA_1_MARK, PORT1_FN3, MSEL3CR_12_0),
447 PINMUX_DATA(DU0_DR19_MARK, PORT1_FN7),
448 PINMUX_DATA(IRQ1_MARK, PORT1_FN0),
449
450 /* Port2 */
451 PINMUX_DATA(LCDD2_MARK, PORT2_FN1),
452 PINMUX_DATA(PDM3_CLK_2_MARK, PORT2_FN3),
453 PINMUX_DATA(DU0_DR2_MARK, PORT2_FN7),
454 PINMUX_DATA(IRQ2_MARK, PORT2_FN0),
455
456 /* Port3 */
457 PINMUX_DATA(LCDD3_MARK, PORT3_FN1),
458 PINMUX_DATA(PDM3_DATA_3_MARK, PORT3_FN3, MSEL3CR_12_0),
459 PINMUX_DATA(DU0_DR3_MARK, PORT3_FN7),
460 PINMUX_DATA(IRQ3_MARK, PORT3_FN0),
461
462 /* Port4 */
463 PINMUX_DATA(LCDD4_MARK, PORT4_FN1),
464 PINMUX_DATA(PDM4_CLK_4_MARK, PORT4_FN3),
465 PINMUX_DATA(DU0_DR4_MARK, PORT4_FN7),
466 PINMUX_DATA(IRQ4_MARK, PORT4_FN0),
467
468 /* Port5 */
469 PINMUX_DATA(LCDD5_MARK, PORT5_FN1),
470 PINMUX_DATA(PDM4_DATA_5_MARK, PORT5_FN3, MSEL3CR_12_0),
471 PINMUX_DATA(DU0_DR5_MARK, PORT5_FN7),
472 PINMUX_DATA(IRQ5_MARK, PORT5_FN0),
473
474 /* Port6 */
475 PINMUX_DATA(LCDD6_MARK, PORT6_FN1),
476 PINMUX_DATA(PDM0_OUTCLK_6_MARK, PORT6_FN3),
477 PINMUX_DATA(DU0_DR6_MARK, PORT6_FN7),
478 PINMUX_DATA(IRQ6_MARK, PORT6_FN0),
479
480 /* Port7 */
481 PINMUX_DATA(LCDD7_MARK, PORT7_FN1),
482 PINMUX_DATA(PDM0_OUTDATA_7_MARK, PORT7_FN3),
483 PINMUX_DATA(DU0_DR7_MARK, PORT7_FN7),
484 PINMUX_DATA(IRQ7_MARK, PORT7_FN0),
485
486 /* Port8 */
487 PINMUX_DATA(LCDD8_MARK, PORT8_FN1),
488 PINMUX_DATA(PDM1_OUTCLK_8_MARK, PORT8_FN3),
489 PINMUX_DATA(DU0_DG0_MARK, PORT8_FN7),
490 PINMUX_DATA(IRQ8_MARK, PORT8_FN0),
491
492 /* Port9 */
493 PINMUX_DATA(LCDD9_MARK, PORT9_FN1),
494 PINMUX_DATA(PDM1_OUTDATA_9_MARK, PORT9_FN3),
495 PINMUX_DATA(DU0_DG1_MARK, PORT9_FN7),
496 PINMUX_DATA(IRQ9_MARK, PORT9_FN0),
497
498 /* Port10 */
499 PINMUX_DATA(LCDD10_MARK, PORT10_FN1),
500 PINMUX_DATA(FSICCK_MARK, PORT10_FN3),
501 PINMUX_DATA(DU0_DG2_MARK, PORT10_FN7),
502 PINMUX_DATA(IRQ10_MARK, PORT10_FN0),
503
504 /* Port11 */
505 PINMUX_DATA(LCDD11_MARK, PORT11_FN1),
506 PINMUX_DATA(FSICISLD_MARK, PORT11_FN3),
507 PINMUX_DATA(DU0_DG3_MARK, PORT11_FN7),
508 PINMUX_DATA(IRQ11_MARK, PORT11_FN0),
509
510 /* Port12 */
511 PINMUX_DATA(LCDD12_MARK, PORT12_FN1),
512 PINMUX_DATA(FSICOMC_MARK, PORT12_FN3),
513 PINMUX_DATA(DU0_DG4_MARK, PORT12_FN7),
514 PINMUX_DATA(IRQ12_MARK, PORT12_FN0),
515
516 /* Port13 */
517 PINMUX_DATA(LCDD13_MARK, PORT13_FN1),
518 PINMUX_DATA(FSICOLR_MARK, PORT13_FN3),
519 PINMUX_DATA(FSICILR_MARK, PORT13_FN4),
520 PINMUX_DATA(DU0_DG5_MARK, PORT13_FN7),
521 PINMUX_DATA(IRQ13_MARK, PORT13_FN0),
522
523 /* Port14 */
524 PINMUX_DATA(LCDD14_MARK, PORT14_FN1),
525 PINMUX_DATA(FSICOBT_MARK, PORT14_FN3),
526 PINMUX_DATA(FSICIBT_MARK, PORT14_FN4),
527 PINMUX_DATA(DU0_DG6_MARK, PORT14_FN7),
528 PINMUX_DATA(IRQ14_MARK, PORT14_FN0),
529
530 /* Port15 */
531 PINMUX_DATA(LCDD15_MARK, PORT15_FN1),
532 PINMUX_DATA(FSICOSLD_MARK, PORT15_FN3),
533 PINMUX_DATA(DU0_DG7_MARK, PORT15_FN7),
534 PINMUX_DATA(IRQ15_MARK, PORT15_FN0),
535
536 /* Port16 */
537 PINMUX_DATA(LCDD16_MARK, PORT16_FN1),
538 PINMUX_DATA(TPU1TO1_MARK, PORT16_FN4),
539 PINMUX_DATA(DU0_DB0_MARK, PORT16_FN7),
540
541 /* Port17 */
542 PINMUX_DATA(LCDD17_MARK, PORT17_FN1),
543 PINMUX_DATA(SF_IRQ_00_MARK, PORT17_FN4),
544 PINMUX_DATA(DU0_DB1_MARK, PORT17_FN7),
545
546 /* Port18 */
547 PINMUX_DATA(LCDD18_MARK, PORT18_FN1),
548 PINMUX_DATA(SF_IRQ_01_MARK, PORT18_FN4),
549 PINMUX_DATA(DU0_DB2_MARK, PORT18_FN7),
550
551 /* Port19 */
552 PINMUX_DATA(LCDD19_MARK, PORT19_FN1),
553 PINMUX_DATA(SCIFB3_RTS_19_MARK, PORT19_FN3),
554 PINMUX_DATA(DU0_DB3_MARK, PORT19_FN7),
555
556 /* Port20 */
557 PINMUX_DATA(LCDD20_MARK, PORT20_FN1),
558 PINMUX_DATA(SCIFB3_CTS_20_MARK, PORT20_FN3, MSEL3CR_09_0),
559 PINMUX_DATA(DU0_DB4_MARK, PORT20_FN7),
560
561 /* Port21 */
562 PINMUX_DATA(LCDD21_MARK, PORT21_FN1),
563 PINMUX_DATA(SCIFB3_TXD_21_MARK, PORT21_FN3, MSEL3CR_09_0),
564 PINMUX_DATA(DU0_DB5_MARK, PORT21_FN7),
565
566 /* Port22 */
567 PINMUX_DATA(LCDD22_MARK, PORT22_FN1),
568 PINMUX_DATA(SCIFB3_RXD_22_MARK, PORT22_FN3, MSEL3CR_09_0),
569 PINMUX_DATA(DU0_DB6_MARK, PORT22_FN7),
570
571 /* Port23 */
572 PINMUX_DATA(LCDD23_MARK, PORT23_FN1),
573 PINMUX_DATA(SCIFB3_SCK_23_MARK, PORT23_FN3),
574 PINMUX_DATA(DU0_DB7_MARK, PORT23_FN7),
575
576 /* Port24 */
577 PINMUX_DATA(LCDHSYN_MARK, PORT24_FN1),
578 PINMUX_DATA(LCDCS_MARK, PORT24_FN2),
579 PINMUX_DATA(SCIFB1_RTS_24_MARK, PORT24_FN3),
580 PINMUX_DATA(DU0_EXHSYNC_N_CSYNC_N_HSYNC_N_MARK, PORT24_FN7),
581
582 /* Port25 */
583 PINMUX_DATA(LCDVSYN_MARK, PORT25_FN1),
584 PINMUX_DATA(SCIFB1_CTS_25_MARK, PORT25_FN3, MSEL3CR_11_0),
585 PINMUX_DATA(DU0_EXVSYNC_N_VSYNC_N_CSYNC_N_MARK, PORT25_FN7),
586
587 /* Port26 */
588 PINMUX_DATA(LCDDCK_MARK, PORT26_FN1),
589 PINMUX_DATA(LCDWR_MARK, PORT26_FN2),
590 PINMUX_DATA(SCIFB1_TXD_26_MARK, PORT26_FN3, MSEL3CR_11_0),
591 PINMUX_DATA(DU0_DOTCLKIN_MARK, PORT26_FN7),
592
593 /* Port27 */
594 PINMUX_DATA(LCDDISP_MARK, PORT27_FN1),
595 PINMUX_DATA(LCDRS_MARK, PORT27_FN2),
596 PINMUX_DATA(SCIFB1_RXD_27_MARK, PORT27_FN3, MSEL3CR_11_0),
597 PINMUX_DATA(DU0_DOTCLKOUT_MARK, PORT27_FN7),
598
599 /* Port28 */
600 PINMUX_DATA(LCDRD_N_MARK, PORT28_FN1),
601 PINMUX_DATA(SCIFB1_SCK_28_MARK, PORT28_FN3),
602 PINMUX_DATA(DU0_DOTCLKOUTB_MARK, PORT28_FN7),
603
604 /* Port29 */
605 PINMUX_DATA(LCDLCLK_MARK, PORT29_FN1),
606 PINMUX_DATA(SF_IRQ_02_MARK, PORT29_FN4),
607 PINMUX_DATA(DU0_DISP_CSYNC_N_DE_MARK, PORT29_FN7),
608
609 /* Port30 */
610 PINMUX_DATA(LCDDON_MARK, PORT30_FN1),
611 PINMUX_DATA(SF_IRQ_03_MARK, PORT30_FN4),
612 PINMUX_DATA(DU0_ODDF_N_CLAMP_MARK, PORT30_FN7),
613
614 /* Port32 */
615 PINMUX_DATA(SCIFA0_RTS_MARK, PORT32_FN1),
616 PINMUX_DATA(SIM0_DET_MARK, PORT32_FN5),
617 PINMUX_DATA(CSCIF0_RTS_MARK, PORT32_FN7),
618
619 /* Port33 */
620 PINMUX_DATA(SCIFA0_CTS_MARK, PORT33_FN1),
621 PINMUX_DATA(SIM1_DET_MARK, PORT33_FN5),
622 PINMUX_DATA(CSCIF0_CTS_MARK, PORT33_FN7),
623
624 /* Port34 */
625 PINMUX_DATA(SCIFA0_SCK_MARK, PORT34_FN1),
626 PINMUX_DATA(SIM0_PWRON_MARK, PORT34_FN5),
627 PINMUX_DATA(CSCIF0_SCK_MARK, PORT34_FN7),
628
629 /* Port35 */
630 PINMUX_DATA(SCIFA1_RTS_MARK, PORT35_FN1),
631 PINMUX_DATA(CSCIF1_RTS_MARK, PORT35_FN7),
632
633 /* Port36 */
634 PINMUX_DATA(SCIFA1_CTS_MARK, PORT36_FN1),
635 PINMUX_DATA(CSCIF1_CTS_MARK, PORT36_FN7),
636
637 /* Port37 */
638 PINMUX_DATA(SCIFA1_SCK_MARK, PORT37_FN1),
639 PINMUX_DATA(CSCIF1_SCK_MARK, PORT37_FN7),
640
641 /* Port38 */
642 PINMUX_DATA(SCIFB0_RTS_MARK, PORT38_FN1),
643 PINMUX_DATA(TPU0TO1_MARK, PORT38_FN3),
644 PINMUX_DATA(SCIFB3_RTS_38_MARK, PORT38_FN4),
645 PINMUX_DATA(CHSCIF0_HRTS_MARK, PORT38_FN7),
646
647 /* Port39 */
648 PINMUX_DATA(SCIFB0_CTS_MARK, PORT39_FN1),
649 PINMUX_DATA(TPU0TO2_MARK, PORT39_FN3),
650 PINMUX_DATA(SCIFB3_CTS_39_MARK, PORT39_FN4, MSEL3CR_09_1),
651 PINMUX_DATA(CHSCIF0_HCTS_MARK, PORT39_FN7),
652
653 /* Port40 */
654 PINMUX_DATA(SCIFB0_SCK_MARK, PORT40_FN1),
655 PINMUX_DATA(TPU0TO3_MARK, PORT40_FN3),
656 PINMUX_DATA(SCIFB3_SCK_40_MARK, PORT40_FN4),
657 PINMUX_DATA(CHSCIF0_HSCK_MARK, PORT40_FN7),
658
659 /* Port64 */
660 PINMUX_DATA(PDM0_DATA_MARK, PORT64_FN1),
661
662 /* Port65 */
663 PINMUX_DATA(PDM1_DATA_MARK, PORT65_FN1),
664
665 /* Port66 */
666 PINMUX_DATA(HSI_RX_WAKE_MARK, PORT66_FN1),
667 PINMUX_DATA(SCIFB2_CTS_66_MARK, PORT66_FN2, MSEL3CR_10_0),
668 PINMUX_DATA(MSIOF3_SYNC_MARK, PORT66_FN3),
669 PINMUX_DATA(GenIO4_MARK, PORT66_FN5),
670 PINMUX_DATA(IRQ40_MARK, PORT66_FN0),
671
672 /* Port67 */
673 PINMUX_DATA(HSI_RX_READY_MARK, PORT67_FN1),
674 PINMUX_DATA(SCIFB1_TXD_67_MARK, PORT67_FN2, MSEL3CR_11_1),
675 PINMUX_DATA(GIO_OUT3_67_MARK, PORT67_FN5),
676 PINMUX_DATA(CHSCIF1_HTX_MARK, PORT67_FN7),
677
678 /* Port68 */
679 PINMUX_DATA(HSI_RX_FLAG_MARK, PORT68_FN1),
680 PINMUX_DATA(SCIFB2_TXD_68_MARK, PORT68_FN2, MSEL3CR_10_0),
681 PINMUX_DATA(MSIOF3_TXD_MARK, PORT68_FN3),
682 PINMUX_DATA(GIO_OUT4_68_MARK, PORT68_FN5),
683
684 /* Port69 */
685 PINMUX_DATA(HSI_RX_DATA_MARK, PORT69_FN1),
686 PINMUX_DATA(SCIFB2_RXD_69_MARK, PORT69_FN2, MSEL3CR_10_0),
687 PINMUX_DATA(MSIOF3_RXD_MARK, PORT69_FN3),
688 PINMUX_DATA(GIO_OUT5_69_MARK, PORT69_FN5),
689
690 /* Port70 */
691 PINMUX_DATA(HSI_TX_FLAG_MARK, PORT70_FN1),
692 PINMUX_DATA(SCIFB1_RTS_70_MARK, PORT70_FN2),
693 PINMUX_DATA(GIO_OUT1_70_MARK, PORT70_FN5),
694 PINMUX_DATA(HSIC_TSTCLK0_MARK, PORT70_FN6),
695 PINMUX_DATA(CHSCIF1_HRTS_MARK, PORT70_FN7),
696
697 /* Port71 */
698 PINMUX_DATA(HSI_TX_DATA_MARK, PORT71_FN1),
699 PINMUX_DATA(SCIFB1_CTS_71_MARK, PORT71_FN2, MSEL3CR_11_1),
700 PINMUX_DATA(GIO_OUT2_71_MARK, PORT71_FN5),
701 PINMUX_DATA(HSIC_TSTCLK1_MARK, PORT71_FN6),
702 PINMUX_DATA(CHSCIF1_HCTS_MARK, PORT71_FN7),
703
704 /* Port72 */
705 PINMUX_DATA(HSI_TX_WAKE_MARK, PORT72_FN1),
706 PINMUX_DATA(SCIFB1_RXD_72_MARK, PORT72_FN2, MSEL3CR_11_1),
707 PINMUX_DATA(GenIO8_MARK, PORT72_FN5),
708 PINMUX_DATA(CHSCIF1_HRX_MARK, PORT72_FN7),
709
710 /* Port73 */
711 PINMUX_DATA(HSI_TX_READY_MARK, PORT73_FN1),
712 PINMUX_DATA(SCIFB2_RTS_73_MARK, PORT73_FN2),
713 PINMUX_DATA(MSIOF3_SCK_MARK, PORT73_FN3),
714 PINMUX_DATA(GIO_OUT0_73_MARK, PORT73_FN5),
715
716 /* Port74 - Port85 */
717 PINMUX_DATA(IRDA_OUT_MARK, PORT74_FN1),
718 PINMUX_DATA(IRDA_IN_MARK, PORT75_FN1),
719 PINMUX_DATA(IRDA_FIRSEL_MARK, PORT76_FN1),
720 PINMUX_DATA(TPU0TO0_MARK, PORT77_FN1),
721 PINMUX_DATA(DIGRFEN_MARK, PORT78_FN1),
722 PINMUX_DATA(GPS_TIMESTAMP_MARK, PORT79_FN1),
723 PINMUX_DATA(TXP_MARK, PORT80_FN1),
724 PINMUX_DATA(TXP2_MARK, PORT81_FN1),
725 PINMUX_DATA(COEX_0_MARK, PORT82_FN1),
726 PINMUX_DATA(COEX_1_MARK, PORT83_FN1),
727 PINMUX_DATA(IRQ19_MARK, PORT84_FN0),
728 PINMUX_DATA(IRQ18_MARK, PORT85_FN0),
729
730 /* Port96 - Port101 */
731 PINMUX_DATA(KEYIN0_MARK, PORT96_FN1),
732 PINMUX_DATA(KEYIN1_MARK, PORT97_FN1),
733 PINMUX_DATA(KEYIN2_MARK, PORT98_FN1),
734 PINMUX_DATA(KEYIN3_MARK, PORT99_FN1),
735 PINMUX_DATA(KEYIN4_MARK, PORT100_FN1),
736 PINMUX_DATA(KEYIN5_MARK, PORT101_FN1),
737
738 /* Port102 */
739 PINMUX_DATA(KEYIN6_MARK, PORT102_FN1),
740 PINMUX_DATA(IRQ41_MARK, PORT102_FN0),
741
742 /* Port103 */
743 PINMUX_DATA(KEYIN7_MARK, PORT103_FN1),
744 PINMUX_DATA(IRQ42_MARK, PORT103_FN0),
745
746 /* Port104 - Port108 */
747 PINMUX_DATA(KEYOUT0_MARK, PORT104_FN2),
748 PINMUX_DATA(KEYOUT1_MARK, PORT105_FN2),
749 PINMUX_DATA(KEYOUT2_MARK, PORT106_FN2),
750 PINMUX_DATA(KEYOUT3_MARK, PORT107_FN2),
751 PINMUX_DATA(KEYOUT4_MARK, PORT108_FN2),
752
753 /* Port109 */
754 PINMUX_DATA(KEYOUT5_MARK, PORT109_FN2),
755 PINMUX_DATA(IRQ43_MARK, PORT109_FN0),
756
757 /* Port110 */
758 PINMUX_DATA(KEYOUT6_MARK, PORT110_FN2),
759 PINMUX_DATA(IRQ44_MARK, PORT110_FN0),
760
761 /* Port111 */
762 PINMUX_DATA(KEYOUT7_MARK, PORT111_FN2),
763 PINMUX_DATA(RFANAEN_MARK, PORT111_FN5),
764 PINMUX_DATA(IRQ45_MARK, PORT111_FN0),
765
766 /* Port112 */
767 PINMUX_DATA(KEYIN8_MARK, PORT112_FN1),
768 PINMUX_DATA(KEYOUT8_MARK, PORT112_FN2),
769 PINMUX_DATA(SF_IRQ_04_MARK, PORT112_FN4),
770 PINMUX_DATA(IRQ46_MARK, PORT112_FN0),
771
772 /* Port113 */
773 PINMUX_DATA(KEYIN9_MARK, PORT113_FN1),
774 PINMUX_DATA(KEYOUT9_MARK, PORT113_FN2),
775 PINMUX_DATA(SF_IRQ_05_MARK, PORT113_FN4),
776 PINMUX_DATA(IRQ47_MARK, PORT113_FN0),
777
778 /* Port114 */
779 PINMUX_DATA(KEYIN10_MARK, PORT114_FN1),
780 PINMUX_DATA(KEYOUT10_MARK, PORT114_FN2),
781 PINMUX_DATA(SF_IRQ_06_MARK, PORT114_FN4),
782 PINMUX_DATA(IRQ48_MARK, PORT114_FN0),
783
784 /* Port115 */
785 PINMUX_DATA(KEYIN11_MARK, PORT115_FN1),
786 PINMUX_DATA(KEYOUT11_MARK, PORT115_FN2),
787 PINMUX_DATA(SF_IRQ_07_MARK, PORT115_FN4),
788 PINMUX_DATA(IRQ49_MARK, PORT115_FN0),
789
790 /* Port116 */
791 PINMUX_DATA(SCIFA0_TXD_MARK, PORT116_FN1),
792 PINMUX_DATA(CSCIF0_TX_MARK, PORT116_FN7),
793
794 /* Port117 */
795 PINMUX_DATA(SCIFA0_RXD_MARK, PORT117_FN1),
796 PINMUX_DATA(CSCIF0_RX_MARK, PORT117_FN7),
797
798 /* Port118 */
799 PINMUX_DATA(SCIFA1_TXD_MARK, PORT118_FN1),
800 PINMUX_DATA(CSCIF1_TX_MARK, PORT118_FN7),
801
802 /* Port119 */
803 PINMUX_DATA(SCIFA1_RXD_MARK, PORT119_FN1),
804 PINMUX_DATA(CSCIF1_RX_MARK, PORT119_FN7),
805
806 /* Port120 */
807 PINMUX_DATA(SF_PORT_1_120_MARK, PORT120_FN3),
808 PINMUX_DATA(SCIFB3_RXD_120_MARK, PORT120_FN4, MSEL3CR_09_1),
809 PINMUX_DATA(DU0_CDE_MARK, PORT120_FN7),
810
811 /* Port121 */
812 PINMUX_DATA(SF_PORT_0_121_MARK, PORT121_FN3),
813 PINMUX_DATA(SCIFB3_TXD_121_MARK, PORT121_FN4, MSEL3CR_09_1),
814
815 /* Port122 */
816 PINMUX_DATA(SCIFB0_TXD_MARK, PORT122_FN1),
817 PINMUX_DATA(CHSCIF0_HTX_MARK, PORT122_FN7),
818
819 /* Port123 */
820 PINMUX_DATA(SCIFB0_RXD_MARK, PORT123_FN1),
821 PINMUX_DATA(CHSCIF0_HRX_MARK, PORT123_FN7),
822
823 /* Port124 */
824 PINMUX_DATA(ISP_STROBE_124_MARK, PORT124_FN3),
825
826 /* Port125 */
827 PINMUX_DATA(STP_ISD_0_MARK, PORT125_FN1),
828 PINMUX_DATA(PDM4_CLK_125_MARK, PORT125_FN2),
829 PINMUX_DATA(MSIOF2_TXD_MARK, PORT125_FN3),
830 PINMUX_DATA(SIM0_VOLTSEL0_MARK, PORT125_FN5),
831
832 /* Port126 */
833 PINMUX_DATA(TS_SDEN_MARK, PORT126_FN1),
834 PINMUX_DATA(MSIOF7_SYNC_MARK, PORT126_FN2),
835 PINMUX_DATA(STP_ISEN_1_MARK, PORT126_FN3),
836
837 /* Port128 */
838 PINMUX_DATA(STP_ISEN_0_MARK, PORT128_FN1),
839 PINMUX_DATA(PDM1_OUTDATA_128_MARK, PORT128_FN2),
840 PINMUX_DATA(MSIOF2_SYNC_MARK, PORT128_FN3),
841 PINMUX_DATA(SIM1_VOLTSEL1_MARK, PORT128_FN5),
842
843 /* Port129 */
844 PINMUX_DATA(TS_SPSYNC_MARK, PORT129_FN1),
845 PINMUX_DATA(MSIOF7_RXD_MARK, PORT129_FN2),
846 PINMUX_DATA(STP_ISSYNC_1_MARK, PORT129_FN3),
847
848 /* Port130 */
849 PINMUX_DATA(STP_ISSYNC_0_MARK, PORT130_FN1),
850 PINMUX_DATA(PDM4_DATA_130_MARK, PORT130_FN2, MSEL3CR_12_1),
851 PINMUX_DATA(MSIOF2_RXD_MARK, PORT130_FN3),
852 PINMUX_DATA(SIM0_VOLTSEL1_MARK, PORT130_FN5),
853
854 /* Port131 */
855 PINMUX_DATA(STP_OPWM_0_MARK, PORT131_FN1),
856 PINMUX_DATA(SIM1_PWRON_MARK, PORT131_FN5),
857
858 /* Port132 */
859 PINMUX_DATA(TS_SCK_MARK, PORT132_FN1),
860 PINMUX_DATA(MSIOF7_SCK_MARK, PORT132_FN2),
861 PINMUX_DATA(STP_ISCLK_1_MARK, PORT132_FN3),
862
863 /* Port133 */
864 PINMUX_DATA(STP_ISCLK_0_MARK, PORT133_FN1),
865 PINMUX_DATA(PDM1_OUTCLK_133_MARK, PORT133_FN2),
866 PINMUX_DATA(MSIOF2_SCK_MARK, PORT133_FN3),
867 PINMUX_DATA(SIM1_VOLTSEL0_MARK, PORT133_FN5),
868
869 /* Port134 */
870 PINMUX_DATA(TS_SDAT_MARK, PORT134_FN1),
871 PINMUX_DATA(MSIOF7_TXD_MARK, PORT134_FN2),
872 PINMUX_DATA(STP_ISD_1_MARK, PORT134_FN3),
873
874 /* Port160 - Port178 */
875 PINMUX_DATA(IRQ20_MARK, PORT160_FN0),
876 PINMUX_DATA(IRQ21_MARK, PORT161_FN0),
877 PINMUX_DATA(IRQ22_MARK, PORT162_FN0),
878 PINMUX_DATA(IRQ23_MARK, PORT163_FN0),
879 PINMUX_DATA(MMCD0_0_MARK, PORT164_FN1),
880 PINMUX_DATA(MMCD0_1_MARK, PORT165_FN1),
881 PINMUX_DATA(MMCD0_2_MARK, PORT166_FN1),
882 PINMUX_DATA(MMCD0_3_MARK, PORT167_FN1),
883 PINMUX_DATA(MMCD0_4_MARK, PORT168_FN1),
884 PINMUX_DATA(MMCD0_5_MARK, PORT169_FN1),
885 PINMUX_DATA(MMCD0_6_MARK, PORT170_FN1),
886 PINMUX_DATA(MMCD0_7_MARK, PORT171_FN1),
887 PINMUX_DATA(MMCCMD0_MARK, PORT172_FN1),
888 PINMUX_DATA(MMCCLK0_MARK, PORT173_FN1),
889 PINMUX_DATA(MMCRST_MARK, PORT174_FN1),
890 PINMUX_DATA(IRQ24_MARK, PORT175_FN0),
891 PINMUX_DATA(IRQ25_MARK, PORT176_FN0),
892 PINMUX_DATA(IRQ26_MARK, PORT177_FN0),
893 PINMUX_DATA(IRQ27_MARK, PORT178_FN0),
894
895 /* Port192 - Port200 FN1 */
896 PINMUX_DATA(A10_MARK, PORT192_FN1),
897 PINMUX_DATA(A9_MARK, PORT193_FN1),
898 PINMUX_DATA(A8_MARK, PORT194_FN1),
899 PINMUX_DATA(A7_MARK, PORT195_FN1),
900 PINMUX_DATA(A6_MARK, PORT196_FN1),
901 PINMUX_DATA(A5_MARK, PORT197_FN1),
902 PINMUX_DATA(A4_MARK, PORT198_FN1),
903 PINMUX_DATA(A3_MARK, PORT199_FN1),
904 PINMUX_DATA(A2_MARK, PORT200_FN1),
905
906 /* Port192 - Port200 FN2 */
907 PINMUX_DATA(MMCD1_7_MARK, PORT192_FN2),
908 PINMUX_DATA(MMCD1_6_MARK, PORT193_FN2),
909 PINMUX_DATA(MMCD1_5_MARK, PORT194_FN2),
910 PINMUX_DATA(MMCD1_4_MARK, PORT195_FN2),
911 PINMUX_DATA(MMCD1_3_MARK, PORT196_FN2),
912 PINMUX_DATA(MMCD1_2_MARK, PORT197_FN2),
913 PINMUX_DATA(MMCD1_1_MARK, PORT198_FN2),
914 PINMUX_DATA(MMCD1_0_MARK, PORT199_FN2),
915 PINMUX_DATA(MMCCMD1_MARK, PORT200_FN2),
916
917 /* Port192 - Port200 IRQ */
918 PINMUX_DATA(IRQ31_MARK, PORT192_FN0),
919 PINMUX_DATA(IRQ32_MARK, PORT193_FN0),
920 PINMUX_DATA(IRQ33_MARK, PORT194_FN0),
921 PINMUX_DATA(IRQ34_MARK, PORT195_FN0),
922 PINMUX_DATA(IRQ35_MARK, PORT196_FN0),
923 PINMUX_DATA(IRQ36_MARK, PORT197_FN0),
924 PINMUX_DATA(IRQ37_MARK, PORT198_FN0),
925 PINMUX_DATA(IRQ38_MARK, PORT199_FN0),
926 PINMUX_DATA(IRQ39_MARK, PORT200_FN0),
927
928 /* Port201 */
929 PINMUX_DATA(A1_MARK, PORT201_FN1),
930
931 /* Port202 */
932 PINMUX_DATA(A0_MARK, PORT202_FN1),
933 PINMUX_DATA(BS_MARK, PORT202_FN2),
934
935 /* Port203 */
936 PINMUX_DATA(CKO_MARK, PORT203_FN1),
937 PINMUX_DATA(MMCCLK1_MARK, PORT203_FN2),
938
939 /* Port204 */
940 PINMUX_DATA(CS0_N_MARK, PORT204_FN1),
941 PINMUX_DATA(SIM0_GPO1_MARK, PORT204_FN5),
942
943 /* Port205 */
944 PINMUX_DATA(CS2_N_MARK, PORT205_FN1),
945 PINMUX_DATA(SIM0_GPO2_MARK, PORT205_FN5),
946
947 /* Port206 */
948 PINMUX_DATA(CS4_N_MARK, PORT206_FN1),
949 PINMUX_DATA(VIO_VD_MARK, PORT206_FN2),
950 PINMUX_DATA(SIM1_GPO0_MARK, PORT206_FN5),
951
952 /* Port207 - Port212 FN1 */
953 PINMUX_DATA(D15_MARK, PORT207_FN1),
954 PINMUX_DATA(D14_MARK, PORT208_FN1),
955 PINMUX_DATA(D13_MARK, PORT209_FN1),
956 PINMUX_DATA(D12_MARK, PORT210_FN1),
957 PINMUX_DATA(D11_MARK, PORT211_FN1),
958 PINMUX_DATA(D10_MARK, PORT212_FN1),
959
960 /* Port207 - Port212 FN5 */
961 PINMUX_DATA(GIO_OUT15_MARK, PORT207_FN5),
962 PINMUX_DATA(GIO_OUT14_MARK, PORT208_FN5),
963 PINMUX_DATA(GIO_OUT13_MARK, PORT209_FN5),
964 PINMUX_DATA(GIO_OUT12_MARK, PORT210_FN5),
965 PINMUX_DATA(WGM_TXP2_MARK, PORT211_FN5),
966 PINMUX_DATA(WGM_GPS_TIMEM_ASK_RFCLK_MARK, PORT212_FN5),
967
968 /* Port213 - Port222 FN1 */
969 PINMUX_DATA(D9_MARK, PORT213_FN1),
970 PINMUX_DATA(D8_MARK, PORT214_FN1),
971 PINMUX_DATA(D7_MARK, PORT215_FN1),
972 PINMUX_DATA(D6_MARK, PORT216_FN1),
973 PINMUX_DATA(D5_MARK, PORT217_FN1),
974 PINMUX_DATA(D4_MARK, PORT218_FN1),
975 PINMUX_DATA(D3_MARK, PORT219_FN1),
976 PINMUX_DATA(D2_MARK, PORT220_FN1),
977 PINMUX_DATA(D1_MARK, PORT221_FN1),
978 PINMUX_DATA(D0_MARK, PORT222_FN1),
979
980 /* Port213 - Port222 FN2 */
981 PINMUX_DATA(VIO_D9_MARK, PORT213_FN2),
982 PINMUX_DATA(VIO_D8_MARK, PORT214_FN2),
983 PINMUX_DATA(VIO_D7_MARK, PORT215_FN2),
984 PINMUX_DATA(VIO_D6_MARK, PORT216_FN2),
985 PINMUX_DATA(VIO_D5_MARK, PORT217_FN2),
986 PINMUX_DATA(VIO_D4_MARK, PORT218_FN2),
987 PINMUX_DATA(VIO_D3_MARK, PORT219_FN2),
988 PINMUX_DATA(VIO_D2_MARK, PORT220_FN2),
989 PINMUX_DATA(VIO_D1_MARK, PORT221_FN2),
990 PINMUX_DATA(VIO_D0_MARK, PORT222_FN2),
991
992 /* Port213 - Port222 FN5 */
993 PINMUX_DATA(GIO_OUT9_MARK, PORT213_FN5),
994 PINMUX_DATA(GIO_OUT8_MARK, PORT214_FN5),
995 PINMUX_DATA(GIO_OUT7_MARK, PORT215_FN5),
996 PINMUX_DATA(GIO_OUT6_MARK, PORT216_FN5),
997 PINMUX_DATA(GIO_OUT5_217_MARK, PORT217_FN5),
998 PINMUX_DATA(GIO_OUT4_218_MARK, PORT218_FN5),
999 PINMUX_DATA(GIO_OUT3_219_MARK, PORT219_FN5),
1000 PINMUX_DATA(GIO_OUT2_220_MARK, PORT220_FN5),
1001 PINMUX_DATA(GIO_OUT1_221_MARK, PORT221_FN5),
1002 PINMUX_DATA(GIO_OUT0_222_MARK, PORT222_FN5),
1003
1004 /* Port224 */
1005 PINMUX_DATA(RDWR_224_MARK, PORT224_FN1),
1006 PINMUX_DATA(VIO_HD_MARK, PORT224_FN2),
1007 PINMUX_DATA(SIM1_GPO2_MARK, PORT224_FN5),
1008
1009 /* Port225 */
1010 PINMUX_DATA(RD_N_MARK, PORT225_FN1),
1011
1012 /* Port226 */
1013 PINMUX_DATA(WAIT_N_MARK, PORT226_FN1),
1014 PINMUX_DATA(VIO_CLK_MARK, PORT226_FN2),
1015 PINMUX_DATA(SIM1_GPO1_MARK, PORT226_FN5),
1016
1017 /* Port227 */
1018 PINMUX_DATA(WE0_N_MARK, PORT227_FN1),
1019 PINMUX_DATA(RDWR_227_MARK, PORT227_FN2),
1020
1021 /* Port228 */
1022 PINMUX_DATA(WE1_N_MARK, PORT228_FN1),
1023 PINMUX_DATA(SIM0_GPO0_MARK, PORT228_FN5),
1024
1025 /* Port229 */
1026 PINMUX_DATA(PWMO_MARK, PORT229_FN1),
1027 PINMUX_DATA(VIO_CKO1_229_MARK, PORT229_FN2),
1028
1029 /* Port230 */
1030 PINMUX_DATA(SLIM_CLK_MARK, PORT230_FN1),
1031 PINMUX_DATA(VIO_CKO4_230_MARK, PORT230_FN2),
1032
1033 /* Port231 */
1034 PINMUX_DATA(SLIM_DATA_MARK, PORT231_FN1),
1035 PINMUX_DATA(VIO_CKO5_231_MARK, PORT231_FN2),
1036
1037 /* Port232 */
1038 PINMUX_DATA(VIO_CKO2_232_MARK, PORT232_FN2),
1039 PINMUX_DATA(SF_PORT_0_232_MARK, PORT232_FN4),
1040
1041 /* Port233 */
1042 PINMUX_DATA(VIO_CKO3_233_MARK, PORT233_FN2),
1043 PINMUX_DATA(SF_PORT_1_233_MARK, PORT233_FN4),
1044
1045 /* Port234 */
1046 PINMUX_DATA(FSIACK_MARK, PORT234_FN1),
1047 PINMUX_DATA(PDM3_CLK_234_MARK, PORT234_FN2),
1048 PINMUX_DATA(ISP_IRIS1_234_MARK, PORT234_FN3),
1049
1050 /* Port235 */
1051 PINMUX_DATA(FSIAISLD_MARK, PORT235_FN1),
1052 PINMUX_DATA(PDM3_DATA_235_MARK, PORT235_FN2, MSEL3CR_12_1),
1053
1054 /* Port236 */
1055 PINMUX_DATA(FSIAOMC_MARK, PORT236_FN1),
1056 PINMUX_DATA(PDM0_OUTCLK_236_MARK, PORT236_FN2),
1057 PINMUX_DATA(ISP_IRIS0_236_MARK, PORT236_FN3),
1058
1059 /* Port237 */
1060 PINMUX_DATA(FSIAOLR_MARK, PORT237_FN1),
1061 PINMUX_DATA(FSIAILR_MARK, PORT237_FN2),
1062
1063 /* Port238 */
1064 PINMUX_DATA(FSIAOBT_MARK, PORT238_FN1),
1065 PINMUX_DATA(FSIAIBT_MARK, PORT238_FN2),
1066
1067 /* Port239 */
1068 PINMUX_DATA(FSIAOSLD_MARK, PORT239_FN1),
1069 PINMUX_DATA(PDM0_OUTDATA_239_MARK, PORT239_FN2),
1070
1071 /* Port240 */
1072 PINMUX_DATA(FSIBISLD_MARK, PORT240_FN1),
1073
1074 /* Port241 */
1075 PINMUX_DATA(FSIBOLR_MARK, PORT241_FN1),
1076 PINMUX_DATA(FSIBILR_MARK, PORT241_FN2),
1077
1078 /* Port242 */
1079 PINMUX_DATA(FSIBOMC_MARK, PORT242_FN1),
1080 PINMUX_DATA(ISP_SHUTTER1_242_MARK, PORT242_FN3),
1081
1082 /* Port243 */
1083 PINMUX_DATA(FSIBOBT_MARK, PORT243_FN1),
1084 PINMUX_DATA(FSIBIBT_MARK, PORT243_FN2),
1085
1086 /* Port244 */
1087 PINMUX_DATA(FSIBOSLD_MARK, PORT244_FN1),
1088 PINMUX_DATA(FSIASPDIF_MARK, PORT244_FN2),
1089
1090 /* Port245 */
1091 PINMUX_DATA(FSIBCK_MARK, PORT245_FN1),
1092 PINMUX_DATA(ISP_SHUTTER0_245_MARK, PORT245_FN3),
1093
1094 /* Port246 - Port250 FN1 */
1095 PINMUX_DATA(ISP_IRIS1_246_MARK, PORT246_FN1),
1096 PINMUX_DATA(ISP_IRIS0_247_MARK, PORT247_FN1),
1097 PINMUX_DATA(ISP_SHUTTER1_248_MARK, PORT248_FN1),
1098 PINMUX_DATA(ISP_SHUTTER0_249_MARK, PORT249_FN1),
1099 PINMUX_DATA(ISP_STROBE_250_MARK, PORT250_FN1),
1100
1101 /* Port256 - Port258 */
1102 PINMUX_DATA(MSIOF0_SYNC_MARK, PORT256_FN1),
1103 PINMUX_DATA(MSIOF0_RXD_MARK, PORT257_FN1),
1104 PINMUX_DATA(MSIOF0_SCK_MARK, PORT258_FN1),
1105
1106 /* Port259 */
1107 PINMUX_DATA(MSIOF0_SS2_MARK, PORT259_FN1),
1108 PINMUX_DATA(VIO_CKO3_259_MARK, PORT259_FN3),
1109
1110 /* Port260 */
1111 PINMUX_DATA(MSIOF0_TXD_MARK, PORT260_FN1),
1112
1113 /* Port261 */
1114 PINMUX_DATA(SCIFB1_SCK_261_MARK, PORT261_FN2),
1115 PINMUX_DATA(CHSCIF1_HSCK_MARK, PORT261_FN7),
1116
1117 /* Port262 */
1118 PINMUX_DATA(SCIFB2_SCK_262_MARK, PORT262_FN2),
1119
1120 /* Port263 - Port266 FN1 */
1121 PINMUX_DATA(MSIOF1_SS2_MARK, PORT263_FN1),
1122 PINMUX_DATA(MSIOF1_TXD_MARK, PORT264_FN1),
1123 PINMUX_DATA(MSIOF1_RXD_MARK, PORT265_FN1),
1124 PINMUX_DATA(MSIOF1_SS1_MARK, PORT266_FN1),
1125
1126 /* Port263 - Port266 FN4 */
1127 PINMUX_DATA(MSIOF5_SS2_MARK, PORT263_FN4),
1128 PINMUX_DATA(MSIOF5_TXD_MARK, PORT264_FN4),
1129 PINMUX_DATA(MSIOF5_RXD_MARK, PORT265_FN4),
1130 PINMUX_DATA(MSIOF5_SS1_MARK, PORT266_FN4),
1131
1132 /* Port267 */
1133 PINMUX_DATA(MSIOF0_SS1_MARK, PORT267_FN1),
1134
1135 /* Port268 */
1136 PINMUX_DATA(MSIOF1_SCK_MARK, PORT268_FN1),
1137 PINMUX_DATA(MSIOF5_SCK_MARK, PORT268_FN4),
1138
1139 /* Port269 */
1140 PINMUX_DATA(MSIOF1_SYNC_MARK, PORT269_FN1),
1141 PINMUX_DATA(MSIOF5_SYNC_MARK, PORT269_FN4),
1142
1143 /* Port270 - Port273 FN1 */
1144 PINMUX_DATA(MSIOF2_SS1_MARK, PORT270_FN1),
1145 PINMUX_DATA(MSIOF2_SS2_MARK, PORT271_FN1),
1146 PINMUX_DATA(MSIOF3_SS2_MARK, PORT272_FN1),
1147 PINMUX_DATA(MSIOF3_SS1_MARK, PORT273_FN1),
1148
1149 /* Port270 - Port273 FN3 */
1150 PINMUX_DATA(VIO_CKO5_270_MARK, PORT270_FN3),
1151 PINMUX_DATA(VIO_CKO2_271_MARK, PORT271_FN3),
1152 PINMUX_DATA(VIO_CKO1_272_MARK, PORT272_FN3),
1153 PINMUX_DATA(VIO_CKO4_273_MARK, PORT273_FN3),
1154
1155 /* Port274 */
1156 PINMUX_DATA(MSIOF4_SS2_MARK, PORT274_FN1),
1157 PINMUX_DATA(TPU1TO0_MARK, PORT274_FN4),
1158
1159 /* Port275 - Port280 */
1160 PINMUX_DATA(IC_DP_MARK, PORT275_FN1),
1161 PINMUX_DATA(SIM0_RST_MARK, PORT276_FN1),
1162 PINMUX_DATA(IC_DM_MARK, PORT277_FN1),
1163 PINMUX_DATA(SIM0_BSICOMP_MARK, PORT278_FN1),
1164 PINMUX_DATA(SIM0_CLK_MARK, PORT279_FN1),
1165 PINMUX_DATA(SIM0_IO_MARK, PORT280_FN1),
1166
1167 /* Port281 */
1168 PINMUX_DATA(SIM1_IO_MARK, PORT281_FN1),
1169 PINMUX_DATA(PDM2_DATA_281_MARK, PORT281_FN2, MSEL3CR_12_1),
1170
1171 /* Port282 */
1172 PINMUX_DATA(SIM1_CLK_MARK, PORT282_FN1),
1173 PINMUX_DATA(PDM2_CLK_282_MARK, PORT282_FN2),
1174
1175 /* Port283 */
1176 PINMUX_DATA(SIM1_RST_MARK, PORT283_FN1),
1177
1178 /* Port289 */
1179 PINMUX_DATA(SDHID1_0_MARK, PORT289_FN1),
1180 PINMUX_DATA(STMDATA0_2_MARK, PORT289_FN3),
1181
1182 /* Port290 */
1183 PINMUX_DATA(SDHID1_1_MARK, PORT290_FN1),
1184 PINMUX_DATA(STMDATA1_2_MARK, PORT290_FN3),
1185 PINMUX_DATA(IRQ51_MARK, PORT290_FN0),
1186
1187 /* Port291 - Port294 FN1 */
1188 PINMUX_DATA(SDHID1_2_MARK, PORT291_FN1),
1189 PINMUX_DATA(SDHID1_3_MARK, PORT292_FN1),
1190 PINMUX_DATA(SDHICLK1_MARK, PORT293_FN1),
1191 PINMUX_DATA(SDHICMD1_MARK, PORT294_FN1),
1192
1193 /* Port291 - Port294 FN3 */
1194 PINMUX_DATA(STMDATA2_2_MARK, PORT291_FN3),
1195 PINMUX_DATA(STMDATA3_2_MARK, PORT292_FN3),
1196 PINMUX_DATA(STMCLK_2_MARK, PORT293_FN3),
1197 PINMUX_DATA(STMSIDI_2_MARK, PORT294_FN3),
1198
1199 /* Port295 */
1200 PINMUX_DATA(SDHID2_0_MARK, PORT295_FN1),
1201 PINMUX_DATA(MSIOF4_TXD_MARK, PORT295_FN2),
1202 PINMUX_DATA(SCIFB2_TXD_295_MARK, PORT295_FN3, MSEL3CR_10_1),
1203 PINMUX_DATA(MSIOF6_TXD_MARK, PORT295_FN4),
1204
1205 /* Port296 */
1206 PINMUX_DATA(SDHID2_1_MARK, PORT296_FN1),
1207 PINMUX_DATA(MSIOF6_SS2_MARK, PORT296_FN4),
1208 PINMUX_DATA(IRQ52_MARK, PORT296_FN0),
1209
1210 /* Port297 - Port300 FN1 */
1211 PINMUX_DATA(SDHID2_2_MARK, PORT297_FN1),
1212 PINMUX_DATA(SDHID2_3_MARK, PORT298_FN1),
1213 PINMUX_DATA(SDHICLK2_MARK, PORT299_FN1),
1214 PINMUX_DATA(SDHICMD2_MARK, PORT300_FN1),
1215
1216 /* Port297 - Port300 FN2 */
1217 PINMUX_DATA(MSIOF4_RXD_MARK, PORT297_FN2),
1218 PINMUX_DATA(MSIOF4_SYNC_MARK, PORT298_FN2),
1219 PINMUX_DATA(MSIOF4_SCK_MARK, PORT299_FN2),
1220 PINMUX_DATA(MSIOF4_SS1_MARK, PORT300_FN2),
1221
1222 /* Port297 - Port300 FN3 */
1223 PINMUX_DATA(SCIFB2_RXD_297_MARK, PORT297_FN3, MSEL3CR_10_1),
1224 PINMUX_DATA(SCIFB2_CTS_298_MARK, PORT298_FN3, MSEL3CR_10_1),
1225 PINMUX_DATA(SCIFB2_SCK_299_MARK, PORT299_FN3),
1226 PINMUX_DATA(SCIFB2_RTS_300_MARK, PORT300_FN3),
1227
1228 /* Port297 - Port300 FN4 */
1229 PINMUX_DATA(MSIOF6_RXD_MARK, PORT297_FN4),
1230 PINMUX_DATA(MSIOF6_SYNC_MARK, PORT298_FN4),
1231 PINMUX_DATA(MSIOF6_SCK_MARK, PORT299_FN4),
1232 PINMUX_DATA(MSIOF6_SS1_MARK, PORT300_FN4),
1233
1234 /* Port301 */
1235 PINMUX_DATA(SDHICD0_MARK, PORT301_FN1),
1236 PINMUX_DATA(IRQ50_MARK, PORT301_FN0),
1237
1238 /* Port302 - Port306 FN1 */
1239 PINMUX_DATA(SDHID0_0_MARK, PORT302_FN1),
1240 PINMUX_DATA(SDHID0_1_MARK, PORT303_FN1),
1241 PINMUX_DATA(SDHID0_2_MARK, PORT304_FN1),
1242 PINMUX_DATA(SDHID0_3_MARK, PORT305_FN1),
1243 PINMUX_DATA(SDHICMD0_MARK, PORT306_FN1),
1244
1245 /* Port302 - Port306 FN3 */
1246 PINMUX_DATA(STMDATA0_1_MARK, PORT302_FN3),
1247 PINMUX_DATA(STMDATA1_1_MARK, PORT303_FN3),
1248 PINMUX_DATA(STMDATA2_1_MARK, PORT304_FN3),
1249 PINMUX_DATA(STMDATA3_1_MARK, PORT305_FN3),
1250 PINMUX_DATA(STMSIDI_1_MARK, PORT306_FN3),
1251
1252 /* Port307 */
1253 PINMUX_DATA(SDHIWP0_MARK, PORT307_FN1),
1254
1255 /* Port308 */
1256 PINMUX_DATA(SDHICLK0_MARK, PORT308_FN1),
1257 PINMUX_DATA(STMCLK_1_MARK, PORT308_FN3),
1258
1259 /* Port320 - Port329 */
1260 PINMUX_DATA(IRQ16_MARK, PORT320_FN0),
1261 PINMUX_DATA(IRQ17_MARK, PORT321_FN0),
1262 PINMUX_DATA(IRQ28_MARK, PORT322_FN0),
1263 PINMUX_DATA(IRQ29_MARK, PORT323_FN0),
1264 PINMUX_DATA(IRQ30_MARK, PORT324_FN0),
1265 PINMUX_DATA(IRQ53_MARK, PORT325_FN0),
1266 PINMUX_DATA(IRQ54_MARK, PORT326_FN0),
1267 PINMUX_DATA(IRQ55_MARK, PORT327_FN0),
1268 PINMUX_DATA(IRQ56_MARK, PORT328_FN0),
1269 PINMUX_DATA(IRQ57_MARK, PORT329_FN0),
1270 };
1271
1272 #define R8A73A4_PIN(pin, cfgs) \
1273 { \
1274 .name = __stringify(PORT##pin), \
1275 .enum_id = PORT##pin##_DATA, \
1276 .configs = cfgs, \
1277 }
1278
1279 #define __O (SH_PFC_PIN_CFG_OUTPUT)
1280 #define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
1281 #define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
1282
1283 #define R8A73A4_PIN_IO_PU_PD(pin) R8A73A4_PIN(pin, __IO | __PUD)
1284 #define R8A73A4_PIN_O(pin) R8A73A4_PIN(pin, __O)
1285
1286 static struct sh_pfc_pin pinmux_pins[] = {
1287 R8A73A4_PIN_IO_PU_PD(0), R8A73A4_PIN_IO_PU_PD(1),
1288 R8A73A4_PIN_IO_PU_PD(2), R8A73A4_PIN_IO_PU_PD(3),
1289 R8A73A4_PIN_IO_PU_PD(4), R8A73A4_PIN_IO_PU_PD(5),
1290 R8A73A4_PIN_IO_PU_PD(6), R8A73A4_PIN_IO_PU_PD(7),
1291 R8A73A4_PIN_IO_PU_PD(8), R8A73A4_PIN_IO_PU_PD(9),
1292 R8A73A4_PIN_IO_PU_PD(10), R8A73A4_PIN_IO_PU_PD(11),
1293 R8A73A4_PIN_IO_PU_PD(12), R8A73A4_PIN_IO_PU_PD(13),
1294 R8A73A4_PIN_IO_PU_PD(14), R8A73A4_PIN_IO_PU_PD(15),
1295 R8A73A4_PIN_IO_PU_PD(16), R8A73A4_PIN_IO_PU_PD(17),
1296 R8A73A4_PIN_IO_PU_PD(18), R8A73A4_PIN_IO_PU_PD(19),
1297 R8A73A4_PIN_IO_PU_PD(20), R8A73A4_PIN_IO_PU_PD(21),
1298 R8A73A4_PIN_IO_PU_PD(22), R8A73A4_PIN_IO_PU_PD(23),
1299 R8A73A4_PIN_IO_PU_PD(24), R8A73A4_PIN_IO_PU_PD(25),
1300 R8A73A4_PIN_IO_PU_PD(26), R8A73A4_PIN_IO_PU_PD(27),
1301 R8A73A4_PIN_IO_PU_PD(28), R8A73A4_PIN_IO_PU_PD(29),
1302 R8A73A4_PIN_IO_PU_PD(30),
1303 R8A73A4_PIN_IO_PU_PD(32), R8A73A4_PIN_IO_PU_PD(33),
1304 R8A73A4_PIN_IO_PU_PD(34), R8A73A4_PIN_IO_PU_PD(35),
1305 R8A73A4_PIN_IO_PU_PD(36), R8A73A4_PIN_IO_PU_PD(37),
1306 R8A73A4_PIN_IO_PU_PD(38), R8A73A4_PIN_IO_PU_PD(39),
1307 R8A73A4_PIN_IO_PU_PD(40),
1308 R8A73A4_PIN_IO_PU_PD(64), R8A73A4_PIN_IO_PU_PD(65),
1309 R8A73A4_PIN_IO_PU_PD(66), R8A73A4_PIN_IO_PU_PD(67),
1310 R8A73A4_PIN_IO_PU_PD(68), R8A73A4_PIN_IO_PU_PD(69),
1311 R8A73A4_PIN_IO_PU_PD(70), R8A73A4_PIN_IO_PU_PD(71),
1312 R8A73A4_PIN_IO_PU_PD(72), R8A73A4_PIN_IO_PU_PD(73),
1313 R8A73A4_PIN_O(74), R8A73A4_PIN_IO_PU_PD(75),
1314 R8A73A4_PIN_IO_PU_PD(76), R8A73A4_PIN_IO_PU_PD(77),
1315 R8A73A4_PIN_IO_PU_PD(78), R8A73A4_PIN_IO_PU_PD(79),
1316 R8A73A4_PIN_IO_PU_PD(80), R8A73A4_PIN_IO_PU_PD(81),
1317 R8A73A4_PIN_IO_PU_PD(82), R8A73A4_PIN_IO_PU_PD(83),
1318 R8A73A4_PIN_IO_PU_PD(84), R8A73A4_PIN_IO_PU_PD(85),
1319 R8A73A4_PIN_IO_PU_PD(96), R8A73A4_PIN_IO_PU_PD(97),
1320 R8A73A4_PIN_IO_PU_PD(98), R8A73A4_PIN_IO_PU_PD(99),
1321 R8A73A4_PIN_IO_PU_PD(100), R8A73A4_PIN_IO_PU_PD(101),
1322 R8A73A4_PIN_IO_PU_PD(102), R8A73A4_PIN_IO_PU_PD(103),
1323 R8A73A4_PIN_IO_PU_PD(104), R8A73A4_PIN_IO_PU_PD(105),
1324 R8A73A4_PIN_IO_PU_PD(106), R8A73A4_PIN_IO_PU_PD(107),
1325 R8A73A4_PIN_IO_PU_PD(108), R8A73A4_PIN_IO_PU_PD(109),
1326 R8A73A4_PIN_IO_PU_PD(110), R8A73A4_PIN_IO_PU_PD(111),
1327 R8A73A4_PIN_IO_PU_PD(112), R8A73A4_PIN_IO_PU_PD(113),
1328 R8A73A4_PIN_IO_PU_PD(114), R8A73A4_PIN_IO_PU_PD(115),
1329 R8A73A4_PIN_IO_PU_PD(116), R8A73A4_PIN_IO_PU_PD(117),
1330 R8A73A4_PIN_IO_PU_PD(118), R8A73A4_PIN_IO_PU_PD(119),
1331 R8A73A4_PIN_IO_PU_PD(120), R8A73A4_PIN_IO_PU_PD(121),
1332 R8A73A4_PIN_IO_PU_PD(122), R8A73A4_PIN_IO_PU_PD(123),
1333 R8A73A4_PIN_IO_PU_PD(124), R8A73A4_PIN_IO_PU_PD(125),
1334 R8A73A4_PIN_IO_PU_PD(126),
1335 R8A73A4_PIN_IO_PU_PD(128), R8A73A4_PIN_IO_PU_PD(129),
1336 R8A73A4_PIN_IO_PU_PD(130), R8A73A4_PIN_IO_PU_PD(131),
1337 R8A73A4_PIN_IO_PU_PD(132), R8A73A4_PIN_IO_PU_PD(133),
1338 R8A73A4_PIN_IO_PU_PD(134),
1339 R8A73A4_PIN_IO_PU_PD(160), R8A73A4_PIN_IO_PU_PD(161),
1340 R8A73A4_PIN_IO_PU_PD(162), R8A73A4_PIN_IO_PU_PD(163),
1341 R8A73A4_PIN_IO_PU_PD(164), R8A73A4_PIN_IO_PU_PD(165),
1342 R8A73A4_PIN_IO_PU_PD(166), R8A73A4_PIN_IO_PU_PD(167),
1343 R8A73A4_PIN_IO_PU_PD(168), R8A73A4_PIN_IO_PU_PD(169),
1344 R8A73A4_PIN_IO_PU_PD(170), R8A73A4_PIN_IO_PU_PD(171),
1345 R8A73A4_PIN_IO_PU_PD(172), R8A73A4_PIN_IO_PU_PD(173),
1346 R8A73A4_PIN_IO_PU_PD(174), R8A73A4_PIN_IO_PU_PD(175),
1347 R8A73A4_PIN_IO_PU_PD(176), R8A73A4_PIN_IO_PU_PD(177),
1348 R8A73A4_PIN_IO_PU_PD(178),
1349 R8A73A4_PIN_IO_PU_PD(192), R8A73A4_PIN_IO_PU_PD(193),
1350 R8A73A4_PIN_IO_PU_PD(194), R8A73A4_PIN_IO_PU_PD(195),
1351 R8A73A4_PIN_IO_PU_PD(196), R8A73A4_PIN_IO_PU_PD(197),
1352 R8A73A4_PIN_IO_PU_PD(198), R8A73A4_PIN_IO_PU_PD(199),
1353 R8A73A4_PIN_IO_PU_PD(200), R8A73A4_PIN_IO_PU_PD(201),
1354 R8A73A4_PIN_IO_PU_PD(202), R8A73A4_PIN_IO_PU_PD(203),
1355 R8A73A4_PIN_IO_PU_PD(204), R8A73A4_PIN_IO_PU_PD(205),
1356 R8A73A4_PIN_IO_PU_PD(206), R8A73A4_PIN_IO_PU_PD(207),
1357 R8A73A4_PIN_IO_PU_PD(208), R8A73A4_PIN_IO_PU_PD(209),
1358 R8A73A4_PIN_IO_PU_PD(210), R8A73A4_PIN_IO_PU_PD(211),
1359 R8A73A4_PIN_IO_PU_PD(212), R8A73A4_PIN_IO_PU_PD(213),
1360 R8A73A4_PIN_IO_PU_PD(214), R8A73A4_PIN_IO_PU_PD(215),
1361 R8A73A4_PIN_IO_PU_PD(216), R8A73A4_PIN_IO_PU_PD(217),
1362 R8A73A4_PIN_IO_PU_PD(218), R8A73A4_PIN_IO_PU_PD(219),
1363 R8A73A4_PIN_IO_PU_PD(220), R8A73A4_PIN_IO_PU_PD(221),
1364 R8A73A4_PIN_IO_PU_PD(222),
1365 R8A73A4_PIN_IO_PU_PD(224), R8A73A4_PIN_IO_PU_PD(225),
1366 R8A73A4_PIN_IO_PU_PD(226), R8A73A4_PIN_IO_PU_PD(227),
1367 R8A73A4_PIN_IO_PU_PD(228), R8A73A4_PIN_IO_PU_PD(229),
1368 R8A73A4_PIN_IO_PU_PD(230), R8A73A4_PIN_IO_PU_PD(231),
1369 R8A73A4_PIN_IO_PU_PD(232), R8A73A4_PIN_IO_PU_PD(233),
1370 R8A73A4_PIN_IO_PU_PD(234), R8A73A4_PIN_IO_PU_PD(235),
1371 R8A73A4_PIN_IO_PU_PD(236), R8A73A4_PIN_IO_PU_PD(237),
1372 R8A73A4_PIN_IO_PU_PD(238), R8A73A4_PIN_IO_PU_PD(239),
1373 R8A73A4_PIN_IO_PU_PD(240), R8A73A4_PIN_IO_PU_PD(241),
1374 R8A73A4_PIN_IO_PU_PD(242), R8A73A4_PIN_IO_PU_PD(243),
1375 R8A73A4_PIN_IO_PU_PD(244), R8A73A4_PIN_IO_PU_PD(245),
1376 R8A73A4_PIN_IO_PU_PD(246), R8A73A4_PIN_IO_PU_PD(247),
1377 R8A73A4_PIN_IO_PU_PD(248), R8A73A4_PIN_IO_PU_PD(249),
1378 R8A73A4_PIN_IO_PU_PD(250),
1379 R8A73A4_PIN_IO_PU_PD(256), R8A73A4_PIN_IO_PU_PD(257),
1380 R8A73A4_PIN_IO_PU_PD(258), R8A73A4_PIN_IO_PU_PD(259),
1381 R8A73A4_PIN_IO_PU_PD(260), R8A73A4_PIN_IO_PU_PD(261),
1382 R8A73A4_PIN_IO_PU_PD(262), R8A73A4_PIN_IO_PU_PD(263),
1383 R8A73A4_PIN_IO_PU_PD(264), R8A73A4_PIN_IO_PU_PD(265),
1384 R8A73A4_PIN_IO_PU_PD(266), R8A73A4_PIN_IO_PU_PD(267),
1385 R8A73A4_PIN_IO_PU_PD(268), R8A73A4_PIN_IO_PU_PD(269),
1386 R8A73A4_PIN_IO_PU_PD(270), R8A73A4_PIN_IO_PU_PD(271),
1387 R8A73A4_PIN_IO_PU_PD(272), R8A73A4_PIN_IO_PU_PD(273),
1388 R8A73A4_PIN_IO_PU_PD(274), R8A73A4_PIN_IO_PU_PD(275),
1389 R8A73A4_PIN_IO_PU_PD(276), R8A73A4_PIN_IO_PU_PD(277),
1390 R8A73A4_PIN_IO_PU_PD(278), R8A73A4_PIN_IO_PU_PD(279),
1391 R8A73A4_PIN_IO_PU_PD(280), R8A73A4_PIN_IO_PU_PD(281),
1392 R8A73A4_PIN_IO_PU_PD(282), R8A73A4_PIN_IO_PU_PD(283),
1393 R8A73A4_PIN_O(288), R8A73A4_PIN_IO_PU_PD(289),
1394 R8A73A4_PIN_IO_PU_PD(290), R8A73A4_PIN_IO_PU_PD(291),
1395 R8A73A4_PIN_IO_PU_PD(292), R8A73A4_PIN_IO_PU_PD(293),
1396 R8A73A4_PIN_IO_PU_PD(294), R8A73A4_PIN_IO_PU_PD(295),
1397 R8A73A4_PIN_IO_PU_PD(296), R8A73A4_PIN_IO_PU_PD(297),
1398 R8A73A4_PIN_IO_PU_PD(298), R8A73A4_PIN_IO_PU_PD(299),
1399 R8A73A4_PIN_IO_PU_PD(300), R8A73A4_PIN_IO_PU_PD(301),
1400 R8A73A4_PIN_IO_PU_PD(302), R8A73A4_PIN_IO_PU_PD(303),
1401 R8A73A4_PIN_IO_PU_PD(304), R8A73A4_PIN_IO_PU_PD(305),
1402 R8A73A4_PIN_IO_PU_PD(306), R8A73A4_PIN_IO_PU_PD(307),
1403 R8A73A4_PIN_IO_PU_PD(308),
1404 R8A73A4_PIN_IO_PU_PD(320), R8A73A4_PIN_IO_PU_PD(321),
1405 R8A73A4_PIN_IO_PU_PD(322), R8A73A4_PIN_IO_PU_PD(323),
1406 R8A73A4_PIN_IO_PU_PD(324), R8A73A4_PIN_IO_PU_PD(325),
1407 R8A73A4_PIN_IO_PU_PD(326), R8A73A4_PIN_IO_PU_PD(327),
1408 R8A73A4_PIN_IO_PU_PD(328), R8A73A4_PIN_IO_PU_PD(329),
1409 };
1410
1411 static const struct pinmux_range pinmux_ranges[] = {
1412 {.begin = 0, .end = 30,},
1413 {.begin = 32, .end = 40,},
1414 {.begin = 64, .end = 85,},
1415 {.begin = 96, .end = 126,},
1416 {.begin = 128, .end = 134,},
1417 {.begin = 160, .end = 178,},
1418 {.begin = 192, .end = 222,},
1419 {.begin = 224, .end = 250,},
1420 {.begin = 256, .end = 283,},
1421 {.begin = 288, .end = 308,},
1422 {.begin = 320, .end = 329,},
1423 };
1424
1425 /* - IRQC ------------------------------------------------------------------- */
1426 #define IRQC_PINS_MUX(pin, irq_mark) \
1427 static const unsigned int irqc_irq##irq_mark##_pins[] = { \
1428 pin, \
1429 }; \
1430 static const unsigned int irqc_irq##irq_mark##_mux[] = { \
1431 IRQ##irq_mark##_MARK, \
1432 }
1433 IRQC_PINS_MUX(0, 0);
1434 IRQC_PINS_MUX(1, 1);
1435 IRQC_PINS_MUX(2, 2);
1436 IRQC_PINS_MUX(3, 3);
1437 IRQC_PINS_MUX(4, 4);
1438 IRQC_PINS_MUX(5, 5);
1439 IRQC_PINS_MUX(6, 6);
1440 IRQC_PINS_MUX(7, 7);
1441 IRQC_PINS_MUX(8, 8);
1442 IRQC_PINS_MUX(9, 9);
1443 IRQC_PINS_MUX(10, 10);
1444 IRQC_PINS_MUX(11, 11);
1445 IRQC_PINS_MUX(12, 12);
1446 IRQC_PINS_MUX(13, 13);
1447 IRQC_PINS_MUX(14, 14);
1448 IRQC_PINS_MUX(15, 15);
1449 IRQC_PINS_MUX(66, 40);
1450 IRQC_PINS_MUX(84, 19);
1451 IRQC_PINS_MUX(85, 18);
1452 IRQC_PINS_MUX(102, 41);
1453 IRQC_PINS_MUX(103, 42);
1454 IRQC_PINS_MUX(109, 43);
1455 IRQC_PINS_MUX(110, 44);
1456 IRQC_PINS_MUX(111, 45);
1457 IRQC_PINS_MUX(112, 46);
1458 IRQC_PINS_MUX(113, 47);
1459 IRQC_PINS_MUX(114, 48);
1460 IRQC_PINS_MUX(115, 49);
1461 IRQC_PINS_MUX(160, 20);
1462 IRQC_PINS_MUX(161, 21);
1463 IRQC_PINS_MUX(162, 22);
1464 IRQC_PINS_MUX(163, 23);
1465 IRQC_PINS_MUX(175, 24);
1466 IRQC_PINS_MUX(176, 25);
1467 IRQC_PINS_MUX(177, 26);
1468 IRQC_PINS_MUX(178, 27);
1469 IRQC_PINS_MUX(192, 31);
1470 IRQC_PINS_MUX(193, 32);
1471 IRQC_PINS_MUX(194, 33);
1472 IRQC_PINS_MUX(195, 34);
1473 IRQC_PINS_MUX(196, 35);
1474 IRQC_PINS_MUX(197, 36);
1475 IRQC_PINS_MUX(198, 37);
1476 IRQC_PINS_MUX(199, 38);
1477 IRQC_PINS_MUX(200, 39);
1478 IRQC_PINS_MUX(290, 51);
1479 IRQC_PINS_MUX(296, 52);
1480 IRQC_PINS_MUX(301, 50);
1481 IRQC_PINS_MUX(320, 16);
1482 IRQC_PINS_MUX(321, 17);
1483 IRQC_PINS_MUX(322, 28);
1484 IRQC_PINS_MUX(323, 29);
1485 IRQC_PINS_MUX(324, 30);
1486 IRQC_PINS_MUX(325, 53);
1487 IRQC_PINS_MUX(326, 54);
1488 IRQC_PINS_MUX(327, 55);
1489 IRQC_PINS_MUX(328, 56);
1490 IRQC_PINS_MUX(329, 57);
1491 /* - MMCIF0 ----------------------------------------------------------------- */
1492 static const unsigned int mmc0_data1_pins[] = {
1493 /* D[0] */
1494 164,
1495 };
1496 static const unsigned int mmc0_data1_mux[] = {
1497 MMCD0_0_MARK,
1498 };
1499 static const unsigned int mmc0_data4_pins[] = {
1500 /* D[0:3] */
1501 164, 165, 166, 167,
1502 };
1503 static const unsigned int mmc0_data4_mux[] = {
1504 MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
1505 };
1506 static const unsigned int mmc0_data8_pins[] = {
1507 /* D[0:7] */
1508 164, 165, 166, 167, 168, 169, 170, 171,
1509 };
1510 static const unsigned int mmc0_data8_mux[] = {
1511 MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
1512 MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK,
1513 };
1514 static const unsigned int mmc0_ctrl_pins[] = {
1515 /* CMD, CLK */
1516 172, 173,
1517 };
1518 static const unsigned int mmc0_ctrl_mux[] = {
1519 MMCCMD0_MARK, MMCCLK0_MARK,
1520 };
1521 /* - MMCIF1 ----------------------------------------------------------------- */
1522 static const unsigned int mmc1_data1_pins[] = {
1523 /* D[0] */
1524 199,
1525 };
1526 static const unsigned int mmc1_data1_mux[] = {
1527 MMCD1_0_MARK,
1528 };
1529 static const unsigned int mmc1_data4_pins[] = {
1530 /* D[0:3] */
1531 199, 198, 197, 196,
1532 };
1533 static const unsigned int mmc1_data4_mux[] = {
1534 MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
1535 };
1536 static const unsigned int mmc1_data8_pins[] = {
1537 /* D[0:7] */
1538 199, 198, 197, 196, 195, 194, 193, 192,
1539 };
1540 static const unsigned int mmc1_data8_mux[] = {
1541 MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
1542 MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK,
1543 };
1544 static const unsigned int mmc1_ctrl_pins[] = {
1545 /* CMD, CLK */
1546 200, 203,
1547 };
1548 static const unsigned int mmc1_ctrl_mux[] = {
1549 MMCCMD1_MARK, MMCCLK1_MARK,
1550 };
1551 /* - SCIFA0 ----------------------------------------------------------------- */
1552 static const unsigned int scifa0_data_pins[] = {
1553 /* SCIFA0_RXD, SCIFA0_TXD */
1554 117, 116,
1555 };
1556 static const unsigned int scifa0_data_mux[] = {
1557 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
1558 };
1559 static const unsigned int scifa0_clk_pins[] = {
1560 /* SCIFA0_SCK */
1561 34,
1562 };
1563 static const unsigned int scifa0_clk_mux[] = {
1564 SCIFA0_SCK_MARK,
1565 };
1566 static const unsigned int scifa0_ctrl_pins[] = {
1567 /* SCIFA0_RTS, SCIFA0_CTS */
1568 32, 33,
1569 };
1570 static const unsigned int scifa0_ctrl_mux[] = {
1571 SCIFA0_RTS_MARK, SCIFA0_CTS_MARK,
1572 };
1573 /* - SCIFA1 ----------------------------------------------------------------- */
1574 static const unsigned int scifa1_data_pins[] = {
1575 /* SCIFA1_RXD, SCIFA1_TXD */
1576 119, 118,
1577 };
1578 static const unsigned int scifa1_data_mux[] = {
1579 SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
1580 };
1581 static const unsigned int scifa1_clk_pins[] = {
1582 /* SCIFA1_SCK */
1583 37,
1584 };
1585 static const unsigned int scifa1_clk_mux[] = {
1586 SCIFA1_SCK_MARK,
1587 };
1588 static const unsigned int scifa1_ctrl_pins[] = {
1589 /* SCIFA1_RTS, SCIFA1_CTS */
1590 35, 36,
1591 };
1592 static const unsigned int scifa1_ctrl_mux[] = {
1593 SCIFA1_RTS_MARK, SCIFA1_CTS_MARK,
1594 };
1595 /* - SCIFB0 ----------------------------------------------------------------- */
1596 static const unsigned int scifb0_data_pins[] = {
1597 /* SCIFB0_RXD, SCIFB0_TXD */
1598 123, 122,
1599 };
1600 static const unsigned int scifb0_data_mux[] = {
1601 SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
1602 };
1603 static const unsigned int scifb0_clk_pins[] = {
1604 /* SCIFB0_SCK */
1605 40,
1606 };
1607 static const unsigned int scifb0_clk_mux[] = {
1608 SCIFB0_SCK_MARK,
1609 };
1610 static const unsigned int scifb0_ctrl_pins[] = {
1611 /* SCIFB0_RTS, SCIFB0_CTS */
1612 38, 39,
1613 };
1614 static const unsigned int scifb0_ctrl_mux[] = {
1615 SCIFB0_RTS_MARK, SCIFB0_CTS_MARK,
1616 };
1617 /* - SCIFB1 ----------------------------------------------------------------- */
1618 static const unsigned int scifb1_data_pins[] = {
1619 /* SCIFB1_RXD, SCIFB1_TXD */
1620 27, 26,
1621 };
1622 static const unsigned int scifb1_data_mux[] = {
1623 SCIFB1_RXD_27_MARK, SCIFB1_TXD_26_MARK,
1624 };
1625 static const unsigned int scifb1_clk_pins[] = {
1626 /* SCIFB1_SCK */
1627 28,
1628 };
1629 static const unsigned int scifb1_clk_mux[] = {
1630 SCIFB1_SCK_28_MARK,
1631 };
1632 static const unsigned int scifb1_ctrl_pins[] = {
1633 /* SCIFB1_RTS, SCIFB1_CTS */
1634 24, 25,
1635 };
1636 static const unsigned int scifb1_ctrl_mux[] = {
1637 SCIFB1_RTS_24_MARK, SCIFB1_CTS_25_MARK,
1638 };
1639 static const unsigned int scifb1_data_b_pins[] = {
1640 /* SCIFB1_RXD, SCIFB1_TXD */
1641 72, 67,
1642 };
1643 static const unsigned int scifb1_data_b_mux[] = {
1644 SCIFB1_RXD_72_MARK, SCIFB1_TXD_67_MARK,
1645 };
1646 static const unsigned int scifb1_clk_b_pins[] = {
1647 /* SCIFB1_SCK */
1648 261,
1649 };
1650 static const unsigned int scifb1_clk_b_mux[] = {
1651 SCIFB1_SCK_261_MARK,
1652 };
1653 static const unsigned int scifb1_ctrl_b_pins[] = {
1654 /* SCIFB1_RTS, SCIFB1_CTS */
1655 70, 71,
1656 };
1657 static const unsigned int scifb1_ctrl_b_mux[] = {
1658 SCIFB1_RTS_70_MARK, SCIFB1_CTS_71_MARK,
1659 };
1660 /* - SCIFB2 ----------------------------------------------------------------- */
1661 static const unsigned int scifb2_data_pins[] = {
1662 /* SCIFB2_RXD, SCIFB2_TXD */
1663 69, 68,
1664 };
1665 static const unsigned int scifb2_data_mux[] = {
1666 SCIFB2_RXD_69_MARK, SCIFB2_TXD_68_MARK,
1667 };
1668 static const unsigned int scifb2_clk_pins[] = {
1669 /* SCIFB2_SCK */
1670 262,
1671 };
1672 static const unsigned int scifb2_clk_mux[] = {
1673 SCIFB2_SCK_262_MARK,
1674 };
1675 static const unsigned int scifb2_ctrl_pins[] = {
1676 /* SCIFB2_RTS, SCIFB2_CTS */
1677 73, 66,
1678 };
1679 static const unsigned int scifb2_ctrl_mux[] = {
1680 SCIFB2_RTS_73_MARK, SCIFB2_CTS_66_MARK,
1681 };
1682 static const unsigned int scifb2_data_b_pins[] = {
1683 /* SCIFB2_RXD, SCIFB2_TXD */
1684 297, 295,
1685 };
1686 static const unsigned int scifb2_data_b_mux[] = {
1687 SCIFB2_RXD_297_MARK, SCIFB2_TXD_295_MARK,
1688 };
1689 static const unsigned int scifb2_clk_b_pins[] = {
1690 /* SCIFB2_SCK */
1691 299,
1692 };
1693 static const unsigned int scifb2_clk_b_mux[] = {
1694 SCIFB2_SCK_299_MARK,
1695 };
1696 static const unsigned int scifb2_ctrl_b_pins[] = {
1697 /* SCIFB2_RTS, SCIFB2_CTS */
1698 300, 298,
1699 };
1700 static const unsigned int scifb2_ctrl_b_mux[] = {
1701 SCIFB2_RTS_300_MARK, SCIFB2_CTS_298_MARK,
1702 };
1703 /* - SCIFB3 ----------------------------------------------------------------- */
1704 static const unsigned int scifb3_data_pins[] = {
1705 /* SCIFB3_RXD, SCIFB3_TXD */
1706 22, 21,
1707 };
1708 static const unsigned int scifb3_data_mux[] = {
1709 SCIFB3_RXD_22_MARK, SCIFB3_TXD_21_MARK,
1710 };
1711 static const unsigned int scifb3_clk_pins[] = {
1712 /* SCIFB3_SCK */
1713 23,
1714 };
1715 static const unsigned int scifb3_clk_mux[] = {
1716 SCIFB3_SCK_23_MARK,
1717 };
1718 static const unsigned int scifb3_ctrl_pins[] = {
1719 /* SCIFB3_RTS, SCIFB3_CTS */
1720 19, 20,
1721 };
1722 static const unsigned int scifb3_ctrl_mux[] = {
1723 SCIFB3_RTS_19_MARK, SCIFB3_CTS_20_MARK,
1724 };
1725 static const unsigned int scifb3_data_b_pins[] = {
1726 /* SCIFB3_RXD, SCIFB3_TXD */
1727 120, 121,
1728 };
1729 static const unsigned int scifb3_data_b_mux[] = {
1730 SCIFB3_RXD_120_MARK, SCIFB3_TXD_121_MARK,
1731 };
1732 static const unsigned int scifb3_clk_b_pins[] = {
1733 /* SCIFB3_SCK */
1734 40,
1735 };
1736 static const unsigned int scifb3_clk_b_mux[] = {
1737 SCIFB3_SCK_40_MARK,
1738 };
1739 static const unsigned int scifb3_ctrl_b_pins[] = {
1740 /* SCIFB3_RTS, SCIFB3_CTS */
1741 38, 39,
1742 };
1743 static const unsigned int scifb3_ctrl_b_mux[] = {
1744 SCIFB3_RTS_38_MARK, SCIFB3_CTS_39_MARK,
1745 };
1746 /* - SDHI0 ------------------------------------------------------------------ */
1747 static const unsigned int sdhi0_data1_pins[] = {
1748 /* D0 */
1749 302,
1750 };
1751 static const unsigned int sdhi0_data1_mux[] = {
1752 SDHID0_0_MARK,
1753 };
1754 static const unsigned int sdhi0_data4_pins[] = {
1755 /* D[0:3] */
1756 302, 303, 304, 305,
1757 };
1758 static const unsigned int sdhi0_data4_mux[] = {
1759 SDHID0_0_MARK, SDHID0_1_MARK, SDHID0_2_MARK, SDHID0_3_MARK,
1760 };
1761 static const unsigned int sdhi0_ctrl_pins[] = {
1762 /* CLK, CMD */
1763 308, 306,
1764 };
1765 static const unsigned int sdhi0_ctrl_mux[] = {
1766 SDHICLK0_MARK, SDHICMD0_MARK,
1767 };
1768 static const unsigned int sdhi0_cd_pins[] = {
1769 /* CD */
1770 301,
1771 };
1772 static const unsigned int sdhi0_cd_mux[] = {
1773 SDHICD0_MARK,
1774 };
1775 static const unsigned int sdhi0_wp_pins[] = {
1776 /* WP */
1777 307,
1778 };
1779 static const unsigned int sdhi0_wp_mux[] = {
1780 SDHIWP0_MARK,
1781 };
1782 /* - SDHI1 ------------------------------------------------------------------ */
1783 static const unsigned int sdhi1_data1_pins[] = {
1784 /* D0 */
1785 289,
1786 };
1787 static const unsigned int sdhi1_data1_mux[] = {
1788 SDHID1_0_MARK,
1789 };
1790 static const unsigned int sdhi1_data4_pins[] = {
1791 /* D[0:3] */
1792 289, 290, 291, 292,
1793 };
1794 static const unsigned int sdhi1_data4_mux[] = {
1795 SDHID1_0_MARK, SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK,
1796 };
1797 static const unsigned int sdhi1_ctrl_pins[] = {
1798 /* CLK, CMD */
1799 293, 294,
1800 };
1801 static const unsigned int sdhi1_ctrl_mux[] = {
1802 SDHICLK1_MARK, SDHICMD1_MARK,
1803 };
1804 /* - SDHI2 ------------------------------------------------------------------ */
1805 static const unsigned int sdhi2_data1_pins[] = {
1806 /* D0 */
1807 295,
1808 };
1809 static const unsigned int sdhi2_data1_mux[] = {
1810 SDHID2_0_MARK,
1811 };
1812 static const unsigned int sdhi2_data4_pins[] = {
1813 /* D[0:3] */
1814 295, 296, 297, 298,
1815 };
1816 static const unsigned int sdhi2_data4_mux[] = {
1817 SDHID2_0_MARK, SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK,
1818 };
1819 static const unsigned int sdhi2_ctrl_pins[] = {
1820 /* CLK, CMD */
1821 299, 300,
1822 };
1823 static const unsigned int sdhi2_ctrl_mux[] = {
1824 SDHICLK2_MARK, SDHICMD2_MARK,
1825 };
1826
1827 static const struct sh_pfc_pin_group pinmux_groups[] = {
1828 SH_PFC_PIN_GROUP(irqc_irq0),
1829 SH_PFC_PIN_GROUP(irqc_irq1),
1830 SH_PFC_PIN_GROUP(irqc_irq2),
1831 SH_PFC_PIN_GROUP(irqc_irq3),
1832 SH_PFC_PIN_GROUP(irqc_irq4),
1833 SH_PFC_PIN_GROUP(irqc_irq5),
1834 SH_PFC_PIN_GROUP(irqc_irq6),
1835 SH_PFC_PIN_GROUP(irqc_irq7),
1836 SH_PFC_PIN_GROUP(irqc_irq8),
1837 SH_PFC_PIN_GROUP(irqc_irq9),
1838 SH_PFC_PIN_GROUP(irqc_irq10),
1839 SH_PFC_PIN_GROUP(irqc_irq11),
1840 SH_PFC_PIN_GROUP(irqc_irq12),
1841 SH_PFC_PIN_GROUP(irqc_irq13),
1842 SH_PFC_PIN_GROUP(irqc_irq14),
1843 SH_PFC_PIN_GROUP(irqc_irq15),
1844 SH_PFC_PIN_GROUP(irqc_irq16),
1845 SH_PFC_PIN_GROUP(irqc_irq17),
1846 SH_PFC_PIN_GROUP(irqc_irq18),
1847 SH_PFC_PIN_GROUP(irqc_irq19),
1848 SH_PFC_PIN_GROUP(irqc_irq20),
1849 SH_PFC_PIN_GROUP(irqc_irq21),
1850 SH_PFC_PIN_GROUP(irqc_irq22),
1851 SH_PFC_PIN_GROUP(irqc_irq23),
1852 SH_PFC_PIN_GROUP(irqc_irq24),
1853 SH_PFC_PIN_GROUP(irqc_irq25),
1854 SH_PFC_PIN_GROUP(irqc_irq26),
1855 SH_PFC_PIN_GROUP(irqc_irq27),
1856 SH_PFC_PIN_GROUP(irqc_irq28),
1857 SH_PFC_PIN_GROUP(irqc_irq29),
1858 SH_PFC_PIN_GROUP(irqc_irq30),
1859 SH_PFC_PIN_GROUP(irqc_irq31),
1860 SH_PFC_PIN_GROUP(irqc_irq32),
1861 SH_PFC_PIN_GROUP(irqc_irq33),
1862 SH_PFC_PIN_GROUP(irqc_irq34),
1863 SH_PFC_PIN_GROUP(irqc_irq35),
1864 SH_PFC_PIN_GROUP(irqc_irq36),
1865 SH_PFC_PIN_GROUP(irqc_irq37),
1866 SH_PFC_PIN_GROUP(irqc_irq38),
1867 SH_PFC_PIN_GROUP(irqc_irq39),
1868 SH_PFC_PIN_GROUP(irqc_irq40),
1869 SH_PFC_PIN_GROUP(irqc_irq41),
1870 SH_PFC_PIN_GROUP(irqc_irq42),
1871 SH_PFC_PIN_GROUP(irqc_irq43),
1872 SH_PFC_PIN_GROUP(irqc_irq44),
1873 SH_PFC_PIN_GROUP(irqc_irq45),
1874 SH_PFC_PIN_GROUP(irqc_irq46),
1875 SH_PFC_PIN_GROUP(irqc_irq47),
1876 SH_PFC_PIN_GROUP(irqc_irq48),
1877 SH_PFC_PIN_GROUP(irqc_irq49),
1878 SH_PFC_PIN_GROUP(irqc_irq50),
1879 SH_PFC_PIN_GROUP(irqc_irq51),
1880 SH_PFC_PIN_GROUP(irqc_irq52),
1881 SH_PFC_PIN_GROUP(irqc_irq53),
1882 SH_PFC_PIN_GROUP(irqc_irq54),
1883 SH_PFC_PIN_GROUP(irqc_irq55),
1884 SH_PFC_PIN_GROUP(irqc_irq56),
1885 SH_PFC_PIN_GROUP(irqc_irq57),
1886 SH_PFC_PIN_GROUP(mmc0_data1),
1887 SH_PFC_PIN_GROUP(mmc0_data4),
1888 SH_PFC_PIN_GROUP(mmc0_data8),
1889 SH_PFC_PIN_GROUP(mmc0_ctrl),
1890 SH_PFC_PIN_GROUP(mmc1_data1),
1891 SH_PFC_PIN_GROUP(mmc1_data4),
1892 SH_PFC_PIN_GROUP(mmc1_data8),
1893 SH_PFC_PIN_GROUP(mmc1_ctrl),
1894 SH_PFC_PIN_GROUP(scifa0_data),
1895 SH_PFC_PIN_GROUP(scifa0_clk),
1896 SH_PFC_PIN_GROUP(scifa0_ctrl),
1897 SH_PFC_PIN_GROUP(scifa1_data),
1898 SH_PFC_PIN_GROUP(scifa1_clk),
1899 SH_PFC_PIN_GROUP(scifa1_ctrl),
1900 SH_PFC_PIN_GROUP(scifb0_data),
1901 SH_PFC_PIN_GROUP(scifb0_clk),
1902 SH_PFC_PIN_GROUP(scifb0_ctrl),
1903 SH_PFC_PIN_GROUP(scifb1_data),
1904 SH_PFC_PIN_GROUP(scifb1_clk),
1905 SH_PFC_PIN_GROUP(scifb1_ctrl),
1906 SH_PFC_PIN_GROUP(scifb1_data_b),
1907 SH_PFC_PIN_GROUP(scifb1_clk_b),
1908 SH_PFC_PIN_GROUP(scifb1_ctrl_b),
1909 SH_PFC_PIN_GROUP(scifb2_data),
1910 SH_PFC_PIN_GROUP(scifb2_clk),
1911 SH_PFC_PIN_GROUP(scifb2_ctrl),
1912 SH_PFC_PIN_GROUP(scifb2_data_b),
1913 SH_PFC_PIN_GROUP(scifb2_clk_b),
1914 SH_PFC_PIN_GROUP(scifb2_ctrl_b),
1915 SH_PFC_PIN_GROUP(scifb3_data),
1916 SH_PFC_PIN_GROUP(scifb3_clk),
1917 SH_PFC_PIN_GROUP(scifb3_ctrl),
1918 SH_PFC_PIN_GROUP(scifb3_data_b),
1919 SH_PFC_PIN_GROUP(scifb3_clk_b),
1920 SH_PFC_PIN_GROUP(scifb3_ctrl_b),
1921 SH_PFC_PIN_GROUP(sdhi0_data1),
1922 SH_PFC_PIN_GROUP(sdhi0_data4),
1923 SH_PFC_PIN_GROUP(sdhi0_ctrl),
1924 SH_PFC_PIN_GROUP(sdhi0_cd),
1925 SH_PFC_PIN_GROUP(sdhi0_wp),
1926 SH_PFC_PIN_GROUP(sdhi1_data1),
1927 SH_PFC_PIN_GROUP(sdhi1_data4),
1928 SH_PFC_PIN_GROUP(sdhi1_ctrl),
1929 SH_PFC_PIN_GROUP(sdhi2_data1),
1930 SH_PFC_PIN_GROUP(sdhi2_data4),
1931 SH_PFC_PIN_GROUP(sdhi2_ctrl),
1932 };
1933
1934 static const char * const irqc_groups[] = {
1935 "irqc_irq0",
1936 "irqc_irq1",
1937 "irqc_irq2",
1938 "irqc_irq3",
1939 "irqc_irq4",
1940 "irqc_irq5",
1941 "irqc_irq6",
1942 "irqc_irq7",
1943 "irqc_irq8",
1944 "irqc_irq9",
1945 "irqc_irq10",
1946 "irqc_irq11",
1947 "irqc_irq12",
1948 "irqc_irq13",
1949 "irqc_irq14",
1950 "irqc_irq15",
1951 "irqc_irq16",
1952 "irqc_irq17",
1953 "irqc_irq18",
1954 "irqc_irq19",
1955 "irqc_irq20",
1956 "irqc_irq21",
1957 "irqc_irq22",
1958 "irqc_irq23",
1959 "irqc_irq24",
1960 "irqc_irq25",
1961 "irqc_irq26",
1962 "irqc_irq27",
1963 "irqc_irq28",
1964 "irqc_irq29",
1965 "irqc_irq30",
1966 "irqc_irq31",
1967 "irqc_irq32",
1968 "irqc_irq33",
1969 "irqc_irq34",
1970 "irqc_irq35",
1971 "irqc_irq36",
1972 "irqc_irq37",
1973 "irqc_irq38",
1974 "irqc_irq39",
1975 "irqc_irq40",
1976 "irqc_irq41",
1977 "irqc_irq42",
1978 "irqc_irq43",
1979 "irqc_irq44",
1980 "irqc_irq45",
1981 "irqc_irq46",
1982 "irqc_irq47",
1983 "irqc_irq48",
1984 "irqc_irq49",
1985 "irqc_irq50",
1986 "irqc_irq51",
1987 "irqc_irq52",
1988 "irqc_irq53",
1989 "irqc_irq54",
1990 "irqc_irq55",
1991 "irqc_irq56",
1992 "irqc_irq57",
1993 };
1994
1995 static const char * const mmc0_groups[] = {
1996 "mmc0_data1",
1997 "mmc0_data4",
1998 "mmc0_data8",
1999 "mmc0_ctrl",
2000 };
2001
2002 static const char * const mmc1_groups[] = {
2003 "mmc1_data1",
2004 "mmc1_data4",
2005 "mmc1_data8",
2006 "mmc1_ctrl",
2007 };
2008
2009 static const char * const scifa0_groups[] = {
2010 "scifa0_data",
2011 "scifa0_clk",
2012 "scifa0_ctrl",
2013 };
2014
2015 static const char * const scifa1_groups[] = {
2016 "scifa1_data",
2017 "scifa1_clk",
2018 "scifa1_ctrl",
2019 };
2020
2021 static const char * const scifb0_groups[] = {
2022 "scifb0_data",
2023 "scifb0_clk",
2024 "scifb0_ctrl",
2025 };
2026
2027 static const char * const scifb1_groups[] = {
2028 "scifb1_data",
2029 "scifb1_clk",
2030 "scifb1_ctrl",
2031 "scifb1_data_b",
2032 "scifb1_clk_b",
2033 "scifb1_ctrl_b",
2034 };
2035
2036 static const char * const scifb2_groups[] = {
2037 "scifb2_data",
2038 "scifb2_clk",
2039 "scifb2_ctrl",
2040 "scifb2_data_b",
2041 "scifb2_clk_b",
2042 "scifb2_ctrl_b",
2043 };
2044
2045 static const char * const scifb3_groups[] = {
2046 "scifb3_data",
2047 "scifb3_clk",
2048 "scifb3_ctrl",
2049 "scifb3_data_b",
2050 "scifb3_clk_b",
2051 "scifb3_ctrl_b",
2052 };
2053
2054 static const char * const sdhi0_groups[] = {
2055 "sdhi0_data1",
2056 "sdhi0_data4",
2057 "sdhi0_ctrl",
2058 "sdhi0_cd",
2059 "sdhi0_wp",
2060 };
2061
2062 static const char * const sdhi1_groups[] = {
2063 "sdhi1_data1",
2064 "sdhi1_data4",
2065 "sdhi1_ctrl",
2066 };
2067
2068 static const char * const sdhi2_groups[] = {
2069 "sdhi2_data1",
2070 "sdhi2_data4",
2071 "sdhi2_ctrl",
2072 };
2073
2074 static const struct sh_pfc_function pinmux_functions[] = {
2075 SH_PFC_FUNCTION(irqc),
2076 SH_PFC_FUNCTION(mmc0),
2077 SH_PFC_FUNCTION(mmc1),
2078 SH_PFC_FUNCTION(scifa0),
2079 SH_PFC_FUNCTION(scifa1),
2080 SH_PFC_FUNCTION(scifb0),
2081 SH_PFC_FUNCTION(scifb1),
2082 SH_PFC_FUNCTION(scifb2),
2083 SH_PFC_FUNCTION(scifb3),
2084 SH_PFC_FUNCTION(sdhi0),
2085 SH_PFC_FUNCTION(sdhi1),
2086 SH_PFC_FUNCTION(sdhi2),
2087 };
2088
2089 #undef PORTCR
2090 #define PORTCR(nr, reg) \
2091 { \
2092 PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \
2093 _PCRH(PORT##nr##_IN, 0, 0, PORT##nr##_OUT), \
2094 PORT##nr##_FN0, PORT##nr##_FN1, \
2095 PORT##nr##_FN2, PORT##nr##_FN3, \
2096 PORT##nr##_FN4, PORT##nr##_FN5, \
2097 PORT##nr##_FN6, PORT##nr##_FN7 } \
2098 }
2099
2100 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2101 PORTCR(0, 0xe6050000),
2102 PORTCR(1, 0xe6050001),
2103 PORTCR(2, 0xe6050002),
2104 PORTCR(3, 0xe6050003),
2105 PORTCR(4, 0xe6050004),
2106 PORTCR(5, 0xe6050005),
2107 PORTCR(6, 0xe6050006),
2108 PORTCR(7, 0xe6050007),
2109 PORTCR(8, 0xe6050008),
2110 PORTCR(9, 0xe6050009),
2111 PORTCR(10, 0xe605000A),
2112 PORTCR(11, 0xe605000B),
2113 PORTCR(12, 0xe605000C),
2114 PORTCR(13, 0xe605000D),
2115 PORTCR(14, 0xe605000E),
2116 PORTCR(15, 0xe605000F),
2117 PORTCR(16, 0xe6050010),
2118 PORTCR(17, 0xe6050011),
2119 PORTCR(18, 0xe6050012),
2120 PORTCR(19, 0xe6050013),
2121 PORTCR(20, 0xe6050014),
2122 PORTCR(21, 0xe6050015),
2123 PORTCR(22, 0xe6050016),
2124 PORTCR(23, 0xe6050017),
2125 PORTCR(24, 0xe6050018),
2126 PORTCR(25, 0xe6050019),
2127 PORTCR(26, 0xe605001A),
2128 PORTCR(27, 0xe605001B),
2129 PORTCR(28, 0xe605001C),
2130 PORTCR(29, 0xe605001D),
2131 PORTCR(30, 0xe605001E),
2132 PORTCR(32, 0xe6051020),
2133 PORTCR(33, 0xe6051021),
2134 PORTCR(34, 0xe6051022),
2135 PORTCR(35, 0xe6051023),
2136 PORTCR(36, 0xe6051024),
2137 PORTCR(37, 0xe6051025),
2138 PORTCR(38, 0xe6051026),
2139 PORTCR(39, 0xe6051027),
2140 PORTCR(40, 0xe6051028),
2141 PORTCR(64, 0xe6050040),
2142 PORTCR(65, 0xe6050041),
2143 PORTCR(66, 0xe6050042),
2144 PORTCR(67, 0xe6050043),
2145 PORTCR(68, 0xe6050044),
2146 PORTCR(69, 0xe6050045),
2147 PORTCR(70, 0xe6050046),
2148 PORTCR(71, 0xe6050047),
2149 PORTCR(72, 0xe6050048),
2150 PORTCR(73, 0xe6050049),
2151 PORTCR(74, 0xe605004A),
2152 PORTCR(75, 0xe605004B),
2153 PORTCR(76, 0xe605004C),
2154 PORTCR(77, 0xe605004D),
2155 PORTCR(78, 0xe605004E),
2156 PORTCR(79, 0xe605004F),
2157 PORTCR(80, 0xe6050050),
2158 PORTCR(81, 0xe6050051),
2159 PORTCR(82, 0xe6050052),
2160 PORTCR(83, 0xe6050053),
2161 PORTCR(84, 0xe6050054),
2162 PORTCR(85, 0xe6050055),
2163 PORTCR(96, 0xe6051060),
2164 PORTCR(97, 0xe6051061),
2165 PORTCR(98, 0xe6051062),
2166 PORTCR(99, 0xe6051063),
2167 PORTCR(100, 0xe6051064),
2168 PORTCR(101, 0xe6051065),
2169 PORTCR(102, 0xe6051066),
2170 PORTCR(103, 0xe6051067),
2171 PORTCR(104, 0xe6051068),
2172 PORTCR(105, 0xe6051069),
2173 PORTCR(106, 0xe605106A),
2174 PORTCR(107, 0xe605106B),
2175 PORTCR(108, 0xe605106C),
2176 PORTCR(109, 0xe605106D),
2177 PORTCR(110, 0xe605106E),
2178 PORTCR(111, 0xe605106F),
2179 PORTCR(112, 0xe6051070),
2180 PORTCR(113, 0xe6051071),
2181 PORTCR(114, 0xe6051072),
2182 PORTCR(115, 0xe6051073),
2183 PORTCR(116, 0xe6051074),
2184 PORTCR(117, 0xe6051075),
2185 PORTCR(118, 0xe6051076),
2186 PORTCR(119, 0xe6051077),
2187 PORTCR(120, 0xe6051078),
2188 PORTCR(121, 0xe6051079),
2189 PORTCR(122, 0xe605107A),
2190 PORTCR(123, 0xe605107B),
2191 PORTCR(124, 0xe605107C),
2192 PORTCR(125, 0xe605107D),
2193 PORTCR(126, 0xe605107E),
2194 PORTCR(128, 0xe6051080),
2195 PORTCR(129, 0xe6051081),
2196 PORTCR(130, 0xe6051082),
2197 PORTCR(131, 0xe6051083),
2198 PORTCR(132, 0xe6051084),
2199 PORTCR(133, 0xe6051085),
2200 PORTCR(134, 0xe6051086),
2201 PORTCR(160, 0xe60520A0),
2202 PORTCR(161, 0xe60520A1),
2203 PORTCR(162, 0xe60520A2),
2204 PORTCR(163, 0xe60520A3),
2205 PORTCR(164, 0xe60520A4),
2206 PORTCR(165, 0xe60520A5),
2207 PORTCR(166, 0xe60520A6),
2208 PORTCR(167, 0xe60520A7),
2209 PORTCR(168, 0xe60520A8),
2210 PORTCR(169, 0xe60520A9),
2211 PORTCR(170, 0xe60520AA),
2212 PORTCR(171, 0xe60520AB),
2213 PORTCR(172, 0xe60520AC),
2214 PORTCR(173, 0xe60520AD),
2215 PORTCR(174, 0xe60520AE),
2216 PORTCR(175, 0xe60520AF),
2217 PORTCR(176, 0xe60520B0),
2218 PORTCR(177, 0xe60520B1),
2219 PORTCR(178, 0xe60520B2),
2220 PORTCR(192, 0xe60520C0),
2221 PORTCR(193, 0xe60520C1),
2222 PORTCR(194, 0xe60520C2),
2223 PORTCR(195, 0xe60520C3),
2224 PORTCR(196, 0xe60520C4),
2225 PORTCR(197, 0xe60520C5),
2226 PORTCR(198, 0xe60520C6),
2227 PORTCR(199, 0xe60520C7),
2228 PORTCR(200, 0xe60520C8),
2229 PORTCR(201, 0xe60520C9),
2230 PORTCR(202, 0xe60520CA),
2231 PORTCR(203, 0xe60520CB),
2232 PORTCR(204, 0xe60520CC),
2233 PORTCR(205, 0xe60520CD),
2234 PORTCR(206, 0xe60520CE),
2235 PORTCR(207, 0xe60520CF),
2236 PORTCR(208, 0xe60520D0),
2237 PORTCR(209, 0xe60520D1),
2238 PORTCR(210, 0xe60520D2),
2239 PORTCR(211, 0xe60520D3),
2240 PORTCR(212, 0xe60520D4),
2241 PORTCR(213, 0xe60520D5),
2242 PORTCR(214, 0xe60520D6),
2243 PORTCR(215, 0xe60520D7),
2244 PORTCR(216, 0xe60520D8),
2245 PORTCR(217, 0xe60520D9),
2246 PORTCR(218, 0xe60520DA),
2247 PORTCR(219, 0xe60520DB),
2248 PORTCR(220, 0xe60520DC),
2249 PORTCR(221, 0xe60520DD),
2250 PORTCR(222, 0xe60520DE),
2251 PORTCR(224, 0xe60520E0),
2252 PORTCR(225, 0xe60520E1),
2253 PORTCR(226, 0xe60520E2),
2254 PORTCR(227, 0xe60520E3),
2255 PORTCR(228, 0xe60520E4),
2256 PORTCR(229, 0xe60520E5),
2257 PORTCR(230, 0xe60520e6),
2258 PORTCR(231, 0xe60520E7),
2259 PORTCR(232, 0xe60520E8),
2260 PORTCR(233, 0xe60520E9),
2261 PORTCR(234, 0xe60520EA),
2262 PORTCR(235, 0xe60520EB),
2263 PORTCR(236, 0xe60520EC),
2264 PORTCR(237, 0xe60520ED),
2265 PORTCR(238, 0xe60520EE),
2266 PORTCR(239, 0xe60520EF),
2267 PORTCR(240, 0xe60520F0),
2268 PORTCR(241, 0xe60520F1),
2269 PORTCR(242, 0xe60520F2),
2270 PORTCR(243, 0xe60520F3),
2271 PORTCR(244, 0xe60520F4),
2272 PORTCR(245, 0xe60520F5),
2273 PORTCR(246, 0xe60520F6),
2274 PORTCR(247, 0xe60520F7),
2275 PORTCR(248, 0xe60520F8),
2276 PORTCR(249, 0xe60520F9),
2277 PORTCR(250, 0xe60520FA),
2278 PORTCR(256, 0xe6052100),
2279 PORTCR(257, 0xe6052101),
2280 PORTCR(258, 0xe6052102),
2281 PORTCR(259, 0xe6052103),
2282 PORTCR(260, 0xe6052104),
2283 PORTCR(261, 0xe6052105),
2284 PORTCR(262, 0xe6052106),
2285 PORTCR(263, 0xe6052107),
2286 PORTCR(264, 0xe6052108),
2287 PORTCR(265, 0xe6052109),
2288 PORTCR(266, 0xe605210A),
2289 PORTCR(267, 0xe605210B),
2290 PORTCR(268, 0xe605210C),
2291 PORTCR(269, 0xe605210D),
2292 PORTCR(270, 0xe605210E),
2293 PORTCR(271, 0xe605210F),
2294 PORTCR(272, 0xe6052110),
2295 PORTCR(273, 0xe6052111),
2296 PORTCR(274, 0xe6052112),
2297 PORTCR(275, 0xe6052113),
2298 PORTCR(276, 0xe6052114),
2299 PORTCR(277, 0xe6052115),
2300 PORTCR(278, 0xe6052116),
2301 PORTCR(279, 0xe6052117),
2302 PORTCR(280, 0xe6052118),
2303 PORTCR(281, 0xe6052119),
2304 PORTCR(282, 0xe605211A),
2305 PORTCR(283, 0xe605211B),
2306 PORTCR(288, 0xe6053120),
2307 PORTCR(289, 0xe6053121),
2308 PORTCR(290, 0xe6053122),
2309 PORTCR(291, 0xe6053123),
2310 PORTCR(292, 0xe6053124),
2311 PORTCR(293, 0xe6053125),
2312 PORTCR(294, 0xe6053126),
2313 PORTCR(295, 0xe6053127),
2314 PORTCR(296, 0xe6053128),
2315 PORTCR(297, 0xe6053129),
2316 PORTCR(298, 0xe605312A),
2317 PORTCR(299, 0xe605312B),
2318 PORTCR(300, 0xe605312C),
2319 PORTCR(301, 0xe605312D),
2320 PORTCR(302, 0xe605312E),
2321 PORTCR(303, 0xe605312F),
2322 PORTCR(304, 0xe6053130),
2323 PORTCR(305, 0xe6053131),
2324 PORTCR(306, 0xe6053132),
2325 PORTCR(307, 0xe6053133),
2326 PORTCR(308, 0xe6053134),
2327 PORTCR(320, 0xe6053140),
2328 PORTCR(321, 0xe6053141),
2329 PORTCR(322, 0xe6053142),
2330 PORTCR(323, 0xe6053143),
2331 PORTCR(324, 0xe6053144),
2332 PORTCR(325, 0xe6053145),
2333 PORTCR(326, 0xe6053146),
2334 PORTCR(327, 0xe6053147),
2335 PORTCR(328, 0xe6053148),
2336 PORTCR(329, 0xe6053149),
2337
2338 { PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1) {
2339 MSEL1CR_31_0, MSEL1CR_31_1,
2340 0, 0,
2341 0, 0,
2342 0, 0,
2343 MSEL1CR_27_0, MSEL1CR_27_1,
2344 0, 0,
2345 MSEL1CR_25_0, MSEL1CR_25_1,
2346 MSEL1CR_24_0, MSEL1CR_24_1,
2347 0, 0,
2348 MSEL1CR_22_0, MSEL1CR_22_1,
2349 MSEL1CR_21_0, MSEL1CR_21_1,
2350 MSEL1CR_20_0, MSEL1CR_20_1,
2351 MSEL1CR_19_0, MSEL1CR_19_1,
2352 MSEL1CR_18_0, MSEL1CR_18_1,
2353 MSEL1CR_17_0, MSEL1CR_17_1,
2354 MSEL1CR_16_0, MSEL1CR_16_1,
2355 MSEL1CR_15_0, MSEL1CR_15_1,
2356 MSEL1CR_14_0, MSEL1CR_14_1,
2357 MSEL1CR_13_0, MSEL1CR_13_1,
2358 MSEL1CR_12_0, MSEL1CR_12_1,
2359 MSEL1CR_11_0, MSEL1CR_11_1,
2360 MSEL1CR_10_0, MSEL1CR_10_1,
2361 MSEL1CR_09_0, MSEL1CR_09_1,
2362 MSEL1CR_08_0, MSEL1CR_08_1,
2363 MSEL1CR_07_0, MSEL1CR_07_1,
2364 MSEL1CR_06_0, MSEL1CR_06_1,
2365 MSEL1CR_05_0, MSEL1CR_05_1,
2366 MSEL1CR_04_0, MSEL1CR_04_1,
2367 MSEL1CR_03_0, MSEL1CR_03_1,
2368 MSEL1CR_02_0, MSEL1CR_02_1,
2369 MSEL1CR_01_0, MSEL1CR_01_1,
2370 MSEL1CR_00_0, MSEL1CR_00_1,
2371 }
2372 },
2373 { PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1) {
2374 MSEL3CR_31_0, MSEL3CR_31_1,
2375 0, 0,
2376 0, 0,
2377 MSEL3CR_28_0, MSEL3CR_28_1,
2378 MSEL3CR_27_0, MSEL3CR_27_1,
2379 MSEL3CR_26_0, MSEL3CR_26_1,
2380 0, 0,
2381 0, 0,
2382 MSEL3CR_23_0, MSEL3CR_23_1,
2383 MSEL3CR_22_0, MSEL3CR_22_1,
2384 MSEL3CR_21_0, MSEL3CR_21_1,
2385 MSEL3CR_20_0, MSEL3CR_20_1,
2386 MSEL3CR_19_0, MSEL3CR_19_1,
2387 MSEL3CR_18_0, MSEL3CR_18_1,
2388 MSEL3CR_17_0, MSEL3CR_17_1,
2389 MSEL3CR_16_0, MSEL3CR_16_1,
2390 MSEL3CR_15_0, MSEL3CR_15_1,
2391 0, 0,
2392 0, 0,
2393 MSEL3CR_12_0, MSEL3CR_12_1,
2394 MSEL3CR_11_0, MSEL3CR_11_1,
2395 MSEL3CR_10_0, MSEL3CR_10_1,
2396 MSEL3CR_09_0, MSEL3CR_09_1,
2397 0, 0,
2398 0, 0,
2399 MSEL3CR_06_0, MSEL3CR_06_1,
2400 0, 0,
2401 0, 0,
2402 MSEL3CR_03_0, MSEL3CR_03_1,
2403 0, 0,
2404 MSEL3CR_01_0, MSEL3CR_01_1,
2405 MSEL3CR_00_0, MSEL3CR_00_1,
2406 }
2407 },
2408 { PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1) {
2409 0, 0,
2410 MSEL4CR_30_0, MSEL4CR_30_1,
2411 MSEL4CR_29_0, MSEL4CR_29_1,
2412 MSEL4CR_28_0, MSEL4CR_28_1,
2413 MSEL4CR_27_0, MSEL4CR_27_1,
2414 MSEL4CR_26_0, MSEL4CR_26_1,
2415 MSEL4CR_25_0, MSEL4CR_25_1,
2416 MSEL4CR_24_0, MSEL4CR_24_1,
2417 MSEL4CR_23_0, MSEL4CR_23_1,
2418 MSEL4CR_22_0, MSEL4CR_22_1,
2419 MSEL4CR_21_0, MSEL4CR_21_1,
2420 MSEL4CR_20_0, MSEL4CR_20_1,
2421 MSEL4CR_19_0, MSEL4CR_19_1,
2422 MSEL4CR_18_0, MSEL4CR_18_1,
2423 MSEL4CR_17_0, MSEL4CR_17_1,
2424 MSEL4CR_16_0, MSEL4CR_16_1,
2425 MSEL4CR_15_0, MSEL4CR_15_1,
2426 MSEL4CR_14_0, MSEL4CR_14_1,
2427 MSEL4CR_13_0, MSEL4CR_13_1,
2428 MSEL4CR_12_0, MSEL4CR_12_1,
2429 MSEL4CR_11_0, MSEL4CR_11_1,
2430 MSEL4CR_10_0, MSEL4CR_10_1,
2431 MSEL4CR_09_0, MSEL4CR_09_1,
2432 0, 0,
2433 MSEL4CR_07_0, MSEL4CR_07_1,
2434 0, 0,
2435 0, 0,
2436 MSEL4CR_04_0, MSEL4CR_04_1,
2437 0, 0,
2438 0, 0,
2439 MSEL4CR_01_0, MSEL4CR_01_1,
2440 0, 0,
2441 }
2442 },
2443 { PINMUX_CFG_REG("MSEL5CR", 0xe6058028, 32, 1) {
2444 MSEL5CR_31_0, MSEL5CR_31_1,
2445 MSEL5CR_30_0, MSEL5CR_30_1,
2446 MSEL5CR_29_0, MSEL5CR_29_1,
2447 MSEL5CR_28_0, MSEL5CR_28_1,
2448 MSEL5CR_27_0, MSEL5CR_27_1,
2449 MSEL5CR_26_0, MSEL5CR_26_1,
2450 MSEL5CR_25_0, MSEL5CR_25_1,
2451 MSEL5CR_24_0, MSEL5CR_24_1,
2452 MSEL5CR_23_0, MSEL5CR_23_1,
2453 MSEL5CR_22_0, MSEL5CR_22_1,
2454 MSEL5CR_21_0, MSEL5CR_21_1,
2455 MSEL5CR_20_0, MSEL5CR_20_1,
2456 MSEL5CR_19_0, MSEL5CR_19_1,
2457 MSEL5CR_18_0, MSEL5CR_18_1,
2458 MSEL5CR_17_0, MSEL5CR_17_1,
2459 MSEL5CR_16_0, MSEL5CR_16_1,
2460 MSEL5CR_15_0, MSEL5CR_15_1,
2461 MSEL5CR_14_0, MSEL5CR_14_1,
2462 MSEL5CR_13_0, MSEL5CR_13_1,
2463 MSEL5CR_12_0, MSEL5CR_12_1,
2464 MSEL5CR_11_0, MSEL5CR_11_1,
2465 MSEL5CR_10_0, MSEL5CR_10_1,
2466 MSEL5CR_09_0, MSEL5CR_09_1,
2467 MSEL5CR_08_0, MSEL5CR_08_1,
2468 MSEL5CR_07_0, MSEL5CR_07_1,
2469 MSEL5CR_06_0, MSEL5CR_06_1,
2470 0, 0,
2471 0, 0,
2472 0, 0,
2473 0, 0,
2474 0, 0,
2475 0, 0,
2476 }
2477 },
2478 { PINMUX_CFG_REG("MSEL8CR", 0xe6058034, 32, 1) {
2479 0, 0,
2480 0, 0,
2481 0, 0,
2482 0, 0,
2483 0, 0,
2484 0, 0,
2485 0, 0,
2486 0, 0,
2487 0, 0,
2488 0, 0,
2489 0, 0,
2490 0, 0,
2491 0, 0,
2492 0, 0,
2493 0, 0,
2494 MSEL8CR_16_0, MSEL8CR_16_1,
2495 0, 0,
2496 0, 0,
2497 0, 0,
2498 0, 0,
2499 0, 0,
2500 0, 0,
2501 0, 0,
2502 0, 0,
2503 0, 0,
2504 0, 0,
2505 0, 0,
2506 0, 0,
2507 0, 0,
2508 0, 0,
2509 MSEL8CR_01_0, MSEL8CR_01_1,
2510 MSEL8CR_00_0, MSEL8CR_00_1,
2511 }
2512 },
2513 { },
2514 };
2515
2516 static const struct pinmux_data_reg pinmux_data_regs[] = {
2517
2518 { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) {
2519 0, PORT30_DATA, PORT29_DATA, PORT28_DATA,
2520 PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
2521 PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
2522 PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
2523 PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
2524 PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
2525 PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
2526 PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA,
2527 }
2528 },
2529 { PINMUX_DATA_REG("PORTD063_032DR", 0xe6055000, 32) {
2530 0, 0, 0, 0,
2531 0, 0, 0, 0,
2532 0, 0, 0, 0,
2533 0, 0, 0, 0,
2534 0, 0, 0, 0,
2535 0, 0, 0, PORT40_DATA,
2536 PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
2537 PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA,
2538 }
2539 },
2540 { PINMUX_DATA_REG("PORTL095_064DR", 0xe6054004, 32) {
2541 0, 0, 0, 0,
2542 0, 0, 0, 0,
2543 0, 0, PORT85_DATA, PORT84_DATA,
2544 PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
2545 PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
2546 PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
2547 PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
2548 PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA,
2549 }
2550 },
2551 { PINMUX_DATA_REG("PORTD127_096DR", 0xe6055004, 32) {
2552 0, PORT126_DATA, PORT125_DATA, PORT124_DATA,
2553 PORT123_DATA, PORT122_DATA, PORT121_DATA, PORT120_DATA,
2554 PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA,
2555 PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA,
2556 PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
2557 PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
2558 PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
2559 PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA,
2560 }
2561 },
2562 { PINMUX_DATA_REG("PORTD159_128DR", 0xe6055008, 32) {
2563 0, 0, 0, 0,
2564 0, 0, 0, 0,
2565 0, 0, 0, 0,
2566 0, 0, 0, 0,
2567 0, 0, 0, 0,
2568 0, 0, 0, 0,
2569 0, PORT134_DATA, PORT133_DATA, PORT132_DATA,
2570 PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA,
2571 }
2572 },
2573 { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056000, 32) {
2574 0, 0, 0, 0,
2575 0, 0, 0, 0,
2576 0, 0, 0, 0,
2577 0, PORT178_DATA, PORT177_DATA, PORT176_DATA,
2578 PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA,
2579 PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA,
2580 PORT167_DATA, PORT166_DATA, PORT165_DATA, PORT164_DATA,
2581 PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA,
2582 }
2583 },
2584 { PINMUX_DATA_REG("PORTR223_192DR", 0xe6056004, 32) {
2585 0, PORT222_DATA, PORT221_DATA, PORT220_DATA,
2586 PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA,
2587 PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA,
2588 PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA,
2589 PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
2590 PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
2591 PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
2592 PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA,
2593 }
2594 },
2595 { PINMUX_DATA_REG("PORTR255_224DR", 0xe6056008, 32) {
2596 0, 0, 0, 0,
2597 0, PORT250_DATA, PORT249_DATA, PORT248_DATA,
2598 PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA,
2599 PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA,
2600 PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA,
2601 PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA,
2602 PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA,
2603 PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA,
2604 }
2605 },
2606 { PINMUX_DATA_REG("PORTR287_256DR", 0xe605600C, 32) {
2607 0, 0, 0, 0,
2608 PORT283_DATA, PORT282_DATA, PORT281_DATA, PORT280_DATA,
2609 PORT279_DATA, PORT278_DATA, PORT277_DATA, PORT276_DATA,
2610 PORT275_DATA, PORT274_DATA, PORT273_DATA, PORT272_DATA,
2611 PORT271_DATA, PORT270_DATA, PORT269_DATA, PORT268_DATA,
2612 PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA,
2613 PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA,
2614 PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA,
2615 }
2616 },
2617 { PINMUX_DATA_REG("PORTU319_288DR", 0xe6057000, 32) {
2618 0, 0, 0, 0,
2619 0, 0, 0, 0,
2620 0, 0, 0, PORT308_DATA,
2621 PORT307_DATA, PORT306_DATA, PORT305_DATA, PORT304_DATA,
2622 PORT303_DATA, PORT302_DATA, PORT301_DATA, PORT300_DATA,
2623 PORT299_DATA, PORT298_DATA, PORT297_DATA, PORT296_DATA,
2624 PORT295_DATA, PORT294_DATA, PORT293_DATA, PORT292_DATA,
2625 PORT291_DATA, PORT290_DATA, PORT289_DATA, PORT288_DATA,
2626 }
2627 },
2628 { PINMUX_DATA_REG("PORTU351_320DR", 0xe6057004, 32) {
2629 0, 0, 0, 0,
2630 0, 0, 0, 0,
2631 0, 0, 0, 0,
2632 0, 0, 0, 0,
2633 0, 0, 0, 0,
2634 0, 0, PORT329_DATA, PORT328_DATA,
2635 PORT327_DATA, PORT326_DATA, PORT325_DATA, PORT324_DATA,
2636 PORT323_DATA, PORT322_DATA, PORT321_DATA, PORT320_DATA,
2637 }
2638 },
2639 { },
2640 };
2641
2642 static const struct pinmux_irq pinmux_irqs[] = {
2643 PINMUX_IRQ(irq_pin(0), 0),
2644 PINMUX_IRQ(irq_pin(1), 1),
2645 PINMUX_IRQ(irq_pin(2), 2),
2646 PINMUX_IRQ(irq_pin(3), 3),
2647 PINMUX_IRQ(irq_pin(4), 4),
2648 PINMUX_IRQ(irq_pin(5), 5),
2649 PINMUX_IRQ(irq_pin(6), 6),
2650 PINMUX_IRQ(irq_pin(7), 7),
2651 PINMUX_IRQ(irq_pin(8), 8),
2652 PINMUX_IRQ(irq_pin(9), 9),
2653 PINMUX_IRQ(irq_pin(10), 10),
2654 PINMUX_IRQ(irq_pin(11), 11),
2655 PINMUX_IRQ(irq_pin(12), 12),
2656 PINMUX_IRQ(irq_pin(13), 13),
2657 PINMUX_IRQ(irq_pin(14), 14),
2658 PINMUX_IRQ(irq_pin(15), 15),
2659 PINMUX_IRQ(irq_pin(16), 320),
2660 PINMUX_IRQ(irq_pin(17), 321),
2661 PINMUX_IRQ(irq_pin(18), 85),
2662 PINMUX_IRQ(irq_pin(19), 84),
2663 PINMUX_IRQ(irq_pin(20), 160),
2664 PINMUX_IRQ(irq_pin(21), 161),
2665 PINMUX_IRQ(irq_pin(22), 162),
2666 PINMUX_IRQ(irq_pin(23), 163),
2667 PINMUX_IRQ(irq_pin(24), 175),
2668 PINMUX_IRQ(irq_pin(25), 176),
2669 PINMUX_IRQ(irq_pin(26), 177),
2670 PINMUX_IRQ(irq_pin(27), 178),
2671 PINMUX_IRQ(irq_pin(28), 322),
2672 PINMUX_IRQ(irq_pin(29), 323),
2673 PINMUX_IRQ(irq_pin(30), 324),
2674 PINMUX_IRQ(irq_pin(31), 192),
2675 PINMUX_IRQ(irq_pin(32), 193),
2676 PINMUX_IRQ(irq_pin(33), 194),
2677 PINMUX_IRQ(irq_pin(34), 195),
2678 PINMUX_IRQ(irq_pin(35), 196),
2679 PINMUX_IRQ(irq_pin(36), 197),
2680 PINMUX_IRQ(irq_pin(37), 198),
2681 PINMUX_IRQ(irq_pin(38), 199),
2682 PINMUX_IRQ(irq_pin(39), 200),
2683 PINMUX_IRQ(irq_pin(40), 66),
2684 PINMUX_IRQ(irq_pin(41), 102),
2685 PINMUX_IRQ(irq_pin(42), 103),
2686 PINMUX_IRQ(irq_pin(43), 109),
2687 PINMUX_IRQ(irq_pin(44), 110),
2688 PINMUX_IRQ(irq_pin(45), 111),
2689 PINMUX_IRQ(irq_pin(46), 112),
2690 PINMUX_IRQ(irq_pin(47), 113),
2691 PINMUX_IRQ(irq_pin(48), 114),
2692 PINMUX_IRQ(irq_pin(49), 115),
2693 PINMUX_IRQ(irq_pin(50), 301),
2694 PINMUX_IRQ(irq_pin(51), 290),
2695 PINMUX_IRQ(irq_pin(52), 296),
2696 PINMUX_IRQ(irq_pin(53), 325),
2697 PINMUX_IRQ(irq_pin(54), 326),
2698 PINMUX_IRQ(irq_pin(55), 327),
2699 PINMUX_IRQ(irq_pin(56), 328),
2700 PINMUX_IRQ(irq_pin(57), 329),
2701 };
2702
2703 #define PORTCR_PULMD_OFF (0 << 6)
2704 #define PORTCR_PULMD_DOWN (2 << 6)
2705 #define PORTCR_PULMD_UP (3 << 6)
2706 #define PORTCR_PULMD_MASK (3 << 6)
2707
2708 static const unsigned int r8a73a4_portcr_offsets[] = {
2709 0x00000000, 0x00001000, 0x00000000, 0x00001000,
2710 0x00001000, 0x00002000, 0x00002000, 0x00002000,
2711 0x00002000, 0x00003000, 0x00003000,
2712 };
2713
2714 static unsigned int r8a73a4_pinmux_get_bias(struct sh_pfc *pfc,
2715 unsigned int pin)
2716 {
2717 void __iomem *addr;
2718
2719 addr = pfc->window->virt + r8a73a4_portcr_offsets[pin >> 5] + pin;
2720
2721 switch (ioread8(addr) & PORTCR_PULMD_MASK) {
2722 case PORTCR_PULMD_UP:
2723 return PIN_CONFIG_BIAS_PULL_UP;
2724 case PORTCR_PULMD_DOWN:
2725 return PIN_CONFIG_BIAS_PULL_DOWN;
2726 case PORTCR_PULMD_OFF:
2727 default:
2728 return PIN_CONFIG_BIAS_DISABLE;
2729 }
2730 }
2731
2732 static void r8a73a4_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
2733 unsigned int bias)
2734 {
2735 void __iomem *addr;
2736 u32 value;
2737
2738 addr = pfc->window->virt + r8a73a4_portcr_offsets[pin >> 5] + pin;
2739 value = ioread8(addr) & ~PORTCR_PULMD_MASK;
2740
2741 switch (bias) {
2742 case PIN_CONFIG_BIAS_PULL_UP:
2743 value |= PORTCR_PULMD_UP;
2744 break;
2745 case PIN_CONFIG_BIAS_PULL_DOWN:
2746 value |= PORTCR_PULMD_DOWN;
2747 break;
2748 }
2749
2750 iowrite8(value, addr);
2751 }
2752
2753 static const struct sh_pfc_soc_operations r8a73a4_pinmux_ops = {
2754 .get_bias = r8a73a4_pinmux_get_bias,
2755 .set_bias = r8a73a4_pinmux_set_bias,
2756 };
2757
2758 const struct sh_pfc_soc_info r8a73a4_pinmux_info = {
2759 .name = "r8a73a4_pfc",
2760 .ops = &r8a73a4_pinmux_ops,
2761
2762 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
2763 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
2764 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2765
2766 .pins = pinmux_pins,
2767 .nr_pins = ARRAY_SIZE(pinmux_pins),
2768
2769 .ranges = pinmux_ranges,
2770 .nr_ranges = ARRAY_SIZE(pinmux_ranges),
2771
2772 .groups = pinmux_groups,
2773 .nr_groups = ARRAY_SIZE(pinmux_groups),
2774 .functions = pinmux_functions,
2775 .nr_functions = ARRAY_SIZE(pinmux_functions),
2776
2777 .cfg_regs = pinmux_config_regs,
2778 .data_regs = pinmux_data_regs,
2779
2780 .gpio_data = pinmux_data,
2781 .gpio_data_size = ARRAY_SIZE(pinmux_data),
2782
2783 .gpio_irq = pinmux_irqs,
2784 .gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
2785 };
CRIS linux kernel tree