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Linux 3.11-rc3
[cris-mirror.git] / drivers / pinctrl / sh-pfc / pfc-sh7786.c
blob8ae0e32844e953eccac3c473ccdeb4fda2200b52
1 /*
2 * SH7786 Pinmux
3 *
4 * Copyright (C) 2008, 2009 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
6 *
7 * Based on SH7785 pinmux
8 *
9 * Copyright (C) 2008 Magnus Damm
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file "COPYING" in the main directory of this archive
13 * for more details.
14 */
15
16 #include <linux/init.h>
17 #include <linux/kernel.h>
18 #include <cpu/sh7786.h>
19
20 #include "sh_pfc.h"
21
22 enum {
23 PINMUX_RESERVED = 0,
24
25 PINMUX_DATA_BEGIN,
26 PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
27 PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA,
28 PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
29 PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA,
30 PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
31 PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA,
32 PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
33 PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA,
34 PE7_DATA, PE6_DATA,
35 PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
36 PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA,
37 PG7_DATA, PG6_DATA, PG5_DATA,
38 PH7_DATA, PH6_DATA, PH5_DATA, PH4_DATA,
39 PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA,
40 PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA,
41 PJ3_DATA, PJ2_DATA, PJ1_DATA,
42 PINMUX_DATA_END,
43
44 PINMUX_INPUT_BEGIN,
45 PA7_IN, PA6_IN, PA5_IN, PA4_IN,
46 PA3_IN, PA2_IN, PA1_IN, PA0_IN,
47 PB7_IN, PB6_IN, PB5_IN, PB4_IN,
48 PB3_IN, PB2_IN, PB1_IN, PB0_IN,
49 PC7_IN, PC6_IN, PC5_IN, PC4_IN,
50 PC3_IN, PC2_IN, PC1_IN, PC0_IN,
51 PD7_IN, PD6_IN, PD5_IN, PD4_IN,
52 PD3_IN, PD2_IN, PD1_IN, PD0_IN,
53 PE7_IN, PE6_IN,
54 PF7_IN, PF6_IN, PF5_IN, PF4_IN,
55 PF3_IN, PF2_IN, PF1_IN, PF0_IN,
56 PG7_IN, PG6_IN, PG5_IN,
57 PH7_IN, PH6_IN, PH5_IN, PH4_IN,
58 PH3_IN, PH2_IN, PH1_IN, PH0_IN,
59 PJ7_IN, PJ6_IN, PJ5_IN, PJ4_IN,
60 PJ3_IN, PJ2_IN, PJ1_IN,
61 PINMUX_INPUT_END,
62
63 PINMUX_INPUT_PULLUP_BEGIN,
64 PA7_IN_PU, PA6_IN_PU, PA5_IN_PU, PA4_IN_PU,
65 PA3_IN_PU, PA2_IN_PU, PA1_IN_PU, PA0_IN_PU,
66 PB7_IN_PU, PB6_IN_PU, PB5_IN_PU, PB4_IN_PU,
67 PB3_IN_PU, PB2_IN_PU, PB1_IN_PU, PB0_IN_PU,
68 PC7_IN_PU, PC6_IN_PU, PC5_IN_PU, PC4_IN_PU,
69 PC3_IN_PU, PC2_IN_PU, PC1_IN_PU, PC0_IN_PU,
70 PD7_IN_PU, PD6_IN_PU, PD5_IN_PU, PD4_IN_PU,
71 PD3_IN_PU, PD2_IN_PU, PD1_IN_PU, PD0_IN_PU,
72 PE7_IN_PU, PE6_IN_PU,
73 PF7_IN_PU, PF6_IN_PU, PF5_IN_PU, PF4_IN_PU,
74 PF3_IN_PU, PF2_IN_PU, PF1_IN_PU, PF0_IN_PU,
75 PG7_IN_PU, PG6_IN_PU, PG5_IN_PU,
76 PH7_IN_PU, PH6_IN_PU, PH5_IN_PU, PH4_IN_PU,
77 PH3_IN_PU, PH2_IN_PU, PH1_IN_PU, PH0_IN_PU,
78 PJ7_IN_PU, PJ6_IN_PU, PJ5_IN_PU, PJ4_IN_PU,
79 PJ3_IN_PU, PJ2_IN_PU, PJ1_IN_PU,
80 PINMUX_INPUT_PULLUP_END,
81
82 PINMUX_OUTPUT_BEGIN,
83 PA7_OUT, PA6_OUT, PA5_OUT, PA4_OUT,
84 PA3_OUT, PA2_OUT, PA1_OUT, PA0_OUT,
85 PB7_OUT, PB6_OUT, PB5_OUT, PB4_OUT,
86 PB3_OUT, PB2_OUT, PB1_OUT, PB0_OUT,
87 PC7_OUT, PC6_OUT, PC5_OUT, PC4_OUT,
88 PC3_OUT, PC2_OUT, PC1_OUT, PC0_OUT,
89 PD7_OUT, PD6_OUT, PD5_OUT, PD4_OUT,
90 PD3_OUT, PD2_OUT, PD1_OUT, PD0_OUT,
91 PE7_OUT, PE6_OUT,
92 PF7_OUT, PF6_OUT, PF5_OUT, PF4_OUT,
93 PF3_OUT, PF2_OUT, PF1_OUT, PF0_OUT,
94 PG7_OUT, PG6_OUT, PG5_OUT,
95 PH7_OUT, PH6_OUT, PH5_OUT, PH4_OUT,
96 PH3_OUT, PH2_OUT, PH1_OUT, PH0_OUT,
97 PJ7_OUT, PJ6_OUT, PJ5_OUT, PJ4_OUT,
98 PJ3_OUT, PJ2_OUT, PJ1_OUT,
99 PINMUX_OUTPUT_END,
100
101 PINMUX_FUNCTION_BEGIN,
102 PA7_FN, PA6_FN, PA5_FN, PA4_FN,
103 PA3_FN, PA2_FN, PA1_FN, PA0_FN,
104 PB7_FN, PB6_FN, PB5_FN, PB4_FN,
105 PB3_FN, PB2_FN, PB1_FN, PB0_FN,
106 PC7_FN, PC6_FN, PC5_FN, PC4_FN,
107 PC3_FN, PC2_FN, PC1_FN, PC0_FN,
108 PD7_FN, PD6_FN, PD5_FN, PD4_FN,
109 PD3_FN, PD2_FN, PD1_FN, PD0_FN,
110 PE7_FN, PE6_FN,
111 PF7_FN, PF6_FN, PF5_FN, PF4_FN,
112 PF3_FN, PF2_FN, PF1_FN, PF0_FN,
113 PG7_FN, PG6_FN, PG5_FN,
114 PH7_FN, PH6_FN, PH5_FN, PH4_FN,
115 PH3_FN, PH2_FN, PH1_FN, PH0_FN,
116 PJ7_FN, PJ6_FN, PJ5_FN, PJ4_FN,
117 PJ3_FN, PJ2_FN, PJ1_FN,
118 P1MSEL14_0, P1MSEL14_1,
119 P1MSEL13_0, P1MSEL13_1,
120 P1MSEL12_0, P1MSEL12_1,
121 P1MSEL11_0, P1MSEL11_1,
122 P1MSEL10_0, P1MSEL10_1,
123 P1MSEL9_0, P1MSEL9_1,
124 P1MSEL8_0, P1MSEL8_1,
125 P1MSEL7_0, P1MSEL7_1,
126 P1MSEL6_0, P1MSEL6_1,
127 P1MSEL5_0, P1MSEL5_1,
128 P1MSEL4_0, P1MSEL4_1,
129 P1MSEL3_0, P1MSEL3_1,
130 P1MSEL2_0, P1MSEL2_1,
131 P1MSEL1_0, P1MSEL1_1,
132 P1MSEL0_0, P1MSEL0_1,
133
134 P2MSEL15_0, P2MSEL15_1,
135 P2MSEL14_0, P2MSEL14_1,
136 P2MSEL13_0, P2MSEL13_1,
137 P2MSEL12_0, P2MSEL12_1,
138 P2MSEL11_0, P2MSEL11_1,
139 P2MSEL10_0, P2MSEL10_1,
140 P2MSEL9_0, P2MSEL9_1,
141 P2MSEL8_0, P2MSEL8_1,
142 P2MSEL7_0, P2MSEL7_1,
143 P2MSEL6_0, P2MSEL6_1,
144 P2MSEL5_0, P2MSEL5_1,
145 P2MSEL4_0, P2MSEL4_1,
146 P2MSEL3_0, P2MSEL3_1,
147 P2MSEL2_0, P2MSEL2_1,
148 P2MSEL1_0, P2MSEL1_1,
149 P2MSEL0_0, P2MSEL0_1,
150 PINMUX_FUNCTION_END,
151
152 PINMUX_MARK_BEGIN,
153 DCLKIN_MARK, DCLKOUT_MARK, ODDF_MARK,
154 VSYNC_MARK, HSYNC_MARK, CDE_MARK, DISP_MARK,
155 DR0_MARK, DR1_MARK, DR2_MARK, DR3_MARK, DR4_MARK, DR5_MARK,
156 DG0_MARK, DG1_MARK, DG2_MARK, DG3_MARK, DG4_MARK, DG5_MARK,
157 DB0_MARK, DB1_MARK, DB2_MARK, DB3_MARK, DB4_MARK, DB5_MARK,
158 ETH_MAGIC_MARK, ETH_LINK_MARK, ETH_TX_ER_MARK, ETH_TX_EN_MARK,
159 ETH_MDIO_MARK, ETH_RX_CLK_MARK, ETH_MDC_MARK, ETH_COL_MARK,
160 ETH_TX_CLK_MARK, ETH_CRS_MARK, ETH_RX_DV_MARK, ETH_RX_ER_MARK,
161 ETH_TXD3_MARK, ETH_TXD2_MARK, ETH_TXD1_MARK, ETH_TXD0_MARK,
162 ETH_RXD3_MARK, ETH_RXD2_MARK, ETH_RXD1_MARK, ETH_RXD0_MARK,
163 HSPI_CLK_MARK, HSPI_CS_MARK, HSPI_RX_MARK, HSPI_TX_MARK,
164 SCIF0_CTS_MARK, SCIF0_RTS_MARK,
165 SCIF0_SCK_MARK, SCIF0_RXD_MARK, SCIF0_TXD_MARK,
166 SCIF1_SCK_MARK, SCIF1_RXD_MARK, SCIF1_TXD_MARK,
167 SCIF3_SCK_MARK, SCIF3_RXD_MARK, SCIF3_TXD_MARK,
168 SCIF4_SCK_MARK, SCIF4_RXD_MARK, SCIF4_TXD_MARK,
169 SCIF5_SCK_MARK, SCIF5_RXD_MARK, SCIF5_TXD_MARK,
170 BREQ_MARK, IOIS16_MARK, CE2B_MARK, CE2A_MARK, BACK_MARK,
171 FALE_MARK, FRB_MARK, FSTATUS_MARK,
172 FSE_MARK, FCLE_MARK,
173 DACK0_MARK, DACK1_MARK, DACK2_MARK, DACK3_MARK,
174 DREQ0_MARK, DREQ1_MARK, DREQ2_MARK, DREQ3_MARK,
175 DRAK0_MARK, DRAK1_MARK, DRAK2_MARK, DRAK3_MARK,
176 USB_OVC1_MARK, USB_OVC0_MARK,
177 USB_PENC1_MARK, USB_PENC0_MARK,
178 HAC_RES_MARK,
179 HAC1_SDOUT_MARK, HAC1_SDIN_MARK, HAC1_SYNC_MARK, HAC1_BITCLK_MARK,
180 HAC0_SDOUT_MARK, HAC0_SDIN_MARK, HAC0_SYNC_MARK, HAC0_BITCLK_MARK,
181 SSI0_SDATA_MARK, SSI0_SCK_MARK, SSI0_WS_MARK, SSI0_CLK_MARK,
182 SSI1_SDATA_MARK, SSI1_SCK_MARK, SSI1_WS_MARK, SSI1_CLK_MARK,
183 SSI2_SDATA_MARK, SSI2_SCK_MARK, SSI2_WS_MARK,
184 SSI3_SDATA_MARK, SSI3_SCK_MARK, SSI3_WS_MARK,
185 SDIF1CMD_MARK, SDIF1CD_MARK, SDIF1WP_MARK, SDIF1CLK_MARK,
186 SDIF1D3_MARK, SDIF1D2_MARK, SDIF1D1_MARK, SDIF1D0_MARK,
187 SDIF0CMD_MARK, SDIF0CD_MARK, SDIF0WP_MARK, SDIF0CLK_MARK,
188 SDIF0D3_MARK, SDIF0D2_MARK, SDIF0D1_MARK, SDIF0D0_MARK,
189 TCLK_MARK,
190 IRL7_MARK, IRL6_MARK, IRL5_MARK, IRL4_MARK,
191 PINMUX_MARK_END,
192 };
193
194 static const pinmux_enum_t pinmux_data[] = {
195
196 /* PA GPIO */
197 PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT, PA7_IN_PU),
198 PINMUX_DATA(PA6_DATA, PA6_IN, PA6_OUT, PA6_IN_PU),
199 PINMUX_DATA(PA5_DATA, PA5_IN, PA5_OUT, PA5_IN_PU),
200 PINMUX_DATA(PA4_DATA, PA4_IN, PA4_OUT, PA4_IN_PU),
201 PINMUX_DATA(PA3_DATA, PA3_IN, PA3_OUT, PA3_IN_PU),
202 PINMUX_DATA(PA2_DATA, PA2_IN, PA2_OUT, PA2_IN_PU),
203 PINMUX_DATA(PA1_DATA, PA1_IN, PA1_OUT, PA1_IN_PU),
204 PINMUX_DATA(PA0_DATA, PA0_IN, PA0_OUT, PA0_IN_PU),
205
206 /* PB GPIO */
207 PINMUX_DATA(PB7_DATA, PB7_IN, PB7_OUT, PB7_IN_PU),
208 PINMUX_DATA(PB6_DATA, PB6_IN, PB6_OUT, PB6_IN_PU),
209 PINMUX_DATA(PB5_DATA, PB5_IN, PB5_OUT, PB5_IN_PU),
210 PINMUX_DATA(PB4_DATA, PB4_IN, PB4_OUT, PB4_IN_PU),
211 PINMUX_DATA(PB3_DATA, PB3_IN, PB3_OUT, PB3_IN_PU),
212 PINMUX_DATA(PB2_DATA, PB2_IN, PB2_OUT, PB2_IN_PU),
213 PINMUX_DATA(PB1_DATA, PB1_IN, PB1_OUT, PB1_IN_PU),
214 PINMUX_DATA(PB0_DATA, PB0_IN, PB0_OUT, PB0_IN_PU),
215
216 /* PC GPIO */
217 PINMUX_DATA(PC7_DATA, PC7_IN, PC7_OUT, PC7_IN_PU),
218 PINMUX_DATA(PC6_DATA, PC6_IN, PC6_OUT, PC6_IN_PU),
219 PINMUX_DATA(PC5_DATA, PC5_IN, PC5_OUT, PC5_IN_PU),
220 PINMUX_DATA(PC4_DATA, PC4_IN, PC4_OUT, PC4_IN_PU),
221 PINMUX_DATA(PC3_DATA, PC3_IN, PC3_OUT, PC3_IN_PU),
222 PINMUX_DATA(PC2_DATA, PC2_IN, PC2_OUT, PC2_IN_PU),
223 PINMUX_DATA(PC1_DATA, PC1_IN, PC1_OUT, PC1_IN_PU),
224 PINMUX_DATA(PC0_DATA, PC0_IN, PC0_OUT, PC0_IN_PU),
225
226 /* PD GPIO */
227 PINMUX_DATA(PD7_DATA, PD7_IN, PD7_OUT, PD7_IN_PU),
228 PINMUX_DATA(PD6_DATA, PD6_IN, PD6_OUT, PD6_IN_PU),
229 PINMUX_DATA(PD5_DATA, PD5_IN, PD5_OUT, PD5_IN_PU),
230 PINMUX_DATA(PD4_DATA, PD4_IN, PD4_OUT, PD4_IN_PU),
231 PINMUX_DATA(PD3_DATA, PD3_IN, PD3_OUT, PD3_IN_PU),
232 PINMUX_DATA(PD2_DATA, PD2_IN, PD2_OUT, PD2_IN_PU),
233 PINMUX_DATA(PD1_DATA, PD1_IN, PD1_OUT, PD1_IN_PU),
234 PINMUX_DATA(PD0_DATA, PD0_IN, PD0_OUT, PD0_IN_PU),
235
236 /* PE GPIO */
237 PINMUX_DATA(PE7_DATA, PE7_IN, PE7_OUT, PE7_IN_PU),
238 PINMUX_DATA(PE6_DATA, PE6_IN, PE6_OUT, PE6_IN_PU),
239
240 /* PF GPIO */
241 PINMUX_DATA(PF7_DATA, PF7_IN, PF7_OUT, PF7_IN_PU),
242 PINMUX_DATA(PF6_DATA, PF6_IN, PF6_OUT, PF6_IN_PU),
243 PINMUX_DATA(PF5_DATA, PF5_IN, PF5_OUT, PF5_IN_PU),
244 PINMUX_DATA(PF4_DATA, PF4_IN, PF4_OUT, PF4_IN_PU),
245 PINMUX_DATA(PF3_DATA, PF3_IN, PF3_OUT, PF3_IN_PU),
246 PINMUX_DATA(PF2_DATA, PF2_IN, PF2_OUT, PF2_IN_PU),
247 PINMUX_DATA(PF1_DATA, PF1_IN, PF1_OUT, PF1_IN_PU),
248 PINMUX_DATA(PF0_DATA, PF0_IN, PF0_OUT, PF0_IN_PU),
249
250 /* PG GPIO */
251 PINMUX_DATA(PG7_DATA, PG7_IN, PG7_OUT, PG7_IN_PU),
252 PINMUX_DATA(PG6_DATA, PG6_IN, PG6_OUT, PG6_IN_PU),
253 PINMUX_DATA(PG5_DATA, PG5_IN, PG5_OUT, PG5_IN_PU),
254
255 /* PH GPIO */
256 PINMUX_DATA(PH7_DATA, PH7_IN, PH7_OUT, PH7_IN_PU),
257 PINMUX_DATA(PH6_DATA, PH6_IN, PH6_OUT, PH6_IN_PU),
258 PINMUX_DATA(PH5_DATA, PH5_IN, PH5_OUT, PH5_IN_PU),
259 PINMUX_DATA(PH4_DATA, PH4_IN, PH4_OUT, PH4_IN_PU),
260 PINMUX_DATA(PH3_DATA, PH3_IN, PH3_OUT, PH3_IN_PU),
261 PINMUX_DATA(PH2_DATA, PH2_IN, PH2_OUT, PH2_IN_PU),
262 PINMUX_DATA(PH1_DATA, PH1_IN, PH1_OUT, PH1_IN_PU),
263 PINMUX_DATA(PH0_DATA, PH0_IN, PH0_OUT, PH0_IN_PU),
264
265 /* PJ GPIO */
266 PINMUX_DATA(PJ7_DATA, PJ7_IN, PJ7_OUT, PJ7_IN_PU),
267 PINMUX_DATA(PJ6_DATA, PJ6_IN, PJ6_OUT, PJ6_IN_PU),
268 PINMUX_DATA(PJ5_DATA, PJ5_IN, PJ5_OUT, PJ5_IN_PU),
269 PINMUX_DATA(PJ4_DATA, PJ4_IN, PJ4_OUT, PJ4_IN_PU),
270 PINMUX_DATA(PJ3_DATA, PJ3_IN, PJ3_OUT, PJ3_IN_PU),
271 PINMUX_DATA(PJ2_DATA, PJ2_IN, PJ2_OUT, PJ2_IN_PU),
272 PINMUX_DATA(PJ1_DATA, PJ1_IN, PJ1_OUT, PJ1_IN_PU),
273
274 /* PA FN */
275 PINMUX_DATA(CDE_MARK, P1MSEL2_0, PA7_FN),
276 PINMUX_DATA(DISP_MARK, P1MSEL2_0, PA6_FN),
277 PINMUX_DATA(DR5_MARK, P1MSEL2_0, PA5_FN),
278 PINMUX_DATA(DR4_MARK, P1MSEL2_0, PA4_FN),
279 PINMUX_DATA(DR3_MARK, P1MSEL2_0, PA3_FN),
280 PINMUX_DATA(DR2_MARK, P1MSEL2_0, PA2_FN),
281 PINMUX_DATA(DR1_MARK, P1MSEL2_0, PA1_FN),
282 PINMUX_DATA(DR0_MARK, P1MSEL2_0, PA0_FN),
283 PINMUX_DATA(ETH_MAGIC_MARK, P1MSEL2_1, PA7_FN),
284 PINMUX_DATA(ETH_LINK_MARK, P1MSEL2_1, PA6_FN),
285 PINMUX_DATA(ETH_TX_ER_MARK, P1MSEL2_1, PA5_FN),
286 PINMUX_DATA(ETH_TX_EN_MARK, P1MSEL2_1, PA4_FN),
287 PINMUX_DATA(ETH_TXD3_MARK, P1MSEL2_1, PA3_FN),
288 PINMUX_DATA(ETH_TXD2_MARK, P1MSEL2_1, PA2_FN),
289 PINMUX_DATA(ETH_TXD1_MARK, P1MSEL2_1, PA1_FN),
290 PINMUX_DATA(ETH_TXD0_MARK, P1MSEL2_1, PA0_FN),
291
292 /* PB FN */
293 PINMUX_DATA(VSYNC_MARK, P1MSEL3_0, PB7_FN),
294 PINMUX_DATA(ODDF_MARK, P1MSEL3_0, PB6_FN),
295 PINMUX_DATA(DG5_MARK, P1MSEL2_0, PB5_FN),
296 PINMUX_DATA(DG4_MARK, P1MSEL2_0, PB4_FN),
297 PINMUX_DATA(DG3_MARK, P1MSEL2_0, PB3_FN),
298 PINMUX_DATA(DG2_MARK, P1MSEL2_0, PB2_FN),
299 PINMUX_DATA(DG1_MARK, P1MSEL2_0, PB1_FN),
300 PINMUX_DATA(DG0_MARK, P1MSEL2_0, PB0_FN),
301 PINMUX_DATA(HSPI_CLK_MARK, P1MSEL3_1, PB7_FN),
302 PINMUX_DATA(HSPI_CS_MARK, P1MSEL3_1, PB6_FN),
303 PINMUX_DATA(ETH_MDIO_MARK, P1MSEL2_1, PB5_FN),
304 PINMUX_DATA(ETH_RX_CLK_MARK, P1MSEL2_1, PB4_FN),
305 PINMUX_DATA(ETH_MDC_MARK, P1MSEL2_1, PB3_FN),
306 PINMUX_DATA(ETH_COL_MARK, P1MSEL2_1, PB2_FN),
307 PINMUX_DATA(ETH_TX_CLK_MARK, P1MSEL2_1, PB1_FN),
308 PINMUX_DATA(ETH_CRS_MARK, P1MSEL2_1, PB0_FN),
309
310 /* PC FN */
311 PINMUX_DATA(DCLKIN_MARK, P1MSEL3_0, PC7_FN),
312 PINMUX_DATA(HSYNC_MARK, P1MSEL3_0, PC6_FN),
313 PINMUX_DATA(DB5_MARK, P1MSEL2_0, PC5_FN),
314 PINMUX_DATA(DB4_MARK, P1MSEL2_0, PC4_FN),
315 PINMUX_DATA(DB3_MARK, P1MSEL2_0, PC3_FN),
316 PINMUX_DATA(DB2_MARK, P1MSEL2_0, PC2_FN),
317 PINMUX_DATA(DB1_MARK, P1MSEL2_0, PC1_FN),
318 PINMUX_DATA(DB0_MARK, P1MSEL2_0, PC0_FN),
319
320 PINMUX_DATA(HSPI_RX_MARK, P1MSEL3_1, PC7_FN),
321 PINMUX_DATA(HSPI_TX_MARK, P1MSEL3_1, PC6_FN),
322 PINMUX_DATA(ETH_RXD3_MARK, P1MSEL2_1, PC5_FN),
323 PINMUX_DATA(ETH_RXD2_MARK, P1MSEL2_1, PC4_FN),
324 PINMUX_DATA(ETH_RXD1_MARK, P1MSEL2_1, PC3_FN),
325 PINMUX_DATA(ETH_RXD0_MARK, P1MSEL2_1, PC2_FN),
326 PINMUX_DATA(ETH_RX_DV_MARK, P1MSEL2_1, PC1_FN),
327 PINMUX_DATA(ETH_RX_ER_MARK, P1MSEL2_1, PC0_FN),
328
329 /* PD FN */
330 PINMUX_DATA(DCLKOUT_MARK, PD7_FN),
331 PINMUX_DATA(SCIF1_SCK_MARK, PD6_FN),
332 PINMUX_DATA(SCIF1_RXD_MARK, PD5_FN),
333 PINMUX_DATA(SCIF1_TXD_MARK, PD4_FN),
334 PINMUX_DATA(DACK1_MARK, P1MSEL13_1, P1MSEL12_0, PD3_FN),
335 PINMUX_DATA(BACK_MARK, P1MSEL13_0, P1MSEL12_1, PD3_FN),
336 PINMUX_DATA(FALE_MARK, P1MSEL13_0, P1MSEL12_0, PD3_FN),
337 PINMUX_DATA(DACK0_MARK, P1MSEL14_1, PD2_FN),
338 PINMUX_DATA(FCLE_MARK, P1MSEL14_0, PD2_FN),
339 PINMUX_DATA(DREQ1_MARK, P1MSEL10_0, P1MSEL9_1, PD1_FN),
340 PINMUX_DATA(BREQ_MARK, P1MSEL10_1, P1MSEL9_0, PD1_FN),
341 PINMUX_DATA(USB_OVC1_MARK, P1MSEL10_0, P1MSEL9_0, PD1_FN),
342 PINMUX_DATA(DREQ0_MARK, P1MSEL11_1, PD0_FN),
343 PINMUX_DATA(USB_OVC0_MARK, P1MSEL11_0, PD0_FN),
344
345 /* PE FN */
346 PINMUX_DATA(USB_PENC1_MARK, PE7_FN),
347 PINMUX_DATA(USB_PENC0_MARK, PE6_FN),
348
349 /* PF FN */
350 PINMUX_DATA(HAC1_SDOUT_MARK, P2MSEL15_0, P2MSEL14_0, PF7_FN),
351 PINMUX_DATA(HAC1_SDIN_MARK, P2MSEL15_0, P2MSEL14_0, PF6_FN),
352 PINMUX_DATA(HAC1_SYNC_MARK, P2MSEL15_0, P2MSEL14_0, PF5_FN),
353 PINMUX_DATA(HAC1_BITCLK_MARK, P2MSEL15_0, P2MSEL14_0, PF4_FN),
354 PINMUX_DATA(HAC0_SDOUT_MARK, P2MSEL13_0, P2MSEL12_0, PF3_FN),
355 PINMUX_DATA(HAC0_SDIN_MARK, P2MSEL13_0, P2MSEL12_0, PF2_FN),
356 PINMUX_DATA(HAC0_SYNC_MARK, P2MSEL13_0, P2MSEL12_0, PF1_FN),
357 PINMUX_DATA(HAC0_BITCLK_MARK, P2MSEL13_0, P2MSEL12_0, PF0_FN),
358 PINMUX_DATA(SSI1_SDATA_MARK, P2MSEL15_0, P2MSEL14_1, PF7_FN),
359 PINMUX_DATA(SSI1_SCK_MARK, P2MSEL15_0, P2MSEL14_1, PF6_FN),
360 PINMUX_DATA(SSI1_WS_MARK, P2MSEL15_0, P2MSEL14_1, PF5_FN),
361 PINMUX_DATA(SSI1_CLK_MARK, P2MSEL15_0, P2MSEL14_1, PF4_FN),
362 PINMUX_DATA(SSI0_SDATA_MARK, P2MSEL13_0, P2MSEL12_1, PF3_FN),
363 PINMUX_DATA(SSI0_SCK_MARK, P2MSEL13_0, P2MSEL12_1, PF2_FN),
364 PINMUX_DATA(SSI0_WS_MARK, P2MSEL13_0, P2MSEL12_1, PF1_FN),
365 PINMUX_DATA(SSI0_CLK_MARK, P2MSEL13_0, P2MSEL12_1, PF0_FN),
366 PINMUX_DATA(SDIF1CMD_MARK, P2MSEL15_1, P2MSEL14_0, PF7_FN),
367 PINMUX_DATA(SDIF1CD_MARK, P2MSEL15_1, P2MSEL14_0, PF6_FN),
368 PINMUX_DATA(SDIF1WP_MARK, P2MSEL15_1, P2MSEL14_0, PF5_FN),
369 PINMUX_DATA(SDIF1CLK_MARK, P2MSEL15_1, P2MSEL14_0, PF4_FN),
370 PINMUX_DATA(SDIF1D3_MARK, P2MSEL13_1, P2MSEL12_0, PF3_FN),
371 PINMUX_DATA(SDIF1D2_MARK, P2MSEL13_1, P2MSEL12_0, PF2_FN),
372 PINMUX_DATA(SDIF1D1_MARK, P2MSEL13_1, P2MSEL12_0, PF1_FN),
373 PINMUX_DATA(SDIF1D0_MARK, P2MSEL13_1, P2MSEL12_0, PF0_FN),
374
375 /* PG FN */
376 PINMUX_DATA(SCIF3_SCK_MARK, P1MSEL8_0, PG7_FN),
377 PINMUX_DATA(SSI2_SDATA_MARK, P1MSEL8_1, PG7_FN),
378 PINMUX_DATA(SCIF3_RXD_MARK, P1MSEL7_0, P1MSEL6_0, PG6_FN),
379 PINMUX_DATA(SSI2_SCK_MARK, P1MSEL7_1, P1MSEL6_0, PG6_FN),
380 PINMUX_DATA(TCLK_MARK, P1MSEL7_0, P1MSEL6_1, PG6_FN),
381 PINMUX_DATA(SCIF3_TXD_MARK, P1MSEL5_0, P1MSEL4_0, PG5_FN),
382 PINMUX_DATA(SSI2_WS_MARK, P1MSEL5_1, P1MSEL4_0, PG5_FN),
383 PINMUX_DATA(HAC_RES_MARK, P1MSEL5_0, P1MSEL4_1, PG5_FN),
384
385 /* PH FN */
386 PINMUX_DATA(DACK3_MARK, P2MSEL4_0, PH7_FN),
387 PINMUX_DATA(SDIF0CMD_MARK, P2MSEL4_1, PH7_FN),
388 PINMUX_DATA(DACK2_MARK, P2MSEL4_0, PH6_FN),
389 PINMUX_DATA(SDIF0CD_MARK, P2MSEL4_1, PH6_FN),
390 PINMUX_DATA(DREQ3_MARK, P2MSEL4_0, PH5_FN),
391 PINMUX_DATA(SDIF0WP_MARK, P2MSEL4_1, PH5_FN),
392 PINMUX_DATA(DREQ2_MARK, P2MSEL3_0, P2MSEL2_1, PH4_FN),
393 PINMUX_DATA(SDIF0CLK_MARK, P2MSEL3_1, P2MSEL2_0, PH4_FN),
394 PINMUX_DATA(SCIF0_CTS_MARK, P2MSEL3_0, P2MSEL2_0, PH4_FN),
395 PINMUX_DATA(SDIF0D3_MARK, P2MSEL1_1, P2MSEL0_0, PH3_FN),
396 PINMUX_DATA(SCIF0_RTS_MARK, P2MSEL1_0, P2MSEL0_0, PH3_FN),
397 PINMUX_DATA(IRL7_MARK, P2MSEL1_0, P2MSEL0_1, PH3_FN),
398 PINMUX_DATA(SDIF0D2_MARK, P2MSEL1_1, P2MSEL0_0, PH2_FN),
399 PINMUX_DATA(SCIF0_SCK_MARK, P2MSEL1_0, P2MSEL0_0, PH2_FN),
400 PINMUX_DATA(IRL6_MARK, P2MSEL1_0, P2MSEL0_1, PH2_FN),
401 PINMUX_DATA(SDIF0D1_MARK, P2MSEL1_1, P2MSEL0_0, PH1_FN),
402 PINMUX_DATA(SCIF0_RXD_MARK, P2MSEL1_0, P2MSEL0_0, PH1_FN),
403 PINMUX_DATA(IRL5_MARK, P2MSEL1_0, P2MSEL0_1, PH1_FN),
404 PINMUX_DATA(SDIF0D0_MARK, P2MSEL1_1, P2MSEL0_0, PH0_FN),
405 PINMUX_DATA(SCIF0_TXD_MARK, P2MSEL1_0, P2MSEL0_0, PH0_FN),
406 PINMUX_DATA(IRL4_MARK, P2MSEL1_0, P2MSEL0_1, PH0_FN),
407
408 /* PJ FN */
409 PINMUX_DATA(SCIF5_SCK_MARK, P2MSEL11_1, PJ7_FN),
410 PINMUX_DATA(FRB_MARK, P2MSEL11_0, PJ7_FN),
411 PINMUX_DATA(SCIF5_RXD_MARK, P2MSEL10_0, PJ6_FN),
412 PINMUX_DATA(IOIS16_MARK, P2MSEL10_1, PJ6_FN),
413 PINMUX_DATA(SCIF5_TXD_MARK, P2MSEL10_0, PJ5_FN),
414 PINMUX_DATA(CE2B_MARK, P2MSEL10_1, PJ5_FN),
415 PINMUX_DATA(DRAK3_MARK, P2MSEL7_0, PJ4_FN),
416 PINMUX_DATA(CE2A_MARK, P2MSEL7_1, PJ4_FN),
417 PINMUX_DATA(SCIF4_SCK_MARK, P2MSEL9_0, P2MSEL8_0, PJ3_FN),
418 PINMUX_DATA(DRAK2_MARK, P2MSEL9_0, P2MSEL8_1, PJ3_FN),
419 PINMUX_DATA(SSI3_WS_MARK, P2MSEL9_1, P2MSEL8_0, PJ3_FN),
420 PINMUX_DATA(SCIF4_RXD_MARK, P2MSEL6_1, P2MSEL5_0, PJ2_FN),
421 PINMUX_DATA(DRAK1_MARK, P2MSEL6_0, P2MSEL5_1, PJ2_FN),
422 PINMUX_DATA(FSTATUS_MARK, P2MSEL6_0, P2MSEL5_0, PJ2_FN),
423 PINMUX_DATA(SSI3_SDATA_MARK, P2MSEL6_1, P2MSEL5_1, PJ2_FN),
424 PINMUX_DATA(SCIF4_TXD_MARK, P2MSEL6_1, P2MSEL5_0, PJ1_FN),
425 PINMUX_DATA(DRAK0_MARK, P2MSEL6_0, P2MSEL5_1, PJ1_FN),
426 PINMUX_DATA(FSE_MARK, P2MSEL6_0, P2MSEL5_0, PJ1_FN),
427 PINMUX_DATA(SSI3_SCK_MARK, P2MSEL6_1, P2MSEL5_1, PJ1_FN),
428 };
429
430 static struct sh_pfc_pin pinmux_pins[] = {
431 /* PA */
432 PINMUX_GPIO(GPIO_PA7, PA7_DATA),
433 PINMUX_GPIO(GPIO_PA6, PA6_DATA),
434 PINMUX_GPIO(GPIO_PA5, PA5_DATA),
435 PINMUX_GPIO(GPIO_PA4, PA4_DATA),
436 PINMUX_GPIO(GPIO_PA3, PA3_DATA),
437 PINMUX_GPIO(GPIO_PA2, PA2_DATA),
438 PINMUX_GPIO(GPIO_PA1, PA1_DATA),
439 PINMUX_GPIO(GPIO_PA0, PA0_DATA),
440
441 /* PB */
442 PINMUX_GPIO(GPIO_PB7, PB7_DATA),
443 PINMUX_GPIO(GPIO_PB6, PB6_DATA),
444 PINMUX_GPIO(GPIO_PB5, PB5_DATA),
445 PINMUX_GPIO(GPIO_PB4, PB4_DATA),
446 PINMUX_GPIO(GPIO_PB3, PB3_DATA),
447 PINMUX_GPIO(GPIO_PB2, PB2_DATA),
448 PINMUX_GPIO(GPIO_PB1, PB1_DATA),
449 PINMUX_GPIO(GPIO_PB0, PB0_DATA),
450
451 /* PC */
452 PINMUX_GPIO(GPIO_PC7, PC7_DATA),
453 PINMUX_GPIO(GPIO_PC6, PC6_DATA),
454 PINMUX_GPIO(GPIO_PC5, PC5_DATA),
455 PINMUX_GPIO(GPIO_PC4, PC4_DATA),
456 PINMUX_GPIO(GPIO_PC3, PC3_DATA),
457 PINMUX_GPIO(GPIO_PC2, PC2_DATA),
458 PINMUX_GPIO(GPIO_PC1, PC1_DATA),
459 PINMUX_GPIO(GPIO_PC0, PC0_DATA),
460
461 /* PD */
462 PINMUX_GPIO(GPIO_PD7, PD7_DATA),
463 PINMUX_GPIO(GPIO_PD6, PD6_DATA),
464 PINMUX_GPIO(GPIO_PD5, PD5_DATA),
465 PINMUX_GPIO(GPIO_PD4, PD4_DATA),
466 PINMUX_GPIO(GPIO_PD3, PD3_DATA),
467 PINMUX_GPIO(GPIO_PD2, PD2_DATA),
468 PINMUX_GPIO(GPIO_PD1, PD1_DATA),
469 PINMUX_GPIO(GPIO_PD0, PD0_DATA),
470
471 /* PE */
472 PINMUX_GPIO(GPIO_PE7, PE7_DATA),
473 PINMUX_GPIO(GPIO_PE6, PE6_DATA),
474
475 /* PF */
476 PINMUX_GPIO(GPIO_PF7, PF7_DATA),
477 PINMUX_GPIO(GPIO_PF6, PF6_DATA),
478 PINMUX_GPIO(GPIO_PF5, PF5_DATA),
479 PINMUX_GPIO(GPIO_PF4, PF4_DATA),
480 PINMUX_GPIO(GPIO_PF3, PF3_DATA),
481 PINMUX_GPIO(GPIO_PF2, PF2_DATA),
482 PINMUX_GPIO(GPIO_PF1, PF1_DATA),
483 PINMUX_GPIO(GPIO_PF0, PF0_DATA),
484
485 /* PG */
486 PINMUX_GPIO(GPIO_PG7, PG7_DATA),
487 PINMUX_GPIO(GPIO_PG6, PG6_DATA),
488 PINMUX_GPIO(GPIO_PG5, PG5_DATA),
489
490 /* PH */
491 PINMUX_GPIO(GPIO_PH7, PH7_DATA),
492 PINMUX_GPIO(GPIO_PH6, PH6_DATA),
493 PINMUX_GPIO(GPIO_PH5, PH5_DATA),
494 PINMUX_GPIO(GPIO_PH4, PH4_DATA),
495 PINMUX_GPIO(GPIO_PH3, PH3_DATA),
496 PINMUX_GPIO(GPIO_PH2, PH2_DATA),
497 PINMUX_GPIO(GPIO_PH1, PH1_DATA),
498 PINMUX_GPIO(GPIO_PH0, PH0_DATA),
499
500 /* PJ */
501 PINMUX_GPIO(GPIO_PJ7, PJ7_DATA),
502 PINMUX_GPIO(GPIO_PJ6, PJ6_DATA),
503 PINMUX_GPIO(GPIO_PJ5, PJ5_DATA),
504 PINMUX_GPIO(GPIO_PJ4, PJ4_DATA),
505 PINMUX_GPIO(GPIO_PJ3, PJ3_DATA),
506 PINMUX_GPIO(GPIO_PJ2, PJ2_DATA),
507 PINMUX_GPIO(GPIO_PJ1, PJ1_DATA),
508 };
509
510 #define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
511
512 static const struct pinmux_func pinmux_func_gpios[] = {
513 /* FN */
514 GPIO_FN(CDE),
515 GPIO_FN(ETH_MAGIC),
516 GPIO_FN(DISP),
517 GPIO_FN(ETH_LINK),
518 GPIO_FN(DR5),
519 GPIO_FN(ETH_TX_ER),
520 GPIO_FN(DR4),
521 GPIO_FN(ETH_TX_EN),
522 GPIO_FN(DR3),
523 GPIO_FN(ETH_TXD3),
524 GPIO_FN(DR2),
525 GPIO_FN(ETH_TXD2),
526 GPIO_FN(DR1),
527 GPIO_FN(ETH_TXD1),
528 GPIO_FN(DR0),
529 GPIO_FN(ETH_TXD0),
530 GPIO_FN(VSYNC),
531 GPIO_FN(HSPI_CLK),
532 GPIO_FN(ODDF),
533 GPIO_FN(HSPI_CS),
534 GPIO_FN(DG5),
535 GPIO_FN(ETH_MDIO),
536 GPIO_FN(DG4),
537 GPIO_FN(ETH_RX_CLK),
538 GPIO_FN(DG3),
539 GPIO_FN(ETH_MDC),
540 GPIO_FN(DG2),
541 GPIO_FN(ETH_COL),
542 GPIO_FN(DG1),
543 GPIO_FN(ETH_TX_CLK),
544 GPIO_FN(DG0),
545 GPIO_FN(ETH_CRS),
546 GPIO_FN(DCLKIN),
547 GPIO_FN(HSPI_RX),
548 GPIO_FN(HSYNC),
549 GPIO_FN(HSPI_TX),
550 GPIO_FN(DB5),
551 GPIO_FN(ETH_RXD3),
552 GPIO_FN(DB4),
553 GPIO_FN(ETH_RXD2),
554 GPIO_FN(DB3),
555 GPIO_FN(ETH_RXD1),
556 GPIO_FN(DB2),
557 GPIO_FN(ETH_RXD0),
558 GPIO_FN(DB1),
559 GPIO_FN(ETH_RX_DV),
560 GPIO_FN(DB0),
561 GPIO_FN(ETH_RX_ER),
562 GPIO_FN(DCLKOUT),
563 GPIO_FN(SCIF1_SCK),
564 GPIO_FN(SCIF1_RXD),
565 GPIO_FN(SCIF1_TXD),
566 GPIO_FN(DACK1),
567 GPIO_FN(BACK),
568 GPIO_FN(FALE),
569 GPIO_FN(DACK0),
570 GPIO_FN(FCLE),
571 GPIO_FN(DREQ1),
572 GPIO_FN(BREQ),
573 GPIO_FN(USB_OVC1),
574 GPIO_FN(DREQ0),
575 GPIO_FN(USB_OVC0),
576 GPIO_FN(USB_PENC1),
577 GPIO_FN(USB_PENC0),
578 GPIO_FN(HAC1_SDOUT),
579 GPIO_FN(SSI1_SDATA),
580 GPIO_FN(SDIF1CMD),
581 GPIO_FN(HAC1_SDIN),
582 GPIO_FN(SSI1_SCK),
583 GPIO_FN(SDIF1CD),
584 GPIO_FN(HAC1_SYNC),
585 GPIO_FN(SSI1_WS),
586 GPIO_FN(SDIF1WP),
587 GPIO_FN(HAC1_BITCLK),
588 GPIO_FN(SSI1_CLK),
589 GPIO_FN(SDIF1CLK),
590 GPIO_FN(HAC0_SDOUT),
591 GPIO_FN(SSI0_SDATA),
592 GPIO_FN(SDIF1D3),
593 GPIO_FN(HAC0_SDIN),
594 GPIO_FN(SSI0_SCK),
595 GPIO_FN(SDIF1D2),
596 GPIO_FN(HAC0_SYNC),
597 GPIO_FN(SSI0_WS),
598 GPIO_FN(SDIF1D1),
599 GPIO_FN(HAC0_BITCLK),
600 GPIO_FN(SSI0_CLK),
601 GPIO_FN(SDIF1D0),
602 GPIO_FN(SCIF3_SCK),
603 GPIO_FN(SSI2_SDATA),
604 GPIO_FN(SCIF3_RXD),
605 GPIO_FN(TCLK),
606 GPIO_FN(SSI2_SCK),
607 GPIO_FN(SCIF3_TXD),
608 GPIO_FN(HAC_RES),
609 GPIO_FN(SSI2_WS),
610 GPIO_FN(DACK3),
611 GPIO_FN(SDIF0CMD),
612 GPIO_FN(DACK2),
613 GPIO_FN(SDIF0CD),
614 GPIO_FN(DREQ3),
615 GPIO_FN(SDIF0WP),
616 GPIO_FN(SCIF0_CTS),
617 GPIO_FN(DREQ2),
618 GPIO_FN(SDIF0CLK),
619 GPIO_FN(SCIF0_RTS),
620 GPIO_FN(IRL7),
621 GPIO_FN(SDIF0D3),
622 GPIO_FN(SCIF0_SCK),
623 GPIO_FN(IRL6),
624 GPIO_FN(SDIF0D2),
625 GPIO_FN(SCIF0_RXD),
626 GPIO_FN(IRL5),
627 GPIO_FN(SDIF0D1),
628 GPIO_FN(SCIF0_TXD),
629 GPIO_FN(IRL4),
630 GPIO_FN(SDIF0D0),
631 GPIO_FN(SCIF5_SCK),
632 GPIO_FN(FRB),
633 GPIO_FN(SCIF5_RXD),
634 GPIO_FN(IOIS16),
635 GPIO_FN(SCIF5_TXD),
636 GPIO_FN(CE2B),
637 GPIO_FN(DRAK3),
638 GPIO_FN(CE2A),
639 GPIO_FN(SCIF4_SCK),
640 GPIO_FN(DRAK2),
641 GPIO_FN(SSI3_WS),
642 GPIO_FN(SCIF4_RXD),
643 GPIO_FN(DRAK1),
644 GPIO_FN(SSI3_SDATA),
645 GPIO_FN(FSTATUS),
646 GPIO_FN(SCIF4_TXD),
647 GPIO_FN(DRAK0),
648 GPIO_FN(SSI3_SCK),
649 GPIO_FN(FSE),
650 };
651
652 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
653 { PINMUX_CFG_REG("PACR", 0xffcc0000, 16, 2) {
654 PA7_FN, PA7_OUT, PA7_IN, PA7_IN_PU,
655 PA6_FN, PA6_OUT, PA6_IN, PA6_IN_PU,
656 PA5_FN, PA5_OUT, PA5_IN, PA5_IN_PU,
657 PA4_FN, PA4_OUT, PA4_IN, PA4_IN_PU,
658 PA3_FN, PA3_OUT, PA3_IN, PA3_IN_PU,
659 PA2_FN, PA2_OUT, PA2_IN, PA2_IN_PU,
660 PA1_FN, PA1_OUT, PA1_IN, PA1_IN_PU,
661 PA0_FN, PA0_OUT, PA0_IN, PA0_IN_PU }
662 },
663 { PINMUX_CFG_REG("PBCR", 0xffcc0002, 16, 2) {
664 PB7_FN, PB7_OUT, PB7_IN, PB7_IN_PU,
665 PB6_FN, PB6_OUT, PB6_IN, PB6_IN_PU,
666 PB5_FN, PB5_OUT, PB5_IN, PB5_IN_PU,
667 PB4_FN, PB4_OUT, PB4_IN, PB4_IN_PU,
668 PB3_FN, PB3_OUT, PB3_IN, PB3_IN_PU,
669 PB2_FN, PB2_OUT, PB2_IN, PB2_IN_PU,
670 PB1_FN, PB1_OUT, PB1_IN, PB1_IN_PU,
671 PB0_FN, PB0_OUT, PB0_IN, PB0_IN_PU }
672 },
673 { PINMUX_CFG_REG("PCCR", 0xffcc0004, 16, 2) {
674 PC7_FN, PC7_OUT, PC7_IN, PC7_IN_PU,
675 PC6_FN, PC6_OUT, PC6_IN, PC6_IN_PU,
676 PC5_FN, PC5_OUT, PC5_IN, PC5_IN_PU,
677 PC4_FN, PC4_OUT, PC4_IN, PC4_IN_PU,
678 PC3_FN, PC3_OUT, PC3_IN, PC3_IN_PU,
679 PC2_FN, PC2_OUT, PC2_IN, PC2_IN_PU,
680 PC1_FN, PC1_OUT, PC1_IN, PC1_IN_PU,
681 PC0_FN, PC0_OUT, PC0_IN, PC0_IN_PU }
682 },
683 { PINMUX_CFG_REG("PDCR", 0xffcc0006, 16, 2) {
684 PD7_FN, PD7_OUT, PD7_IN, PD7_IN_PU,
685 PD6_FN, PD6_OUT, PD6_IN, PD6_IN_PU,
686 PD5_FN, PD5_OUT, PD5_IN, PD5_IN_PU,
687 PD4_FN, PD4_OUT, PD4_IN, PD4_IN_PU,
688 PD3_FN, PD3_OUT, PD3_IN, PD3_IN_PU,
689 PD2_FN, PD2_OUT, PD2_IN, PD2_IN_PU,
690 PD1_FN, PD1_OUT, PD1_IN, PD1_IN_PU,
691 PD0_FN, PD0_OUT, PD0_IN, PD0_IN_PU }
692 },
693 { PINMUX_CFG_REG("PECR", 0xffcc0008, 16, 2) {
694 PE7_FN, PE7_OUT, PE7_IN, PE7_IN_PU,
695 PE6_FN, PE6_OUT, PE6_IN, PE6_IN_PU,
696 0, 0, 0, 0,
697 0, 0, 0, 0,
698 0, 0, 0, 0,
699 0, 0, 0, 0,
700 0, 0, 0, 0,
701 0, 0, 0, 0, }
702 },
703 { PINMUX_CFG_REG("PFCR", 0xffcc000a, 16, 2) {
704 PF7_FN, PF7_OUT, PF7_IN, PF7_IN_PU,
705 PF6_FN, PF6_OUT, PF6_IN, PF6_IN_PU,
706 PF5_FN, PF5_OUT, PF5_IN, PF5_IN_PU,
707 PF4_FN, PF4_OUT, PF4_IN, PF4_IN_PU,
708 PF3_FN, PF3_OUT, PF3_IN, PF3_IN_PU,
709 PF2_FN, PF2_OUT, PF2_IN, PF2_IN_PU,
710 PF1_FN, PF1_OUT, PF1_IN, PF1_IN_PU,
711 PF0_FN, PF0_OUT, PF0_IN, PF0_IN_PU }
712 },
713 { PINMUX_CFG_REG("PGCR", 0xffcc000c, 16, 2) {
714 PG7_FN, PG7_OUT, PG7_IN, PG7_IN_PU,
715 PG6_FN, PG6_OUT, PG6_IN, PG6_IN_PU,
716 PG5_FN, PG5_OUT, PG5_IN, PG5_IN_PU,
717 0, 0, 0, 0,
718 0, 0, 0, 0,
719 0, 0, 0, 0,
720 0, 0, 0, 0,
721 0, 0, 0, 0, }
722 },
723 { PINMUX_CFG_REG("PHCR", 0xffcc000e, 16, 2) {
724 PH7_FN, PH7_OUT, PH7_IN, PH7_IN_PU,
725 PH6_FN, PH6_OUT, PH6_IN, PH6_IN_PU,
726 PH5_FN, PH5_OUT, PH5_IN, PH5_IN_PU,
727 PH4_FN, PH4_OUT, PH4_IN, PH4_IN_PU,
728 PH3_FN, PH3_OUT, PH3_IN, PH3_IN_PU,
729 PH2_FN, PH2_OUT, PH2_IN, PH2_IN_PU,
730 PH1_FN, PH1_OUT, PH1_IN, PH1_IN_PU,
731 PH0_FN, PH0_OUT, PH0_IN, PH0_IN_PU }
732 },
733 { PINMUX_CFG_REG("PJCR", 0xffcc0010, 16, 2) {
734 PJ7_FN, PJ7_OUT, PJ7_IN, PJ7_IN_PU,
735 PJ6_FN, PJ6_OUT, PJ6_IN, PJ6_IN_PU,
736 PJ5_FN, PJ5_OUT, PJ5_IN, PJ5_IN_PU,
737 PJ4_FN, PJ4_OUT, PJ4_IN, PJ4_IN_PU,
738 PJ3_FN, PJ3_OUT, PJ3_IN, PJ3_IN_PU,
739 PJ2_FN, PJ2_OUT, PJ2_IN, PJ2_IN_PU,
740 PJ1_FN, PJ1_OUT, PJ1_IN, PJ1_IN_PU,
741 0, 0, 0, 0, }
742 },
743 { PINMUX_CFG_REG("P1MSELR", 0xffcc0080, 16, 1) {
744 0, 0,
745 P1MSEL14_0, P1MSEL14_1,
746 P1MSEL13_0, P1MSEL13_1,
747 P1MSEL12_0, P1MSEL12_1,
748 P1MSEL11_0, P1MSEL11_1,
749 P1MSEL10_0, P1MSEL10_1,
750 P1MSEL9_0, P1MSEL9_1,
751 P1MSEL8_0, P1MSEL8_1,
752 P1MSEL7_0, P1MSEL7_1,
753 P1MSEL6_0, P1MSEL6_1,
754 P1MSEL5_0, P1MSEL5_1,
755 P1MSEL4_0, P1MSEL4_1,
756 P1MSEL3_0, P1MSEL3_1,
757 P1MSEL2_0, P1MSEL2_1,
758 P1MSEL1_0, P1MSEL1_1,
759 P1MSEL0_0, P1MSEL0_1 }
760 },
761 { PINMUX_CFG_REG("P2MSELR", 0xffcc0082, 16, 1) {
762 P2MSEL15_0, P2MSEL15_1,
763 P2MSEL14_0, P2MSEL14_1,
764 P2MSEL13_0, P2MSEL13_1,
765 P2MSEL12_0, P2MSEL12_1,
766 P2MSEL11_0, P2MSEL11_1,
767 P2MSEL10_0, P2MSEL10_1,
768 P2MSEL9_0, P2MSEL9_1,
769 P2MSEL8_0, P2MSEL8_1,
770 P2MSEL7_0, P2MSEL7_1,
771 P2MSEL6_0, P2MSEL6_1,
772 P2MSEL5_0, P2MSEL5_1,
773 P2MSEL4_0, P2MSEL4_1,
774 P2MSEL3_0, P2MSEL3_1,
775 P2MSEL2_0, P2MSEL2_1,
776 P2MSEL1_0, P2MSEL1_1,
777 P2MSEL0_0, P2MSEL0_1 }
778 },
779 {}
780 };
781
782 static const struct pinmux_data_reg pinmux_data_regs[] = {
783 { PINMUX_DATA_REG("PADR", 0xffcc0020, 8) {
784 PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
785 PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA }
786 },
787 { PINMUX_DATA_REG("PBDR", 0xffcc0022, 8) {
788 PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
789 PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA }
790 },
791 { PINMUX_DATA_REG("PCDR", 0xffcc0024, 8) {
792 PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
793 PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA }
794 },
795 { PINMUX_DATA_REG("PDDR", 0xffcc0026, 8) {
796 PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
797 PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA }
798 },
799 { PINMUX_DATA_REG("PEDR", 0xffcc0028, 8) {
800 PE7_DATA, PE6_DATA,
801 0, 0, 0, 0, 0, 0 }
802 },
803 { PINMUX_DATA_REG("PFDR", 0xffcc002a, 8) {
804 PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
805 PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA }
806 },
807 { PINMUX_DATA_REG("PGDR", 0xffcc002c, 8) {
808 PG7_DATA, PG6_DATA, PG5_DATA, 0,
809 0, 0, 0, 0 }
810 },
811 { PINMUX_DATA_REG("PHDR", 0xffcc002e, 8) {
812 PH7_DATA, PH6_DATA, PH5_DATA, PH4_DATA,
813 PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA }
814 },
815 { PINMUX_DATA_REG("PJDR", 0xffcc0030, 8) {
816 PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA,
817 PJ3_DATA, PJ2_DATA, PJ1_DATA, 0 }
818 },
819 { },
820 };
821
822 const struct sh_pfc_soc_info sh7786_pinmux_info = {
823 .name = "sh7786_pfc",
824 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
825 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
826 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
827 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
828
829 .pins = pinmux_pins,
830 .nr_pins = ARRAY_SIZE(pinmux_pins),
831 .func_gpios = pinmux_func_gpios,
832 .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
833
834 .cfg_regs = pinmux_config_regs,
835 .data_regs = pinmux_data_regs,
836
837 .gpio_data = pinmux_data,
838 .gpio_data_size = ARRAY_SIZE(pinmux_data),
839 };
CRIS linux kernel tree