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Linux 3.11-rc3
[cris-mirror.git] / drivers / tty / serial / amba-pl011.c
blob28b35ad9c6cd361818d94c0cde6ee2aa987979c0
1 /*
2 * Driver for AMBA serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright 1999 ARM Limited
7 * Copyright (C) 2000 Deep Blue Solutions Ltd.
8 * Copyright (C) 2010 ST-Ericsson SA
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 * This is a generic driver for ARM AMBA-type serial ports. They
25 * have a lot of 16550-like features, but are not register compatible.
26 * Note that although they do have CTS, DCD and DSR inputs, they do
27 * not have an RI input, nor do they have DTR or RTS outputs. If
28 * required, these have to be supplied via some other means (eg, GPIO)
29 * and hooked into this driver.
30 */
31
32
33 #if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
34 #define SUPPORT_SYSRQ
35 #endif
36
37 #include <linux/module.h>
38 #include <linux/ioport.h>
39 #include <linux/init.h>
40 #include <linux/console.h>
41 #include <linux/sysrq.h>
42 #include <linux/device.h>
43 #include <linux/tty.h>
44 #include <linux/tty_flip.h>
45 #include <linux/serial_core.h>
46 #include <linux/serial.h>
47 #include <linux/amba/bus.h>
48 #include <linux/amba/serial.h>
49 #include <linux/clk.h>
50 #include <linux/slab.h>
51 #include <linux/dmaengine.h>
52 #include <linux/dma-mapping.h>
53 #include <linux/scatterlist.h>
54 #include <linux/delay.h>
55 #include <linux/types.h>
56 #include <linux/of.h>
57 #include <linux/of_device.h>
58 #include <linux/pinctrl/consumer.h>
59 #include <linux/sizes.h>
60 #include <linux/io.h>
61
62 #define UART_NR 14
63
64 #define SERIAL_AMBA_MAJOR 204
65 #define SERIAL_AMBA_MINOR 64
66 #define SERIAL_AMBA_NR UART_NR
67
68 #define AMBA_ISR_PASS_LIMIT 256
69
70 #define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
71 #define UART_DUMMY_DR_RX (1 << 16)
72
73 /* There is by now at least one vendor with differing details, so handle it */
74 struct vendor_data {
75 unsigned int ifls;
76 unsigned int lcrh_tx;
77 unsigned int lcrh_rx;
78 bool oversampling;
79 bool dma_threshold;
80 bool cts_event_workaround;
81
82 unsigned int (*get_fifosize)(struct amba_device *dev);
83 };
84
85 static unsigned int get_fifosize_arm(struct amba_device *dev)
86 {
87 return amba_rev(dev) < 3 ? 16 : 32;
88 }
89
90 static struct vendor_data vendor_arm = {
91 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
92 .lcrh_tx = UART011_LCRH,
93 .lcrh_rx = UART011_LCRH,
94 .oversampling = false,
95 .dma_threshold = false,
96 .cts_event_workaround = false,
97 .get_fifosize = get_fifosize_arm,
98 };
99
100 static unsigned int get_fifosize_st(struct amba_device *dev)
101 {
102 return 64;
103 }
104
105 static struct vendor_data vendor_st = {
106 .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF,
107 .lcrh_tx = ST_UART011_LCRH_TX,
108 .lcrh_rx = ST_UART011_LCRH_RX,
109 .oversampling = true,
110 .dma_threshold = true,
111 .cts_event_workaround = true,
112 .get_fifosize = get_fifosize_st,
113 };
114
115 static struct uart_amba_port *amba_ports[UART_NR];
116
117 /* Deals with DMA transactions */
118
119 struct pl011_sgbuf {
120 struct scatterlist sg;
121 char *buf;
122 };
123
124 struct pl011_dmarx_data {
125 struct dma_chan *chan;
126 struct completion complete;
127 bool use_buf_b;
128 struct pl011_sgbuf sgbuf_a;
129 struct pl011_sgbuf sgbuf_b;
130 dma_cookie_t cookie;
131 bool running;
132 struct timer_list timer;
133 unsigned int last_residue;
134 unsigned long last_jiffies;
135 bool auto_poll_rate;
136 unsigned int poll_rate;
137 unsigned int poll_timeout;
138 };
139
140 struct pl011_dmatx_data {
141 struct dma_chan *chan;
142 struct scatterlist sg;
143 char *buf;
144 bool queued;
145 };
146
147 /*
148 * We wrap our port structure around the generic uart_port.
149 */
150 struct uart_amba_port {
151 struct uart_port port;
152 struct clk *clk;
153 const struct vendor_data *vendor;
154 unsigned int dmacr; /* dma control reg */
155 unsigned int im; /* interrupt mask */
156 unsigned int old_status;
157 unsigned int fifosize; /* vendor-specific */
158 unsigned int lcrh_tx; /* vendor-specific */
159 unsigned int lcrh_rx; /* vendor-specific */
160 unsigned int old_cr; /* state during shutdown */
161 bool autorts;
162 char type[12];
163 #ifdef CONFIG_DMA_ENGINE
164 /* DMA stuff */
165 bool using_tx_dma;
166 bool using_rx_dma;
167 struct pl011_dmarx_data dmarx;
168 struct pl011_dmatx_data dmatx;
169 #endif
170 };
171
172 /*
173 * Reads up to 256 characters from the FIFO or until it's empty and
174 * inserts them into the TTY layer. Returns the number of characters
175 * read from the FIFO.
176 */
177 static int pl011_fifo_to_tty(struct uart_amba_port *uap)
178 {
179 u16 status, ch;
180 unsigned int flag, max_count = 256;
181 int fifotaken = 0;
182
183 while (max_count--) {
184 status = readw(uap->port.membase + UART01x_FR);
185 if (status & UART01x_FR_RXFE)
186 break;
187
188 /* Take chars from the FIFO and update status */
189 ch = readw(uap->port.membase + UART01x_DR) |
190 UART_DUMMY_DR_RX;
191 flag = TTY_NORMAL;
192 uap->port.icount.rx++;
193 fifotaken++;
194
195 if (unlikely(ch & UART_DR_ERROR)) {
196 if (ch & UART011_DR_BE) {
197 ch &= ~(UART011_DR_FE | UART011_DR_PE);
198 uap->port.icount.brk++;
199 if (uart_handle_break(&uap->port))
200 continue;
201 } else if (ch & UART011_DR_PE)
202 uap->port.icount.parity++;
203 else if (ch & UART011_DR_FE)
204 uap->port.icount.frame++;
205 if (ch & UART011_DR_OE)
206 uap->port.icount.overrun++;
207
208 ch &= uap->port.read_status_mask;
209
210 if (ch & UART011_DR_BE)
211 flag = TTY_BREAK;
212 else if (ch & UART011_DR_PE)
213 flag = TTY_PARITY;
214 else if (ch & UART011_DR_FE)
215 flag = TTY_FRAME;
216 }
217
218 if (uart_handle_sysrq_char(&uap->port, ch & 255))
219 continue;
220
221 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
222 }
223
224 return fifotaken;
225 }
226
227
228 /*
229 * All the DMA operation mode stuff goes inside this ifdef.
230 * This assumes that you have a generic DMA device interface,
231 * no custom DMA interfaces are supported.
232 */
233 #ifdef CONFIG_DMA_ENGINE
234
235 #define PL011_DMA_BUFFER_SIZE PAGE_SIZE
236
237 static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg,
238 enum dma_data_direction dir)
239 {
240 dma_addr_t dma_addr;
241
242 sg->buf = dma_alloc_coherent(chan->device->dev,
243 PL011_DMA_BUFFER_SIZE, &dma_addr, GFP_KERNEL);
244 if (!sg->buf)
245 return -ENOMEM;
246
247 sg_init_table(&sg->sg, 1);
248 sg_set_page(&sg->sg, phys_to_page(dma_addr),
249 PL011_DMA_BUFFER_SIZE, offset_in_page(dma_addr));
250 sg_dma_address(&sg->sg) = dma_addr;
251
252 return 0;
253 }
254
255 static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg,
256 enum dma_data_direction dir)
257 {
258 if (sg->buf) {
259 dma_free_coherent(chan->device->dev,
260 PL011_DMA_BUFFER_SIZE, sg->buf,
261 sg_dma_address(&sg->sg));
262 }
263 }
264
265 static void pl011_dma_probe_initcall(struct device *dev, struct uart_amba_port *uap)
266 {
267 /* DMA is the sole user of the platform data right now */
268 struct amba_pl011_data *plat = uap->port.dev->platform_data;
269 struct dma_slave_config tx_conf = {
270 .dst_addr = uap->port.mapbase + UART01x_DR,
271 .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
272 .direction = DMA_MEM_TO_DEV,
273 .dst_maxburst = uap->fifosize >> 1,
274 .device_fc = false,
275 };
276 struct dma_chan *chan;
277 dma_cap_mask_t mask;
278
279 chan = dma_request_slave_channel(dev, "tx");
280
281 if (!chan) {
282 /* We need platform data */
283 if (!plat || !plat->dma_filter) {
284 dev_info(uap->port.dev, "no DMA platform data\n");
285 return;
286 }
287
288 /* Try to acquire a generic DMA engine slave TX channel */
289 dma_cap_zero(mask);
290 dma_cap_set(DMA_SLAVE, mask);
291
292 chan = dma_request_channel(mask, plat->dma_filter,
293 plat->dma_tx_param);
294 if (!chan) {
295 dev_err(uap->port.dev, "no TX DMA channel!\n");
296 return;
297 }
298 }
299
300 dmaengine_slave_config(chan, &tx_conf);
301 uap->dmatx.chan = chan;
302
303 dev_info(uap->port.dev, "DMA channel TX %s\n",
304 dma_chan_name(uap->dmatx.chan));
305
306 /* Optionally make use of an RX channel as well */
307 chan = dma_request_slave_channel(dev, "rx");
308
309 if (!chan && plat->dma_rx_param) {
310 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param);
311
312 if (!chan) {
313 dev_err(uap->port.dev, "no RX DMA channel!\n");
314 return;
315 }
316 }
317
318 if (chan) {
319 struct dma_slave_config rx_conf = {
320 .src_addr = uap->port.mapbase + UART01x_DR,
321 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
322 .direction = DMA_DEV_TO_MEM,
323 .src_maxburst = uap->fifosize >> 1,
324 .device_fc = false,
325 };
326
327 dmaengine_slave_config(chan, &rx_conf);
328 uap->dmarx.chan = chan;
329
330 if (plat && plat->dma_rx_poll_enable) {
331 /* Set poll rate if specified. */
332 if (plat->dma_rx_poll_rate) {
333 uap->dmarx.auto_poll_rate = false;
334 uap->dmarx.poll_rate = plat->dma_rx_poll_rate;
335 } else {
336 /*
337 * 100 ms defaults to poll rate if not
338 * specified. This will be adjusted with
339 * the baud rate at set_termios.
340 */
341 uap->dmarx.auto_poll_rate = true;
342 uap->dmarx.poll_rate = 100;
343 }
344 /* 3 secs defaults poll_timeout if not specified. */
345 if (plat->dma_rx_poll_timeout)
346 uap->dmarx.poll_timeout =
347 plat->dma_rx_poll_timeout;
348 else
349 uap->dmarx.poll_timeout = 3000;
350 } else
351 uap->dmarx.auto_poll_rate = false;
352
353 dev_info(uap->port.dev, "DMA channel RX %s\n",
354 dma_chan_name(uap->dmarx.chan));
355 }
356 }
357
358 #ifndef MODULE
359 /*
360 * Stack up the UARTs and let the above initcall be done at device
361 * initcall time, because the serial driver is called as an arch
362 * initcall, and at this time the DMA subsystem is not yet registered.
363 * At this point the driver will switch over to using DMA where desired.
364 */
365 struct dma_uap {
366 struct list_head node;
367 struct uart_amba_port *uap;
368 struct device *dev;
369 };
370
371 static LIST_HEAD(pl011_dma_uarts);
372
373 static int __init pl011_dma_initcall(void)
374 {
375 struct list_head *node, *tmp;
376
377 list_for_each_safe(node, tmp, &pl011_dma_uarts) {
378 struct dma_uap *dmau = list_entry(node, struct dma_uap, node);
379 pl011_dma_probe_initcall(dmau->dev, dmau->uap);
380 list_del(node);
381 kfree(dmau);
382 }
383 return 0;
384 }
385
386 device_initcall(pl011_dma_initcall);
387
388 static void pl011_dma_probe(struct device *dev, struct uart_amba_port *uap)
389 {
390 struct dma_uap *dmau = kzalloc(sizeof(struct dma_uap), GFP_KERNEL);
391 if (dmau) {
392 dmau->uap = uap;
393 dmau->dev = dev;
394 list_add_tail(&dmau->node, &pl011_dma_uarts);
395 }
396 }
397 #else
398 static void pl011_dma_probe(struct device *dev, struct uart_amba_port *uap)
399 {
400 pl011_dma_probe_initcall(dev, uap);
401 }
402 #endif
403
404 static void pl011_dma_remove(struct uart_amba_port *uap)
405 {
406 /* TODO: remove the initcall if it has not yet executed */
407 if (uap->dmatx.chan)
408 dma_release_channel(uap->dmatx.chan);
409 if (uap->dmarx.chan)
410 dma_release_channel(uap->dmarx.chan);
411 }
412
413 /* Forward declare this for the refill routine */
414 static int pl011_dma_tx_refill(struct uart_amba_port *uap);
415
416 /*
417 * The current DMA TX buffer has been sent.
418 * Try to queue up another DMA buffer.
419 */
420 static void pl011_dma_tx_callback(void *data)
421 {
422 struct uart_amba_port *uap = data;
423 struct pl011_dmatx_data *dmatx = &uap->dmatx;
424 unsigned long flags;
425 u16 dmacr;
426
427 spin_lock_irqsave(&uap->port.lock, flags);
428 if (uap->dmatx.queued)
429 dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1,
430 DMA_TO_DEVICE);
431
432 dmacr = uap->dmacr;
433 uap->dmacr = dmacr & ~UART011_TXDMAE;
434 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
435
436 /*
437 * If TX DMA was disabled, it means that we've stopped the DMA for
438 * some reason (eg, XOFF received, or we want to send an X-char.)
439 *
440 * Note: we need to be careful here of a potential race between DMA
441 * and the rest of the driver - if the driver disables TX DMA while
442 * a TX buffer completing, we must update the tx queued status to
443 * get further refills (hence we check dmacr).
444 */
445 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) ||
446 uart_circ_empty(&uap->port.state->xmit)) {
447 uap->dmatx.queued = false;
448 spin_unlock_irqrestore(&uap->port.lock, flags);
449 return;
450 }
451
452 if (pl011_dma_tx_refill(uap) <= 0) {
453 /*
454 * We didn't queue a DMA buffer for some reason, but we
455 * have data pending to be sent. Re-enable the TX IRQ.
456 */
457 uap->im |= UART011_TXIM;
458 writew(uap->im, uap->port.membase + UART011_IMSC);
459 }
460 spin_unlock_irqrestore(&uap->port.lock, flags);
461 }
462
463 /*
464 * Try to refill the TX DMA buffer.
465 * Locking: called with port lock held and IRQs disabled.
466 * Returns:
467 * 1 if we queued up a TX DMA buffer.
468 * 0 if we didn't want to handle this by DMA
469 * <0 on error
470 */
471 static int pl011_dma_tx_refill(struct uart_amba_port *uap)
472 {
473 struct pl011_dmatx_data *dmatx = &uap->dmatx;
474 struct dma_chan *chan = dmatx->chan;
475 struct dma_device *dma_dev = chan->device;
476 struct dma_async_tx_descriptor *desc;
477 struct circ_buf *xmit = &uap->port.state->xmit;
478 unsigned int count;
479
480 /*
481 * Try to avoid the overhead involved in using DMA if the
482 * transaction fits in the first half of the FIFO, by using
483 * the standard interrupt handling. This ensures that we
484 * issue a uart_write_wakeup() at the appropriate time.
485 */
486 count = uart_circ_chars_pending(xmit);
487 if (count < (uap->fifosize >> 1)) {
488 uap->dmatx.queued = false;
489 return 0;
490 }
491
492 /*
493 * Bodge: don't send the last character by DMA, as this
494 * will prevent XON from notifying us to restart DMA.
495 */
496 count -= 1;
497
498 /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */
499 if (count > PL011_DMA_BUFFER_SIZE)
500 count = PL011_DMA_BUFFER_SIZE;
501
502 if (xmit->tail < xmit->head)
503 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count);
504 else {
505 size_t first = UART_XMIT_SIZE - xmit->tail;
506 size_t second = xmit->head;
507
508 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first);
509 if (second)
510 memcpy(&dmatx->buf[first], &xmit->buf[0], second);
511 }
512
513 dmatx->sg.length = count;
514
515 if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) {
516 uap->dmatx.queued = false;
517 dev_dbg(uap->port.dev, "unable to map TX DMA\n");
518 return -EBUSY;
519 }
520
521 desc = dmaengine_prep_slave_sg(chan, &dmatx->sg, 1, DMA_MEM_TO_DEV,
522 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
523 if (!desc) {
524 dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE);
525 uap->dmatx.queued = false;
526 /*
527 * If DMA cannot be used right now, we complete this
528 * transaction via IRQ and let the TTY layer retry.
529 */
530 dev_dbg(uap->port.dev, "TX DMA busy\n");
531 return -EBUSY;
532 }
533
534 /* Some data to go along to the callback */
535 desc->callback = pl011_dma_tx_callback;
536 desc->callback_param = uap;
537
538 /* All errors should happen at prepare time */
539 dmaengine_submit(desc);
540
541 /* Fire the DMA transaction */
542 dma_dev->device_issue_pending(chan);
543
544 uap->dmacr |= UART011_TXDMAE;
545 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
546 uap->dmatx.queued = true;
547
548 /*
549 * Now we know that DMA will fire, so advance the ring buffer
550 * with the stuff we just dispatched.
551 */
552 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
553 uap->port.icount.tx += count;
554
555 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
556 uart_write_wakeup(&uap->port);
557
558 return 1;
559 }
560
561 /*
562 * We received a transmit interrupt without a pending X-char but with
563 * pending characters.
564 * Locking: called with port lock held and IRQs disabled.
565 * Returns:
566 * false if we want to use PIO to transmit
567 * true if we queued a DMA buffer
568 */
569 static bool pl011_dma_tx_irq(struct uart_amba_port *uap)
570 {
571 if (!uap->using_tx_dma)
572 return false;
573
574 /*
575 * If we already have a TX buffer queued, but received a
576 * TX interrupt, it will be because we've just sent an X-char.
577 * Ensure the TX DMA is enabled and the TX IRQ is disabled.
578 */
579 if (uap->dmatx.queued) {
580 uap->dmacr |= UART011_TXDMAE;
581 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
582 uap->im &= ~UART011_TXIM;
583 writew(uap->im, uap->port.membase + UART011_IMSC);
584 return true;
585 }
586
587 /*
588 * We don't have a TX buffer queued, so try to queue one.
589 * If we successfully queued a buffer, mask the TX IRQ.
590 */
591 if (pl011_dma_tx_refill(uap) > 0) {
592 uap->im &= ~UART011_TXIM;
593 writew(uap->im, uap->port.membase + UART011_IMSC);
594 return true;
595 }
596 return false;
597 }
598
599 /*
600 * Stop the DMA transmit (eg, due to received XOFF).
601 * Locking: called with port lock held and IRQs disabled.
602 */
603 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
604 {
605 if (uap->dmatx.queued) {
606 uap->dmacr &= ~UART011_TXDMAE;
607 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
608 }
609 }
610
611 /*
612 * Try to start a DMA transmit, or in the case of an XON/OFF
613 * character queued for send, try to get that character out ASAP.
614 * Locking: called with port lock held and IRQs disabled.
615 * Returns:
616 * false if we want the TX IRQ to be enabled
617 * true if we have a buffer queued
618 */
619 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
620 {
621 u16 dmacr;
622
623 if (!uap->using_tx_dma)
624 return false;
625
626 if (!uap->port.x_char) {
627 /* no X-char, try to push chars out in DMA mode */
628 bool ret = true;
629
630 if (!uap->dmatx.queued) {
631 if (pl011_dma_tx_refill(uap) > 0) {
632 uap->im &= ~UART011_TXIM;
633 ret = true;
634 } else {
635 uap->im |= UART011_TXIM;
636 ret = false;
637 }
638 writew(uap->im, uap->port.membase + UART011_IMSC);
639 } else if (!(uap->dmacr & UART011_TXDMAE)) {
640 uap->dmacr |= UART011_TXDMAE;
641 writew(uap->dmacr,
642 uap->port.membase + UART011_DMACR);
643 }
644 return ret;
645 }
646
647 /*
648 * We have an X-char to send. Disable DMA to prevent it loading
649 * the TX fifo, and then see if we can stuff it into the FIFO.
650 */
651 dmacr = uap->dmacr;
652 uap->dmacr &= ~UART011_TXDMAE;
653 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
654
655 if (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) {
656 /*
657 * No space in the FIFO, so enable the transmit interrupt
658 * so we know when there is space. Note that once we've
659 * loaded the character, we should just re-enable DMA.
660 */
661 return false;
662 }
663
664 writew(uap->port.x_char, uap->port.membase + UART01x_DR);
665 uap->port.icount.tx++;
666 uap->port.x_char = 0;
667
668 /* Success - restore the DMA state */
669 uap->dmacr = dmacr;
670 writew(dmacr, uap->port.membase + UART011_DMACR);
671
672 return true;
673 }
674
675 /*
676 * Flush the transmit buffer.
677 * Locking: called with port lock held and IRQs disabled.
678 */
679 static void pl011_dma_flush_buffer(struct uart_port *port)
680 {
681 struct uart_amba_port *uap = (struct uart_amba_port *)port;
682
683 if (!uap->using_tx_dma)
684 return;
685
686 /* Avoid deadlock with the DMA engine callback */
687 spin_unlock(&uap->port.lock);
688 dmaengine_terminate_all(uap->dmatx.chan);
689 spin_lock(&uap->port.lock);
690 if (uap->dmatx.queued) {
691 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
692 DMA_TO_DEVICE);
693 uap->dmatx.queued = false;
694 uap->dmacr &= ~UART011_TXDMAE;
695 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
696 }
697 }
698
699 static void pl011_dma_rx_callback(void *data);
700
701 static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
702 {
703 struct dma_chan *rxchan = uap->dmarx.chan;
704 struct pl011_dmarx_data *dmarx = &uap->dmarx;
705 struct dma_async_tx_descriptor *desc;
706 struct pl011_sgbuf *sgbuf;
707
708 if (!rxchan)
709 return -EIO;
710
711 /* Start the RX DMA job */
712 sgbuf = uap->dmarx.use_buf_b ?
713 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
714 desc = dmaengine_prep_slave_sg(rxchan, &sgbuf->sg, 1,
715 DMA_DEV_TO_MEM,
716 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
717 /*
718 * If the DMA engine is busy and cannot prepare a
719 * channel, no big deal, the driver will fall back
720 * to interrupt mode as a result of this error code.
721 */
722 if (!desc) {
723 uap->dmarx.running = false;
724 dmaengine_terminate_all(rxchan);
725 return -EBUSY;
726 }
727
728 /* Some data to go along to the callback */
729 desc->callback = pl011_dma_rx_callback;
730 desc->callback_param = uap;
731 dmarx->cookie = dmaengine_submit(desc);
732 dma_async_issue_pending(rxchan);
733
734 uap->dmacr |= UART011_RXDMAE;
735 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
736 uap->dmarx.running = true;
737
738 uap->im &= ~UART011_RXIM;
739 writew(uap->im, uap->port.membase + UART011_IMSC);
740
741 return 0;
742 }
743
744 /*
745 * This is called when either the DMA job is complete, or
746 * the FIFO timeout interrupt occurred. This must be called
747 * with the port spinlock uap->port.lock held.
748 */
749 static void pl011_dma_rx_chars(struct uart_amba_port *uap,
750 u32 pending, bool use_buf_b,
751 bool readfifo)
752 {
753 struct tty_port *port = &uap->port.state->port;
754 struct pl011_sgbuf *sgbuf = use_buf_b ?
755 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
756 int dma_count = 0;
757 u32 fifotaken = 0; /* only used for vdbg() */
758
759 struct pl011_dmarx_data *dmarx = &uap->dmarx;
760 int dmataken = 0;
761
762 if (uap->dmarx.poll_rate) {
763 /* The data can be taken by polling */
764 dmataken = sgbuf->sg.length - dmarx->last_residue;
765 /* Recalculate the pending size */
766 if (pending >= dmataken)
767 pending -= dmataken;
768 }
769
770 /* Pick the remain data from the DMA */
771 if (pending) {
772
773 /*
774 * First take all chars in the DMA pipe, then look in the FIFO.
775 * Note that tty_insert_flip_buf() tries to take as many chars
776 * as it can.
777 */
778 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken,
779 pending);
780
781 uap->port.icount.rx += dma_count;
782 if (dma_count < pending)
783 dev_warn(uap->port.dev,
784 "couldn't insert all characters (TTY is full?)\n");
785 }
786
787 /* Reset the last_residue for Rx DMA poll */
788 if (uap->dmarx.poll_rate)
789 dmarx->last_residue = sgbuf->sg.length;
790
791 /*
792 * Only continue with trying to read the FIFO if all DMA chars have
793 * been taken first.
794 */
795 if (dma_count == pending && readfifo) {
796 /* Clear any error flags */
797 writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS,
798 uap->port.membase + UART011_ICR);
799
800 /*
801 * If we read all the DMA'd characters, and we had an
802 * incomplete buffer, that could be due to an rx error, or
803 * maybe we just timed out. Read any pending chars and check
804 * the error status.
805 *
806 * Error conditions will only occur in the FIFO, these will
807 * trigger an immediate interrupt and stop the DMA job, so we
808 * will always find the error in the FIFO, never in the DMA
809 * buffer.
810 */
811 fifotaken = pl011_fifo_to_tty(uap);
812 }
813
814 spin_unlock(&uap->port.lock);
815 dev_vdbg(uap->port.dev,
816 "Took %d chars from DMA buffer and %d chars from the FIFO\n",
817 dma_count, fifotaken);
818 tty_flip_buffer_push(port);
819 spin_lock(&uap->port.lock);
820 }
821
822 static void pl011_dma_rx_irq(struct uart_amba_port *uap)
823 {
824 struct pl011_dmarx_data *dmarx = &uap->dmarx;
825 struct dma_chan *rxchan = dmarx->chan;
826 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
827 &dmarx->sgbuf_b : &dmarx->sgbuf_a;
828 size_t pending;
829 struct dma_tx_state state;
830 enum dma_status dmastat;
831
832 /*
833 * Pause the transfer so we can trust the current counter,
834 * do this before we pause the PL011 block, else we may
835 * overflow the FIFO.
836 */
837 if (dmaengine_pause(rxchan))
838 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
839 dmastat = rxchan->device->device_tx_status(rxchan,
840 dmarx->cookie, &state);
841 if (dmastat != DMA_PAUSED)
842 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
843
844 /* Disable RX DMA - incoming data will wait in the FIFO */
845 uap->dmacr &= ~UART011_RXDMAE;
846 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
847 uap->dmarx.running = false;
848
849 pending = sgbuf->sg.length - state.residue;
850 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
851 /* Then we terminate the transfer - we now know our residue */
852 dmaengine_terminate_all(rxchan);
853
854 /*
855 * This will take the chars we have so far and insert
856 * into the framework.
857 */
858 pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true);
859
860 /* Switch buffer & re-trigger DMA job */
861 dmarx->use_buf_b = !dmarx->use_buf_b;
862 if (pl011_dma_rx_trigger_dma(uap)) {
863 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
864 "fall back to interrupt mode\n");
865 uap->im |= UART011_RXIM;
866 writew(uap->im, uap->port.membase + UART011_IMSC);
867 }
868 }
869
870 static void pl011_dma_rx_callback(void *data)
871 {
872 struct uart_amba_port *uap = data;
873 struct pl011_dmarx_data *dmarx = &uap->dmarx;
874 struct dma_chan *rxchan = dmarx->chan;
875 bool lastbuf = dmarx->use_buf_b;
876 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
877 &dmarx->sgbuf_b : &dmarx->sgbuf_a;
878 size_t pending;
879 struct dma_tx_state state;
880 int ret;
881
882 /*
883 * This completion interrupt occurs typically when the
884 * RX buffer is totally stuffed but no timeout has yet
885 * occurred. When that happens, we just want the RX
886 * routine to flush out the secondary DMA buffer while
887 * we immediately trigger the next DMA job.
888 */
889 spin_lock_irq(&uap->port.lock);
890 /*
891 * Rx data can be taken by the UART interrupts during
892 * the DMA irq handler. So we check the residue here.
893 */
894 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
895 pending = sgbuf->sg.length - state.residue;
896 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
897 /* Then we terminate the transfer - we now know our residue */
898 dmaengine_terminate_all(rxchan);
899
900 uap->dmarx.running = false;
901 dmarx->use_buf_b = !lastbuf;
902 ret = pl011_dma_rx_trigger_dma(uap);
903
904 pl011_dma_rx_chars(uap, pending, lastbuf, false);
905 spin_unlock_irq(&uap->port.lock);
906 /*
907 * Do this check after we picked the DMA chars so we don't
908 * get some IRQ immediately from RX.
909 */
910 if (ret) {
911 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
912 "fall back to interrupt mode\n");
913 uap->im |= UART011_RXIM;
914 writew(uap->im, uap->port.membase + UART011_IMSC);
915 }
916 }
917
918 /*
919 * Stop accepting received characters, when we're shutting down or
920 * suspending this port.
921 * Locking: called with port lock held and IRQs disabled.
922 */
923 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
924 {
925 /* FIXME. Just disable the DMA enable */
926 uap->dmacr &= ~UART011_RXDMAE;
927 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
928 }
929
930 /*
931 * Timer handler for Rx DMA polling.
932 * Every polling, It checks the residue in the dma buffer and transfer
933 * data to the tty. Also, last_residue is updated for the next polling.
934 */
935 static void pl011_dma_rx_poll(unsigned long args)
936 {
937 struct uart_amba_port *uap = (struct uart_amba_port *)args;
938 struct tty_port *port = &uap->port.state->port;
939 struct pl011_dmarx_data *dmarx = &uap->dmarx;
940 struct dma_chan *rxchan = uap->dmarx.chan;
941 unsigned long flags = 0;
942 unsigned int dmataken = 0;
943 unsigned int size = 0;
944 struct pl011_sgbuf *sgbuf;
945 int dma_count;
946 struct dma_tx_state state;
947
948 sgbuf = dmarx->use_buf_b ? &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
949 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
950 if (likely(state.residue < dmarx->last_residue)) {
951 dmataken = sgbuf->sg.length - dmarx->last_residue;
952 size = dmarx->last_residue - state.residue;
953 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken,
954 size);
955 if (dma_count == size)
956 dmarx->last_residue = state.residue;
957 dmarx->last_jiffies = jiffies;
958 }
959 tty_flip_buffer_push(port);
960
961 /*
962 * If no data is received in poll_timeout, the driver will fall back
963 * to interrupt mode. We will retrigger DMA at the first interrupt.
964 */
965 if (jiffies_to_msecs(jiffies - dmarx->last_jiffies)
966 > uap->dmarx.poll_timeout) {
967
968 spin_lock_irqsave(&uap->port.lock, flags);
969 pl011_dma_rx_stop(uap);
970 spin_unlock_irqrestore(&uap->port.lock, flags);
971
972 uap->dmarx.running = false;
973 dmaengine_terminate_all(rxchan);
974 del_timer(&uap->dmarx.timer);
975 } else {
976 mod_timer(&uap->dmarx.timer,
977 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate));
978 }
979 }
980
981 static void pl011_dma_startup(struct uart_amba_port *uap)
982 {
983 int ret;
984
985 if (!uap->dmatx.chan)
986 return;
987
988 uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL);
989 if (!uap->dmatx.buf) {
990 dev_err(uap->port.dev, "no memory for DMA TX buffer\n");
991 uap->port.fifosize = uap->fifosize;
992 return;
993 }
994
995 sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE);
996
997 /* The DMA buffer is now the FIFO the TTY subsystem can use */
998 uap->port.fifosize = PL011_DMA_BUFFER_SIZE;
999 uap->using_tx_dma = true;
1000
1001 if (!uap->dmarx.chan)
1002 goto skip_rx;
1003
1004 /* Allocate and map DMA RX buffers */
1005 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
1006 DMA_FROM_DEVICE);
1007 if (ret) {
1008 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
1009 "RX buffer A", ret);
1010 goto skip_rx;
1011 }
1012
1013 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_b,
1014 DMA_FROM_DEVICE);
1015 if (ret) {
1016 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
1017 "RX buffer B", ret);
1018 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
1019 DMA_FROM_DEVICE);
1020 goto skip_rx;
1021 }
1022
1023 uap->using_rx_dma = true;
1024
1025 skip_rx:
1026 /* Turn on DMA error (RX/TX will be enabled on demand) */
1027 uap->dmacr |= UART011_DMAONERR;
1028 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
1029
1030 /*
1031 * ST Micro variants has some specific dma burst threshold
1032 * compensation. Set this to 16 bytes, so burst will only
1033 * be issued above/below 16 bytes.
1034 */
1035 if (uap->vendor->dma_threshold)
1036 writew(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16,
1037 uap->port.membase + ST_UART011_DMAWM);
1038
1039 if (uap->using_rx_dma) {
1040 if (pl011_dma_rx_trigger_dma(uap))
1041 dev_dbg(uap->port.dev, "could not trigger initial "
1042 "RX DMA job, fall back to interrupt mode\n");
1043 if (uap->dmarx.poll_rate) {
1044 init_timer(&(uap->dmarx.timer));
1045 uap->dmarx.timer.function = pl011_dma_rx_poll;
1046 uap->dmarx.timer.data = (unsigned long)uap;
1047 mod_timer(&uap->dmarx.timer,
1048 jiffies +
1049 msecs_to_jiffies(uap->dmarx.poll_rate));
1050 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
1051 uap->dmarx.last_jiffies = jiffies;
1052 }
1053 }
1054 }
1055
1056 static void pl011_dma_shutdown(struct uart_amba_port *uap)
1057 {
1058 if (!(uap->using_tx_dma || uap->using_rx_dma))
1059 return;
1060
1061 /* Disable RX and TX DMA */
1062 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY)
1063 barrier();
1064
1065 spin_lock_irq(&uap->port.lock);
1066 uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE);
1067 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
1068 spin_unlock_irq(&uap->port.lock);
1069
1070 if (uap->using_tx_dma) {
1071 /* In theory, this should already be done by pl011_dma_flush_buffer */
1072 dmaengine_terminate_all(uap->dmatx.chan);
1073 if (uap->dmatx.queued) {
1074 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
1075 DMA_TO_DEVICE);
1076 uap->dmatx.queued = false;
1077 }
1078
1079 kfree(uap->dmatx.buf);
1080 uap->using_tx_dma = false;
1081 }
1082
1083 if (uap->using_rx_dma) {
1084 dmaengine_terminate_all(uap->dmarx.chan);
1085 /* Clean up the RX DMA */
1086 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, DMA_FROM_DEVICE);
1087 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_b, DMA_FROM_DEVICE);
1088 if (uap->dmarx.poll_rate)
1089 del_timer_sync(&uap->dmarx.timer);
1090 uap->using_rx_dma = false;
1091 }
1092 }
1093
1094 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1095 {
1096 return uap->using_rx_dma;
1097 }
1098
1099 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1100 {
1101 return uap->using_rx_dma && uap->dmarx.running;
1102 }
1103
1104 #else
1105 /* Blank functions if the DMA engine is not available */
1106 static inline void pl011_dma_probe(struct device *dev, struct uart_amba_port *uap)
1107 {
1108 }
1109
1110 static inline void pl011_dma_remove(struct uart_amba_port *uap)
1111 {
1112 }
1113
1114 static inline void pl011_dma_startup(struct uart_amba_port *uap)
1115 {
1116 }
1117
1118 static inline void pl011_dma_shutdown(struct uart_amba_port *uap)
1119 {
1120 }
1121
1122 static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap)
1123 {
1124 return false;
1125 }
1126
1127 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
1128 {
1129 }
1130
1131 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
1132 {
1133 return false;
1134 }
1135
1136 static inline void pl011_dma_rx_irq(struct uart_amba_port *uap)
1137 {
1138 }
1139
1140 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1141 {
1142 }
1143
1144 static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
1145 {
1146 return -EIO;
1147 }
1148
1149 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1150 {
1151 return false;
1152 }
1153
1154 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1155 {
1156 return false;
1157 }
1158
1159 #define pl011_dma_flush_buffer NULL
1160 #endif
1161
1162 static void pl011_stop_tx(struct uart_port *port)
1163 {
1164 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1165
1166 uap->im &= ~UART011_TXIM;
1167 writew(uap->im, uap->port.membase + UART011_IMSC);
1168 pl011_dma_tx_stop(uap);
1169 }
1170
1171 static void pl011_start_tx(struct uart_port *port)
1172 {
1173 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1174
1175 if (!pl011_dma_tx_start(uap)) {
1176 uap->im |= UART011_TXIM;
1177 writew(uap->im, uap->port.membase + UART011_IMSC);
1178 }
1179 }
1180
1181 static void pl011_stop_rx(struct uart_port *port)
1182 {
1183 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1184
1185 uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM|
1186 UART011_PEIM|UART011_BEIM|UART011_OEIM);
1187 writew(uap->im, uap->port.membase + UART011_IMSC);
1188
1189 pl011_dma_rx_stop(uap);
1190 }
1191
1192 static void pl011_enable_ms(struct uart_port *port)
1193 {
1194 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1195
1196 uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM;
1197 writew(uap->im, uap->port.membase + UART011_IMSC);
1198 }
1199
1200 static void pl011_rx_chars(struct uart_amba_port *uap)
1201 {
1202 pl011_fifo_to_tty(uap);
1203
1204 spin_unlock(&uap->port.lock);
1205 tty_flip_buffer_push(&uap->port.state->port);
1206 /*
1207 * If we were temporarily out of DMA mode for a while,
1208 * attempt to switch back to DMA mode again.
1209 */
1210 if (pl011_dma_rx_available(uap)) {
1211 if (pl011_dma_rx_trigger_dma(uap)) {
1212 dev_dbg(uap->port.dev, "could not trigger RX DMA job "
1213 "fall back to interrupt mode again\n");
1214 uap->im |= UART011_RXIM;
1215 } else {
1216 uap->im &= ~UART011_RXIM;
1217 #ifdef CONFIG_DMA_ENGINE
1218 /* Start Rx DMA poll */
1219 if (uap->dmarx.poll_rate) {
1220 uap->dmarx.last_jiffies = jiffies;
1221 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
1222 mod_timer(&uap->dmarx.timer,
1223 jiffies +
1224 msecs_to_jiffies(uap->dmarx.poll_rate));
1225 }
1226 #endif
1227 }
1228
1229 writew(uap->im, uap->port.membase + UART011_IMSC);
1230 }
1231 spin_lock(&uap->port.lock);
1232 }
1233
1234 static void pl011_tx_chars(struct uart_amba_port *uap)
1235 {
1236 struct circ_buf *xmit = &uap->port.state->xmit;
1237 int count;
1238
1239 if (uap->port.x_char) {
1240 writew(uap->port.x_char, uap->port.membase + UART01x_DR);
1241 uap->port.icount.tx++;
1242 uap->port.x_char = 0;
1243 return;
1244 }
1245 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
1246 pl011_stop_tx(&uap->port);
1247 return;
1248 }
1249
1250 /* If we are using DMA mode, try to send some characters. */
1251 if (pl011_dma_tx_irq(uap))
1252 return;
1253
1254 count = uap->fifosize >> 1;
1255 do {
1256 writew(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);
1257 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1258 uap->port.icount.tx++;
1259 if (uart_circ_empty(xmit))
1260 break;
1261 } while (--count > 0);
1262
1263 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1264 uart_write_wakeup(&uap->port);
1265
1266 if (uart_circ_empty(xmit))
1267 pl011_stop_tx(&uap->port);
1268 }
1269
1270 static void pl011_modem_status(struct uart_amba_port *uap)
1271 {
1272 unsigned int status, delta;
1273
1274 status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
1275
1276 delta = status ^ uap->old_status;
1277 uap->old_status = status;
1278
1279 if (!delta)
1280 return;
1281
1282 if (delta & UART01x_FR_DCD)
1283 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
1284
1285 if (delta & UART01x_FR_DSR)
1286 uap->port.icount.dsr++;
1287
1288 if (delta & UART01x_FR_CTS)
1289 uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS);
1290
1291 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
1292 }
1293
1294 static irqreturn_t pl011_int(int irq, void *dev_id)
1295 {
1296 struct uart_amba_port *uap = dev_id;
1297 unsigned long flags;
1298 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
1299 int handled = 0;
1300 unsigned int dummy_read;
1301
1302 spin_lock_irqsave(&uap->port.lock, flags);
1303 status = readw(uap->port.membase + UART011_MIS);
1304 if (status) {
1305 do {
1306 if (uap->vendor->cts_event_workaround) {
1307 /* workaround to make sure that all bits are unlocked.. */
1308 writew(0x00, uap->port.membase + UART011_ICR);
1309
1310 /*
1311 * WA: introduce 26ns(1 uart clk) delay before W1C;
1312 * single apb access will incur 2 pclk(133.12Mhz) delay,
1313 * so add 2 dummy reads
1314 */
1315 dummy_read = readw(uap->port.membase + UART011_ICR);
1316 dummy_read = readw(uap->port.membase + UART011_ICR);
1317 }
1318
1319 writew(status & ~(UART011_TXIS|UART011_RTIS|
1320 UART011_RXIS),
1321 uap->port.membase + UART011_ICR);
1322
1323 if (status & (UART011_RTIS|UART011_RXIS)) {
1324 if (pl011_dma_rx_running(uap))
1325 pl011_dma_rx_irq(uap);
1326 else
1327 pl011_rx_chars(uap);
1328 }
1329 if (status & (UART011_DSRMIS|UART011_DCDMIS|
1330 UART011_CTSMIS|UART011_RIMIS))
1331 pl011_modem_status(uap);
1332 if (status & UART011_TXIS)
1333 pl011_tx_chars(uap);
1334
1335 if (pass_counter-- == 0)
1336 break;
1337
1338 status = readw(uap->port.membase + UART011_MIS);
1339 } while (status != 0);
1340 handled = 1;
1341 }
1342
1343 spin_unlock_irqrestore(&uap->port.lock, flags);
1344
1345 return IRQ_RETVAL(handled);
1346 }
1347
1348 static unsigned int pl011_tx_empty(struct uart_port *port)
1349 {
1350 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1351 unsigned int status = readw(uap->port.membase + UART01x_FR);
1352 return status & (UART01x_FR_BUSY|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT;
1353 }
1354
1355 static unsigned int pl011_get_mctrl(struct uart_port *port)
1356 {
1357 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1358 unsigned int result = 0;
1359 unsigned int status = readw(uap->port.membase + UART01x_FR);
1360
1361 #define TIOCMBIT(uartbit, tiocmbit) \
1362 if (status & uartbit) \
1363 result |= tiocmbit
1364
1365 TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR);
1366 TIOCMBIT(UART01x_FR_DSR, TIOCM_DSR);
1367 TIOCMBIT(UART01x_FR_CTS, TIOCM_CTS);
1368 TIOCMBIT(UART011_FR_RI, TIOCM_RNG);
1369 #undef TIOCMBIT
1370 return result;
1371 }
1372
1373 static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
1374 {
1375 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1376 unsigned int cr;
1377
1378 cr = readw(uap->port.membase + UART011_CR);
1379
1380 #define TIOCMBIT(tiocmbit, uartbit) \
1381 if (mctrl & tiocmbit) \
1382 cr |= uartbit; \
1383 else \
1384 cr &= ~uartbit
1385
1386 TIOCMBIT(TIOCM_RTS, UART011_CR_RTS);
1387 TIOCMBIT(TIOCM_DTR, UART011_CR_DTR);
1388 TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1);
1389 TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2);
1390 TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE);
1391
1392 if (uap->autorts) {
1393 /* We need to disable auto-RTS if we want to turn RTS off */
1394 TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN);
1395 }
1396 #undef TIOCMBIT
1397
1398 writew(cr, uap->port.membase + UART011_CR);
1399 }
1400
1401 static void pl011_break_ctl(struct uart_port *port, int break_state)
1402 {
1403 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1404 unsigned long flags;
1405 unsigned int lcr_h;
1406
1407 spin_lock_irqsave(&uap->port.lock, flags);
1408 lcr_h = readw(uap->port.membase + uap->lcrh_tx);
1409 if (break_state == -1)
1410 lcr_h |= UART01x_LCRH_BRK;
1411 else
1412 lcr_h &= ~UART01x_LCRH_BRK;
1413 writew(lcr_h, uap->port.membase + uap->lcrh_tx);
1414 spin_unlock_irqrestore(&uap->port.lock, flags);
1415 }
1416
1417 #ifdef CONFIG_CONSOLE_POLL
1418
1419 static void pl011_quiesce_irqs(struct uart_port *port)
1420 {
1421 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1422 unsigned char __iomem *regs = uap->port.membase;
1423
1424 writew(readw(regs + UART011_MIS), regs + UART011_ICR);
1425 /*
1426 * There is no way to clear TXIM as this is "ready to transmit IRQ", so
1427 * we simply mask it. start_tx() will unmask it.
1428 *
1429 * Note we can race with start_tx(), and if the race happens, the
1430 * polling user might get another interrupt just after we clear it.
1431 * But it should be OK and can happen even w/o the race, e.g.
1432 * controller immediately got some new data and raised the IRQ.
1433 *
1434 * And whoever uses polling routines assumes that it manages the device
1435 * (including tx queue), so we're also fine with start_tx()'s caller
1436 * side.
1437 */
1438 writew(readw(regs + UART011_IMSC) & ~UART011_TXIM, regs + UART011_IMSC);
1439 }
1440
1441 static int pl011_get_poll_char(struct uart_port *port)
1442 {
1443 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1444 unsigned int status;
1445
1446 /*
1447 * The caller might need IRQs lowered, e.g. if used with KDB NMI
1448 * debugger.
1449 */
1450 pl011_quiesce_irqs(port);
1451
1452 status = readw(uap->port.membase + UART01x_FR);
1453 if (status & UART01x_FR_RXFE)
1454 return NO_POLL_CHAR;
1455
1456 return readw(uap->port.membase + UART01x_DR);
1457 }
1458
1459 static void pl011_put_poll_char(struct uart_port *port,
1460 unsigned char ch)
1461 {
1462 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1463
1464 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)
1465 barrier();
1466
1467 writew(ch, uap->port.membase + UART01x_DR);
1468 }
1469
1470 #endif /* CONFIG_CONSOLE_POLL */
1471
1472 static int pl011_hwinit(struct uart_port *port)
1473 {
1474 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1475 int retval;
1476
1477 /* Optionaly enable pins to be muxed in and configured */
1478 pinctrl_pm_select_default_state(port->dev);
1479
1480 /*
1481 * Try to enable the clock producer.
1482 */
1483 retval = clk_prepare_enable(uap->clk);
1484 if (retval)
1485 goto out;
1486
1487 uap->port.uartclk = clk_get_rate(uap->clk);
1488
1489 /* Clear pending error and receive interrupts */
1490 writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS |
1491 UART011_RTIS | UART011_RXIS, uap->port.membase + UART011_ICR);
1492
1493 /*
1494 * Save interrupts enable mask, and enable RX interrupts in case if
1495 * the interrupt is used for NMI entry.
1496 */
1497 uap->im = readw(uap->port.membase + UART011_IMSC);
1498 writew(UART011_RTIM | UART011_RXIM, uap->port.membase + UART011_IMSC);
1499
1500 if (uap->port.dev->platform_data) {
1501 struct amba_pl011_data *plat;
1502
1503 plat = uap->port.dev->platform_data;
1504 if (plat->init)
1505 plat->init();
1506 }
1507 return 0;
1508 out:
1509 return retval;
1510 }
1511
1512 static int pl011_startup(struct uart_port *port)
1513 {
1514 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1515 unsigned int cr;
1516 int retval;
1517
1518 retval = pl011_hwinit(port);
1519 if (retval)
1520 goto clk_dis;
1521
1522 writew(uap->im, uap->port.membase + UART011_IMSC);
1523
1524 /*
1525 * Allocate the IRQ
1526 */
1527 retval = request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap);
1528 if (retval)
1529 goto clk_dis;
1530
1531 writew(uap->vendor->ifls, uap->port.membase + UART011_IFLS);
1532
1533 /*
1534 * Provoke TX FIFO interrupt into asserting.
1535 */
1536 cr = UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_LBE;
1537 writew(cr, uap->port.membase + UART011_CR);
1538 writew(0, uap->port.membase + UART011_FBRD);
1539 writew(1, uap->port.membase + UART011_IBRD);
1540 writew(0, uap->port.membase + uap->lcrh_rx);
1541 if (uap->lcrh_tx != uap->lcrh_rx) {
1542 int i;
1543 /*
1544 * Wait 10 PCLKs before writing LCRH_TX register,
1545 * to get this delay write read only register 10 times
1546 */
1547 for (i = 0; i < 10; ++i)
1548 writew(0xff, uap->port.membase + UART011_MIS);
1549 writew(0, uap->port.membase + uap->lcrh_tx);
1550 }
1551 writew(0, uap->port.membase + UART01x_DR);
1552 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY)
1553 barrier();
1554
1555 /* restore RTS and DTR */
1556 cr = uap->old_cr & (UART011_CR_RTS | UART011_CR_DTR);
1557 cr |= UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE;
1558 writew(cr, uap->port.membase + UART011_CR);
1559
1560 /*
1561 * initialise the old status of the modem signals
1562 */
1563 uap->old_status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
1564
1565 /* Startup DMA */
1566 pl011_dma_startup(uap);
1567
1568 /*
1569 * Finally, enable interrupts, only timeouts when using DMA
1570 * if initial RX DMA job failed, start in interrupt mode
1571 * as well.
1572 */
1573 spin_lock_irq(&uap->port.lock);
1574 /* Clear out any spuriously appearing RX interrupts */
1575 writew(UART011_RTIS | UART011_RXIS,
1576 uap->port.membase + UART011_ICR);
1577 uap->im = UART011_RTIM;
1578 if (!pl011_dma_rx_running(uap))
1579 uap->im |= UART011_RXIM;
1580 writew(uap->im, uap->port.membase + UART011_IMSC);
1581 spin_unlock_irq(&uap->port.lock);
1582
1583 return 0;
1584
1585 clk_dis:
1586 clk_disable_unprepare(uap->clk);
1587 return retval;
1588 }
1589
1590 static void pl011_shutdown_channel(struct uart_amba_port *uap,
1591 unsigned int lcrh)
1592 {
1593 unsigned long val;
1594
1595 val = readw(uap->port.membase + lcrh);
1596 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
1597 writew(val, uap->port.membase + lcrh);
1598 }
1599
1600 static void pl011_shutdown(struct uart_port *port)
1601 {
1602 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1603 unsigned int cr;
1604
1605 /*
1606 * disable all interrupts
1607 */
1608 spin_lock_irq(&uap->port.lock);
1609 uap->im = 0;
1610 writew(uap->im, uap->port.membase + UART011_IMSC);
1611 writew(0xffff, uap->port.membase + UART011_ICR);
1612 spin_unlock_irq(&uap->port.lock);
1613
1614 pl011_dma_shutdown(uap);
1615
1616 /*
1617 * Free the interrupt
1618 */
1619 free_irq(uap->port.irq, uap);
1620
1621 /*
1622 * disable the port
1623 * disable the port. It should not disable RTS and DTR.
1624 * Also RTS and DTR state should be preserved to restore
1625 * it during startup().
1626 */
1627 uap->autorts = false;
1628 cr = readw(uap->port.membase + UART011_CR);
1629 uap->old_cr = cr;
1630 cr &= UART011_CR_RTS | UART011_CR_DTR;
1631 cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
1632 writew(cr, uap->port.membase + UART011_CR);
1633
1634 /*
1635 * disable break condition and fifos
1636 */
1637 pl011_shutdown_channel(uap, uap->lcrh_rx);
1638 if (uap->lcrh_rx != uap->lcrh_tx)
1639 pl011_shutdown_channel(uap, uap->lcrh_tx);
1640
1641 /*
1642 * Shut down the clock producer
1643 */
1644 clk_disable_unprepare(uap->clk);
1645 /* Optionally let pins go into sleep states */
1646 pinctrl_pm_select_sleep_state(port->dev);
1647
1648 if (uap->port.dev->platform_data) {
1649 struct amba_pl011_data *plat;
1650
1651 plat = uap->port.dev->platform_data;
1652 if (plat->exit)
1653 plat->exit();
1654 }
1655
1656 }
1657
1658 static void
1659 pl011_set_termios(struct uart_port *port, struct ktermios *termios,
1660 struct ktermios *old)
1661 {
1662 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1663 unsigned int lcr_h, old_cr;
1664 unsigned long flags;
1665 unsigned int baud, quot, clkdiv;
1666
1667 if (uap->vendor->oversampling)
1668 clkdiv = 8;
1669 else
1670 clkdiv = 16;
1671
1672 /*
1673 * Ask the core to calculate the divisor for us.
1674 */
1675 baud = uart_get_baud_rate(port, termios, old, 0,
1676 port->uartclk / clkdiv);
1677 #ifdef CONFIG_DMA_ENGINE
1678 /*
1679 * Adjust RX DMA polling rate with baud rate if not specified.
1680 */
1681 if (uap->dmarx.auto_poll_rate)
1682 uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud);
1683 #endif
1684
1685 if (baud > port->uartclk/16)
1686 quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud);
1687 else
1688 quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud);
1689
1690 switch (termios->c_cflag & CSIZE) {
1691 case CS5:
1692 lcr_h = UART01x_LCRH_WLEN_5;
1693 break;
1694 case CS6:
1695 lcr_h = UART01x_LCRH_WLEN_6;
1696 break;
1697 case CS7:
1698 lcr_h = UART01x_LCRH_WLEN_7;
1699 break;
1700 default: // CS8
1701 lcr_h = UART01x_LCRH_WLEN_8;
1702 break;
1703 }
1704 if (termios->c_cflag & CSTOPB)
1705 lcr_h |= UART01x_LCRH_STP2;
1706 if (termios->c_cflag & PARENB) {
1707 lcr_h |= UART01x_LCRH_PEN;
1708 if (!(termios->c_cflag & PARODD))
1709 lcr_h |= UART01x_LCRH_EPS;
1710 }
1711 if (uap->fifosize > 1)
1712 lcr_h |= UART01x_LCRH_FEN;
1713
1714 spin_lock_irqsave(&port->lock, flags);
1715
1716 /*
1717 * Update the per-port timeout.
1718 */
1719 uart_update_timeout(port, termios->c_cflag, baud);
1720
1721 port->read_status_mask = UART011_DR_OE | 255;
1722 if (termios->c_iflag & INPCK)
1723 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE;
1724 if (termios->c_iflag & (BRKINT | PARMRK))
1725 port->read_status_mask |= UART011_DR_BE;
1726
1727 /*
1728 * Characters to ignore
1729 */
1730 port->ignore_status_mask = 0;
1731 if (termios->c_iflag & IGNPAR)
1732 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE;
1733 if (termios->c_iflag & IGNBRK) {
1734 port->ignore_status_mask |= UART011_DR_BE;
1735 /*
1736 * If we're ignoring parity and break indicators,
1737 * ignore overruns too (for real raw support).
1738 */
1739 if (termios->c_iflag & IGNPAR)
1740 port->ignore_status_mask |= UART011_DR_OE;
1741 }
1742
1743 /*
1744 * Ignore all characters if CREAD is not set.
1745 */
1746 if ((termios->c_cflag & CREAD) == 0)
1747 port->ignore_status_mask |= UART_DUMMY_DR_RX;
1748
1749 if (UART_ENABLE_MS(port, termios->c_cflag))
1750 pl011_enable_ms(port);
1751
1752 /* first, disable everything */
1753 old_cr = readw(port->membase + UART011_CR);
1754 writew(0, port->membase + UART011_CR);
1755
1756 if (termios->c_cflag & CRTSCTS) {
1757 if (old_cr & UART011_CR_RTS)
1758 old_cr |= UART011_CR_RTSEN;
1759
1760 old_cr |= UART011_CR_CTSEN;
1761 uap->autorts = true;
1762 } else {
1763 old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN);
1764 uap->autorts = false;
1765 }
1766
1767 if (uap->vendor->oversampling) {
1768 if (baud > port->uartclk / 16)
1769 old_cr |= ST_UART011_CR_OVSFACT;
1770 else
1771 old_cr &= ~ST_UART011_CR_OVSFACT;
1772 }
1773
1774 /*
1775 * Workaround for the ST Micro oversampling variants to
1776 * increase the bitrate slightly, by lowering the divisor,
1777 * to avoid delayed sampling of start bit at high speeds,
1778 * else we see data corruption.
1779 */
1780 if (uap->vendor->oversampling) {
1781 if ((baud >= 3000000) && (baud < 3250000) && (quot > 1))
1782 quot -= 1;
1783 else if ((baud > 3250000) && (quot > 2))
1784 quot -= 2;
1785 }
1786 /* Set baud rate */
1787 writew(quot & 0x3f, port->membase + UART011_FBRD);
1788 writew(quot >> 6, port->membase + UART011_IBRD);
1789
1790 /*
1791 * ----------v----------v----------v----------v-----
1792 * NOTE: lcrh_tx and lcrh_rx MUST BE WRITTEN AFTER
1793 * UART011_FBRD & UART011_IBRD.
1794 * ----------^----------^----------^----------^-----
1795 */
1796 writew(lcr_h, port->membase + uap->lcrh_rx);
1797 if (uap->lcrh_rx != uap->lcrh_tx) {
1798 int i;
1799 /*
1800 * Wait 10 PCLKs before writing LCRH_TX register,
1801 * to get this delay write read only register 10 times
1802 */
1803 for (i = 0; i < 10; ++i)
1804 writew(0xff, uap->port.membase + UART011_MIS);
1805 writew(lcr_h, port->membase + uap->lcrh_tx);
1806 }
1807 writew(old_cr, port->membase + UART011_CR);
1808
1809 spin_unlock_irqrestore(&port->lock, flags);
1810 }
1811
1812 static const char *pl011_type(struct uart_port *port)
1813 {
1814 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1815 return uap->port.type == PORT_AMBA ? uap->type : NULL;
1816 }
1817
1818 /*
1819 * Release the memory region(s) being used by 'port'
1820 */
1821 static void pl011_release_port(struct uart_port *port)
1822 {
1823 release_mem_region(port->mapbase, SZ_4K);
1824 }
1825
1826 /*
1827 * Request the memory region(s) being used by 'port'
1828 */
1829 static int pl011_request_port(struct uart_port *port)
1830 {
1831 return request_mem_region(port->mapbase, SZ_4K, "uart-pl011")
1832 != NULL ? 0 : -EBUSY;
1833 }
1834
1835 /*
1836 * Configure/autoconfigure the port.
1837 */
1838 static void pl011_config_port(struct uart_port *port, int flags)
1839 {
1840 if (flags & UART_CONFIG_TYPE) {
1841 port->type = PORT_AMBA;
1842 pl011_request_port(port);
1843 }
1844 }
1845
1846 /*
1847 * verify the new serial_struct (for TIOCSSERIAL).
1848 */
1849 static int pl011_verify_port(struct uart_port *port, struct serial_struct *ser)
1850 {
1851 int ret = 0;
1852 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
1853 ret = -EINVAL;
1854 if (ser->irq < 0 || ser->irq >= nr_irqs)
1855 ret = -EINVAL;
1856 if (ser->baud_base < 9600)
1857 ret = -EINVAL;
1858 return ret;
1859 }
1860
1861 static struct uart_ops amba_pl011_pops = {
1862 .tx_empty = pl011_tx_empty,
1863 .set_mctrl = pl011_set_mctrl,
1864 .get_mctrl = pl011_get_mctrl,
1865 .stop_tx = pl011_stop_tx,
1866 .start_tx = pl011_start_tx,
1867 .stop_rx = pl011_stop_rx,
1868 .enable_ms = pl011_enable_ms,
1869 .break_ctl = pl011_break_ctl,
1870 .startup = pl011_startup,
1871 .shutdown = pl011_shutdown,
1872 .flush_buffer = pl011_dma_flush_buffer,
1873 .set_termios = pl011_set_termios,
1874 .type = pl011_type,
1875 .release_port = pl011_release_port,
1876 .request_port = pl011_request_port,
1877 .config_port = pl011_config_port,
1878 .verify_port = pl011_verify_port,
1879 #ifdef CONFIG_CONSOLE_POLL
1880 .poll_init = pl011_hwinit,
1881 .poll_get_char = pl011_get_poll_char,
1882 .poll_put_char = pl011_put_poll_char,
1883 #endif
1884 };
1885
1886 static struct uart_amba_port *amba_ports[UART_NR];
1887
1888 #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE
1889
1890 static void pl011_console_putchar(struct uart_port *port, int ch)
1891 {
1892 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1893
1894 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)
1895 barrier();
1896 writew(ch, uap->port.membase + UART01x_DR);
1897 }
1898
1899 static void
1900 pl011_console_write(struct console *co, const char *s, unsigned int count)
1901 {
1902 struct uart_amba_port *uap = amba_ports[co->index];
1903 unsigned int status, old_cr, new_cr;
1904 unsigned long flags;
1905 int locked = 1;
1906
1907 clk_enable(uap->clk);
1908
1909 local_irq_save(flags);
1910 if (uap->port.sysrq)
1911 locked = 0;
1912 else if (oops_in_progress)
1913 locked = spin_trylock(&uap->port.lock);
1914 else
1915 spin_lock(&uap->port.lock);
1916
1917 /*
1918 * First save the CR then disable the interrupts
1919 */
1920 old_cr = readw(uap->port.membase + UART011_CR);
1921 new_cr = old_cr & ~UART011_CR_CTSEN;
1922 new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
1923 writew(new_cr, uap->port.membase + UART011_CR);
1924
1925 uart_console_write(&uap->port, s, count, pl011_console_putchar);
1926
1927 /*
1928 * Finally, wait for transmitter to become empty
1929 * and restore the TCR
1930 */
1931 do {
1932 status = readw(uap->port.membase + UART01x_FR);
1933 } while (status & UART01x_FR_BUSY);
1934 writew(old_cr, uap->port.membase + UART011_CR);
1935
1936 if (locked)
1937 spin_unlock(&uap->port.lock);
1938 local_irq_restore(flags);
1939
1940 clk_disable(uap->clk);
1941 }
1942
1943 static void __init
1944 pl011_console_get_options(struct uart_amba_port *uap, int *baud,
1945 int *parity, int *bits)
1946 {
1947 if (readw(uap->port.membase + UART011_CR) & UART01x_CR_UARTEN) {
1948 unsigned int lcr_h, ibrd, fbrd;
1949
1950 lcr_h = readw(uap->port.membase + uap->lcrh_tx);
1951
1952 *parity = 'n';
1953 if (lcr_h & UART01x_LCRH_PEN) {
1954 if (lcr_h & UART01x_LCRH_EPS)
1955 *parity = 'e';
1956 else
1957 *parity = 'o';
1958 }
1959
1960 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
1961 *bits = 7;
1962 else
1963 *bits = 8;
1964
1965 ibrd = readw(uap->port.membase + UART011_IBRD);
1966 fbrd = readw(uap->port.membase + UART011_FBRD);
1967
1968 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
1969
1970 if (uap->vendor->oversampling) {
1971 if (readw(uap->port.membase + UART011_CR)
1972 & ST_UART011_CR_OVSFACT)
1973 *baud *= 2;
1974 }
1975 }
1976 }
1977
1978 static int __init pl011_console_setup(struct console *co, char *options)
1979 {
1980 struct uart_amba_port *uap;
1981 int baud = 38400;
1982 int bits = 8;
1983 int parity = 'n';
1984 int flow = 'n';
1985 int ret;
1986
1987 /*
1988 * Check whether an invalid uart number has been specified, and
1989 * if so, search for the first available port that does have
1990 * console support.
1991 */
1992 if (co->index >= UART_NR)
1993 co->index = 0;
1994 uap = amba_ports[co->index];
1995 if (!uap)
1996 return -ENODEV;
1997
1998 /* Allow pins to be muxed in and configured */
1999 pinctrl_pm_select_default_state(uap->port.dev);
2000
2001 ret = clk_prepare(uap->clk);
2002 if (ret)
2003 return ret;
2004
2005 if (uap->port.dev->platform_data) {
2006 struct amba_pl011_data *plat;
2007
2008 plat = uap->port.dev->platform_data;
2009 if (plat->init)
2010 plat->init();
2011 }
2012
2013 uap->port.uartclk = clk_get_rate(uap->clk);
2014
2015 if (options)
2016 uart_parse_options(options, &baud, &parity, &bits, &flow);
2017 else
2018 pl011_console_get_options(uap, &baud, &parity, &bits);
2019
2020 return uart_set_options(&uap->port, co, baud, parity, bits, flow);
2021 }
2022
2023 static struct uart_driver amba_reg;
2024 static struct console amba_console = {
2025 .name = "ttyAMA",
2026 .write = pl011_console_write,
2027 .device = uart_console_device,
2028 .setup = pl011_console_setup,
2029 .flags = CON_PRINTBUFFER,
2030 .index = -1,
2031 .data = &amba_reg,
2032 };
2033
2034 #define AMBA_CONSOLE (&amba_console)
2035 #else
2036 #define AMBA_CONSOLE NULL
2037 #endif
2038
2039 static struct uart_driver amba_reg = {
2040 .owner = THIS_MODULE,
2041 .driver_name = "ttyAMA",
2042 .dev_name = "ttyAMA",
2043 .major = SERIAL_AMBA_MAJOR,
2044 .minor = SERIAL_AMBA_MINOR,
2045 .nr = UART_NR,
2046 .cons = AMBA_CONSOLE,
2047 };
2048
2049 static int pl011_probe_dt_alias(int index, struct device *dev)
2050 {
2051 struct device_node *np;
2052 static bool seen_dev_with_alias = false;
2053 static bool seen_dev_without_alias = false;
2054 int ret = index;
2055
2056 if (!IS_ENABLED(CONFIG_OF))
2057 return ret;
2058
2059 np = dev->of_node;
2060 if (!np)
2061 return ret;
2062
2063 ret = of_alias_get_id(np, "serial");
2064 if (IS_ERR_VALUE(ret)) {
2065 seen_dev_without_alias = true;
2066 ret = index;
2067 } else {
2068 seen_dev_with_alias = true;
2069 if (ret >= ARRAY_SIZE(amba_ports) || amba_ports[ret] != NULL) {
2070 dev_warn(dev, "requested serial port %d not available.\n", ret);
2071 ret = index;
2072 }
2073 }
2074
2075 if (seen_dev_with_alias && seen_dev_without_alias)
2076 dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeration may be unpredictable.\n");
2077
2078 return ret;
2079 }
2080
2081 static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
2082 {
2083 struct uart_amba_port *uap;
2084 struct vendor_data *vendor = id->data;
2085 void __iomem *base;
2086 int i, ret;
2087
2088 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
2089 if (amba_ports[i] == NULL)
2090 break;
2091
2092 if (i == ARRAY_SIZE(amba_ports)) {
2093 ret = -EBUSY;
2094 goto out;
2095 }
2096
2097 uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port),
2098 GFP_KERNEL);
2099 if (uap == NULL) {
2100 ret = -ENOMEM;
2101 goto out;
2102 }
2103
2104 i = pl011_probe_dt_alias(i, &dev->dev);
2105
2106 base = devm_ioremap(&dev->dev, dev->res.start,
2107 resource_size(&dev->res));
2108 if (!base) {
2109 ret = -ENOMEM;
2110 goto out;
2111 }
2112
2113 uap->clk = devm_clk_get(&dev->dev, NULL);
2114 if (IS_ERR(uap->clk)) {
2115 ret = PTR_ERR(uap->clk);
2116 goto out;
2117 }
2118
2119 uap->vendor = vendor;
2120 uap->lcrh_rx = vendor->lcrh_rx;
2121 uap->lcrh_tx = vendor->lcrh_tx;
2122 uap->old_cr = 0;
2123 uap->fifosize = vendor->get_fifosize(dev);
2124 uap->port.dev = &dev->dev;
2125 uap->port.mapbase = dev->res.start;
2126 uap->port.membase = base;
2127 uap->port.iotype = UPIO_MEM;
2128 uap->port.irq = dev->irq[0];
2129 uap->port.fifosize = uap->fifosize;
2130 uap->port.ops = &amba_pl011_pops;
2131 uap->port.flags = UPF_BOOT_AUTOCONF;
2132 uap->port.line = i;
2133 pl011_dma_probe(&dev->dev, uap);
2134
2135 /* Ensure interrupts from this UART are masked and cleared */
2136 writew(0, uap->port.membase + UART011_IMSC);
2137 writew(0xffff, uap->port.membase + UART011_ICR);
2138
2139 snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev));
2140
2141 amba_ports[i] = uap;
2142
2143 amba_set_drvdata(dev, uap);
2144 ret = uart_add_one_port(&amba_reg, &uap->port);
2145 if (ret) {
2146 amba_set_drvdata(dev, NULL);
2147 amba_ports[i] = NULL;
2148 pl011_dma_remove(uap);
2149 }
2150 out:
2151 return ret;
2152 }
2153
2154 static int pl011_remove(struct amba_device *dev)
2155 {
2156 struct uart_amba_port *uap = amba_get_drvdata(dev);
2157 int i;
2158
2159 amba_set_drvdata(dev, NULL);
2160
2161 uart_remove_one_port(&amba_reg, &uap->port);
2162
2163 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
2164 if (amba_ports[i] == uap)
2165 amba_ports[i] = NULL;
2166
2167 pl011_dma_remove(uap);
2168 return 0;
2169 }
2170
2171 #ifdef CONFIG_PM
2172 static int pl011_suspend(struct amba_device *dev, pm_message_t state)
2173 {
2174 struct uart_amba_port *uap = amba_get_drvdata(dev);
2175
2176 if (!uap)
2177 return -EINVAL;
2178
2179 return uart_suspend_port(&amba_reg, &uap->port);
2180 }
2181
2182 static int pl011_resume(struct amba_device *dev)
2183 {
2184 struct uart_amba_port *uap = amba_get_drvdata(dev);
2185
2186 if (!uap)
2187 return -EINVAL;
2188
2189 return uart_resume_port(&amba_reg, &uap->port);
2190 }
2191 #endif
2192
2193 static struct amba_id pl011_ids[] = {
2194 {
2195 .id = 0x00041011,
2196 .mask = 0x000fffff,
2197 .data = &vendor_arm,
2198 },
2199 {
2200 .id = 0x00380802,
2201 .mask = 0x00ffffff,
2202 .data = &vendor_st,
2203 },
2204 { 0, 0 },
2205 };
2206
2207 MODULE_DEVICE_TABLE(amba, pl011_ids);
2208
2209 static struct amba_driver pl011_driver = {
2210 .drv = {
2211 .name = "uart-pl011",
2212 },
2213 .id_table = pl011_ids,
2214 .probe = pl011_probe,
2215 .remove = pl011_remove,
2216 #ifdef CONFIG_PM
2217 .suspend = pl011_suspend,
2218 .resume = pl011_resume,
2219 #endif
2220 };
2221
2222 static int __init pl011_init(void)
2223 {
2224 int ret;
2225 printk(KERN_INFO "Serial: AMBA PL011 UART driver\n");
2226
2227 ret = uart_register_driver(&amba_reg);
2228 if (ret == 0) {
2229 ret = amba_driver_register(&pl011_driver);
2230 if (ret)
2231 uart_unregister_driver(&amba_reg);
2232 }
2233 return ret;
2234 }
2235
2236 static void __exit pl011_exit(void)
2237 {
2238 amba_driver_unregister(&pl011_driver);
2239 uart_unregister_driver(&amba_reg);
2240 }
2241
2242 /*
2243 * While this can be a module, if builtin it's most likely the console
2244 * So let's leave module_exit but move module_init to an earlier place
2245 */
2246 arch_initcall(pl011_init);
2247 module_exit(pl011_exit);
2248
2249 MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
2250 MODULE_DESCRIPTION("ARM AMBA serial port driver");
2251 MODULE_LICENSE("GPL");
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