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Linux 3.11-rc3
[cris-mirror.git] / drivers / tty / serial / efm32-uart.c
blob7d199c8e1a750949ccb0edae4d2c730eea790bb9
1 #if defined(CONFIG_SERIAL_EFM32_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
2 #define SUPPORT_SYSRQ
3 #endif
4
5 #include <linux/kernel.h>
6 #include <linux/module.h>
7 #include <linux/io.h>
8 #include <linux/platform_device.h>
9 #include <linux/console.h>
10 #include <linux/sysrq.h>
11 #include <linux/serial_core.h>
12 #include <linux/tty_flip.h>
13 #include <linux/slab.h>
14 #include <linux/clk.h>
15 #include <linux/of.h>
16 #include <linux/of_device.h>
17
18 #include <linux/platform_data/efm32-uart.h>
19
20 #define DRIVER_NAME "efm32-uart"
21 #define DEV_NAME "ttyefm"
22
23 #define UARTn_CTRL 0x00
24 #define UARTn_CTRL_SYNC 0x0001
25 #define UARTn_CTRL_TXBIL 0x1000
26
27 #define UARTn_FRAME 0x04
28 #define UARTn_FRAME_DATABITS__MASK 0x000f
29 #define UARTn_FRAME_DATABITS(n) ((n) - 3)
30 #define UARTn_FRAME_PARITY_NONE 0x0000
31 #define UARTn_FRAME_PARITY_EVEN 0x0200
32 #define UARTn_FRAME_PARITY_ODD 0x0300
33 #define UARTn_FRAME_STOPBITS_HALF 0x0000
34 #define UARTn_FRAME_STOPBITS_ONE 0x1000
35 #define UARTn_FRAME_STOPBITS_TWO 0x3000
36
37 #define UARTn_CMD 0x0c
38 #define UARTn_CMD_RXEN 0x0001
39 #define UARTn_CMD_RXDIS 0x0002
40 #define UARTn_CMD_TXEN 0x0004
41 #define UARTn_CMD_TXDIS 0x0008
42
43 #define UARTn_STATUS 0x10
44 #define UARTn_STATUS_TXENS 0x0002
45 #define UARTn_STATUS_TXC 0x0020
46 #define UARTn_STATUS_TXBL 0x0040
47 #define UARTn_STATUS_RXDATAV 0x0080
48
49 #define UARTn_CLKDIV 0x14
50
51 #define UARTn_RXDATAX 0x18
52 #define UARTn_RXDATAX_RXDATA__MASK 0x01ff
53 #define UARTn_RXDATAX_PERR 0x4000
54 #define UARTn_RXDATAX_FERR 0x8000
55 /*
56 * This is a software only flag used for ignore_status_mask and
57 * read_status_mask! It's used for breaks that the hardware doesn't report
58 * explicitly.
59 */
60 #define SW_UARTn_RXDATAX_BERR 0x2000
61
62 #define UARTn_TXDATA 0x34
63
64 #define UARTn_IF 0x40
65 #define UARTn_IF_TXC 0x0001
66 #define UARTn_IF_TXBL 0x0002
67 #define UARTn_IF_RXDATAV 0x0004
68 #define UARTn_IF_RXOF 0x0010
69
70 #define UARTn_IFS 0x44
71 #define UARTn_IFC 0x48
72 #define UARTn_IEN 0x4c
73
74 #define UARTn_ROUTE 0x54
75 #define UARTn_ROUTE_LOCATION__MASK 0x0700
76 #define UARTn_ROUTE_LOCATION(n) (((n) << 8) & UARTn_ROUTE_LOCATION__MASK)
77 #define UARTn_ROUTE_RXPEN 0x0001
78 #define UARTn_ROUTE_TXPEN 0x0002
79
80 struct efm32_uart_port {
81 struct uart_port port;
82 unsigned int txirq;
83 struct clk *clk;
84 struct efm32_uart_pdata pdata;
85 };
86 #define to_efm_port(_port) container_of(_port, struct efm32_uart_port, port)
87 #define efm_debug(efm_port, format, arg...) \
88 dev_dbg(efm_port->port.dev, format, ##arg)
89
90 static void efm32_uart_write32(struct efm32_uart_port *efm_port,
91 u32 value, unsigned offset)
92 {
93 writel_relaxed(value, efm_port->port.membase + offset);
94 }
95
96 static u32 efm32_uart_read32(struct efm32_uart_port *efm_port,
97 unsigned offset)
98 {
99 return readl_relaxed(efm_port->port.membase + offset);
100 }
101
102 static unsigned int efm32_uart_tx_empty(struct uart_port *port)
103 {
104 struct efm32_uart_port *efm_port = to_efm_port(port);
105 u32 status = efm32_uart_read32(efm_port, UARTn_STATUS);
106
107 if (status & UARTn_STATUS_TXC)
108 return TIOCSER_TEMT;
109 else
110 return 0;
111 }
112
113 static void efm32_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
114 {
115 /* sorry, neither handshaking lines nor loop functionallity */
116 }
117
118 static unsigned int efm32_uart_get_mctrl(struct uart_port *port)
119 {
120 /* sorry, no handshaking lines available */
121 return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR;
122 }
123
124 static void efm32_uart_stop_tx(struct uart_port *port)
125 {
126 struct efm32_uart_port *efm_port = to_efm_port(port);
127 u32 ien = efm32_uart_read32(efm_port, UARTn_IEN);
128
129 efm32_uart_write32(efm_port, UARTn_CMD_TXDIS, UARTn_CMD);
130 ien &= ~(UARTn_IF_TXC | UARTn_IF_TXBL);
131 efm32_uart_write32(efm_port, ien, UARTn_IEN);
132 }
133
134 static void efm32_uart_tx_chars(struct efm32_uart_port *efm_port)
135 {
136 struct uart_port *port = &efm_port->port;
137 struct circ_buf *xmit = &port->state->xmit;
138
139 while (efm32_uart_read32(efm_port, UARTn_STATUS) &
140 UARTn_STATUS_TXBL) {
141 if (port->x_char) {
142 port->icount.tx++;
143 efm32_uart_write32(efm_port, port->x_char,
144 UARTn_TXDATA);
145 port->x_char = 0;
146 continue;
147 }
148 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
149 port->icount.tx++;
150 efm32_uart_write32(efm_port, xmit->buf[xmit->tail],
151 UARTn_TXDATA);
152 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
153 } else
154 break;
155 }
156
157 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
158 uart_write_wakeup(port);
159
160 if (!port->x_char && uart_circ_empty(xmit) &&
161 efm32_uart_read32(efm_port, UARTn_STATUS) &
162 UARTn_STATUS_TXC)
163 efm32_uart_stop_tx(port);
164 }
165
166 static void efm32_uart_start_tx(struct uart_port *port)
167 {
168 struct efm32_uart_port *efm_port = to_efm_port(port);
169 u32 ien;
170
171 efm32_uart_write32(efm_port,
172 UARTn_IF_TXBL | UARTn_IF_TXC, UARTn_IFC);
173 ien = efm32_uart_read32(efm_port, UARTn_IEN);
174 efm32_uart_write32(efm_port,
175 ien | UARTn_IF_TXBL | UARTn_IF_TXC, UARTn_IEN);
176 efm32_uart_write32(efm_port, UARTn_CMD_TXEN, UARTn_CMD);
177
178 efm32_uart_tx_chars(efm_port);
179 }
180
181 static void efm32_uart_stop_rx(struct uart_port *port)
182 {
183 struct efm32_uart_port *efm_port = to_efm_port(port);
184
185 efm32_uart_write32(efm_port, UARTn_CMD_RXDIS, UARTn_CMD);
186 }
187
188 static void efm32_uart_enable_ms(struct uart_port *port)
189 {
190 /* no handshake lines, no modem status interrupts */
191 }
192
193 static void efm32_uart_break_ctl(struct uart_port *port, int ctl)
194 {
195 /* not possible without fiddling with gpios */
196 }
197
198 static void efm32_uart_rx_chars(struct efm32_uart_port *efm_port)
199 {
200 struct uart_port *port = &efm_port->port;
201
202 while (efm32_uart_read32(efm_port, UARTn_STATUS) &
203 UARTn_STATUS_RXDATAV) {
204 u32 rxdata = efm32_uart_read32(efm_port, UARTn_RXDATAX);
205 int flag = 0;
206
207 /*
208 * This is a reserved bit and I only saw it read as 0. But to be
209 * sure not to be confused too much by new devices adhere to the
210 * warning in the reference manual that reserverd bits might
211 * read as 1 in the future.
212 */
213 rxdata &= ~SW_UARTn_RXDATAX_BERR;
214
215 port->icount.rx++;
216
217 if ((rxdata & UARTn_RXDATAX_FERR) &&
218 !(rxdata & UARTn_RXDATAX_RXDATA__MASK)) {
219 rxdata |= SW_UARTn_RXDATAX_BERR;
220 port->icount.brk++;
221 if (uart_handle_break(port))
222 continue;
223 } else if (rxdata & UARTn_RXDATAX_PERR)
224 port->icount.parity++;
225 else if (rxdata & UARTn_RXDATAX_FERR)
226 port->icount.frame++;
227
228 rxdata &= port->read_status_mask;
229
230 if (rxdata & SW_UARTn_RXDATAX_BERR)
231 flag = TTY_BREAK;
232 else if (rxdata & UARTn_RXDATAX_PERR)
233 flag = TTY_PARITY;
234 else if (rxdata & UARTn_RXDATAX_FERR)
235 flag = TTY_FRAME;
236 else if (uart_handle_sysrq_char(port,
237 rxdata & UARTn_RXDATAX_RXDATA__MASK))
238 continue;
239
240 if ((rxdata & port->ignore_status_mask) == 0)
241 tty_insert_flip_char(&port->state->port,
242 rxdata & UARTn_RXDATAX_RXDATA__MASK, flag);
243 }
244 }
245
246 static irqreturn_t efm32_uart_rxirq(int irq, void *data)
247 {
248 struct efm32_uart_port *efm_port = data;
249 u32 irqflag = efm32_uart_read32(efm_port, UARTn_IF);
250 int handled = IRQ_NONE;
251 struct uart_port *port = &efm_port->port;
252 struct tty_port *tport = &port->state->port;
253
254 spin_lock(&port->lock);
255
256 if (irqflag & UARTn_IF_RXDATAV) {
257 efm32_uart_write32(efm_port, UARTn_IF_RXDATAV, UARTn_IFC);
258 efm32_uart_rx_chars(efm_port);
259
260 handled = IRQ_HANDLED;
261 }
262
263 if (irqflag & UARTn_IF_RXOF) {
264 efm32_uart_write32(efm_port, UARTn_IF_RXOF, UARTn_IFC);
265 port->icount.overrun++;
266 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
267
268 handled = IRQ_HANDLED;
269 }
270
271 tty_flip_buffer_push(tport);
272
273 spin_unlock(&port->lock);
274
275 return handled;
276 }
277
278 static irqreturn_t efm32_uart_txirq(int irq, void *data)
279 {
280 struct efm32_uart_port *efm_port = data;
281 u32 irqflag = efm32_uart_read32(efm_port, UARTn_IF);
282
283 /* TXBL doesn't need to be cleared */
284 if (irqflag & UARTn_IF_TXC)
285 efm32_uart_write32(efm_port, UARTn_IF_TXC, UARTn_IFC);
286
287 if (irqflag & (UARTn_IF_TXC | UARTn_IF_TXBL)) {
288 efm32_uart_tx_chars(efm_port);
289 return IRQ_HANDLED;
290 } else
291 return IRQ_NONE;
292 }
293
294 static int efm32_uart_startup(struct uart_port *port)
295 {
296 struct efm32_uart_port *efm_port = to_efm_port(port);
297 int ret;
298
299 ret = clk_enable(efm_port->clk);
300 if (ret) {
301 efm_debug(efm_port, "failed to enable clk\n");
302 goto err_clk_enable;
303 }
304 port->uartclk = clk_get_rate(efm_port->clk);
305
306 /* Enable pins at configured location */
307 efm32_uart_write32(efm_port,
308 UARTn_ROUTE_LOCATION(efm_port->pdata.location) |
309 UARTn_ROUTE_RXPEN | UARTn_ROUTE_TXPEN,
310 UARTn_ROUTE);
311
312 ret = request_irq(port->irq, efm32_uart_rxirq, 0,
313 DRIVER_NAME, efm_port);
314 if (ret) {
315 efm_debug(efm_port, "failed to register rxirq\n");
316 goto err_request_irq_rx;
317 }
318
319 /* disable all irqs */
320 efm32_uart_write32(efm_port, 0, UARTn_IEN);
321
322 ret = request_irq(efm_port->txirq, efm32_uart_txirq, 0,
323 DRIVER_NAME, efm_port);
324 if (ret) {
325 efm_debug(efm_port, "failed to register txirq\n");
326 free_irq(port->irq, efm_port);
327 err_request_irq_rx:
328
329 clk_disable(efm_port->clk);
330 } else {
331 efm32_uart_write32(efm_port,
332 UARTn_IF_RXDATAV | UARTn_IF_RXOF, UARTn_IEN);
333 efm32_uart_write32(efm_port, UARTn_CMD_RXEN, UARTn_CMD);
334 }
335
336 err_clk_enable:
337 return ret;
338 }
339
340 static void efm32_uart_shutdown(struct uart_port *port)
341 {
342 struct efm32_uart_port *efm_port = to_efm_port(port);
343
344 efm32_uart_write32(efm_port, 0, UARTn_IEN);
345 free_irq(port->irq, efm_port);
346
347 clk_disable(efm_port->clk);
348 }
349
350 static void efm32_uart_set_termios(struct uart_port *port,
351 struct ktermios *new, struct ktermios *old)
352 {
353 struct efm32_uart_port *efm_port = to_efm_port(port);
354 unsigned long flags;
355 unsigned baud;
356 u32 clkdiv;
357 u32 frame = 0;
358
359 /* no modem control lines */
360 new->c_cflag &= ~(CRTSCTS | CMSPAR);
361
362 baud = uart_get_baud_rate(port, new, old,
363 DIV_ROUND_CLOSEST(port->uartclk, 16 * 8192),
364 DIV_ROUND_CLOSEST(port->uartclk, 16));
365
366 switch (new->c_cflag & CSIZE) {
367 case CS5:
368 frame |= UARTn_FRAME_DATABITS(5);
369 break;
370 case CS6:
371 frame |= UARTn_FRAME_DATABITS(6);
372 break;
373 case CS7:
374 frame |= UARTn_FRAME_DATABITS(7);
375 break;
376 case CS8:
377 frame |= UARTn_FRAME_DATABITS(8);
378 break;
379 }
380
381 if (new->c_cflag & CSTOPB)
382 /* the receiver only verifies the first stop bit */
383 frame |= UARTn_FRAME_STOPBITS_TWO;
384 else
385 frame |= UARTn_FRAME_STOPBITS_ONE;
386
387 if (new->c_cflag & PARENB) {
388 if (new->c_cflag & PARODD)
389 frame |= UARTn_FRAME_PARITY_ODD;
390 else
391 frame |= UARTn_FRAME_PARITY_EVEN;
392 } else
393 frame |= UARTn_FRAME_PARITY_NONE;
394
395 /*
396 * the 6 lowest bits of CLKDIV are dc, bit 6 has value 0.25.
397 * port->uartclk <= 14e6, so 4 * port->uartclk doesn't overflow.
398 */
399 clkdiv = (DIV_ROUND_CLOSEST(4 * port->uartclk, 16 * baud) - 4) << 6;
400
401 spin_lock_irqsave(&port->lock, flags);
402
403 efm32_uart_write32(efm_port,
404 UARTn_CMD_TXDIS | UARTn_CMD_RXDIS, UARTn_CMD);
405
406 port->read_status_mask = UARTn_RXDATAX_RXDATA__MASK;
407 if (new->c_iflag & INPCK)
408 port->read_status_mask |=
409 UARTn_RXDATAX_FERR | UARTn_RXDATAX_PERR;
410 if (new->c_iflag & (BRKINT | PARMRK))
411 port->read_status_mask |= SW_UARTn_RXDATAX_BERR;
412
413 port->ignore_status_mask = 0;
414 if (new->c_iflag & IGNPAR)
415 port->ignore_status_mask |=
416 UARTn_RXDATAX_FERR | UARTn_RXDATAX_PERR;
417 if (new->c_iflag & IGNBRK)
418 port->ignore_status_mask |= SW_UARTn_RXDATAX_BERR;
419
420 uart_update_timeout(port, new->c_cflag, baud);
421
422 efm32_uart_write32(efm_port, UARTn_CTRL_TXBIL, UARTn_CTRL);
423 efm32_uart_write32(efm_port, frame, UARTn_FRAME);
424 efm32_uart_write32(efm_port, clkdiv, UARTn_CLKDIV);
425
426 efm32_uart_write32(efm_port, UARTn_CMD_TXEN | UARTn_CMD_RXEN,
427 UARTn_CMD);
428
429 spin_unlock_irqrestore(&port->lock, flags);
430 }
431
432 static const char *efm32_uart_type(struct uart_port *port)
433 {
434 return port->type == PORT_EFMUART ? "efm32-uart" : NULL;
435 }
436
437 static void efm32_uart_release_port(struct uart_port *port)
438 {
439 struct efm32_uart_port *efm_port = to_efm_port(port);
440
441 clk_unprepare(efm_port->clk);
442 clk_put(efm_port->clk);
443 iounmap(port->membase);
444 }
445
446 static int efm32_uart_request_port(struct uart_port *port)
447 {
448 struct efm32_uart_port *efm_port = to_efm_port(port);
449 int ret;
450
451 port->membase = ioremap(port->mapbase, 60);
452 if (!efm_port->port.membase) {
453 ret = -ENOMEM;
454 efm_debug(efm_port, "failed to remap\n");
455 goto err_ioremap;
456 }
457
458 efm_port->clk = clk_get(port->dev, NULL);
459 if (IS_ERR(efm_port->clk)) {
460 ret = PTR_ERR(efm_port->clk);
461 efm_debug(efm_port, "failed to get clock\n");
462 goto err_clk_get;
463 }
464
465 ret = clk_prepare(efm_port->clk);
466 if (ret) {
467 clk_put(efm_port->clk);
468 err_clk_get:
469
470 iounmap(port->membase);
471 err_ioremap:
472 return ret;
473 }
474 return 0;
475 }
476
477 static void efm32_uart_config_port(struct uart_port *port, int type)
478 {
479 if (type & UART_CONFIG_TYPE &&
480 !efm32_uart_request_port(port))
481 port->type = PORT_EFMUART;
482 }
483
484 static int efm32_uart_verify_port(struct uart_port *port,
485 struct serial_struct *serinfo)
486 {
487 int ret = 0;
488
489 if (serinfo->type != PORT_UNKNOWN && serinfo->type != PORT_EFMUART)
490 ret = -EINVAL;
491
492 return ret;
493 }
494
495 static struct uart_ops efm32_uart_pops = {
496 .tx_empty = efm32_uart_tx_empty,
497 .set_mctrl = efm32_uart_set_mctrl,
498 .get_mctrl = efm32_uart_get_mctrl,
499 .stop_tx = efm32_uart_stop_tx,
500 .start_tx = efm32_uart_start_tx,
501 .stop_rx = efm32_uart_stop_rx,
502 .enable_ms = efm32_uart_enable_ms,
503 .break_ctl = efm32_uart_break_ctl,
504 .startup = efm32_uart_startup,
505 .shutdown = efm32_uart_shutdown,
506 .set_termios = efm32_uart_set_termios,
507 .type = efm32_uart_type,
508 .release_port = efm32_uart_release_port,
509 .request_port = efm32_uart_request_port,
510 .config_port = efm32_uart_config_port,
511 .verify_port = efm32_uart_verify_port,
512 };
513
514 static struct efm32_uart_port *efm32_uart_ports[5];
515
516 #ifdef CONFIG_SERIAL_EFM32_UART_CONSOLE
517 static void efm32_uart_console_putchar(struct uart_port *port, int ch)
518 {
519 struct efm32_uart_port *efm_port = to_efm_port(port);
520 unsigned int timeout = 0x400;
521 u32 status;
522
523 while (1) {
524 status = efm32_uart_read32(efm_port, UARTn_STATUS);
525
526 if (status & UARTn_STATUS_TXBL)
527 break;
528 if (!timeout--)
529 return;
530 }
531 efm32_uart_write32(efm_port, ch, UARTn_TXDATA);
532 }
533
534 static void efm32_uart_console_write(struct console *co, const char *s,
535 unsigned int count)
536 {
537 struct efm32_uart_port *efm_port = efm32_uart_ports[co->index];
538 u32 status = efm32_uart_read32(efm_port, UARTn_STATUS);
539 unsigned int timeout = 0x400;
540
541 if (!(status & UARTn_STATUS_TXENS))
542 efm32_uart_write32(efm_port, UARTn_CMD_TXEN, UARTn_CMD);
543
544 uart_console_write(&efm_port->port, s, count,
545 efm32_uart_console_putchar);
546
547 /* Wait for the transmitter to become empty */
548 while (1) {
549 u32 status = efm32_uart_read32(efm_port, UARTn_STATUS);
550 if (status & UARTn_STATUS_TXC)
551 break;
552 if (!timeout--)
553 break;
554 }
555
556 if (!(status & UARTn_STATUS_TXENS))
557 efm32_uart_write32(efm_port, UARTn_CMD_TXDIS, UARTn_CMD);
558 }
559
560 static void efm32_uart_console_get_options(struct efm32_uart_port *efm_port,
561 int *baud, int *parity, int *bits)
562 {
563 u32 ctrl = efm32_uart_read32(efm_port, UARTn_CTRL);
564 u32 route, clkdiv, frame;
565
566 if (ctrl & UARTn_CTRL_SYNC)
567 /* not operating in async mode */
568 return;
569
570 route = efm32_uart_read32(efm_port, UARTn_ROUTE);
571 if (!(route & UARTn_ROUTE_TXPEN))
572 /* tx pin not routed */
573 return;
574
575 clkdiv = efm32_uart_read32(efm_port, UARTn_CLKDIV);
576
577 *baud = DIV_ROUND_CLOSEST(4 * efm_port->port.uartclk,
578 16 * (4 + (clkdiv >> 6)));
579
580 frame = efm32_uart_read32(efm_port, UARTn_FRAME);
581 if (frame & UARTn_FRAME_PARITY_ODD)
582 *parity = 'o';
583 else if (frame & UARTn_FRAME_PARITY_EVEN)
584 *parity = 'e';
585 else
586 *parity = 'n';
587
588 *bits = (frame & UARTn_FRAME_DATABITS__MASK) -
589 UARTn_FRAME_DATABITS(4) + 4;
590
591 efm_debug(efm_port, "get_opts: options=%d%c%d\n",
592 *baud, *parity, *bits);
593 }
594
595 static int efm32_uart_console_setup(struct console *co, char *options)
596 {
597 struct efm32_uart_port *efm_port;
598 int baud = 115200;
599 int bits = 8;
600 int parity = 'n';
601 int flow = 'n';
602 int ret;
603
604 if (co->index < 0 || co->index >= ARRAY_SIZE(efm32_uart_ports)) {
605 unsigned i;
606 for (i = 0; i < ARRAY_SIZE(efm32_uart_ports); ++i) {
607 if (efm32_uart_ports[i]) {
608 pr_warn("efm32-console: fall back to console index %u (from %hhi)\n",
609 i, co->index);
610 co->index = i;
611 break;
612 }
613 }
614 }
615
616 efm_port = efm32_uart_ports[co->index];
617 if (!efm_port) {
618 pr_warn("efm32-console: No port at %d\n", co->index);
619 return -ENODEV;
620 }
621
622 ret = clk_prepare(efm_port->clk);
623 if (ret) {
624 dev_warn(efm_port->port.dev,
625 "console: clk_prepare failed: %d\n", ret);
626 return ret;
627 }
628
629 efm_port->port.uartclk = clk_get_rate(efm_port->clk);
630
631 if (options)
632 uart_parse_options(options, &baud, &parity, &bits, &flow);
633 else
634 efm32_uart_console_get_options(efm_port,
635 &baud, &parity, &bits);
636
637 return uart_set_options(&efm_port->port, co, baud, parity, bits, flow);
638 }
639
640 static struct uart_driver efm32_uart_reg;
641
642 static struct console efm32_uart_console = {
643 .name = DEV_NAME,
644 .write = efm32_uart_console_write,
645 .device = uart_console_device,
646 .setup = efm32_uart_console_setup,
647 .flags = CON_PRINTBUFFER,
648 .index = -1,
649 .data = &efm32_uart_reg,
650 };
651
652 #else
653 #define efm32_uart_console (*(struct console *)NULL)
654 #endif /* ifdef CONFIG_SERIAL_EFM32_UART_CONSOLE / else */
655
656 static struct uart_driver efm32_uart_reg = {
657 .owner = THIS_MODULE,
658 .driver_name = DRIVER_NAME,
659 .dev_name = DEV_NAME,
660 .nr = ARRAY_SIZE(efm32_uart_ports),
661 .cons = &efm32_uart_console,
662 };
663
664 static int efm32_uart_probe_dt(struct platform_device *pdev,
665 struct efm32_uart_port *efm_port)
666 {
667 struct device_node *np = pdev->dev.of_node;
668 u32 location;
669 int ret;
670
671 if (!np)
672 return 1;
673
674 ret = of_property_read_u32(np, "location", &location);
675 if (!ret) {
676 if (location > 5) {
677 dev_err(&pdev->dev, "invalid location\n");
678 return -EINVAL;
679 }
680 efm_debug(efm_port, "using location %u\n", location);
681 efm_port->pdata.location = location;
682 } else {
683 efm_debug(efm_port, "fall back to location 0\n");
684 }
685
686 ret = of_alias_get_id(np, "serial");
687 if (ret < 0) {
688 dev_err(&pdev->dev, "failed to get alias id: %d\n", ret);
689 return ret;
690 } else {
691 efm_port->port.line = ret;
692 return 0;
693 }
694
695 }
696
697 static int efm32_uart_probe(struct platform_device *pdev)
698 {
699 struct efm32_uart_port *efm_port;
700 struct resource *res;
701 int ret;
702
703 efm_port = kzalloc(sizeof(*efm_port), GFP_KERNEL);
704 if (!efm_port) {
705 dev_dbg(&pdev->dev, "failed to allocate private data\n");
706 return -ENOMEM;
707 }
708
709 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
710 if (!res) {
711 ret = -ENODEV;
712 dev_dbg(&pdev->dev, "failed to determine base address\n");
713 goto err_get_base;
714 }
715
716 if (resource_size(res) < 60) {
717 ret = -EINVAL;
718 dev_dbg(&pdev->dev, "memory resource too small\n");
719 goto err_too_small;
720 }
721
722 ret = platform_get_irq(pdev, 0);
723 if (ret <= 0) {
724 dev_dbg(&pdev->dev, "failed to get rx irq\n");
725 goto err_get_rxirq;
726 }
727
728 efm_port->port.irq = ret;
729
730 ret = platform_get_irq(pdev, 1);
731 if (ret <= 0)
732 ret = efm_port->port.irq + 1;
733
734 efm_port->txirq = ret;
735
736 efm_port->port.dev = &pdev->dev;
737 efm_port->port.mapbase = res->start;
738 efm_port->port.type = PORT_EFMUART;
739 efm_port->port.iotype = UPIO_MEM32;
740 efm_port->port.fifosize = 2;
741 efm_port->port.ops = &efm32_uart_pops;
742 efm_port->port.flags = UPF_BOOT_AUTOCONF;
743
744 ret = efm32_uart_probe_dt(pdev, efm_port);
745 if (ret > 0) {
746 /* not created by device tree */
747 const struct efm32_uart_pdata *pdata = dev_get_platdata(&pdev->dev);
748
749 efm_port->port.line = pdev->id;
750
751 if (pdata)
752 efm_port->pdata = *pdata;
753 }
754
755 if (efm_port->port.line >= 0 &&
756 efm_port->port.line < ARRAY_SIZE(efm32_uart_ports))
757 efm32_uart_ports[efm_port->port.line] = efm_port;
758
759 ret = uart_add_one_port(&efm32_uart_reg, &efm_port->port);
760 if (ret) {
761 dev_dbg(&pdev->dev, "failed to add port: %d\n", ret);
762
763 if (pdev->id >= 0 && pdev->id < ARRAY_SIZE(efm32_uart_ports))
764 efm32_uart_ports[pdev->id] = NULL;
765 err_get_rxirq:
766 err_too_small:
767 err_get_base:
768 kfree(efm_port);
769 } else {
770 platform_set_drvdata(pdev, efm_port);
771 dev_dbg(&pdev->dev, "\\o/\n");
772 }
773
774 return ret;
775 }
776
777 static int efm32_uart_remove(struct platform_device *pdev)
778 {
779 struct efm32_uart_port *efm_port = platform_get_drvdata(pdev);
780
781 platform_set_drvdata(pdev, NULL);
782
783 uart_remove_one_port(&efm32_uart_reg, &efm_port->port);
784
785 if (pdev->id >= 0 && pdev->id < ARRAY_SIZE(efm32_uart_ports))
786 efm32_uart_ports[pdev->id] = NULL;
787
788 kfree(efm_port);
789
790 return 0;
791 }
792
793 static struct of_device_id efm32_uart_dt_ids[] = {
794 {
795 .compatible = "efm32,uart",
796 }, {
797 /* sentinel */
798 }
799 };
800 MODULE_DEVICE_TABLE(of, efm32_uart_dt_ids);
801
802 static struct platform_driver efm32_uart_driver = {
803 .probe = efm32_uart_probe,
804 .remove = efm32_uart_remove,
805
806 .driver = {
807 .name = DRIVER_NAME,
808 .owner = THIS_MODULE,
809 .of_match_table = efm32_uart_dt_ids,
810 },
811 };
812
813 static int __init efm32_uart_init(void)
814 {
815 int ret;
816
817 ret = uart_register_driver(&efm32_uart_reg);
818 if (ret)
819 return ret;
820
821 ret = platform_driver_register(&efm32_uart_driver);
822 if (ret)
823 uart_unregister_driver(&efm32_uart_reg);
824
825 pr_info("EFM32 UART/USART driver\n");
826
827 return ret;
828 }
829 module_init(efm32_uart_init);
830
831 static void __exit efm32_uart_exit(void)
832 {
833 platform_driver_unregister(&efm32_uart_driver);
834 uart_unregister_driver(&efm32_uart_reg);
835 }
836
837 MODULE_AUTHOR("Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>");
838 MODULE_DESCRIPTION("EFM32 UART/USART driver");
839 MODULE_LICENSE("GPL v2");
840 MODULE_ALIAS("platform:" DRIVER_NAME);
CRIS linux kernel tree