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Linux 3.11-rc3
[cris-mirror.git] / drivers / tty / serial / imx.c
blob415cec62073fbc61d9770e6a8c613a42f2ba6865
1 /*
2 * Driver for Motorola IMX serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Author: Sascha Hauer <sascha@saschahauer.de>
7 * Copyright (C) 2004 Pengutronix
8 *
9 * Copyright (C) 2009 emlix GmbH
10 * Author: Fabian Godehardt (added IrDA support for iMX)
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 * [29-Mar-2005] Mike Lee
27 * Added hardware handshake
28 */
29
30 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
31 #define SUPPORT_SYSRQ
32 #endif
33
34 #include <linux/module.h>
35 #include <linux/ioport.h>
36 #include <linux/init.h>
37 #include <linux/console.h>
38 #include <linux/sysrq.h>
39 #include <linux/platform_device.h>
40 #include <linux/tty.h>
41 #include <linux/tty_flip.h>
42 #include <linux/serial_core.h>
43 #include <linux/serial.h>
44 #include <linux/clk.h>
45 #include <linux/delay.h>
46 #include <linux/rational.h>
47 #include <linux/slab.h>
48 #include <linux/of.h>
49 #include <linux/of_device.h>
50 #include <linux/pinctrl/consumer.h>
51 #include <linux/io.h>
52
53 #include <asm/irq.h>
54 #include <linux/platform_data/serial-imx.h>
55
56 /* Register definitions */
57 #define URXD0 0x0 /* Receiver Register */
58 #define URTX0 0x40 /* Transmitter Register */
59 #define UCR1 0x80 /* Control Register 1 */
60 #define UCR2 0x84 /* Control Register 2 */
61 #define UCR3 0x88 /* Control Register 3 */
62 #define UCR4 0x8c /* Control Register 4 */
63 #define UFCR 0x90 /* FIFO Control Register */
64 #define USR1 0x94 /* Status Register 1 */
65 #define USR2 0x98 /* Status Register 2 */
66 #define UESC 0x9c /* Escape Character Register */
67 #define UTIM 0xa0 /* Escape Timer Register */
68 #define UBIR 0xa4 /* BRM Incremental Register */
69 #define UBMR 0xa8 /* BRM Modulator Register */
70 #define UBRC 0xac /* Baud Rate Count Register */
71 #define IMX21_ONEMS 0xb0 /* One Millisecond register */
72 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
73 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
74
75 /* UART Control Register Bit Fields.*/
76 #define URXD_CHARRDY (1<<15)
77 #define URXD_ERR (1<<14)
78 #define URXD_OVRRUN (1<<13)
79 #define URXD_FRMERR (1<<12)
80 #define URXD_BRK (1<<11)
81 #define URXD_PRERR (1<<10)
82 #define UCR1_ADEN (1<<15) /* Auto detect interrupt */
83 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
84 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
85 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
86 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
87 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
88 #define UCR1_IREN (1<<7) /* Infrared interface enable */
89 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
90 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
91 #define UCR1_SNDBRK (1<<4) /* Send break */
92 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
93 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
94 #define UCR1_DOZE (1<<1) /* Doze */
95 #define UCR1_UARTEN (1<<0) /* UART enabled */
96 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
97 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
98 #define UCR2_CTSC (1<<13) /* CTS pin control */
99 #define UCR2_CTS (1<<12) /* Clear to send */
100 #define UCR2_ESCEN (1<<11) /* Escape enable */
101 #define UCR2_PREN (1<<8) /* Parity enable */
102 #define UCR2_PROE (1<<7) /* Parity odd/even */
103 #define UCR2_STPB (1<<6) /* Stop */
104 #define UCR2_WS (1<<5) /* Word size */
105 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
106 #define UCR2_ATEN (1<<3) /* Aging Timer Enable */
107 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
108 #define UCR2_RXEN (1<<1) /* Receiver enabled */
109 #define UCR2_SRST (1<<0) /* SW reset */
110 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
111 #define UCR3_PARERREN (1<<12) /* Parity enable */
112 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
113 #define UCR3_DSR (1<<10) /* Data set ready */
114 #define UCR3_DCD (1<<9) /* Data carrier detect */
115 #define UCR3_RI (1<<8) /* Ring indicator */
116 #define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
117 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
118 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
119 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
120 #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
121 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
122 #define UCR3_BPEN (1<<0) /* Preset registers enable */
123 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
124 #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
125 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
126 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
127 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
128 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
129 #define UCR4_IRSC (1<<5) /* IR special case */
130 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
131 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
132 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
133 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
134 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
135 #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
136 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
137 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
138 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
139 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
140 #define USR1_RTSS (1<<14) /* RTS pin status */
141 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
142 #define USR1_RTSD (1<<12) /* RTS delta */
143 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
144 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
145 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
146 #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
147 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
148 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
149 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
150 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
151 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
152 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
153 #define USR2_IDLE (1<<12) /* Idle condition */
154 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
155 #define USR2_WAKE (1<<7) /* Wake */
156 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
157 #define USR2_TXDC (1<<3) /* Transmitter complete */
158 #define USR2_BRCD (1<<2) /* Break condition */
159 #define USR2_ORE (1<<1) /* Overrun error */
160 #define USR2_RDR (1<<0) /* Recv data ready */
161 #define UTS_FRCPERR (1<<13) /* Force parity error */
162 #define UTS_LOOP (1<<12) /* Loop tx and rx */
163 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
164 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
165 #define UTS_TXFULL (1<<4) /* TxFIFO full */
166 #define UTS_RXFULL (1<<3) /* RxFIFO full */
167 #define UTS_SOFTRST (1<<0) /* Software reset */
168
169 /* We've been assigned a range on the "Low-density serial ports" major */
170 #define SERIAL_IMX_MAJOR 207
171 #define MINOR_START 16
172 #define DEV_NAME "ttymxc"
173
174 /*
175 * This determines how often we check the modem status signals
176 * for any change. They generally aren't connected to an IRQ
177 * so we have to poll them. We also check immediately before
178 * filling the TX fifo incase CTS has been dropped.
179 */
180 #define MCTRL_TIMEOUT (250*HZ/1000)
181
182 #define DRIVER_NAME "IMX-uart"
183
184 #define UART_NR 8
185
186 /* i.mx21 type uart runs on all i.mx except i.mx1 */
187 enum imx_uart_type {
188 IMX1_UART,
189 IMX21_UART,
190 };
191
192 /* device type dependent stuff */
193 struct imx_uart_data {
194 unsigned uts_reg;
195 enum imx_uart_type devtype;
196 };
197
198 struct imx_port {
199 struct uart_port port;
200 struct timer_list timer;
201 unsigned int old_status;
202 int txirq, rxirq, rtsirq;
203 unsigned int have_rtscts:1;
204 unsigned int dte_mode:1;
205 unsigned int use_irda:1;
206 unsigned int irda_inv_rx:1;
207 unsigned int irda_inv_tx:1;
208 unsigned short trcv_delay; /* transceiver delay */
209 struct clk *clk_ipg;
210 struct clk *clk_per;
211 const struct imx_uart_data *devdata;
212 };
213
214 struct imx_port_ucrs {
215 unsigned int ucr1;
216 unsigned int ucr2;
217 unsigned int ucr3;
218 };
219
220 #ifdef CONFIG_IRDA
221 #define USE_IRDA(sport) ((sport)->use_irda)
222 #else
223 #define USE_IRDA(sport) (0)
224 #endif
225
226 static struct imx_uart_data imx_uart_devdata[] = {
227 [IMX1_UART] = {
228 .uts_reg = IMX1_UTS,
229 .devtype = IMX1_UART,
230 },
231 [IMX21_UART] = {
232 .uts_reg = IMX21_UTS,
233 .devtype = IMX21_UART,
234 },
235 };
236
237 static struct platform_device_id imx_uart_devtype[] = {
238 {
239 .name = "imx1-uart",
240 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART],
241 }, {
242 .name = "imx21-uart",
243 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART],
244 }, {
245 /* sentinel */
246 }
247 };
248 MODULE_DEVICE_TABLE(platform, imx_uart_devtype);
249
250 static struct of_device_id imx_uart_dt_ids[] = {
251 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
252 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
253 { /* sentinel */ }
254 };
255 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
256
257 static inline unsigned uts_reg(struct imx_port *sport)
258 {
259 return sport->devdata->uts_reg;
260 }
261
262 static inline int is_imx1_uart(struct imx_port *sport)
263 {
264 return sport->devdata->devtype == IMX1_UART;
265 }
266
267 static inline int is_imx21_uart(struct imx_port *sport)
268 {
269 return sport->devdata->devtype == IMX21_UART;
270 }
271
272 /*
273 * Save and restore functions for UCR1, UCR2 and UCR3 registers
274 */
275 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_IMX_CONSOLE)
276 static void imx_port_ucrs_save(struct uart_port *port,
277 struct imx_port_ucrs *ucr)
278 {
279 /* save control registers */
280 ucr->ucr1 = readl(port->membase + UCR1);
281 ucr->ucr2 = readl(port->membase + UCR2);
282 ucr->ucr3 = readl(port->membase + UCR3);
283 }
284
285 static void imx_port_ucrs_restore(struct uart_port *port,
286 struct imx_port_ucrs *ucr)
287 {
288 /* restore control registers */
289 writel(ucr->ucr1, port->membase + UCR1);
290 writel(ucr->ucr2, port->membase + UCR2);
291 writel(ucr->ucr3, port->membase + UCR3);
292 }
293 #endif
294
295 /*
296 * Handle any change of modem status signal since we were last called.
297 */
298 static void imx_mctrl_check(struct imx_port *sport)
299 {
300 unsigned int status, changed;
301
302 status = sport->port.ops->get_mctrl(&sport->port);
303 changed = status ^ sport->old_status;
304
305 if (changed == 0)
306 return;
307
308 sport->old_status = status;
309
310 if (changed & TIOCM_RI)
311 sport->port.icount.rng++;
312 if (changed & TIOCM_DSR)
313 sport->port.icount.dsr++;
314 if (changed & TIOCM_CAR)
315 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
316 if (changed & TIOCM_CTS)
317 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
318
319 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
320 }
321
322 /*
323 * This is our per-port timeout handler, for checking the
324 * modem status signals.
325 */
326 static void imx_timeout(unsigned long data)
327 {
328 struct imx_port *sport = (struct imx_port *)data;
329 unsigned long flags;
330
331 if (sport->port.state) {
332 spin_lock_irqsave(&sport->port.lock, flags);
333 imx_mctrl_check(sport);
334 spin_unlock_irqrestore(&sport->port.lock, flags);
335
336 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
337 }
338 }
339
340 /*
341 * interrupts disabled on entry
342 */
343 static void imx_stop_tx(struct uart_port *port)
344 {
345 struct imx_port *sport = (struct imx_port *)port;
346 unsigned long temp;
347
348 if (USE_IRDA(sport)) {
349 /* half duplex - wait for end of transmission */
350 int n = 256;
351 while ((--n > 0) &&
352 !(readl(sport->port.membase + USR2) & USR2_TXDC)) {
353 udelay(5);
354 barrier();
355 }
356 /*
357 * irda transceiver - wait a bit more to avoid
358 * cutoff, hardware dependent
359 */
360 udelay(sport->trcv_delay);
361
362 /*
363 * half duplex - reactivate receive mode,
364 * flush receive pipe echo crap
365 */
366 if (readl(sport->port.membase + USR2) & USR2_TXDC) {
367 temp = readl(sport->port.membase + UCR1);
368 temp &= ~(UCR1_TXMPTYEN | UCR1_TRDYEN);
369 writel(temp, sport->port.membase + UCR1);
370
371 temp = readl(sport->port.membase + UCR4);
372 temp &= ~(UCR4_TCEN);
373 writel(temp, sport->port.membase + UCR4);
374
375 while (readl(sport->port.membase + URXD0) &
376 URXD_CHARRDY)
377 barrier();
378
379 temp = readl(sport->port.membase + UCR1);
380 temp |= UCR1_RRDYEN;
381 writel(temp, sport->port.membase + UCR1);
382
383 temp = readl(sport->port.membase + UCR4);
384 temp |= UCR4_DREN;
385 writel(temp, sport->port.membase + UCR4);
386 }
387 return;
388 }
389
390 temp = readl(sport->port.membase + UCR1);
391 writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1);
392 }
393
394 /*
395 * interrupts disabled on entry
396 */
397 static void imx_stop_rx(struct uart_port *port)
398 {
399 struct imx_port *sport = (struct imx_port *)port;
400 unsigned long temp;
401
402 temp = readl(sport->port.membase + UCR2);
403 writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2);
404 }
405
406 /*
407 * Set the modem control timer to fire immediately.
408 */
409 static void imx_enable_ms(struct uart_port *port)
410 {
411 struct imx_port *sport = (struct imx_port *)port;
412
413 mod_timer(&sport->timer, jiffies);
414 }
415
416 static inline void imx_transmit_buffer(struct imx_port *sport)
417 {
418 struct circ_buf *xmit = &sport->port.state->xmit;
419
420 while (!uart_circ_empty(xmit) &&
421 !(readl(sport->port.membase + uts_reg(sport))
422 & UTS_TXFULL)) {
423 /* send xmit->buf[xmit->tail]
424 * out the port here */
425 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
426 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
427 sport->port.icount.tx++;
428 }
429
430 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
431 uart_write_wakeup(&sport->port);
432
433 if (uart_circ_empty(xmit))
434 imx_stop_tx(&sport->port);
435 }
436
437 /*
438 * interrupts disabled on entry
439 */
440 static void imx_start_tx(struct uart_port *port)
441 {
442 struct imx_port *sport = (struct imx_port *)port;
443 unsigned long temp;
444
445 if (USE_IRDA(sport)) {
446 /* half duplex in IrDA mode; have to disable receive mode */
447 temp = readl(sport->port.membase + UCR4);
448 temp &= ~(UCR4_DREN);
449 writel(temp, sport->port.membase + UCR4);
450
451 temp = readl(sport->port.membase + UCR1);
452 temp &= ~(UCR1_RRDYEN);
453 writel(temp, sport->port.membase + UCR1);
454 }
455 /* Clear any pending ORE flag before enabling interrupt */
456 temp = readl(sport->port.membase + USR2);
457 writel(temp | USR2_ORE, sport->port.membase + USR2);
458
459 temp = readl(sport->port.membase + UCR4);
460 temp |= UCR4_OREN;
461 writel(temp, sport->port.membase + UCR4);
462
463 temp = readl(sport->port.membase + UCR1);
464 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
465
466 if (USE_IRDA(sport)) {
467 temp = readl(sport->port.membase + UCR1);
468 temp |= UCR1_TRDYEN;
469 writel(temp, sport->port.membase + UCR1);
470
471 temp = readl(sport->port.membase + UCR4);
472 temp |= UCR4_TCEN;
473 writel(temp, sport->port.membase + UCR4);
474 }
475
476 if (readl(sport->port.membase + uts_reg(sport)) & UTS_TXEMPTY)
477 imx_transmit_buffer(sport);
478 }
479
480 static irqreturn_t imx_rtsint(int irq, void *dev_id)
481 {
482 struct imx_port *sport = dev_id;
483 unsigned int val;
484 unsigned long flags;
485
486 spin_lock_irqsave(&sport->port.lock, flags);
487
488 writel(USR1_RTSD, sport->port.membase + USR1);
489 val = readl(sport->port.membase + USR1) & USR1_RTSS;
490 uart_handle_cts_change(&sport->port, !!val);
491 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
492
493 spin_unlock_irqrestore(&sport->port.lock, flags);
494 return IRQ_HANDLED;
495 }
496
497 static irqreturn_t imx_txint(int irq, void *dev_id)
498 {
499 struct imx_port *sport = dev_id;
500 struct circ_buf *xmit = &sport->port.state->xmit;
501 unsigned long flags;
502
503 spin_lock_irqsave(&sport->port.lock, flags);
504 if (sport->port.x_char) {
505 /* Send next char */
506 writel(sport->port.x_char, sport->port.membase + URTX0);
507 goto out;
508 }
509
510 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
511 imx_stop_tx(&sport->port);
512 goto out;
513 }
514
515 imx_transmit_buffer(sport);
516
517 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
518 uart_write_wakeup(&sport->port);
519
520 out:
521 spin_unlock_irqrestore(&sport->port.lock, flags);
522 return IRQ_HANDLED;
523 }
524
525 static irqreturn_t imx_rxint(int irq, void *dev_id)
526 {
527 struct imx_port *sport = dev_id;
528 unsigned int rx, flg, ignored = 0;
529 struct tty_port *port = &sport->port.state->port;
530 unsigned long flags, temp;
531
532 spin_lock_irqsave(&sport->port.lock, flags);
533
534 while (readl(sport->port.membase + USR2) & USR2_RDR) {
535 flg = TTY_NORMAL;
536 sport->port.icount.rx++;
537
538 rx = readl(sport->port.membase + URXD0);
539
540 temp = readl(sport->port.membase + USR2);
541 if (temp & USR2_BRCD) {
542 writel(USR2_BRCD, sport->port.membase + USR2);
543 if (uart_handle_break(&sport->port))
544 continue;
545 }
546
547 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
548 continue;
549
550 if (unlikely(rx & URXD_ERR)) {
551 if (rx & URXD_BRK)
552 sport->port.icount.brk++;
553 else if (rx & URXD_PRERR)
554 sport->port.icount.parity++;
555 else if (rx & URXD_FRMERR)
556 sport->port.icount.frame++;
557 if (rx & URXD_OVRRUN)
558 sport->port.icount.overrun++;
559
560 if (rx & sport->port.ignore_status_mask) {
561 if (++ignored > 100)
562 goto out;
563 continue;
564 }
565
566 rx &= sport->port.read_status_mask;
567
568 if (rx & URXD_BRK)
569 flg = TTY_BREAK;
570 else if (rx & URXD_PRERR)
571 flg = TTY_PARITY;
572 else if (rx & URXD_FRMERR)
573 flg = TTY_FRAME;
574 if (rx & URXD_OVRRUN)
575 flg = TTY_OVERRUN;
576
577 #ifdef SUPPORT_SYSRQ
578 sport->port.sysrq = 0;
579 #endif
580 }
581
582 tty_insert_flip_char(port, rx, flg);
583 }
584
585 out:
586 spin_unlock_irqrestore(&sport->port.lock, flags);
587 tty_flip_buffer_push(port);
588 return IRQ_HANDLED;
589 }
590
591 static irqreturn_t imx_int(int irq, void *dev_id)
592 {
593 struct imx_port *sport = dev_id;
594 unsigned int sts;
595 unsigned int sts2;
596
597 sts = readl(sport->port.membase + USR1);
598
599 if (sts & USR1_RRDY)
600 imx_rxint(irq, dev_id);
601
602 if (sts & USR1_TRDY &&
603 readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN)
604 imx_txint(irq, dev_id);
605
606 if (sts & USR1_RTSD)
607 imx_rtsint(irq, dev_id);
608
609 if (sts & USR1_AWAKE)
610 writel(USR1_AWAKE, sport->port.membase + USR1);
611
612 sts2 = readl(sport->port.membase + USR2);
613 if (sts2 & USR2_ORE) {
614 dev_err(sport->port.dev, "Rx FIFO overrun\n");
615 sport->port.icount.overrun++;
616 writel(sts2 | USR2_ORE, sport->port.membase + USR2);
617 }
618
619 return IRQ_HANDLED;
620 }
621
622 /*
623 * Return TIOCSER_TEMT when transmitter is not busy.
624 */
625 static unsigned int imx_tx_empty(struct uart_port *port)
626 {
627 struct imx_port *sport = (struct imx_port *)port;
628
629 return (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
630 }
631
632 /*
633 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
634 */
635 static unsigned int imx_get_mctrl(struct uart_port *port)
636 {
637 struct imx_port *sport = (struct imx_port *)port;
638 unsigned int tmp = TIOCM_DSR | TIOCM_CAR;
639
640 if (readl(sport->port.membase + USR1) & USR1_RTSS)
641 tmp |= TIOCM_CTS;
642
643 if (readl(sport->port.membase + UCR2) & UCR2_CTS)
644 tmp |= TIOCM_RTS;
645
646 return tmp;
647 }
648
649 static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
650 {
651 struct imx_port *sport = (struct imx_port *)port;
652 unsigned long temp;
653
654 temp = readl(sport->port.membase + UCR2) & ~UCR2_CTS;
655
656 if (mctrl & TIOCM_RTS)
657 temp |= UCR2_CTS;
658
659 writel(temp, sport->port.membase + UCR2);
660 }
661
662 /*
663 * Interrupts always disabled.
664 */
665 static void imx_break_ctl(struct uart_port *port, int break_state)
666 {
667 struct imx_port *sport = (struct imx_port *)port;
668 unsigned long flags, temp;
669
670 spin_lock_irqsave(&sport->port.lock, flags);
671
672 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
673
674 if (break_state != 0)
675 temp |= UCR1_SNDBRK;
676
677 writel(temp, sport->port.membase + UCR1);
678
679 spin_unlock_irqrestore(&sport->port.lock, flags);
680 }
681
682 #define TXTL 2 /* reset default */
683 #define RXTL 1 /* reset default */
684
685 static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
686 {
687 unsigned int val;
688
689 /* set receiver / transmitter trigger level */
690 val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
691 val |= TXTL << UFCR_TXTL_SHF | RXTL;
692 writel(val, sport->port.membase + UFCR);
693 return 0;
694 }
695
696 /* half the RX buffer size */
697 #define CTSTL 16
698
699 static int imx_startup(struct uart_port *port)
700 {
701 struct imx_port *sport = (struct imx_port *)port;
702 int retval;
703 unsigned long flags, temp;
704
705 if (!uart_console(port)) {
706 retval = clk_prepare_enable(sport->clk_per);
707 if (retval)
708 goto error_out1;
709 retval = clk_prepare_enable(sport->clk_ipg);
710 if (retval) {
711 clk_disable_unprepare(sport->clk_per);
712 goto error_out1;
713 }
714 }
715
716 imx_setup_ufcr(sport, 0);
717
718 /* disable the DREN bit (Data Ready interrupt enable) before
719 * requesting IRQs
720 */
721 temp = readl(sport->port.membase + UCR4);
722
723 if (USE_IRDA(sport))
724 temp |= UCR4_IRSC;
725
726 /* set the trigger level for CTS */
727 temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
728 temp |= CTSTL << UCR4_CTSTL_SHF;
729
730 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
731
732 if (USE_IRDA(sport)) {
733 /* reset fifo's and state machines */
734 int i = 100;
735 temp = readl(sport->port.membase + UCR2);
736 temp &= ~UCR2_SRST;
737 writel(temp, sport->port.membase + UCR2);
738 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) &&
739 (--i > 0)) {
740 udelay(1);
741 }
742 }
743
744 /*
745 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
746 * chips only have one interrupt.
747 */
748 if (sport->txirq > 0) {
749 retval = request_irq(sport->rxirq, imx_rxint, 0,
750 DRIVER_NAME, sport);
751 if (retval)
752 goto error_out1;
753
754 retval = request_irq(sport->txirq, imx_txint, 0,
755 DRIVER_NAME, sport);
756 if (retval)
757 goto error_out2;
758
759 /* do not use RTS IRQ on IrDA */
760 if (!USE_IRDA(sport)) {
761 retval = request_irq(sport->rtsirq, imx_rtsint, 0,
762 DRIVER_NAME, sport);
763 if (retval)
764 goto error_out3;
765 }
766 } else {
767 retval = request_irq(sport->port.irq, imx_int, 0,
768 DRIVER_NAME, sport);
769 if (retval) {
770 free_irq(sport->port.irq, sport);
771 goto error_out1;
772 }
773 }
774
775 spin_lock_irqsave(&sport->port.lock, flags);
776 /*
777 * Finally, clear and enable interrupts
778 */
779 writel(USR1_RTSD, sport->port.membase + USR1);
780
781 temp = readl(sport->port.membase + UCR1);
782 temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN;
783
784 if (USE_IRDA(sport)) {
785 temp |= UCR1_IREN;
786 temp &= ~(UCR1_RTSDEN);
787 }
788
789 writel(temp, sport->port.membase + UCR1);
790
791 temp = readl(sport->port.membase + UCR2);
792 temp |= (UCR2_RXEN | UCR2_TXEN);
793 if (!sport->have_rtscts)
794 temp |= UCR2_IRTS;
795 writel(temp, sport->port.membase + UCR2);
796
797 if (USE_IRDA(sport)) {
798 /* clear RX-FIFO */
799 int i = 64;
800 while ((--i > 0) &&
801 (readl(sport->port.membase + URXD0) & URXD_CHARRDY)) {
802 barrier();
803 }
804 }
805
806 if (is_imx21_uart(sport)) {
807 temp = readl(sport->port.membase + UCR3);
808 temp |= IMX21_UCR3_RXDMUXSEL;
809 writel(temp, sport->port.membase + UCR3);
810 }
811
812 if (USE_IRDA(sport)) {
813 temp = readl(sport->port.membase + UCR4);
814 if (sport->irda_inv_rx)
815 temp |= UCR4_INVR;
816 else
817 temp &= ~(UCR4_INVR);
818 writel(temp | UCR4_DREN, sport->port.membase + UCR4);
819
820 temp = readl(sport->port.membase + UCR3);
821 if (sport->irda_inv_tx)
822 temp |= UCR3_INVT;
823 else
824 temp &= ~(UCR3_INVT);
825 writel(temp, sport->port.membase + UCR3);
826 }
827
828 /*
829 * Enable modem status interrupts
830 */
831 imx_enable_ms(&sport->port);
832 spin_unlock_irqrestore(&sport->port.lock, flags);
833
834 if (USE_IRDA(sport)) {
835 struct imxuart_platform_data *pdata;
836 pdata = sport->port.dev->platform_data;
837 sport->irda_inv_rx = pdata->irda_inv_rx;
838 sport->irda_inv_tx = pdata->irda_inv_tx;
839 sport->trcv_delay = pdata->transceiver_delay;
840 if (pdata->irda_enable)
841 pdata->irda_enable(1);
842 }
843
844 return 0;
845
846 error_out3:
847 if (sport->txirq)
848 free_irq(sport->txirq, sport);
849 error_out2:
850 if (sport->rxirq)
851 free_irq(sport->rxirq, sport);
852 error_out1:
853 return retval;
854 }
855
856 static void imx_shutdown(struct uart_port *port)
857 {
858 struct imx_port *sport = (struct imx_port *)port;
859 unsigned long temp;
860 unsigned long flags;
861
862 spin_lock_irqsave(&sport->port.lock, flags);
863 temp = readl(sport->port.membase + UCR2);
864 temp &= ~(UCR2_TXEN);
865 writel(temp, sport->port.membase + UCR2);
866 spin_unlock_irqrestore(&sport->port.lock, flags);
867
868 if (USE_IRDA(sport)) {
869 struct imxuart_platform_data *pdata;
870 pdata = sport->port.dev->platform_data;
871 if (pdata->irda_enable)
872 pdata->irda_enable(0);
873 }
874
875 /*
876 * Stop our timer.
877 */
878 del_timer_sync(&sport->timer);
879
880 /*
881 * Free the interrupts
882 */
883 if (sport->txirq > 0) {
884 if (!USE_IRDA(sport))
885 free_irq(sport->rtsirq, sport);
886 free_irq(sport->txirq, sport);
887 free_irq(sport->rxirq, sport);
888 } else
889 free_irq(sport->port.irq, sport);
890
891 /*
892 * Disable all interrupts, port and break condition.
893 */
894
895 spin_lock_irqsave(&sport->port.lock, flags);
896 temp = readl(sport->port.membase + UCR1);
897 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
898 if (USE_IRDA(sport))
899 temp &= ~(UCR1_IREN);
900
901 writel(temp, sport->port.membase + UCR1);
902 spin_unlock_irqrestore(&sport->port.lock, flags);
903
904 if (!uart_console(&sport->port)) {
905 clk_disable_unprepare(sport->clk_per);
906 clk_disable_unprepare(sport->clk_ipg);
907 }
908 }
909
910 static void
911 imx_set_termios(struct uart_port *port, struct ktermios *termios,
912 struct ktermios *old)
913 {
914 struct imx_port *sport = (struct imx_port *)port;
915 unsigned long flags;
916 unsigned int ucr2, old_ucr1, old_txrxen, baud, quot;
917 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
918 unsigned int div, ufcr;
919 unsigned long num, denom;
920 uint64_t tdiv64;
921
922 /*
923 * If we don't support modem control lines, don't allow
924 * these to be set.
925 */
926 if (0) {
927 termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR);
928 termios->c_cflag |= CLOCAL;
929 }
930
931 /*
932 * We only support CS7 and CS8.
933 */
934 while ((termios->c_cflag & CSIZE) != CS7 &&
935 (termios->c_cflag & CSIZE) != CS8) {
936 termios->c_cflag &= ~CSIZE;
937 termios->c_cflag |= old_csize;
938 old_csize = CS8;
939 }
940
941 if ((termios->c_cflag & CSIZE) == CS8)
942 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
943 else
944 ucr2 = UCR2_SRST | UCR2_IRTS;
945
946 if (termios->c_cflag & CRTSCTS) {
947 if (sport->have_rtscts) {
948 ucr2 &= ~UCR2_IRTS;
949 ucr2 |= UCR2_CTSC;
950 } else {
951 termios->c_cflag &= ~CRTSCTS;
952 }
953 }
954
955 if (termios->c_cflag & CSTOPB)
956 ucr2 |= UCR2_STPB;
957 if (termios->c_cflag & PARENB) {
958 ucr2 |= UCR2_PREN;
959 if (termios->c_cflag & PARODD)
960 ucr2 |= UCR2_PROE;
961 }
962
963 del_timer_sync(&sport->timer);
964
965 /*
966 * Ask the core to calculate the divisor for us.
967 */
968 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
969 quot = uart_get_divisor(port, baud);
970
971 spin_lock_irqsave(&sport->port.lock, flags);
972
973 sport->port.read_status_mask = 0;
974 if (termios->c_iflag & INPCK)
975 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
976 if (termios->c_iflag & (BRKINT | PARMRK))
977 sport->port.read_status_mask |= URXD_BRK;
978
979 /*
980 * Characters to ignore
981 */
982 sport->port.ignore_status_mask = 0;
983 if (termios->c_iflag & IGNPAR)
984 sport->port.ignore_status_mask |= URXD_PRERR;
985 if (termios->c_iflag & IGNBRK) {
986 sport->port.ignore_status_mask |= URXD_BRK;
987 /*
988 * If we're ignoring parity and break indicators,
989 * ignore overruns too (for real raw support).
990 */
991 if (termios->c_iflag & IGNPAR)
992 sport->port.ignore_status_mask |= URXD_OVRRUN;
993 }
994
995 /*
996 * Update the per-port timeout.
997 */
998 uart_update_timeout(port, termios->c_cflag, baud);
999
1000 /*
1001 * disable interrupts and drain transmitter
1002 */
1003 old_ucr1 = readl(sport->port.membase + UCR1);
1004 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
1005 sport->port.membase + UCR1);
1006
1007 while (!(readl(sport->port.membase + USR2) & USR2_TXDC))
1008 barrier();
1009
1010 /* then, disable everything */
1011 old_txrxen = readl(sport->port.membase + UCR2);
1012 writel(old_txrxen & ~(UCR2_TXEN | UCR2_RXEN),
1013 sport->port.membase + UCR2);
1014 old_txrxen &= (UCR2_TXEN | UCR2_RXEN);
1015
1016 if (USE_IRDA(sport)) {
1017 /*
1018 * use maximum available submodule frequency to
1019 * avoid missing short pulses due to low sampling rate
1020 */
1021 div = 1;
1022 } else {
1023 div = sport->port.uartclk / (baud * 16);
1024 if (div > 7)
1025 div = 7;
1026 if (!div)
1027 div = 1;
1028 }
1029
1030 rational_best_approximation(16 * div * baud, sport->port.uartclk,
1031 1 << 16, 1 << 16, &num, &denom);
1032
1033 tdiv64 = sport->port.uartclk;
1034 tdiv64 *= num;
1035 do_div(tdiv64, denom * 16 * div);
1036 tty_termios_encode_baud_rate(termios,
1037 (speed_t)tdiv64, (speed_t)tdiv64);
1038
1039 num -= 1;
1040 denom -= 1;
1041
1042 ufcr = readl(sport->port.membase + UFCR);
1043 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
1044 if (sport->dte_mode)
1045 ufcr |= UFCR_DCEDTE;
1046 writel(ufcr, sport->port.membase + UFCR);
1047
1048 writel(num, sport->port.membase + UBIR);
1049 writel(denom, sport->port.membase + UBMR);
1050
1051 if (is_imx21_uart(sport))
1052 writel(sport->port.uartclk / div / 1000,
1053 sport->port.membase + IMX21_ONEMS);
1054
1055 writel(old_ucr1, sport->port.membase + UCR1);
1056
1057 /* set the parity, stop bits and data size */
1058 writel(ucr2 | old_txrxen, sport->port.membase + UCR2);
1059
1060 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1061 imx_enable_ms(&sport->port);
1062
1063 spin_unlock_irqrestore(&sport->port.lock, flags);
1064 }
1065
1066 static const char *imx_type(struct uart_port *port)
1067 {
1068 struct imx_port *sport = (struct imx_port *)port;
1069
1070 return sport->port.type == PORT_IMX ? "IMX" : NULL;
1071 }
1072
1073 /*
1074 * Release the memory region(s) being used by 'port'.
1075 */
1076 static void imx_release_port(struct uart_port *port)
1077 {
1078 struct platform_device *pdev = to_platform_device(port->dev);
1079 struct resource *mmres;
1080
1081 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1082 release_mem_region(mmres->start, resource_size(mmres));
1083 }
1084
1085 /*
1086 * Request the memory region(s) being used by 'port'.
1087 */
1088 static int imx_request_port(struct uart_port *port)
1089 {
1090 struct platform_device *pdev = to_platform_device(port->dev);
1091 struct resource *mmres;
1092 void *ret;
1093
1094 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1095 if (!mmres)
1096 return -ENODEV;
1097
1098 ret = request_mem_region(mmres->start, resource_size(mmres), "imx-uart");
1099
1100 return ret ? 0 : -EBUSY;
1101 }
1102
1103 /*
1104 * Configure/autoconfigure the port.
1105 */
1106 static void imx_config_port(struct uart_port *port, int flags)
1107 {
1108 struct imx_port *sport = (struct imx_port *)port;
1109
1110 if (flags & UART_CONFIG_TYPE &&
1111 imx_request_port(&sport->port) == 0)
1112 sport->port.type = PORT_IMX;
1113 }
1114
1115 /*
1116 * Verify the new serial_struct (for TIOCSSERIAL).
1117 * The only change we allow are to the flags and type, and
1118 * even then only between PORT_IMX and PORT_UNKNOWN
1119 */
1120 static int
1121 imx_verify_port(struct uart_port *port, struct serial_struct *ser)
1122 {
1123 struct imx_port *sport = (struct imx_port *)port;
1124 int ret = 0;
1125
1126 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1127 ret = -EINVAL;
1128 if (sport->port.irq != ser->irq)
1129 ret = -EINVAL;
1130 if (ser->io_type != UPIO_MEM)
1131 ret = -EINVAL;
1132 if (sport->port.uartclk / 16 != ser->baud_base)
1133 ret = -EINVAL;
1134 if ((void *)sport->port.mapbase != ser->iomem_base)
1135 ret = -EINVAL;
1136 if (sport->port.iobase != ser->port)
1137 ret = -EINVAL;
1138 if (ser->hub6 != 0)
1139 ret = -EINVAL;
1140 return ret;
1141 }
1142
1143 #if defined(CONFIG_CONSOLE_POLL)
1144 static int imx_poll_get_char(struct uart_port *port)
1145 {
1146 struct imx_port_ucrs old_ucr;
1147 unsigned int status;
1148 unsigned char c;
1149
1150 /* save control registers */
1151 imx_port_ucrs_save(port, &old_ucr);
1152
1153 /* disable interrupts */
1154 writel(UCR1_UARTEN, port->membase + UCR1);
1155 writel(old_ucr.ucr2 & ~(UCR2_ATEN | UCR2_RTSEN | UCR2_ESCI),
1156 port->membase + UCR2);
1157 writel(old_ucr.ucr3 & ~(UCR3_DCD | UCR3_RI | UCR3_DTREN),
1158 port->membase + UCR3);
1159
1160 /* poll */
1161 do {
1162 status = readl(port->membase + USR2);
1163 } while (~status & USR2_RDR);
1164
1165 /* read */
1166 c = readl(port->membase + URXD0);
1167
1168 /* restore control registers */
1169 imx_port_ucrs_restore(port, &old_ucr);
1170
1171 return c;
1172 }
1173
1174 static void imx_poll_put_char(struct uart_port *port, unsigned char c)
1175 {
1176 struct imx_port_ucrs old_ucr;
1177 unsigned int status;
1178
1179 /* save control registers */
1180 imx_port_ucrs_save(port, &old_ucr);
1181
1182 /* disable interrupts */
1183 writel(UCR1_UARTEN, port->membase + UCR1);
1184 writel(old_ucr.ucr2 & ~(UCR2_ATEN | UCR2_RTSEN | UCR2_ESCI),
1185 port->membase + UCR2);
1186 writel(old_ucr.ucr3 & ~(UCR3_DCD | UCR3_RI | UCR3_DTREN),
1187 port->membase + UCR3);
1188
1189 /* drain */
1190 do {
1191 status = readl(port->membase + USR1);
1192 } while (~status & USR1_TRDY);
1193
1194 /* write */
1195 writel(c, port->membase + URTX0);
1196
1197 /* flush */
1198 do {
1199 status = readl(port->membase + USR2);
1200 } while (~status & USR2_TXDC);
1201
1202 /* restore control registers */
1203 imx_port_ucrs_restore(port, &old_ucr);
1204 }
1205 #endif
1206
1207 static struct uart_ops imx_pops = {
1208 .tx_empty = imx_tx_empty,
1209 .set_mctrl = imx_set_mctrl,
1210 .get_mctrl = imx_get_mctrl,
1211 .stop_tx = imx_stop_tx,
1212 .start_tx = imx_start_tx,
1213 .stop_rx = imx_stop_rx,
1214 .enable_ms = imx_enable_ms,
1215 .break_ctl = imx_break_ctl,
1216 .startup = imx_startup,
1217 .shutdown = imx_shutdown,
1218 .set_termios = imx_set_termios,
1219 .type = imx_type,
1220 .release_port = imx_release_port,
1221 .request_port = imx_request_port,
1222 .config_port = imx_config_port,
1223 .verify_port = imx_verify_port,
1224 #if defined(CONFIG_CONSOLE_POLL)
1225 .poll_get_char = imx_poll_get_char,
1226 .poll_put_char = imx_poll_put_char,
1227 #endif
1228 };
1229
1230 static struct imx_port *imx_ports[UART_NR];
1231
1232 #ifdef CONFIG_SERIAL_IMX_CONSOLE
1233 static void imx_console_putchar(struct uart_port *port, int ch)
1234 {
1235 struct imx_port *sport = (struct imx_port *)port;
1236
1237 while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)
1238 barrier();
1239
1240 writel(ch, sport->port.membase + URTX0);
1241 }
1242
1243 /*
1244 * Interrupts are disabled on entering
1245 */
1246 static void
1247 imx_console_write(struct console *co, const char *s, unsigned int count)
1248 {
1249 struct imx_port *sport = imx_ports[co->index];
1250 struct imx_port_ucrs old_ucr;
1251 unsigned int ucr1;
1252 unsigned long flags = 0;
1253 int locked = 1;
1254
1255 if (sport->port.sysrq)
1256 locked = 0;
1257 else if (oops_in_progress)
1258 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1259 else
1260 spin_lock_irqsave(&sport->port.lock, flags);
1261
1262 /*
1263 * First, save UCR1/2/3 and then disable interrupts
1264 */
1265 imx_port_ucrs_save(&sport->port, &old_ucr);
1266 ucr1 = old_ucr.ucr1;
1267
1268 if (is_imx1_uart(sport))
1269 ucr1 |= IMX1_UCR1_UARTCLKEN;
1270 ucr1 |= UCR1_UARTEN;
1271 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN);
1272
1273 writel(ucr1, sport->port.membase + UCR1);
1274
1275 writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
1276
1277 uart_console_write(&sport->port, s, count, imx_console_putchar);
1278
1279 /*
1280 * Finally, wait for transmitter to become empty
1281 * and restore UCR1/2/3
1282 */
1283 while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
1284
1285 imx_port_ucrs_restore(&sport->port, &old_ucr);
1286
1287 if (locked)
1288 spin_unlock_irqrestore(&sport->port.lock, flags);
1289 }
1290
1291 /*
1292 * If the port was already initialised (eg, by a boot loader),
1293 * try to determine the current setup.
1294 */
1295 static void __init
1296 imx_console_get_options(struct imx_port *sport, int *baud,
1297 int *parity, int *bits)
1298 {
1299
1300 if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) {
1301 /* ok, the port was enabled */
1302 unsigned int ucr2, ubir, ubmr, uartclk;
1303 unsigned int baud_raw;
1304 unsigned int ucfr_rfdiv;
1305
1306 ucr2 = readl(sport->port.membase + UCR2);
1307
1308 *parity = 'n';
1309 if (ucr2 & UCR2_PREN) {
1310 if (ucr2 & UCR2_PROE)
1311 *parity = 'o';
1312 else
1313 *parity = 'e';
1314 }
1315
1316 if (ucr2 & UCR2_WS)
1317 *bits = 8;
1318 else
1319 *bits = 7;
1320
1321 ubir = readl(sport->port.membase + UBIR) & 0xffff;
1322 ubmr = readl(sport->port.membase + UBMR) & 0xffff;
1323
1324 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
1325 if (ucfr_rfdiv == 6)
1326 ucfr_rfdiv = 7;
1327 else
1328 ucfr_rfdiv = 6 - ucfr_rfdiv;
1329
1330 uartclk = clk_get_rate(sport->clk_per);
1331 uartclk /= ucfr_rfdiv;
1332
1333 { /*
1334 * The next code provides exact computation of
1335 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
1336 * without need of float support or long long division,
1337 * which would be required to prevent 32bit arithmetic overflow
1338 */
1339 unsigned int mul = ubir + 1;
1340 unsigned int div = 16 * (ubmr + 1);
1341 unsigned int rem = uartclk % div;
1342
1343 baud_raw = (uartclk / div) * mul;
1344 baud_raw += (rem * mul + div / 2) / div;
1345 *baud = (baud_raw + 50) / 100 * 100;
1346 }
1347
1348 if (*baud != baud_raw)
1349 pr_info("Console IMX rounded baud rate from %d to %d\n",
1350 baud_raw, *baud);
1351 }
1352 }
1353
1354 static int __init
1355 imx_console_setup(struct console *co, char *options)
1356 {
1357 struct imx_port *sport;
1358 int baud = 9600;
1359 int bits = 8;
1360 int parity = 'n';
1361 int flow = 'n';
1362
1363 /*
1364 * Check whether an invalid uart number has been specified, and
1365 * if so, search for the first available port that does have
1366 * console support.
1367 */
1368 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
1369 co->index = 0;
1370 sport = imx_ports[co->index];
1371 if (sport == NULL)
1372 return -ENODEV;
1373
1374 if (options)
1375 uart_parse_options(options, &baud, &parity, &bits, &flow);
1376 else
1377 imx_console_get_options(sport, &baud, &parity, &bits);
1378
1379 imx_setup_ufcr(sport, 0);
1380
1381 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
1382 }
1383
1384 static struct uart_driver imx_reg;
1385 static struct console imx_console = {
1386 .name = DEV_NAME,
1387 .write = imx_console_write,
1388 .device = uart_console_device,
1389 .setup = imx_console_setup,
1390 .flags = CON_PRINTBUFFER,
1391 .index = -1,
1392 .data = &imx_reg,
1393 };
1394
1395 #define IMX_CONSOLE &imx_console
1396 #else
1397 #define IMX_CONSOLE NULL
1398 #endif
1399
1400 static struct uart_driver imx_reg = {
1401 .owner = THIS_MODULE,
1402 .driver_name = DRIVER_NAME,
1403 .dev_name = DEV_NAME,
1404 .major = SERIAL_IMX_MAJOR,
1405 .minor = MINOR_START,
1406 .nr = ARRAY_SIZE(imx_ports),
1407 .cons = IMX_CONSOLE,
1408 };
1409
1410 static int serial_imx_suspend(struct platform_device *dev, pm_message_t state)
1411 {
1412 struct imx_port *sport = platform_get_drvdata(dev);
1413 unsigned int val;
1414
1415 /* enable wakeup from i.MX UART */
1416 val = readl(sport->port.membase + UCR3);
1417 val |= UCR3_AWAKEN;
1418 writel(val, sport->port.membase + UCR3);
1419
1420 uart_suspend_port(&imx_reg, &sport->port);
1421
1422 return 0;
1423 }
1424
1425 static int serial_imx_resume(struct platform_device *dev)
1426 {
1427 struct imx_port *sport = platform_get_drvdata(dev);
1428 unsigned int val;
1429
1430 /* disable wakeup from i.MX UART */
1431 val = readl(sport->port.membase + UCR3);
1432 val &= ~UCR3_AWAKEN;
1433 writel(val, sport->port.membase + UCR3);
1434
1435 uart_resume_port(&imx_reg, &sport->port);
1436
1437 return 0;
1438 }
1439
1440 #ifdef CONFIG_OF
1441 /*
1442 * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it
1443 * could successfully get all information from dt or a negative errno.
1444 */
1445 static int serial_imx_probe_dt(struct imx_port *sport,
1446 struct platform_device *pdev)
1447 {
1448 struct device_node *np = pdev->dev.of_node;
1449 const struct of_device_id *of_id =
1450 of_match_device(imx_uart_dt_ids, &pdev->dev);
1451 int ret;
1452
1453 if (!np)
1454 /* no device tree device */
1455 return 1;
1456
1457 ret = of_alias_get_id(np, "serial");
1458 if (ret < 0) {
1459 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
1460 return ret;
1461 }
1462 sport->port.line = ret;
1463
1464 if (of_get_property(np, "fsl,uart-has-rtscts", NULL))
1465 sport->have_rtscts = 1;
1466
1467 if (of_get_property(np, "fsl,irda-mode", NULL))
1468 sport->use_irda = 1;
1469
1470 if (of_get_property(np, "fsl,dte-mode", NULL))
1471 sport->dte_mode = 1;
1472
1473 sport->devdata = of_id->data;
1474
1475 return 0;
1476 }
1477 #else
1478 static inline int serial_imx_probe_dt(struct imx_port *sport,
1479 struct platform_device *pdev)
1480 {
1481 return 1;
1482 }
1483 #endif
1484
1485 static void serial_imx_probe_pdata(struct imx_port *sport,
1486 struct platform_device *pdev)
1487 {
1488 struct imxuart_platform_data *pdata = pdev->dev.platform_data;
1489
1490 sport->port.line = pdev->id;
1491 sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data;
1492
1493 if (!pdata)
1494 return;
1495
1496 if (pdata->flags & IMXUART_HAVE_RTSCTS)
1497 sport->have_rtscts = 1;
1498
1499 if (pdata->flags & IMXUART_IRDA)
1500 sport->use_irda = 1;
1501 }
1502
1503 static int serial_imx_probe(struct platform_device *pdev)
1504 {
1505 struct imx_port *sport;
1506 struct imxuart_platform_data *pdata;
1507 void __iomem *base;
1508 int ret = 0;
1509 struct resource *res;
1510 struct pinctrl *pinctrl;
1511
1512 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
1513 if (!sport)
1514 return -ENOMEM;
1515
1516 ret = serial_imx_probe_dt(sport, pdev);
1517 if (ret > 0)
1518 serial_imx_probe_pdata(sport, pdev);
1519 else if (ret < 0)
1520 return ret;
1521
1522 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1523 if (!res)
1524 return -ENODEV;
1525
1526 base = devm_ioremap(&pdev->dev, res->start, PAGE_SIZE);
1527 if (!base)
1528 return -ENOMEM;
1529
1530 sport->port.dev = &pdev->dev;
1531 sport->port.mapbase = res->start;
1532 sport->port.membase = base;
1533 sport->port.type = PORT_IMX,
1534 sport->port.iotype = UPIO_MEM;
1535 sport->port.irq = platform_get_irq(pdev, 0);
1536 sport->rxirq = platform_get_irq(pdev, 0);
1537 sport->txirq = platform_get_irq(pdev, 1);
1538 sport->rtsirq = platform_get_irq(pdev, 2);
1539 sport->port.fifosize = 32;
1540 sport->port.ops = &imx_pops;
1541 sport->port.flags = UPF_BOOT_AUTOCONF;
1542 init_timer(&sport->timer);
1543 sport->timer.function = imx_timeout;
1544 sport->timer.data = (unsigned long)sport;
1545
1546 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
1547 if (IS_ERR(pinctrl)) {
1548 ret = PTR_ERR(pinctrl);
1549 dev_err(&pdev->dev, "failed to get default pinctrl: %d\n", ret);
1550 return ret;
1551 }
1552
1553 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1554 if (IS_ERR(sport->clk_ipg)) {
1555 ret = PTR_ERR(sport->clk_ipg);
1556 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
1557 return ret;
1558 }
1559
1560 sport->clk_per = devm_clk_get(&pdev->dev, "per");
1561 if (IS_ERR(sport->clk_per)) {
1562 ret = PTR_ERR(sport->clk_per);
1563 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
1564 return ret;
1565 }
1566
1567 clk_prepare_enable(sport->clk_per);
1568 clk_prepare_enable(sport->clk_ipg);
1569
1570 sport->port.uartclk = clk_get_rate(sport->clk_per);
1571
1572 imx_ports[sport->port.line] = sport;
1573
1574 pdata = pdev->dev.platform_data;
1575 if (pdata && pdata->init) {
1576 ret = pdata->init(pdev);
1577 if (ret)
1578 goto clkput;
1579 }
1580
1581 ret = uart_add_one_port(&imx_reg, &sport->port);
1582 if (ret)
1583 goto deinit;
1584 platform_set_drvdata(pdev, sport);
1585
1586 if (!uart_console(&sport->port)) {
1587 clk_disable_unprepare(sport->clk_per);
1588 clk_disable_unprepare(sport->clk_ipg);
1589 }
1590
1591 return 0;
1592 deinit:
1593 if (pdata && pdata->exit)
1594 pdata->exit(pdev);
1595 clkput:
1596 clk_disable_unprepare(sport->clk_per);
1597 clk_disable_unprepare(sport->clk_ipg);
1598 return ret;
1599 }
1600
1601 static int serial_imx_remove(struct platform_device *pdev)
1602 {
1603 struct imxuart_platform_data *pdata;
1604 struct imx_port *sport = platform_get_drvdata(pdev);
1605
1606 pdata = pdev->dev.platform_data;
1607
1608 platform_set_drvdata(pdev, NULL);
1609
1610 uart_remove_one_port(&imx_reg, &sport->port);
1611
1612 if (pdata && pdata->exit)
1613 pdata->exit(pdev);
1614
1615 return 0;
1616 }
1617
1618 static struct platform_driver serial_imx_driver = {
1619 .probe = serial_imx_probe,
1620 .remove = serial_imx_remove,
1621
1622 .suspend = serial_imx_suspend,
1623 .resume = serial_imx_resume,
1624 .id_table = imx_uart_devtype,
1625 .driver = {
1626 .name = "imx-uart",
1627 .owner = THIS_MODULE,
1628 .of_match_table = imx_uart_dt_ids,
1629 },
1630 };
1631
1632 static int __init imx_serial_init(void)
1633 {
1634 int ret;
1635
1636 pr_info("Serial: IMX driver\n");
1637
1638 ret = uart_register_driver(&imx_reg);
1639 if (ret)
1640 return ret;
1641
1642 ret = platform_driver_register(&serial_imx_driver);
1643 if (ret != 0)
1644 uart_unregister_driver(&imx_reg);
1645
1646 return ret;
1647 }
1648
1649 static void __exit imx_serial_exit(void)
1650 {
1651 platform_driver_unregister(&serial_imx_driver);
1652 uart_unregister_driver(&imx_reg);
1653 }
1654
1655 module_init(imx_serial_init);
1656 module_exit(imx_serial_exit);
1657
1658 MODULE_AUTHOR("Sascha Hauer");
1659 MODULE_DESCRIPTION("IMX generic serial port driver");
1660 MODULE_LICENSE("GPL");
1661 MODULE_ALIAS("platform:imx-uart");
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