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Linux 3.11-rc3
[cris-mirror.git] / drivers / tty / serial / mfd.c
blob4a82267af83fcc95786a79df2b260b84a5dea931
1 /*
2 * mfd.c: driver for High Speed UART device of Intel Medfield platform
3 *
4 * Refer pxa.c, 8250.c and some other drivers in drivers/serial/
5 *
6 * (C) Copyright 2010 Intel Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; version 2
11 * of the License.
12 */
13
14 /* Notes:
15 * 1. DMA channel allocation: 0/1 channel are assigned to port 0,
16 * 2/3 chan to port 1, 4/5 chan to port 3. Even number chans
17 * are used for RX, odd chans for TX
18 *
19 * 2. The RI/DSR/DCD/DTR are not pinned out, DCD & DSR are always
20 * asserted, only when the HW is reset the DDCD and DDSR will
21 * be triggered
22 */
23
24 #if defined(CONFIG_SERIAL_MFD_HSU_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
25 #define SUPPORT_SYSRQ
26 #endif
27
28 #include <linux/module.h>
29 #include <linux/init.h>
30 #include <linux/console.h>
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
33 #include <linux/serial_reg.h>
34 #include <linux/circ_buf.h>
35 #include <linux/delay.h>
36 #include <linux/interrupt.h>
37 #include <linux/tty.h>
38 #include <linux/tty_flip.h>
39 #include <linux/serial_core.h>
40 #include <linux/serial_mfd.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/pci.h>
43 #include <linux/nmi.h>
44 #include <linux/io.h>
45 #include <linux/debugfs.h>
46 #include <linux/pm_runtime.h>
47
48 #define HSU_DMA_BUF_SIZE 2048
49
50 #define chan_readl(chan, offset) readl(chan->reg + offset)
51 #define chan_writel(chan, offset, val) writel(val, chan->reg + offset)
52
53 #define mfd_readl(obj, offset) readl(obj->reg + offset)
54 #define mfd_writel(obj, offset, val) writel(val, obj->reg + offset)
55
56 static int hsu_dma_enable;
57 module_param(hsu_dma_enable, int, 0);
58 MODULE_PARM_DESC(hsu_dma_enable,
59 "It is a bitmap to set working mode, if bit[x] is 1, then port[x] will work in DMA mode, otherwise in PIO mode.");
60
61 struct hsu_dma_buffer {
62 u8 *buf;
63 dma_addr_t dma_addr;
64 u32 dma_size;
65 u32 ofs;
66 };
67
68 struct hsu_dma_chan {
69 u32 id;
70 enum dma_data_direction dirt;
71 struct uart_hsu_port *uport;
72 void __iomem *reg;
73 };
74
75 struct uart_hsu_port {
76 struct uart_port port;
77 unsigned char ier;
78 unsigned char lcr;
79 unsigned char mcr;
80 unsigned int lsr_break_flag;
81 char name[12];
82 int index;
83 struct device *dev;
84
85 struct hsu_dma_chan *txc;
86 struct hsu_dma_chan *rxc;
87 struct hsu_dma_buffer txbuf;
88 struct hsu_dma_buffer rxbuf;
89 int use_dma; /* flag for DMA/PIO */
90 int running;
91 int dma_tx_on;
92 };
93
94 /* Top level data structure of HSU */
95 struct hsu_port {
96 void __iomem *reg;
97 unsigned long paddr;
98 unsigned long iolen;
99 u32 irq;
100
101 struct uart_hsu_port port[3];
102 struct hsu_dma_chan chans[10];
103
104 struct dentry *debugfs;
105 };
106
107 static inline unsigned int serial_in(struct uart_hsu_port *up, int offset)
108 {
109 unsigned int val;
110
111 if (offset > UART_MSR) {
112 offset <<= 2;
113 val = readl(up->port.membase + offset);
114 } else
115 val = (unsigned int)readb(up->port.membase + offset);
116
117 return val;
118 }
119
120 static inline void serial_out(struct uart_hsu_port *up, int offset, int value)
121 {
122 if (offset > UART_MSR) {
123 offset <<= 2;
124 writel(value, up->port.membase + offset);
125 } else {
126 unsigned char val = value & 0xff;
127 writeb(val, up->port.membase + offset);
128 }
129 }
130
131 #ifdef CONFIG_DEBUG_FS
132
133 #define HSU_REGS_BUFSIZE 1024
134
135
136 static ssize_t port_show_regs(struct file *file, char __user *user_buf,
137 size_t count, loff_t *ppos)
138 {
139 struct uart_hsu_port *up = file->private_data;
140 char *buf;
141 u32 len = 0;
142 ssize_t ret;
143
144 buf = kzalloc(HSU_REGS_BUFSIZE, GFP_KERNEL);
145 if (!buf)
146 return 0;
147
148 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
149 "MFD HSU port[%d] regs:\n", up->index);
150
151 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
152 "=================================\n");
153 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
154 "IER: \t\t0x%08x\n", serial_in(up, UART_IER));
155 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
156 "IIR: \t\t0x%08x\n", serial_in(up, UART_IIR));
157 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
158 "LCR: \t\t0x%08x\n", serial_in(up, UART_LCR));
159 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
160 "MCR: \t\t0x%08x\n", serial_in(up, UART_MCR));
161 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
162 "LSR: \t\t0x%08x\n", serial_in(up, UART_LSR));
163 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
164 "MSR: \t\t0x%08x\n", serial_in(up, UART_MSR));
165 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
166 "FOR: \t\t0x%08x\n", serial_in(up, UART_FOR));
167 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
168 "PS: \t\t0x%08x\n", serial_in(up, UART_PS));
169 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
170 "MUL: \t\t0x%08x\n", serial_in(up, UART_MUL));
171 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
172 "DIV: \t\t0x%08x\n", serial_in(up, UART_DIV));
173
174 if (len > HSU_REGS_BUFSIZE)
175 len = HSU_REGS_BUFSIZE;
176
177 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
178 kfree(buf);
179 return ret;
180 }
181
182 static ssize_t dma_show_regs(struct file *file, char __user *user_buf,
183 size_t count, loff_t *ppos)
184 {
185 struct hsu_dma_chan *chan = file->private_data;
186 char *buf;
187 u32 len = 0;
188 ssize_t ret;
189
190 buf = kzalloc(HSU_REGS_BUFSIZE, GFP_KERNEL);
191 if (!buf)
192 return 0;
193
194 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
195 "MFD HSU DMA channel [%d] regs:\n", chan->id);
196
197 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
198 "=================================\n");
199 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
200 "CR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_CR));
201 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
202 "DCR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_DCR));
203 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
204 "BSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_BSR));
205 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
206 "MOTSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_MOTSR));
207 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
208 "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D0SAR));
209 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
210 "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D0TSR));
211 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
212 "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D1SAR));
213 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
214 "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D1TSR));
215 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
216 "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D2SAR));
217 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
218 "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D2TSR));
219 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
220 "D0SAR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D3SAR));
221 len += snprintf(buf + len, HSU_REGS_BUFSIZE - len,
222 "D0TSR: \t\t0x%08x\n", chan_readl(chan, HSU_CH_D3TSR));
223
224 if (len > HSU_REGS_BUFSIZE)
225 len = HSU_REGS_BUFSIZE;
226
227 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
228 kfree(buf);
229 return ret;
230 }
231
232 static const struct file_operations port_regs_ops = {
233 .owner = THIS_MODULE,
234 .open = simple_open,
235 .read = port_show_regs,
236 .llseek = default_llseek,
237 };
238
239 static const struct file_operations dma_regs_ops = {
240 .owner = THIS_MODULE,
241 .open = simple_open,
242 .read = dma_show_regs,
243 .llseek = default_llseek,
244 };
245
246 static int hsu_debugfs_init(struct hsu_port *hsu)
247 {
248 int i;
249 char name[32];
250
251 hsu->debugfs = debugfs_create_dir("hsu", NULL);
252 if (!hsu->debugfs)
253 return -ENOMEM;
254
255 for (i = 0; i < 3; i++) {
256 snprintf(name, sizeof(name), "port_%d_regs", i);
257 debugfs_create_file(name, S_IFREG | S_IRUGO,
258 hsu->debugfs, (void *)(&hsu->port[i]), &port_regs_ops);
259 }
260
261 for (i = 0; i < 6; i++) {
262 snprintf(name, sizeof(name), "dma_chan_%d_regs", i);
263 debugfs_create_file(name, S_IFREG | S_IRUGO,
264 hsu->debugfs, (void *)&hsu->chans[i], &dma_regs_ops);
265 }
266
267 return 0;
268 }
269
270 static void hsu_debugfs_remove(struct hsu_port *hsu)
271 {
272 if (hsu->debugfs)
273 debugfs_remove_recursive(hsu->debugfs);
274 }
275
276 #else
277 static inline int hsu_debugfs_init(struct hsu_port *hsu)
278 {
279 return 0;
280 }
281
282 static inline void hsu_debugfs_remove(struct hsu_port *hsu)
283 {
284 }
285 #endif /* CONFIG_DEBUG_FS */
286
287 static void serial_hsu_enable_ms(struct uart_port *port)
288 {
289 struct uart_hsu_port *up =
290 container_of(port, struct uart_hsu_port, port);
291
292 up->ier |= UART_IER_MSI;
293 serial_out(up, UART_IER, up->ier);
294 }
295
296 void hsu_dma_tx(struct uart_hsu_port *up)
297 {
298 struct circ_buf *xmit = &up->port.state->xmit;
299 struct hsu_dma_buffer *dbuf = &up->txbuf;
300 int count;
301
302 /* test_and_set_bit may be better, but anyway it's in lock protected mode */
303 if (up->dma_tx_on)
304 return;
305
306 /* Update the circ buf info */
307 xmit->tail += dbuf->ofs;
308 xmit->tail &= UART_XMIT_SIZE - 1;
309
310 up->port.icount.tx += dbuf->ofs;
311 dbuf->ofs = 0;
312
313 /* Disable the channel */
314 chan_writel(up->txc, HSU_CH_CR, 0x0);
315
316 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&up->port)) {
317 dma_sync_single_for_device(up->port.dev,
318 dbuf->dma_addr,
319 dbuf->dma_size,
320 DMA_TO_DEVICE);
321
322 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
323 dbuf->ofs = count;
324
325 /* Reprogram the channel */
326 chan_writel(up->txc, HSU_CH_D0SAR, dbuf->dma_addr + xmit->tail);
327 chan_writel(up->txc, HSU_CH_D0TSR, count);
328
329 /* Reenable the channel */
330 chan_writel(up->txc, HSU_CH_DCR, 0x1
331 | (0x1 << 8)
332 | (0x1 << 16)
333 | (0x1 << 24));
334 up->dma_tx_on = 1;
335 chan_writel(up->txc, HSU_CH_CR, 0x1);
336 }
337
338 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
339 uart_write_wakeup(&up->port);
340 }
341
342 /* The buffer is already cache coherent */
343 void hsu_dma_start_rx_chan(struct hsu_dma_chan *rxc, struct hsu_dma_buffer *dbuf)
344 {
345 dbuf->ofs = 0;
346
347 chan_writel(rxc, HSU_CH_BSR, 32);
348 chan_writel(rxc, HSU_CH_MOTSR, 4);
349
350 chan_writel(rxc, HSU_CH_D0SAR, dbuf->dma_addr);
351 chan_writel(rxc, HSU_CH_D0TSR, dbuf->dma_size);
352 chan_writel(rxc, HSU_CH_DCR, 0x1 | (0x1 << 8)
353 | (0x1 << 16)
354 | (0x1 << 24) /* timeout bit, see HSU Errata 1 */
355 );
356 chan_writel(rxc, HSU_CH_CR, 0x3);
357 }
358
359 /* Protected by spin_lock_irqsave(port->lock) */
360 static void serial_hsu_start_tx(struct uart_port *port)
361 {
362 struct uart_hsu_port *up =
363 container_of(port, struct uart_hsu_port, port);
364
365 if (up->use_dma) {
366 hsu_dma_tx(up);
367 } else if (!(up->ier & UART_IER_THRI)) {
368 up->ier |= UART_IER_THRI;
369 serial_out(up, UART_IER, up->ier);
370 }
371 }
372
373 static void serial_hsu_stop_tx(struct uart_port *port)
374 {
375 struct uart_hsu_port *up =
376 container_of(port, struct uart_hsu_port, port);
377 struct hsu_dma_chan *txc = up->txc;
378
379 if (up->use_dma)
380 chan_writel(txc, HSU_CH_CR, 0x0);
381 else if (up->ier & UART_IER_THRI) {
382 up->ier &= ~UART_IER_THRI;
383 serial_out(up, UART_IER, up->ier);
384 }
385 }
386
387 /* This is always called in spinlock protected mode, so
388 * modify timeout timer is safe here */
389 void hsu_dma_rx(struct uart_hsu_port *up, u32 int_sts)
390 {
391 struct hsu_dma_buffer *dbuf = &up->rxbuf;
392 struct hsu_dma_chan *chan = up->rxc;
393 struct uart_port *port = &up->port;
394 struct tty_port *tport = &port->state->port;
395 int count;
396
397 /*
398 * First need to know how many is already transferred,
399 * then check if its a timeout DMA irq, and return
400 * the trail bytes out, push them up and reenable the
401 * channel
402 */
403
404 /* Timeout IRQ, need wait some time, see Errata 2 */
405 if (int_sts & 0xf00)
406 udelay(2);
407
408 /* Stop the channel */
409 chan_writel(chan, HSU_CH_CR, 0x0);
410
411 count = chan_readl(chan, HSU_CH_D0SAR) - dbuf->dma_addr;
412 if (!count) {
413 /* Restart the channel before we leave */
414 chan_writel(chan, HSU_CH_CR, 0x3);
415 return;
416 }
417
418 dma_sync_single_for_cpu(port->dev, dbuf->dma_addr,
419 dbuf->dma_size, DMA_FROM_DEVICE);
420
421 /*
422 * Head will only wrap around when we recycle
423 * the DMA buffer, and when that happens, we
424 * explicitly set tail to 0. So head will
425 * always be greater than tail.
426 */
427 tty_insert_flip_string(tport, dbuf->buf, count);
428 port->icount.rx += count;
429
430 dma_sync_single_for_device(up->port.dev, dbuf->dma_addr,
431 dbuf->dma_size, DMA_FROM_DEVICE);
432
433 /* Reprogram the channel */
434 chan_writel(chan, HSU_CH_D0SAR, dbuf->dma_addr);
435 chan_writel(chan, HSU_CH_D0TSR, dbuf->dma_size);
436 chan_writel(chan, HSU_CH_DCR, 0x1
437 | (0x1 << 8)
438 | (0x1 << 16)
439 | (0x1 << 24) /* timeout bit, see HSU Errata 1 */
440 );
441 tty_flip_buffer_push(tport);
442
443 chan_writel(chan, HSU_CH_CR, 0x3);
444
445 }
446
447 static void serial_hsu_stop_rx(struct uart_port *port)
448 {
449 struct uart_hsu_port *up =
450 container_of(port, struct uart_hsu_port, port);
451 struct hsu_dma_chan *chan = up->rxc;
452
453 if (up->use_dma)
454 chan_writel(chan, HSU_CH_CR, 0x2);
455 else {
456 up->ier &= ~UART_IER_RLSI;
457 up->port.read_status_mask &= ~UART_LSR_DR;
458 serial_out(up, UART_IER, up->ier);
459 }
460 }
461
462 static inline void receive_chars(struct uart_hsu_port *up, int *status)
463 {
464 unsigned int ch, flag;
465 unsigned int max_count = 256;
466
467 do {
468 ch = serial_in(up, UART_RX);
469 flag = TTY_NORMAL;
470 up->port.icount.rx++;
471
472 if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE |
473 UART_LSR_FE | UART_LSR_OE))) {
474
475 dev_warn(up->dev, "We really rush into ERR/BI case"
476 "status = 0x%02x", *status);
477 /* For statistics only */
478 if (*status & UART_LSR_BI) {
479 *status &= ~(UART_LSR_FE | UART_LSR_PE);
480 up->port.icount.brk++;
481 /*
482 * We do the SysRQ and SAK checking
483 * here because otherwise the break
484 * may get masked by ignore_status_mask
485 * or read_status_mask.
486 */
487 if (uart_handle_break(&up->port))
488 goto ignore_char;
489 } else if (*status & UART_LSR_PE)
490 up->port.icount.parity++;
491 else if (*status & UART_LSR_FE)
492 up->port.icount.frame++;
493 if (*status & UART_LSR_OE)
494 up->port.icount.overrun++;
495
496 /* Mask off conditions which should be ignored. */
497 *status &= up->port.read_status_mask;
498
499 #ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE
500 if (up->port.cons &&
501 up->port.cons->index == up->port.line) {
502 /* Recover the break flag from console xmit */
503 *status |= up->lsr_break_flag;
504 up->lsr_break_flag = 0;
505 }
506 #endif
507 if (*status & UART_LSR_BI) {
508 flag = TTY_BREAK;
509 } else if (*status & UART_LSR_PE)
510 flag = TTY_PARITY;
511 else if (*status & UART_LSR_FE)
512 flag = TTY_FRAME;
513 }
514
515 if (uart_handle_sysrq_char(&up->port, ch))
516 goto ignore_char;
517
518 uart_insert_char(&up->port, *status, UART_LSR_OE, ch, flag);
519 ignore_char:
520 *status = serial_in(up, UART_LSR);
521 } while ((*status & UART_LSR_DR) && max_count--);
522 tty_flip_buffer_push(&up->port.state->port);
523 }
524
525 static void transmit_chars(struct uart_hsu_port *up)
526 {
527 struct circ_buf *xmit = &up->port.state->xmit;
528 int count;
529
530 if (up->port.x_char) {
531 serial_out(up, UART_TX, up->port.x_char);
532 up->port.icount.tx++;
533 up->port.x_char = 0;
534 return;
535 }
536 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
537 serial_hsu_stop_tx(&up->port);
538 return;
539 }
540
541 /* The IRQ is for TX FIFO half-empty */
542 count = up->port.fifosize / 2;
543
544 do {
545 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
546 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
547
548 up->port.icount.tx++;
549 if (uart_circ_empty(xmit))
550 break;
551 } while (--count > 0);
552
553 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
554 uart_write_wakeup(&up->port);
555
556 if (uart_circ_empty(xmit))
557 serial_hsu_stop_tx(&up->port);
558 }
559
560 static inline void check_modem_status(struct uart_hsu_port *up)
561 {
562 int status;
563
564 status = serial_in(up, UART_MSR);
565
566 if ((status & UART_MSR_ANY_DELTA) == 0)
567 return;
568
569 if (status & UART_MSR_TERI)
570 up->port.icount.rng++;
571 if (status & UART_MSR_DDSR)
572 up->port.icount.dsr++;
573 /* We may only get DDCD when HW init and reset */
574 if (status & UART_MSR_DDCD)
575 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
576 /* Will start/stop_tx accordingly */
577 if (status & UART_MSR_DCTS)
578 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
579
580 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
581 }
582
583 /*
584 * This handles the interrupt from one port.
585 */
586 static irqreturn_t port_irq(int irq, void *dev_id)
587 {
588 struct uart_hsu_port *up = dev_id;
589 unsigned int iir, lsr;
590 unsigned long flags;
591
592 if (unlikely(!up->running))
593 return IRQ_NONE;
594
595 spin_lock_irqsave(&up->port.lock, flags);
596 if (up->use_dma) {
597 lsr = serial_in(up, UART_LSR);
598 if (unlikely(lsr & (UART_LSR_BI | UART_LSR_PE |
599 UART_LSR_FE | UART_LSR_OE)))
600 dev_warn(up->dev,
601 "Got lsr irq while using DMA, lsr = 0x%2x\n",
602 lsr);
603 check_modem_status(up);
604 spin_unlock_irqrestore(&up->port.lock, flags);
605 return IRQ_HANDLED;
606 }
607
608 iir = serial_in(up, UART_IIR);
609 if (iir & UART_IIR_NO_INT) {
610 spin_unlock_irqrestore(&up->port.lock, flags);
611 return IRQ_NONE;
612 }
613
614 lsr = serial_in(up, UART_LSR);
615 if (lsr & UART_LSR_DR)
616 receive_chars(up, &lsr);
617 check_modem_status(up);
618
619 /* lsr will be renewed during the receive_chars */
620 if (lsr & UART_LSR_THRE)
621 transmit_chars(up);
622
623 spin_unlock_irqrestore(&up->port.lock, flags);
624 return IRQ_HANDLED;
625 }
626
627 static inline void dma_chan_irq(struct hsu_dma_chan *chan)
628 {
629 struct uart_hsu_port *up = chan->uport;
630 unsigned long flags;
631 u32 int_sts;
632
633 spin_lock_irqsave(&up->port.lock, flags);
634
635 if (!up->use_dma || !up->running)
636 goto exit;
637
638 /*
639 * No matter what situation, need read clear the IRQ status
640 * There is a bug, see Errata 5, HSD 2900918
641 */
642 int_sts = chan_readl(chan, HSU_CH_SR);
643
644 /* Rx channel */
645 if (chan->dirt == DMA_FROM_DEVICE)
646 hsu_dma_rx(up, int_sts);
647
648 /* Tx channel */
649 if (chan->dirt == DMA_TO_DEVICE) {
650 chan_writel(chan, HSU_CH_CR, 0x0);
651 up->dma_tx_on = 0;
652 hsu_dma_tx(up);
653 }
654
655 exit:
656 spin_unlock_irqrestore(&up->port.lock, flags);
657 return;
658 }
659
660 static irqreturn_t dma_irq(int irq, void *dev_id)
661 {
662 struct hsu_port *hsu = dev_id;
663 u32 int_sts, i;
664
665 int_sts = mfd_readl(hsu, HSU_GBL_DMAISR);
666
667 /* Currently we only have 6 channels may be used */
668 for (i = 0; i < 6; i++) {
669 if (int_sts & 0x1)
670 dma_chan_irq(&hsu->chans[i]);
671 int_sts >>= 1;
672 }
673
674 return IRQ_HANDLED;
675 }
676
677 static unsigned int serial_hsu_tx_empty(struct uart_port *port)
678 {
679 struct uart_hsu_port *up =
680 container_of(port, struct uart_hsu_port, port);
681 unsigned long flags;
682 unsigned int ret;
683
684 spin_lock_irqsave(&up->port.lock, flags);
685 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
686 spin_unlock_irqrestore(&up->port.lock, flags);
687
688 return ret;
689 }
690
691 static unsigned int serial_hsu_get_mctrl(struct uart_port *port)
692 {
693 struct uart_hsu_port *up =
694 container_of(port, struct uart_hsu_port, port);
695 unsigned char status;
696 unsigned int ret;
697
698 status = serial_in(up, UART_MSR);
699
700 ret = 0;
701 if (status & UART_MSR_DCD)
702 ret |= TIOCM_CAR;
703 if (status & UART_MSR_RI)
704 ret |= TIOCM_RNG;
705 if (status & UART_MSR_DSR)
706 ret |= TIOCM_DSR;
707 if (status & UART_MSR_CTS)
708 ret |= TIOCM_CTS;
709 return ret;
710 }
711
712 static void serial_hsu_set_mctrl(struct uart_port *port, unsigned int mctrl)
713 {
714 struct uart_hsu_port *up =
715 container_of(port, struct uart_hsu_port, port);
716 unsigned char mcr = 0;
717
718 if (mctrl & TIOCM_RTS)
719 mcr |= UART_MCR_RTS;
720 if (mctrl & TIOCM_DTR)
721 mcr |= UART_MCR_DTR;
722 if (mctrl & TIOCM_OUT1)
723 mcr |= UART_MCR_OUT1;
724 if (mctrl & TIOCM_OUT2)
725 mcr |= UART_MCR_OUT2;
726 if (mctrl & TIOCM_LOOP)
727 mcr |= UART_MCR_LOOP;
728
729 mcr |= up->mcr;
730
731 serial_out(up, UART_MCR, mcr);
732 }
733
734 static void serial_hsu_break_ctl(struct uart_port *port, int break_state)
735 {
736 struct uart_hsu_port *up =
737 container_of(port, struct uart_hsu_port, port);
738 unsigned long flags;
739
740 spin_lock_irqsave(&up->port.lock, flags);
741 if (break_state == -1)
742 up->lcr |= UART_LCR_SBC;
743 else
744 up->lcr &= ~UART_LCR_SBC;
745 serial_out(up, UART_LCR, up->lcr);
746 spin_unlock_irqrestore(&up->port.lock, flags);
747 }
748
749 /*
750 * What special to do:
751 * 1. chose the 64B fifo mode
752 * 2. start dma or pio depends on configuration
753 * 3. we only allocate dma memory when needed
754 */
755 static int serial_hsu_startup(struct uart_port *port)
756 {
757 struct uart_hsu_port *up =
758 container_of(port, struct uart_hsu_port, port);
759 unsigned long flags;
760
761 pm_runtime_get_sync(up->dev);
762
763 /*
764 * Clear the FIFO buffers and disable them.
765 * (they will be reenabled in set_termios())
766 */
767 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
768 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
769 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
770 serial_out(up, UART_FCR, 0);
771
772 /* Clear the interrupt registers. */
773 (void) serial_in(up, UART_LSR);
774 (void) serial_in(up, UART_RX);
775 (void) serial_in(up, UART_IIR);
776 (void) serial_in(up, UART_MSR);
777
778 /* Now, initialize the UART, default is 8n1 */
779 serial_out(up, UART_LCR, UART_LCR_WLEN8);
780
781 spin_lock_irqsave(&up->port.lock, flags);
782
783 up->port.mctrl |= TIOCM_OUT2;
784 serial_hsu_set_mctrl(&up->port, up->port.mctrl);
785
786 /*
787 * Finally, enable interrupts. Note: Modem status interrupts
788 * are set via set_termios(), which will be occurring imminently
789 * anyway, so we don't enable them here.
790 */
791 if (!up->use_dma)
792 up->ier = UART_IER_RLSI | UART_IER_RDI | UART_IER_RTOIE;
793 else
794 up->ier = 0;
795 serial_out(up, UART_IER, up->ier);
796
797 spin_unlock_irqrestore(&up->port.lock, flags);
798
799 /* DMA init */
800 if (up->use_dma) {
801 struct hsu_dma_buffer *dbuf;
802 struct circ_buf *xmit = &port->state->xmit;
803
804 up->dma_tx_on = 0;
805
806 /* First allocate the RX buffer */
807 dbuf = &up->rxbuf;
808 dbuf->buf = kzalloc(HSU_DMA_BUF_SIZE, GFP_KERNEL);
809 if (!dbuf->buf) {
810 up->use_dma = 0;
811 goto exit;
812 }
813 dbuf->dma_addr = dma_map_single(port->dev,
814 dbuf->buf,
815 HSU_DMA_BUF_SIZE,
816 DMA_FROM_DEVICE);
817 dbuf->dma_size = HSU_DMA_BUF_SIZE;
818
819 /* Start the RX channel right now */
820 hsu_dma_start_rx_chan(up->rxc, dbuf);
821
822 /* Next init the TX DMA */
823 dbuf = &up->txbuf;
824 dbuf->buf = xmit->buf;
825 dbuf->dma_addr = dma_map_single(port->dev,
826 dbuf->buf,
827 UART_XMIT_SIZE,
828 DMA_TO_DEVICE);
829 dbuf->dma_size = UART_XMIT_SIZE;
830
831 /* This should not be changed all around */
832 chan_writel(up->txc, HSU_CH_BSR, 32);
833 chan_writel(up->txc, HSU_CH_MOTSR, 4);
834 dbuf->ofs = 0;
835 }
836
837 exit:
838 /* And clear the interrupt registers again for luck. */
839 (void) serial_in(up, UART_LSR);
840 (void) serial_in(up, UART_RX);
841 (void) serial_in(up, UART_IIR);
842 (void) serial_in(up, UART_MSR);
843
844 up->running = 1;
845 return 0;
846 }
847
848 static void serial_hsu_shutdown(struct uart_port *port)
849 {
850 struct uart_hsu_port *up =
851 container_of(port, struct uart_hsu_port, port);
852 unsigned long flags;
853
854 /* Disable interrupts from this port */
855 up->ier = 0;
856 serial_out(up, UART_IER, 0);
857 up->running = 0;
858
859 spin_lock_irqsave(&up->port.lock, flags);
860 up->port.mctrl &= ~TIOCM_OUT2;
861 serial_hsu_set_mctrl(&up->port, up->port.mctrl);
862 spin_unlock_irqrestore(&up->port.lock, flags);
863
864 /* Disable break condition and FIFOs */
865 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
866 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
867 UART_FCR_CLEAR_RCVR |
868 UART_FCR_CLEAR_XMIT);
869 serial_out(up, UART_FCR, 0);
870
871 pm_runtime_put(up->dev);
872 }
873
874 static void
875 serial_hsu_set_termios(struct uart_port *port, struct ktermios *termios,
876 struct ktermios *old)
877 {
878 struct uart_hsu_port *up =
879 container_of(port, struct uart_hsu_port, port);
880 unsigned char cval, fcr = 0;
881 unsigned long flags;
882 unsigned int baud, quot;
883 u32 ps, mul;
884
885 switch (termios->c_cflag & CSIZE) {
886 case CS5:
887 cval = UART_LCR_WLEN5;
888 break;
889 case CS6:
890 cval = UART_LCR_WLEN6;
891 break;
892 case CS7:
893 cval = UART_LCR_WLEN7;
894 break;
895 default:
896 case CS8:
897 cval = UART_LCR_WLEN8;
898 break;
899 }
900
901 /* CMSPAR isn't supported by this driver */
902 termios->c_cflag &= ~CMSPAR;
903
904 if (termios->c_cflag & CSTOPB)
905 cval |= UART_LCR_STOP;
906 if (termios->c_cflag & PARENB)
907 cval |= UART_LCR_PARITY;
908 if (!(termios->c_cflag & PARODD))
909 cval |= UART_LCR_EPAR;
910
911 /*
912 * The base clk is 50Mhz, and the baud rate come from:
913 * baud = 50M * MUL / (DIV * PS * DLAB)
914 *
915 * For those basic low baud rate we can get the direct
916 * scalar from 2746800, like 115200 = 2746800/24. For those
917 * higher baud rate, we handle them case by case, mainly by
918 * adjusting the MUL/PS registers, and DIV register is kept
919 * as default value 0x3d09 to make things simple
920 */
921 baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
922
923 quot = 1;
924 ps = 0x10;
925 mul = 0x3600;
926 switch (baud) {
927 case 3500000:
928 mul = 0x3345;
929 ps = 0xC;
930 break;
931 case 1843200:
932 mul = 0x2400;
933 break;
934 case 3000000:
935 case 2500000:
936 case 2000000:
937 case 1500000:
938 case 1000000:
939 case 500000:
940 /* mul/ps/quot = 0x9C4/0x10/0x1 will make a 500000 bps */
941 mul = baud / 500000 * 0x9C4;
942 break;
943 default:
944 /* Use uart_get_divisor to get quot for other baud rates */
945 quot = 0;
946 }
947
948 if (!quot)
949 quot = uart_get_divisor(port, baud);
950
951 if ((up->port.uartclk / quot) < (2400 * 16))
952 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_1B;
953 else if ((up->port.uartclk / quot) < (230400 * 16))
954 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_16B;
955 else
956 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_HSU_64_32B;
957
958 fcr |= UART_FCR_HSU_64B_FIFO;
959
960 /*
961 * Ok, we're now changing the port state. Do it with
962 * interrupts disabled.
963 */
964 spin_lock_irqsave(&up->port.lock, flags);
965
966 /* Update the per-port timeout */
967 uart_update_timeout(port, termios->c_cflag, baud);
968
969 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
970 if (termios->c_iflag & INPCK)
971 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
972 if (termios->c_iflag & (BRKINT | PARMRK))
973 up->port.read_status_mask |= UART_LSR_BI;
974
975 /* Characters to ignore */
976 up->port.ignore_status_mask = 0;
977 if (termios->c_iflag & IGNPAR)
978 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
979 if (termios->c_iflag & IGNBRK) {
980 up->port.ignore_status_mask |= UART_LSR_BI;
981 /*
982 * If we're ignoring parity and break indicators,
983 * ignore overruns too (for real raw support).
984 */
985 if (termios->c_iflag & IGNPAR)
986 up->port.ignore_status_mask |= UART_LSR_OE;
987 }
988
989 /* Ignore all characters if CREAD is not set */
990 if ((termios->c_cflag & CREAD) == 0)
991 up->port.ignore_status_mask |= UART_LSR_DR;
992
993 /*
994 * CTS flow control flag and modem status interrupts, disable
995 * MSI by default
996 */
997 up->ier &= ~UART_IER_MSI;
998 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
999 up->ier |= UART_IER_MSI;
1000
1001 serial_out(up, UART_IER, up->ier);
1002
1003 if (termios->c_cflag & CRTSCTS)
1004 up->mcr |= UART_MCR_AFE | UART_MCR_RTS;
1005 else
1006 up->mcr &= ~UART_MCR_AFE;
1007
1008 serial_out(up, UART_LCR, cval | UART_LCR_DLAB); /* set DLAB */
1009 serial_out(up, UART_DLL, quot & 0xff); /* LS of divisor */
1010 serial_out(up, UART_DLM, quot >> 8); /* MS of divisor */
1011 serial_out(up, UART_LCR, cval); /* reset DLAB */
1012 serial_out(up, UART_MUL, mul); /* set MUL */
1013 serial_out(up, UART_PS, ps); /* set PS */
1014 up->lcr = cval; /* Save LCR */
1015 serial_hsu_set_mctrl(&up->port, up->port.mctrl);
1016 serial_out(up, UART_FCR, fcr);
1017 spin_unlock_irqrestore(&up->port.lock, flags);
1018 }
1019
1020 static void
1021 serial_hsu_pm(struct uart_port *port, unsigned int state,
1022 unsigned int oldstate)
1023 {
1024 }
1025
1026 static void serial_hsu_release_port(struct uart_port *port)
1027 {
1028 }
1029
1030 static int serial_hsu_request_port(struct uart_port *port)
1031 {
1032 return 0;
1033 }
1034
1035 static void serial_hsu_config_port(struct uart_port *port, int flags)
1036 {
1037 struct uart_hsu_port *up =
1038 container_of(port, struct uart_hsu_port, port);
1039 up->port.type = PORT_MFD;
1040 }
1041
1042 static int
1043 serial_hsu_verify_port(struct uart_port *port, struct serial_struct *ser)
1044 {
1045 /* We don't want the core code to modify any port params */
1046 return -EINVAL;
1047 }
1048
1049 static const char *
1050 serial_hsu_type(struct uart_port *port)
1051 {
1052 struct uart_hsu_port *up =
1053 container_of(port, struct uart_hsu_port, port);
1054 return up->name;
1055 }
1056
1057 /* Mainly for uart console use */
1058 static struct uart_hsu_port *serial_hsu_ports[3];
1059 static struct uart_driver serial_hsu_reg;
1060
1061 #ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE
1062
1063 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1064
1065 /* Wait for transmitter & holding register to empty */
1066 static inline void wait_for_xmitr(struct uart_hsu_port *up)
1067 {
1068 unsigned int status, tmout = 1000;
1069
1070 /* Wait up to 1ms for the character to be sent. */
1071 do {
1072 status = serial_in(up, UART_LSR);
1073
1074 if (status & UART_LSR_BI)
1075 up->lsr_break_flag = UART_LSR_BI;
1076
1077 if (--tmout == 0)
1078 break;
1079 udelay(1);
1080 } while (!(status & BOTH_EMPTY));
1081
1082 /* Wait up to 1s for flow control if necessary */
1083 if (up->port.flags & UPF_CONS_FLOW) {
1084 tmout = 1000000;
1085 while (--tmout &&
1086 ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0))
1087 udelay(1);
1088 }
1089 }
1090
1091 static void serial_hsu_console_putchar(struct uart_port *port, int ch)
1092 {
1093 struct uart_hsu_port *up =
1094 container_of(port, struct uart_hsu_port, port);
1095
1096 wait_for_xmitr(up);
1097 serial_out(up, UART_TX, ch);
1098 }
1099
1100 /*
1101 * Print a string to the serial port trying not to disturb
1102 * any possible real use of the port...
1103 *
1104 * The console_lock must be held when we get here.
1105 */
1106 static void
1107 serial_hsu_console_write(struct console *co, const char *s, unsigned int count)
1108 {
1109 struct uart_hsu_port *up = serial_hsu_ports[co->index];
1110 unsigned long flags;
1111 unsigned int ier;
1112 int locked = 1;
1113
1114 touch_nmi_watchdog();
1115
1116 local_irq_save(flags);
1117 if (up->port.sysrq)
1118 locked = 0;
1119 else if (oops_in_progress) {
1120 locked = spin_trylock(&up->port.lock);
1121 } else
1122 spin_lock(&up->port.lock);
1123
1124 /* First save the IER then disable the interrupts */
1125 ier = serial_in(up, UART_IER);
1126 serial_out(up, UART_IER, 0);
1127
1128 uart_console_write(&up->port, s, count, serial_hsu_console_putchar);
1129
1130 /*
1131 * Finally, wait for transmitter to become empty
1132 * and restore the IER
1133 */
1134 wait_for_xmitr(up);
1135 serial_out(up, UART_IER, ier);
1136
1137 if (locked)
1138 spin_unlock(&up->port.lock);
1139 local_irq_restore(flags);
1140 }
1141
1142 static struct console serial_hsu_console;
1143
1144 static int __init
1145 serial_hsu_console_setup(struct console *co, char *options)
1146 {
1147 struct uart_hsu_port *up;
1148 int baud = 115200;
1149 int bits = 8;
1150 int parity = 'n';
1151 int flow = 'n';
1152
1153 if (co->index == -1 || co->index >= serial_hsu_reg.nr)
1154 co->index = 0;
1155 up = serial_hsu_ports[co->index];
1156 if (!up)
1157 return -ENODEV;
1158
1159 if (options)
1160 uart_parse_options(options, &baud, &parity, &bits, &flow);
1161
1162 return uart_set_options(&up->port, co, baud, parity, bits, flow);
1163 }
1164
1165 static struct console serial_hsu_console = {
1166 .name = "ttyMFD",
1167 .write = serial_hsu_console_write,
1168 .device = uart_console_device,
1169 .setup = serial_hsu_console_setup,
1170 .flags = CON_PRINTBUFFER,
1171 .index = -1,
1172 .data = &serial_hsu_reg,
1173 };
1174
1175 #define SERIAL_HSU_CONSOLE (&serial_hsu_console)
1176 #else
1177 #define SERIAL_HSU_CONSOLE NULL
1178 #endif
1179
1180 struct uart_ops serial_hsu_pops = {
1181 .tx_empty = serial_hsu_tx_empty,
1182 .set_mctrl = serial_hsu_set_mctrl,
1183 .get_mctrl = serial_hsu_get_mctrl,
1184 .stop_tx = serial_hsu_stop_tx,
1185 .start_tx = serial_hsu_start_tx,
1186 .stop_rx = serial_hsu_stop_rx,
1187 .enable_ms = serial_hsu_enable_ms,
1188 .break_ctl = serial_hsu_break_ctl,
1189 .startup = serial_hsu_startup,
1190 .shutdown = serial_hsu_shutdown,
1191 .set_termios = serial_hsu_set_termios,
1192 .pm = serial_hsu_pm,
1193 .type = serial_hsu_type,
1194 .release_port = serial_hsu_release_port,
1195 .request_port = serial_hsu_request_port,
1196 .config_port = serial_hsu_config_port,
1197 .verify_port = serial_hsu_verify_port,
1198 };
1199
1200 static struct uart_driver serial_hsu_reg = {
1201 .owner = THIS_MODULE,
1202 .driver_name = "MFD serial",
1203 .dev_name = "ttyMFD",
1204 .major = TTY_MAJOR,
1205 .minor = 128,
1206 .nr = 3,
1207 .cons = SERIAL_HSU_CONSOLE,
1208 };
1209
1210 #ifdef CONFIG_PM
1211 static int serial_hsu_suspend(struct pci_dev *pdev, pm_message_t state)
1212 {
1213 void *priv = pci_get_drvdata(pdev);
1214 struct uart_hsu_port *up;
1215
1216 /* Make sure this is not the internal dma controller */
1217 if (priv && (pdev->device != 0x081E)) {
1218 up = priv;
1219 uart_suspend_port(&serial_hsu_reg, &up->port);
1220 }
1221
1222 pci_save_state(pdev);
1223 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1224 return 0;
1225 }
1226
1227 static int serial_hsu_resume(struct pci_dev *pdev)
1228 {
1229 void *priv = pci_get_drvdata(pdev);
1230 struct uart_hsu_port *up;
1231 int ret;
1232
1233 pci_set_power_state(pdev, PCI_D0);
1234 pci_restore_state(pdev);
1235
1236 ret = pci_enable_device(pdev);
1237 if (ret)
1238 dev_warn(&pdev->dev,
1239 "HSU: can't re-enable device, try to continue\n");
1240
1241 if (priv && (pdev->device != 0x081E)) {
1242 up = priv;
1243 uart_resume_port(&serial_hsu_reg, &up->port);
1244 }
1245 return 0;
1246 }
1247 #else
1248 #define serial_hsu_suspend NULL
1249 #define serial_hsu_resume NULL
1250 #endif
1251
1252 #ifdef CONFIG_PM_RUNTIME
1253 static int serial_hsu_runtime_idle(struct device *dev)
1254 {
1255 pm_schedule_suspend(dev, 500);
1256 return -EBUSY;
1257 }
1258
1259 static int serial_hsu_runtime_suspend(struct device *dev)
1260 {
1261 return 0;
1262 }
1263
1264 static int serial_hsu_runtime_resume(struct device *dev)
1265 {
1266 return 0;
1267 }
1268 #else
1269 #define serial_hsu_runtime_idle NULL
1270 #define serial_hsu_runtime_suspend NULL
1271 #define serial_hsu_runtime_resume NULL
1272 #endif
1273
1274 static const struct dev_pm_ops serial_hsu_pm_ops = {
1275 .runtime_suspend = serial_hsu_runtime_suspend,
1276 .runtime_resume = serial_hsu_runtime_resume,
1277 .runtime_idle = serial_hsu_runtime_idle,
1278 };
1279
1280 /* temp global pointer before we settle down on using one or four PCI dev */
1281 static struct hsu_port *phsu;
1282
1283 static int serial_hsu_probe(struct pci_dev *pdev,
1284 const struct pci_device_id *ent)
1285 {
1286 struct uart_hsu_port *uport;
1287 int index, ret;
1288
1289 printk(KERN_INFO "HSU: found PCI Serial controller(ID: %04x:%04x)\n",
1290 pdev->vendor, pdev->device);
1291
1292 switch (pdev->device) {
1293 case 0x081B:
1294 index = 0;
1295 break;
1296 case 0x081C:
1297 index = 1;
1298 break;
1299 case 0x081D:
1300 index = 2;
1301 break;
1302 case 0x081E:
1303 /* internal DMA controller */
1304 index = 3;
1305 break;
1306 default:
1307 dev_err(&pdev->dev, "HSU: out of index!");
1308 return -ENODEV;
1309 }
1310
1311 ret = pci_enable_device(pdev);
1312 if (ret)
1313 return ret;
1314
1315 if (index == 3) {
1316 /* DMA controller */
1317 ret = request_irq(pdev->irq, dma_irq, 0, "hsu_dma", phsu);
1318 if (ret) {
1319 dev_err(&pdev->dev, "can not get IRQ\n");
1320 goto err_disable;
1321 }
1322 pci_set_drvdata(pdev, phsu);
1323 } else {
1324 /* UART port 0~2 */
1325 uport = &phsu->port[index];
1326 uport->port.irq = pdev->irq;
1327 uport->port.dev = &pdev->dev;
1328 uport->dev = &pdev->dev;
1329
1330 ret = request_irq(pdev->irq, port_irq, 0, uport->name, uport);
1331 if (ret) {
1332 dev_err(&pdev->dev, "can not get IRQ\n");
1333 goto err_disable;
1334 }
1335 uart_add_one_port(&serial_hsu_reg, &uport->port);
1336
1337 pci_set_drvdata(pdev, uport);
1338 }
1339
1340 pm_runtime_put_noidle(&pdev->dev);
1341 pm_runtime_allow(&pdev->dev);
1342
1343 return 0;
1344
1345 err_disable:
1346 pci_disable_device(pdev);
1347 return ret;
1348 }
1349
1350 static void hsu_global_init(void)
1351 {
1352 struct hsu_port *hsu;
1353 struct uart_hsu_port *uport;
1354 struct hsu_dma_chan *dchan;
1355 int i, ret;
1356
1357 hsu = kzalloc(sizeof(struct hsu_port), GFP_KERNEL);
1358 if (!hsu)
1359 return;
1360
1361 /* Get basic io resource and map it */
1362 hsu->paddr = 0xffa28000;
1363 hsu->iolen = 0x1000;
1364
1365 if (!(request_mem_region(hsu->paddr, hsu->iolen, "HSU global")))
1366 pr_warning("HSU: error in request mem region\n");
1367
1368 hsu->reg = ioremap_nocache((unsigned long)hsu->paddr, hsu->iolen);
1369 if (!hsu->reg) {
1370 pr_err("HSU: error in ioremap\n");
1371 ret = -ENOMEM;
1372 goto err_free_region;
1373 }
1374
1375 /* Initialise the 3 UART ports */
1376 uport = hsu->port;
1377 for (i = 0; i < 3; i++) {
1378 uport->port.type = PORT_MFD;
1379 uport->port.iotype = UPIO_MEM;
1380 uport->port.mapbase = (resource_size_t)hsu->paddr
1381 + HSU_PORT_REG_OFFSET
1382 + i * HSU_PORT_REG_LENGTH;
1383 uport->port.membase = hsu->reg + HSU_PORT_REG_OFFSET
1384 + i * HSU_PORT_REG_LENGTH;
1385
1386 sprintf(uport->name, "hsu_port%d", i);
1387 uport->port.fifosize = 64;
1388 uport->port.ops = &serial_hsu_pops;
1389 uport->port.line = i;
1390 uport->port.flags = UPF_IOREMAP;
1391 /* set the scalable maxim support rate to 2746800 bps */
1392 uport->port.uartclk = 115200 * 24 * 16;
1393
1394 uport->running = 0;
1395 uport->txc = &hsu->chans[i * 2];
1396 uport->rxc = &hsu->chans[i * 2 + 1];
1397
1398 serial_hsu_ports[i] = uport;
1399 uport->index = i;
1400
1401 if (hsu_dma_enable & (1<<i))
1402 uport->use_dma = 1;
1403 else
1404 uport->use_dma = 0;
1405
1406 uport++;
1407 }
1408
1409 /* Initialise 6 dma channels */
1410 dchan = hsu->chans;
1411 for (i = 0; i < 6; i++) {
1412 dchan->id = i;
1413 dchan->dirt = (i & 0x1) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1414 dchan->uport = &hsu->port[i/2];
1415 dchan->reg = hsu->reg + HSU_DMA_CHANS_REG_OFFSET +
1416 i * HSU_DMA_CHANS_REG_LENGTH;
1417
1418 dchan++;
1419 }
1420
1421 phsu = hsu;
1422 hsu_debugfs_init(hsu);
1423 return;
1424
1425 err_free_region:
1426 release_mem_region(hsu->paddr, hsu->iolen);
1427 kfree(hsu);
1428 return;
1429 }
1430
1431 static void serial_hsu_remove(struct pci_dev *pdev)
1432 {
1433 void *priv = pci_get_drvdata(pdev);
1434 struct uart_hsu_port *up;
1435
1436 if (!priv)
1437 return;
1438
1439 pm_runtime_forbid(&pdev->dev);
1440 pm_runtime_get_noresume(&pdev->dev);
1441
1442 /* For port 0/1/2, priv is the address of uart_hsu_port */
1443 if (pdev->device != 0x081E) {
1444 up = priv;
1445 uart_remove_one_port(&serial_hsu_reg, &up->port);
1446 }
1447
1448 pci_set_drvdata(pdev, NULL);
1449 free_irq(pdev->irq, priv);
1450 pci_disable_device(pdev);
1451 }
1452
1453 /* First 3 are UART ports, and the 4th is the DMA */
1454 static const struct pci_device_id pci_ids[] = {
1455 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081B) },
1456 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081C) },
1457 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081D) },
1458 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081E) },
1459 {},
1460 };
1461
1462 static struct pci_driver hsu_pci_driver = {
1463 .name = "HSU serial",
1464 .id_table = pci_ids,
1465 .probe = serial_hsu_probe,
1466 .remove = serial_hsu_remove,
1467 .suspend = serial_hsu_suspend,
1468 .resume = serial_hsu_resume,
1469 .driver = {
1470 .pm = &serial_hsu_pm_ops,
1471 },
1472 };
1473
1474 static int __init hsu_pci_init(void)
1475 {
1476 int ret;
1477
1478 hsu_global_init();
1479
1480 ret = uart_register_driver(&serial_hsu_reg);
1481 if (ret)
1482 return ret;
1483
1484 return pci_register_driver(&hsu_pci_driver);
1485 }
1486
1487 static void __exit hsu_pci_exit(void)
1488 {
1489 pci_unregister_driver(&hsu_pci_driver);
1490 uart_unregister_driver(&serial_hsu_reg);
1491
1492 hsu_debugfs_remove(phsu);
1493
1494 kfree(phsu);
1495 }
1496
1497 module_init(hsu_pci_init);
1498 module_exit(hsu_pci_exit);
1499
1500 MODULE_LICENSE("GPL v2");
1501 MODULE_ALIAS("platform:medfield-hsu");
CRIS linux kernel tree