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Linux 3.11-rc3
[cris-mirror.git] / drivers / tty / serial / mpsc.c
blobbc24f4931670d1e70d9bda922a2d3d0341636e0f
1 /*
2 * Generic driver for the MPSC (UART mode) on Marvell parts (e.g., GT64240,
3 * GT64260, MV64340, MV64360, GT96100, ... ).
4 *
5 * Author: Mark A. Greer <mgreer@mvista.com>
6 *
7 * Based on an old MPSC driver that was in the linuxppc tree. It appears to
8 * have been created by Chris Zankel (formerly of MontaVista) but there
9 * is no proper Copyright so I'm not sure. Apparently, parts were also
10 * taken from PPCBoot (now U-Boot). Also based on drivers/serial/8250.c
11 * by Russell King.
12 *
13 * 2004 (c) MontaVista, Software, Inc. This file is licensed under
14 * the terms of the GNU General Public License version 2. This program
15 * is licensed "as is" without any warranty of any kind, whether express
16 * or implied.
17 */
18 /*
19 * The MPSC interface is much like a typical network controller's interface.
20 * That is, you set up separate rings of descriptors for transmitting and
21 * receiving data. There is also a pool of buffers with (one buffer per
22 * descriptor) that incoming data are dma'd into or outgoing data are dma'd
23 * out of.
24 *
25 * The MPSC requires two other controllers to be able to work. The Baud Rate
26 * Generator (BRG) provides a clock at programmable frequencies which determines
27 * the baud rate. The Serial DMA Controller (SDMA) takes incoming data from the
28 * MPSC and DMA's it into memory or DMA's outgoing data and passes it to the
29 * MPSC. It is actually the SDMA interrupt that the driver uses to keep the
30 * transmit and receive "engines" going (i.e., indicate data has been
31 * transmitted or received).
32 *
33 * NOTES:
34 *
35 * 1) Some chips have an erratum where several regs cannot be
36 * read. To work around that, we keep a local copy of those regs in
37 * 'mpsc_port_info'.
38 *
39 * 2) Some chips have an erratum where the ctlr will hang when the SDMA ctlr
40 * accesses system mem with coherency enabled. For that reason, the driver
41 * assumes that coherency for that ctlr has been disabled. This means
42 * that when in a cache coherent system, the driver has to manually manage
43 * the data cache on the areas that it touches because the dma_* macro are
44 * basically no-ops.
45 *
46 * 3) There is an erratum (on PPC) where you can't use the instruction to do
47 * a DMA_TO_DEVICE/cache clean so DMA_BIDIRECTIONAL/flushes are used in places
48 * where a DMA_TO_DEVICE/clean would have [otherwise] sufficed.
49 *
50 * 4) AFAICT, hardware flow control isn't supported by the controller --MAG.
51 */
52
53
54 #if defined(CONFIG_SERIAL_MPSC_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
55 #define SUPPORT_SYSRQ
56 #endif
57
58 #include <linux/module.h>
59 #include <linux/moduleparam.h>
60 #include <linux/tty.h>
61 #include <linux/tty_flip.h>
62 #include <linux/ioport.h>
63 #include <linux/init.h>
64 #include <linux/console.h>
65 #include <linux/sysrq.h>
66 #include <linux/serial.h>
67 #include <linux/serial_core.h>
68 #include <linux/delay.h>
69 #include <linux/device.h>
70 #include <linux/dma-mapping.h>
71 #include <linux/mv643xx.h>
72 #include <linux/platform_device.h>
73 #include <linux/gfp.h>
74
75 #include <asm/io.h>
76 #include <asm/irq.h>
77
78 #define MPSC_NUM_CTLRS 2
79
80 /*
81 * Descriptors and buffers must be cache line aligned.
82 * Buffers lengths must be multiple of cache line size.
83 * Number of Tx & Rx descriptors must be powers of 2.
84 */
85 #define MPSC_RXR_ENTRIES 32
86 #define MPSC_RXRE_SIZE dma_get_cache_alignment()
87 #define MPSC_RXR_SIZE (MPSC_RXR_ENTRIES * MPSC_RXRE_SIZE)
88 #define MPSC_RXBE_SIZE dma_get_cache_alignment()
89 #define MPSC_RXB_SIZE (MPSC_RXR_ENTRIES * MPSC_RXBE_SIZE)
90
91 #define MPSC_TXR_ENTRIES 32
92 #define MPSC_TXRE_SIZE dma_get_cache_alignment()
93 #define MPSC_TXR_SIZE (MPSC_TXR_ENTRIES * MPSC_TXRE_SIZE)
94 #define MPSC_TXBE_SIZE dma_get_cache_alignment()
95 #define MPSC_TXB_SIZE (MPSC_TXR_ENTRIES * MPSC_TXBE_SIZE)
96
97 #define MPSC_DMA_ALLOC_SIZE (MPSC_RXR_SIZE + MPSC_RXB_SIZE + MPSC_TXR_SIZE \
98 + MPSC_TXB_SIZE + dma_get_cache_alignment() /* for alignment */)
99
100 /* Rx and Tx Ring entry descriptors -- assume entry size is <= cacheline size */
101 struct mpsc_rx_desc {
102 u16 bufsize;
103 u16 bytecnt;
104 u32 cmdstat;
105 u32 link;
106 u32 buf_ptr;
107 } __attribute((packed));
108
109 struct mpsc_tx_desc {
110 u16 bytecnt;
111 u16 shadow;
112 u32 cmdstat;
113 u32 link;
114 u32 buf_ptr;
115 } __attribute((packed));
116
117 /*
118 * Some regs that have the erratum that you can't read them are are shared
119 * between the two MPSC controllers. This struct contains those shared regs.
120 */
121 struct mpsc_shared_regs {
122 phys_addr_t mpsc_routing_base_p;
123 phys_addr_t sdma_intr_base_p;
124
125 void __iomem *mpsc_routing_base;
126 void __iomem *sdma_intr_base;
127
128 u32 MPSC_MRR_m;
129 u32 MPSC_RCRR_m;
130 u32 MPSC_TCRR_m;
131 u32 SDMA_INTR_CAUSE_m;
132 u32 SDMA_INTR_MASK_m;
133 };
134
135 /* The main driver data structure */
136 struct mpsc_port_info {
137 struct uart_port port; /* Overlay uart_port structure */
138
139 /* Internal driver state for this ctlr */
140 u8 ready;
141 u8 rcv_data;
142 tcflag_t c_iflag; /* save termios->c_iflag */
143 tcflag_t c_cflag; /* save termios->c_cflag */
144
145 /* Info passed in from platform */
146 u8 mirror_regs; /* Need to mirror regs? */
147 u8 cache_mgmt; /* Need manual cache mgmt? */
148 u8 brg_can_tune; /* BRG has baud tuning? */
149 u32 brg_clk_src;
150 u16 mpsc_max_idle;
151 int default_baud;
152 int default_bits;
153 int default_parity;
154 int default_flow;
155
156 /* Physical addresses of various blocks of registers (from platform) */
157 phys_addr_t mpsc_base_p;
158 phys_addr_t sdma_base_p;
159 phys_addr_t brg_base_p;
160
161 /* Virtual addresses of various blocks of registers (from platform) */
162 void __iomem *mpsc_base;
163 void __iomem *sdma_base;
164 void __iomem *brg_base;
165
166 /* Descriptor ring and buffer allocations */
167 void *dma_region;
168 dma_addr_t dma_region_p;
169
170 dma_addr_t rxr; /* Rx descriptor ring */
171 dma_addr_t rxr_p; /* Phys addr of rxr */
172 u8 *rxb; /* Rx Ring I/O buf */
173 u8 *rxb_p; /* Phys addr of rxb */
174 u32 rxr_posn; /* First desc w/ Rx data */
175
176 dma_addr_t txr; /* Tx descriptor ring */
177 dma_addr_t txr_p; /* Phys addr of txr */
178 u8 *txb; /* Tx Ring I/O buf */
179 u8 *txb_p; /* Phys addr of txb */
180 int txr_head; /* Where new data goes */
181 int txr_tail; /* Where sent data comes off */
182 spinlock_t tx_lock; /* transmit lock */
183
184 /* Mirrored values of regs we can't read (if 'mirror_regs' set) */
185 u32 MPSC_MPCR_m;
186 u32 MPSC_CHR_1_m;
187 u32 MPSC_CHR_2_m;
188 u32 MPSC_CHR_10_m;
189 u32 BRG_BCR_m;
190 struct mpsc_shared_regs *shared_regs;
191 };
192
193 /* Hooks to platform-specific code */
194 int mpsc_platform_register_driver(void);
195 void mpsc_platform_unregister_driver(void);
196
197 /* Hooks back in to mpsc common to be called by platform-specific code */
198 struct mpsc_port_info *mpsc_device_probe(int index);
199 struct mpsc_port_info *mpsc_device_remove(int index);
200
201 /* Main MPSC Configuration Register Offsets */
202 #define MPSC_MMCRL 0x0000
203 #define MPSC_MMCRH 0x0004
204 #define MPSC_MPCR 0x0008
205 #define MPSC_CHR_1 0x000c
206 #define MPSC_CHR_2 0x0010
207 #define MPSC_CHR_3 0x0014
208 #define MPSC_CHR_4 0x0018
209 #define MPSC_CHR_5 0x001c
210 #define MPSC_CHR_6 0x0020
211 #define MPSC_CHR_7 0x0024
212 #define MPSC_CHR_8 0x0028
213 #define MPSC_CHR_9 0x002c
214 #define MPSC_CHR_10 0x0030
215 #define MPSC_CHR_11 0x0034
216
217 #define MPSC_MPCR_FRZ (1 << 9)
218 #define MPSC_MPCR_CL_5 0
219 #define MPSC_MPCR_CL_6 1
220 #define MPSC_MPCR_CL_7 2
221 #define MPSC_MPCR_CL_8 3
222 #define MPSC_MPCR_SBL_1 0
223 #define MPSC_MPCR_SBL_2 1
224
225 #define MPSC_CHR_2_TEV (1<<1)
226 #define MPSC_CHR_2_TA (1<<7)
227 #define MPSC_CHR_2_TTCS (1<<9)
228 #define MPSC_CHR_2_REV (1<<17)
229 #define MPSC_CHR_2_RA (1<<23)
230 #define MPSC_CHR_2_CRD (1<<25)
231 #define MPSC_CHR_2_EH (1<<31)
232 #define MPSC_CHR_2_PAR_ODD 0
233 #define MPSC_CHR_2_PAR_SPACE 1
234 #define MPSC_CHR_2_PAR_EVEN 2
235 #define MPSC_CHR_2_PAR_MARK 3
236
237 /* MPSC Signal Routing */
238 #define MPSC_MRR 0x0000
239 #define MPSC_RCRR 0x0004
240 #define MPSC_TCRR 0x0008
241
242 /* Serial DMA Controller Interface Registers */
243 #define SDMA_SDC 0x0000
244 #define SDMA_SDCM 0x0008
245 #define SDMA_RX_DESC 0x0800
246 #define SDMA_RX_BUF_PTR 0x0808
247 #define SDMA_SCRDP 0x0810
248 #define SDMA_TX_DESC 0x0c00
249 #define SDMA_SCTDP 0x0c10
250 #define SDMA_SFTDP 0x0c14
251
252 #define SDMA_DESC_CMDSTAT_PE (1<<0)
253 #define SDMA_DESC_CMDSTAT_CDL (1<<1)
254 #define SDMA_DESC_CMDSTAT_FR (1<<3)
255 #define SDMA_DESC_CMDSTAT_OR (1<<6)
256 #define SDMA_DESC_CMDSTAT_BR (1<<9)
257 #define SDMA_DESC_CMDSTAT_MI (1<<10)
258 #define SDMA_DESC_CMDSTAT_A (1<<11)
259 #define SDMA_DESC_CMDSTAT_AM (1<<12)
260 #define SDMA_DESC_CMDSTAT_CT (1<<13)
261 #define SDMA_DESC_CMDSTAT_C (1<<14)
262 #define SDMA_DESC_CMDSTAT_ES (1<<15)
263 #define SDMA_DESC_CMDSTAT_L (1<<16)
264 #define SDMA_DESC_CMDSTAT_F (1<<17)
265 #define SDMA_DESC_CMDSTAT_P (1<<18)
266 #define SDMA_DESC_CMDSTAT_EI (1<<23)
267 #define SDMA_DESC_CMDSTAT_O (1<<31)
268
269 #define SDMA_DESC_DFLT (SDMA_DESC_CMDSTAT_O \
270 | SDMA_DESC_CMDSTAT_EI)
271
272 #define SDMA_SDC_RFT (1<<0)
273 #define SDMA_SDC_SFM (1<<1)
274 #define SDMA_SDC_BLMR (1<<6)
275 #define SDMA_SDC_BLMT (1<<7)
276 #define SDMA_SDC_POVR (1<<8)
277 #define SDMA_SDC_RIFB (1<<9)
278
279 #define SDMA_SDCM_ERD (1<<7)
280 #define SDMA_SDCM_AR (1<<15)
281 #define SDMA_SDCM_STD (1<<16)
282 #define SDMA_SDCM_TXD (1<<23)
283 #define SDMA_SDCM_AT (1<<31)
284
285 #define SDMA_0_CAUSE_RXBUF (1<<0)
286 #define SDMA_0_CAUSE_RXERR (1<<1)
287 #define SDMA_0_CAUSE_TXBUF (1<<2)
288 #define SDMA_0_CAUSE_TXEND (1<<3)
289 #define SDMA_1_CAUSE_RXBUF (1<<8)
290 #define SDMA_1_CAUSE_RXERR (1<<9)
291 #define SDMA_1_CAUSE_TXBUF (1<<10)
292 #define SDMA_1_CAUSE_TXEND (1<<11)
293
294 #define SDMA_CAUSE_RX_MASK (SDMA_0_CAUSE_RXBUF | SDMA_0_CAUSE_RXERR \
295 | SDMA_1_CAUSE_RXBUF | SDMA_1_CAUSE_RXERR)
296 #define SDMA_CAUSE_TX_MASK (SDMA_0_CAUSE_TXBUF | SDMA_0_CAUSE_TXEND \
297 | SDMA_1_CAUSE_TXBUF | SDMA_1_CAUSE_TXEND)
298
299 /* SDMA Interrupt registers */
300 #define SDMA_INTR_CAUSE 0x0000
301 #define SDMA_INTR_MASK 0x0080
302
303 /* Baud Rate Generator Interface Registers */
304 #define BRG_BCR 0x0000
305 #define BRG_BTR 0x0004
306
307 /*
308 * Define how this driver is known to the outside (we've been assigned a
309 * range on the "Low-density serial ports" major).
310 */
311 #define MPSC_MAJOR 204
312 #define MPSC_MINOR_START 44
313 #define MPSC_DRIVER_NAME "MPSC"
314 #define MPSC_DEV_NAME "ttyMM"
315 #define MPSC_VERSION "1.00"
316
317 static struct mpsc_port_info mpsc_ports[MPSC_NUM_CTLRS];
318 static struct mpsc_shared_regs mpsc_shared_regs;
319 static struct uart_driver mpsc_reg;
320
321 static void mpsc_start_rx(struct mpsc_port_info *pi);
322 static void mpsc_free_ring_mem(struct mpsc_port_info *pi);
323 static void mpsc_release_port(struct uart_port *port);
324 /*
325 ******************************************************************************
326 *
327 * Baud Rate Generator Routines (BRG)
328 *
329 ******************************************************************************
330 */
331 static void mpsc_brg_init(struct mpsc_port_info *pi, u32 clk_src)
332 {
333 u32 v;
334
335 v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR);
336 v = (v & ~(0xf << 18)) | ((clk_src & 0xf) << 18);
337
338 if (pi->brg_can_tune)
339 v &= ~(1 << 25);
340
341 if (pi->mirror_regs)
342 pi->BRG_BCR_m = v;
343 writel(v, pi->brg_base + BRG_BCR);
344
345 writel(readl(pi->brg_base + BRG_BTR) & 0xffff0000,
346 pi->brg_base + BRG_BTR);
347 }
348
349 static void mpsc_brg_enable(struct mpsc_port_info *pi)
350 {
351 u32 v;
352
353 v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR);
354 v |= (1 << 16);
355
356 if (pi->mirror_regs)
357 pi->BRG_BCR_m = v;
358 writel(v, pi->brg_base + BRG_BCR);
359 }
360
361 static void mpsc_brg_disable(struct mpsc_port_info *pi)
362 {
363 u32 v;
364
365 v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR);
366 v &= ~(1 << 16);
367
368 if (pi->mirror_regs)
369 pi->BRG_BCR_m = v;
370 writel(v, pi->brg_base + BRG_BCR);
371 }
372
373 /*
374 * To set the baud, we adjust the CDV field in the BRG_BCR reg.
375 * From manual: Baud = clk / ((CDV+1)*2) ==> CDV = (clk / (baud*2)) - 1.
376 * However, the input clock is divided by 16 in the MPSC b/c of how
377 * 'MPSC_MMCRH' was set up so we have to divide the 'clk' used in our
378 * calculation by 16 to account for that. So the real calculation
379 * that accounts for the way the mpsc is set up is:
380 * CDV = (clk / (baud*2*16)) - 1 ==> CDV = (clk / (baud << 5)) - 1.
381 */
382 static void mpsc_set_baudrate(struct mpsc_port_info *pi, u32 baud)
383 {
384 u32 cdv = (pi->port.uartclk / (baud << 5)) - 1;
385 u32 v;
386
387 mpsc_brg_disable(pi);
388 v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR);
389 v = (v & 0xffff0000) | (cdv & 0xffff);
390
391 if (pi->mirror_regs)
392 pi->BRG_BCR_m = v;
393 writel(v, pi->brg_base + BRG_BCR);
394 mpsc_brg_enable(pi);
395 }
396
397 /*
398 ******************************************************************************
399 *
400 * Serial DMA Routines (SDMA)
401 *
402 ******************************************************************************
403 */
404
405 static void mpsc_sdma_burstsize(struct mpsc_port_info *pi, u32 burst_size)
406 {
407 u32 v;
408
409 pr_debug("mpsc_sdma_burstsize[%d]: burst_size: %d\n",
410 pi->port.line, burst_size);
411
412 burst_size >>= 3; /* Divide by 8 b/c reg values are 8-byte chunks */
413
414 if (burst_size < 2)
415 v = 0x0; /* 1 64-bit word */
416 else if (burst_size < 4)
417 v = 0x1; /* 2 64-bit words */
418 else if (burst_size < 8)
419 v = 0x2; /* 4 64-bit words */
420 else
421 v = 0x3; /* 8 64-bit words */
422
423 writel((readl(pi->sdma_base + SDMA_SDC) & (0x3 << 12)) | (v << 12),
424 pi->sdma_base + SDMA_SDC);
425 }
426
427 static void mpsc_sdma_init(struct mpsc_port_info *pi, u32 burst_size)
428 {
429 pr_debug("mpsc_sdma_init[%d]: burst_size: %d\n", pi->port.line,
430 burst_size);
431
432 writel((readl(pi->sdma_base + SDMA_SDC) & 0x3ff) | 0x03f,
433 pi->sdma_base + SDMA_SDC);
434 mpsc_sdma_burstsize(pi, burst_size);
435 }
436
437 static u32 mpsc_sdma_intr_mask(struct mpsc_port_info *pi, u32 mask)
438 {
439 u32 old, v;
440
441 pr_debug("mpsc_sdma_intr_mask[%d]: mask: 0x%x\n", pi->port.line, mask);
442
443 old = v = (pi->mirror_regs) ? pi->shared_regs->SDMA_INTR_MASK_m :
444 readl(pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK);
445
446 mask &= 0xf;
447 if (pi->port.line)
448 mask <<= 8;
449 v &= ~mask;
450
451 if (pi->mirror_regs)
452 pi->shared_regs->SDMA_INTR_MASK_m = v;
453 writel(v, pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK);
454
455 if (pi->port.line)
456 old >>= 8;
457 return old & 0xf;
458 }
459
460 static void mpsc_sdma_intr_unmask(struct mpsc_port_info *pi, u32 mask)
461 {
462 u32 v;
463
464 pr_debug("mpsc_sdma_intr_unmask[%d]: mask: 0x%x\n", pi->port.line,mask);
465
466 v = (pi->mirror_regs) ? pi->shared_regs->SDMA_INTR_MASK_m
467 : readl(pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK);
468
469 mask &= 0xf;
470 if (pi->port.line)
471 mask <<= 8;
472 v |= mask;
473
474 if (pi->mirror_regs)
475 pi->shared_regs->SDMA_INTR_MASK_m = v;
476 writel(v, pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK);
477 }
478
479 static void mpsc_sdma_intr_ack(struct mpsc_port_info *pi)
480 {
481 pr_debug("mpsc_sdma_intr_ack[%d]: Acknowledging IRQ\n", pi->port.line);
482
483 if (pi->mirror_regs)
484 pi->shared_regs->SDMA_INTR_CAUSE_m = 0;
485 writeb(0x00, pi->shared_regs->sdma_intr_base + SDMA_INTR_CAUSE
486 + pi->port.line);
487 }
488
489 static void mpsc_sdma_set_rx_ring(struct mpsc_port_info *pi,
490 struct mpsc_rx_desc *rxre_p)
491 {
492 pr_debug("mpsc_sdma_set_rx_ring[%d]: rxre_p: 0x%x\n",
493 pi->port.line, (u32)rxre_p);
494
495 writel((u32)rxre_p, pi->sdma_base + SDMA_SCRDP);
496 }
497
498 static void mpsc_sdma_set_tx_ring(struct mpsc_port_info *pi,
499 struct mpsc_tx_desc *txre_p)
500 {
501 writel((u32)txre_p, pi->sdma_base + SDMA_SFTDP);
502 writel((u32)txre_p, pi->sdma_base + SDMA_SCTDP);
503 }
504
505 static void mpsc_sdma_cmd(struct mpsc_port_info *pi, u32 val)
506 {
507 u32 v;
508
509 v = readl(pi->sdma_base + SDMA_SDCM);
510 if (val)
511 v |= val;
512 else
513 v = 0;
514 wmb();
515 writel(v, pi->sdma_base + SDMA_SDCM);
516 wmb();
517 }
518
519 static uint mpsc_sdma_tx_active(struct mpsc_port_info *pi)
520 {
521 return readl(pi->sdma_base + SDMA_SDCM) & SDMA_SDCM_TXD;
522 }
523
524 static void mpsc_sdma_start_tx(struct mpsc_port_info *pi)
525 {
526 struct mpsc_tx_desc *txre, *txre_p;
527
528 /* If tx isn't running & there's a desc ready to go, start it */
529 if (!mpsc_sdma_tx_active(pi)) {
530 txre = (struct mpsc_tx_desc *)(pi->txr
531 + (pi->txr_tail * MPSC_TXRE_SIZE));
532 dma_cache_sync(pi->port.dev, (void *)txre, MPSC_TXRE_SIZE,
533 DMA_FROM_DEVICE);
534 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
535 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
536 invalidate_dcache_range((ulong)txre,
537 (ulong)txre + MPSC_TXRE_SIZE);
538 #endif
539
540 if (be32_to_cpu(txre->cmdstat) & SDMA_DESC_CMDSTAT_O) {
541 txre_p = (struct mpsc_tx_desc *)
542 (pi->txr_p + (pi->txr_tail * MPSC_TXRE_SIZE));
543
544 mpsc_sdma_set_tx_ring(pi, txre_p);
545 mpsc_sdma_cmd(pi, SDMA_SDCM_STD | SDMA_SDCM_TXD);
546 }
547 }
548 }
549
550 static void mpsc_sdma_stop(struct mpsc_port_info *pi)
551 {
552 pr_debug("mpsc_sdma_stop[%d]: Stopping SDMA\n", pi->port.line);
553
554 /* Abort any SDMA transfers */
555 mpsc_sdma_cmd(pi, 0);
556 mpsc_sdma_cmd(pi, SDMA_SDCM_AR | SDMA_SDCM_AT);
557
558 /* Clear the SDMA current and first TX and RX pointers */
559 mpsc_sdma_set_tx_ring(pi, NULL);
560 mpsc_sdma_set_rx_ring(pi, NULL);
561
562 /* Disable interrupts */
563 mpsc_sdma_intr_mask(pi, 0xf);
564 mpsc_sdma_intr_ack(pi);
565 }
566
567 /*
568 ******************************************************************************
569 *
570 * Multi-Protocol Serial Controller Routines (MPSC)
571 *
572 ******************************************************************************
573 */
574
575 static void mpsc_hw_init(struct mpsc_port_info *pi)
576 {
577 u32 v;
578
579 pr_debug("mpsc_hw_init[%d]: Initializing hardware\n", pi->port.line);
580
581 /* Set up clock routing */
582 if (pi->mirror_regs) {
583 v = pi->shared_regs->MPSC_MRR_m;
584 v &= ~0x1c7;
585 pi->shared_regs->MPSC_MRR_m = v;
586 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_MRR);
587
588 v = pi->shared_regs->MPSC_RCRR_m;
589 v = (v & ~0xf0f) | 0x100;
590 pi->shared_regs->MPSC_RCRR_m = v;
591 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_RCRR);
592
593 v = pi->shared_regs->MPSC_TCRR_m;
594 v = (v & ~0xf0f) | 0x100;
595 pi->shared_regs->MPSC_TCRR_m = v;
596 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_TCRR);
597 } else {
598 v = readl(pi->shared_regs->mpsc_routing_base + MPSC_MRR);
599 v &= ~0x1c7;
600 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_MRR);
601
602 v = readl(pi->shared_regs->mpsc_routing_base + MPSC_RCRR);
603 v = (v & ~0xf0f) | 0x100;
604 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_RCRR);
605
606 v = readl(pi->shared_regs->mpsc_routing_base + MPSC_TCRR);
607 v = (v & ~0xf0f) | 0x100;
608 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_TCRR);
609 }
610
611 /* Put MPSC in UART mode & enabel Tx/Rx egines */
612 writel(0x000004c4, pi->mpsc_base + MPSC_MMCRL);
613
614 /* No preamble, 16x divider, low-latency, */
615 writel(0x04400400, pi->mpsc_base + MPSC_MMCRH);
616 mpsc_set_baudrate(pi, pi->default_baud);
617
618 if (pi->mirror_regs) {
619 pi->MPSC_CHR_1_m = 0;
620 pi->MPSC_CHR_2_m = 0;
621 }
622 writel(0, pi->mpsc_base + MPSC_CHR_1);
623 writel(0, pi->mpsc_base + MPSC_CHR_2);
624 writel(pi->mpsc_max_idle, pi->mpsc_base + MPSC_CHR_3);
625 writel(0, pi->mpsc_base + MPSC_CHR_4);
626 writel(0, pi->mpsc_base + MPSC_CHR_5);
627 writel(0, pi->mpsc_base + MPSC_CHR_6);
628 writel(0, pi->mpsc_base + MPSC_CHR_7);
629 writel(0, pi->mpsc_base + MPSC_CHR_8);
630 writel(0, pi->mpsc_base + MPSC_CHR_9);
631 writel(0, pi->mpsc_base + MPSC_CHR_10);
632 }
633
634 static void mpsc_enter_hunt(struct mpsc_port_info *pi)
635 {
636 pr_debug("mpsc_enter_hunt[%d]: Hunting...\n", pi->port.line);
637
638 if (pi->mirror_regs) {
639 writel(pi->MPSC_CHR_2_m | MPSC_CHR_2_EH,
640 pi->mpsc_base + MPSC_CHR_2);
641 /* Erratum prevents reading CHR_2 so just delay for a while */
642 udelay(100);
643 } else {
644 writel(readl(pi->mpsc_base + MPSC_CHR_2) | MPSC_CHR_2_EH,
645 pi->mpsc_base + MPSC_CHR_2);
646
647 while (readl(pi->mpsc_base + MPSC_CHR_2) & MPSC_CHR_2_EH)
648 udelay(10);
649 }
650 }
651
652 static void mpsc_freeze(struct mpsc_port_info *pi)
653 {
654 u32 v;
655
656 pr_debug("mpsc_freeze[%d]: Freezing\n", pi->port.line);
657
658 v = (pi->mirror_regs) ? pi->MPSC_MPCR_m :
659 readl(pi->mpsc_base + MPSC_MPCR);
660 v |= MPSC_MPCR_FRZ;
661
662 if (pi->mirror_regs)
663 pi->MPSC_MPCR_m = v;
664 writel(v, pi->mpsc_base + MPSC_MPCR);
665 }
666
667 static void mpsc_unfreeze(struct mpsc_port_info *pi)
668 {
669 u32 v;
670
671 v = (pi->mirror_regs) ? pi->MPSC_MPCR_m :
672 readl(pi->mpsc_base + MPSC_MPCR);
673 v &= ~MPSC_MPCR_FRZ;
674
675 if (pi->mirror_regs)
676 pi->MPSC_MPCR_m = v;
677 writel(v, pi->mpsc_base + MPSC_MPCR);
678
679 pr_debug("mpsc_unfreeze[%d]: Unfrozen\n", pi->port.line);
680 }
681
682 static void mpsc_set_char_length(struct mpsc_port_info *pi, u32 len)
683 {
684 u32 v;
685
686 pr_debug("mpsc_set_char_length[%d]: char len: %d\n", pi->port.line,len);
687
688 v = (pi->mirror_regs) ? pi->MPSC_MPCR_m :
689 readl(pi->mpsc_base + MPSC_MPCR);
690 v = (v & ~(0x3 << 12)) | ((len & 0x3) << 12);
691
692 if (pi->mirror_regs)
693 pi->MPSC_MPCR_m = v;
694 writel(v, pi->mpsc_base + MPSC_MPCR);
695 }
696
697 static void mpsc_set_stop_bit_length(struct mpsc_port_info *pi, u32 len)
698 {
699 u32 v;
700
701 pr_debug("mpsc_set_stop_bit_length[%d]: stop bits: %d\n",
702 pi->port.line, len);
703
704 v = (pi->mirror_regs) ? pi->MPSC_MPCR_m :
705 readl(pi->mpsc_base + MPSC_MPCR);
706
707 v = (v & ~(1 << 14)) | ((len & 0x1) << 14);
708
709 if (pi->mirror_regs)
710 pi->MPSC_MPCR_m = v;
711 writel(v, pi->mpsc_base + MPSC_MPCR);
712 }
713
714 static void mpsc_set_parity(struct mpsc_port_info *pi, u32 p)
715 {
716 u32 v;
717
718 pr_debug("mpsc_set_parity[%d]: parity bits: 0x%x\n", pi->port.line, p);
719
720 v = (pi->mirror_regs) ? pi->MPSC_CHR_2_m :
721 readl(pi->mpsc_base + MPSC_CHR_2);
722
723 p &= 0x3;
724 v = (v & ~0xc000c) | (p << 18) | (p << 2);
725
726 if (pi->mirror_regs)
727 pi->MPSC_CHR_2_m = v;
728 writel(v, pi->mpsc_base + MPSC_CHR_2);
729 }
730
731 /*
732 ******************************************************************************
733 *
734 * Driver Init Routines
735 *
736 ******************************************************************************
737 */
738
739 static void mpsc_init_hw(struct mpsc_port_info *pi)
740 {
741 pr_debug("mpsc_init_hw[%d]: Initializing\n", pi->port.line);
742
743 mpsc_brg_init(pi, pi->brg_clk_src);
744 mpsc_brg_enable(pi);
745 mpsc_sdma_init(pi, dma_get_cache_alignment()); /* burst a cacheline */
746 mpsc_sdma_stop(pi);
747 mpsc_hw_init(pi);
748 }
749
750 static int mpsc_alloc_ring_mem(struct mpsc_port_info *pi)
751 {
752 int rc = 0;
753
754 pr_debug("mpsc_alloc_ring_mem[%d]: Allocating ring mem\n",
755 pi->port.line);
756
757 if (!pi->dma_region) {
758 if (!dma_supported(pi->port.dev, 0xffffffff)) {
759 printk(KERN_ERR "MPSC: Inadequate DMA support\n");
760 rc = -ENXIO;
761 } else if ((pi->dma_region = dma_alloc_noncoherent(pi->port.dev,
762 MPSC_DMA_ALLOC_SIZE,
763 &pi->dma_region_p, GFP_KERNEL))
764 == NULL) {
765 printk(KERN_ERR "MPSC: Can't alloc Desc region\n");
766 rc = -ENOMEM;
767 }
768 }
769
770 return rc;
771 }
772
773 static void mpsc_free_ring_mem(struct mpsc_port_info *pi)
774 {
775 pr_debug("mpsc_free_ring_mem[%d]: Freeing ring mem\n", pi->port.line);
776
777 if (pi->dma_region) {
778 dma_free_noncoherent(pi->port.dev, MPSC_DMA_ALLOC_SIZE,
779 pi->dma_region, pi->dma_region_p);
780 pi->dma_region = NULL;
781 pi->dma_region_p = (dma_addr_t)NULL;
782 }
783 }
784
785 static void mpsc_init_rings(struct mpsc_port_info *pi)
786 {
787 struct mpsc_rx_desc *rxre;
788 struct mpsc_tx_desc *txre;
789 dma_addr_t dp, dp_p;
790 u8 *bp, *bp_p;
791 int i;
792
793 pr_debug("mpsc_init_rings[%d]: Initializing rings\n", pi->port.line);
794
795 BUG_ON(pi->dma_region == NULL);
796
797 memset(pi->dma_region, 0, MPSC_DMA_ALLOC_SIZE);
798
799 /*
800 * Descriptors & buffers are multiples of cacheline size and must be
801 * cacheline aligned.
802 */
803 dp = ALIGN((u32)pi->dma_region, dma_get_cache_alignment());
804 dp_p = ALIGN((u32)pi->dma_region_p, dma_get_cache_alignment());
805
806 /*
807 * Partition dma region into rx ring descriptor, rx buffers,
808 * tx ring descriptors, and tx buffers.
809 */
810 pi->rxr = dp;
811 pi->rxr_p = dp_p;
812 dp += MPSC_RXR_SIZE;
813 dp_p += MPSC_RXR_SIZE;
814
815 pi->rxb = (u8 *)dp;
816 pi->rxb_p = (u8 *)dp_p;
817 dp += MPSC_RXB_SIZE;
818 dp_p += MPSC_RXB_SIZE;
819
820 pi->rxr_posn = 0;
821
822 pi->txr = dp;
823 pi->txr_p = dp_p;
824 dp += MPSC_TXR_SIZE;
825 dp_p += MPSC_TXR_SIZE;
826
827 pi->txb = (u8 *)dp;
828 pi->txb_p = (u8 *)dp_p;
829
830 pi->txr_head = 0;
831 pi->txr_tail = 0;
832
833 /* Init rx ring descriptors */
834 dp = pi->rxr;
835 dp_p = pi->rxr_p;
836 bp = pi->rxb;
837 bp_p = pi->rxb_p;
838
839 for (i = 0; i < MPSC_RXR_ENTRIES; i++) {
840 rxre = (struct mpsc_rx_desc *)dp;
841
842 rxre->bufsize = cpu_to_be16(MPSC_RXBE_SIZE);
843 rxre->bytecnt = cpu_to_be16(0);
844 rxre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O
845 | SDMA_DESC_CMDSTAT_EI | SDMA_DESC_CMDSTAT_F
846 | SDMA_DESC_CMDSTAT_L);
847 rxre->link = cpu_to_be32(dp_p + MPSC_RXRE_SIZE);
848 rxre->buf_ptr = cpu_to_be32(bp_p);
849
850 dp += MPSC_RXRE_SIZE;
851 dp_p += MPSC_RXRE_SIZE;
852 bp += MPSC_RXBE_SIZE;
853 bp_p += MPSC_RXBE_SIZE;
854 }
855 rxre->link = cpu_to_be32(pi->rxr_p); /* Wrap last back to first */
856
857 /* Init tx ring descriptors */
858 dp = pi->txr;
859 dp_p = pi->txr_p;
860 bp = pi->txb;
861 bp_p = pi->txb_p;
862
863 for (i = 0; i < MPSC_TXR_ENTRIES; i++) {
864 txre = (struct mpsc_tx_desc *)dp;
865
866 txre->link = cpu_to_be32(dp_p + MPSC_TXRE_SIZE);
867 txre->buf_ptr = cpu_to_be32(bp_p);
868
869 dp += MPSC_TXRE_SIZE;
870 dp_p += MPSC_TXRE_SIZE;
871 bp += MPSC_TXBE_SIZE;
872 bp_p += MPSC_TXBE_SIZE;
873 }
874 txre->link = cpu_to_be32(pi->txr_p); /* Wrap last back to first */
875
876 dma_cache_sync(pi->port.dev, (void *)pi->dma_region,
877 MPSC_DMA_ALLOC_SIZE, DMA_BIDIRECTIONAL);
878 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
879 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
880 flush_dcache_range((ulong)pi->dma_region,
881 (ulong)pi->dma_region
882 + MPSC_DMA_ALLOC_SIZE);
883 #endif
884
885 return;
886 }
887
888 static void mpsc_uninit_rings(struct mpsc_port_info *pi)
889 {
890 pr_debug("mpsc_uninit_rings[%d]: Uninitializing rings\n",pi->port.line);
891
892 BUG_ON(pi->dma_region == NULL);
893
894 pi->rxr = 0;
895 pi->rxr_p = 0;
896 pi->rxb = NULL;
897 pi->rxb_p = NULL;
898 pi->rxr_posn = 0;
899
900 pi->txr = 0;
901 pi->txr_p = 0;
902 pi->txb = NULL;
903 pi->txb_p = NULL;
904 pi->txr_head = 0;
905 pi->txr_tail = 0;
906 }
907
908 static int mpsc_make_ready(struct mpsc_port_info *pi)
909 {
910 int rc;
911
912 pr_debug("mpsc_make_ready[%d]: Making cltr ready\n", pi->port.line);
913
914 if (!pi->ready) {
915 mpsc_init_hw(pi);
916 if ((rc = mpsc_alloc_ring_mem(pi)))
917 return rc;
918 mpsc_init_rings(pi);
919 pi->ready = 1;
920 }
921
922 return 0;
923 }
924
925 #ifdef CONFIG_CONSOLE_POLL
926 static int serial_polled;
927 #endif
928
929 /*
930 ******************************************************************************
931 *
932 * Interrupt Handling Routines
933 *
934 ******************************************************************************
935 */
936
937 static int mpsc_rx_intr(struct mpsc_port_info *pi)
938 {
939 struct mpsc_rx_desc *rxre;
940 struct tty_port *port = &pi->port.state->port;
941 u32 cmdstat, bytes_in, i;
942 int rc = 0;
943 u8 *bp;
944 char flag = TTY_NORMAL;
945
946 pr_debug("mpsc_rx_intr[%d]: Handling Rx intr\n", pi->port.line);
947
948 rxre = (struct mpsc_rx_desc *)(pi->rxr + (pi->rxr_posn*MPSC_RXRE_SIZE));
949
950 dma_cache_sync(pi->port.dev, (void *)rxre, MPSC_RXRE_SIZE,
951 DMA_FROM_DEVICE);
952 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
953 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
954 invalidate_dcache_range((ulong)rxre,
955 (ulong)rxre + MPSC_RXRE_SIZE);
956 #endif
957
958 /*
959 * Loop through Rx descriptors handling ones that have been completed.
960 */
961 while (!((cmdstat = be32_to_cpu(rxre->cmdstat))
962 & SDMA_DESC_CMDSTAT_O)) {
963 bytes_in = be16_to_cpu(rxre->bytecnt);
964 #ifdef CONFIG_CONSOLE_POLL
965 if (unlikely(serial_polled)) {
966 serial_polled = 0;
967 return 0;
968 }
969 #endif
970 /* Following use of tty struct directly is deprecated */
971 if (tty_buffer_request_room(port, bytes_in) < bytes_in) {
972 if (port->low_latency)
973 tty_flip_buffer_push(port);
974 /*
975 * If this failed then we will throw away the bytes
976 * but must do so to clear interrupts.
977 */
978 }
979
980 bp = pi->rxb + (pi->rxr_posn * MPSC_RXBE_SIZE);
981 dma_cache_sync(pi->port.dev, (void *)bp, MPSC_RXBE_SIZE,
982 DMA_FROM_DEVICE);
983 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
984 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
985 invalidate_dcache_range((ulong)bp,
986 (ulong)bp + MPSC_RXBE_SIZE);
987 #endif
988
989 /*
990 * Other than for parity error, the manual provides little
991 * info on what data will be in a frame flagged by any of
992 * these errors. For parity error, it is the last byte in
993 * the buffer that had the error. As for the rest, I guess
994 * we'll assume there is no data in the buffer.
995 * If there is...it gets lost.
996 */
997 if (unlikely(cmdstat & (SDMA_DESC_CMDSTAT_BR
998 | SDMA_DESC_CMDSTAT_FR
999 | SDMA_DESC_CMDSTAT_OR))) {
1000
1001 pi->port.icount.rx++;
1002
1003 if (cmdstat & SDMA_DESC_CMDSTAT_BR) { /* Break */
1004 pi->port.icount.brk++;
1005
1006 if (uart_handle_break(&pi->port))
1007 goto next_frame;
1008 } else if (cmdstat & SDMA_DESC_CMDSTAT_FR) {
1009 pi->port.icount.frame++;
1010 } else if (cmdstat & SDMA_DESC_CMDSTAT_OR) {
1011 pi->port.icount.overrun++;
1012 }
1013
1014 cmdstat &= pi->port.read_status_mask;
1015
1016 if (cmdstat & SDMA_DESC_CMDSTAT_BR)
1017 flag = TTY_BREAK;
1018 else if (cmdstat & SDMA_DESC_CMDSTAT_FR)
1019 flag = TTY_FRAME;
1020 else if (cmdstat & SDMA_DESC_CMDSTAT_OR)
1021 flag = TTY_OVERRUN;
1022 else if (cmdstat & SDMA_DESC_CMDSTAT_PE)
1023 flag = TTY_PARITY;
1024 }
1025
1026 if (uart_handle_sysrq_char(&pi->port, *bp)) {
1027 bp++;
1028 bytes_in--;
1029 #ifdef CONFIG_CONSOLE_POLL
1030 if (unlikely(serial_polled)) {
1031 serial_polled = 0;
1032 return 0;
1033 }
1034 #endif
1035 goto next_frame;
1036 }
1037
1038 if ((unlikely(cmdstat & (SDMA_DESC_CMDSTAT_BR
1039 | SDMA_DESC_CMDSTAT_FR
1040 | SDMA_DESC_CMDSTAT_OR)))
1041 && !(cmdstat & pi->port.ignore_status_mask)) {
1042 tty_insert_flip_char(port, *bp, flag);
1043 } else {
1044 for (i=0; i<bytes_in; i++)
1045 tty_insert_flip_char(port, *bp++, TTY_NORMAL);
1046
1047 pi->port.icount.rx += bytes_in;
1048 }
1049
1050 next_frame:
1051 rxre->bytecnt = cpu_to_be16(0);
1052 wmb();
1053 rxre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O
1054 | SDMA_DESC_CMDSTAT_EI | SDMA_DESC_CMDSTAT_F
1055 | SDMA_DESC_CMDSTAT_L);
1056 wmb();
1057 dma_cache_sync(pi->port.dev, (void *)rxre, MPSC_RXRE_SIZE,
1058 DMA_BIDIRECTIONAL);
1059 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1060 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1061 flush_dcache_range((ulong)rxre,
1062 (ulong)rxre + MPSC_RXRE_SIZE);
1063 #endif
1064
1065 /* Advance to next descriptor */
1066 pi->rxr_posn = (pi->rxr_posn + 1) & (MPSC_RXR_ENTRIES - 1);
1067 rxre = (struct mpsc_rx_desc *)
1068 (pi->rxr + (pi->rxr_posn * MPSC_RXRE_SIZE));
1069 dma_cache_sync(pi->port.dev, (void *)rxre, MPSC_RXRE_SIZE,
1070 DMA_FROM_DEVICE);
1071 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1072 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1073 invalidate_dcache_range((ulong)rxre,
1074 (ulong)rxre + MPSC_RXRE_SIZE);
1075 #endif
1076 rc = 1;
1077 }
1078
1079 /* Restart rx engine, if its stopped */
1080 if ((readl(pi->sdma_base + SDMA_SDCM) & SDMA_SDCM_ERD) == 0)
1081 mpsc_start_rx(pi);
1082
1083 tty_flip_buffer_push(port);
1084 return rc;
1085 }
1086
1087 static void mpsc_setup_tx_desc(struct mpsc_port_info *pi, u32 count, u32 intr)
1088 {
1089 struct mpsc_tx_desc *txre;
1090
1091 txre = (struct mpsc_tx_desc *)(pi->txr
1092 + (pi->txr_head * MPSC_TXRE_SIZE));
1093
1094 txre->bytecnt = cpu_to_be16(count);
1095 txre->shadow = txre->bytecnt;
1096 wmb(); /* ensure cmdstat is last field updated */
1097 txre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O | SDMA_DESC_CMDSTAT_F
1098 | SDMA_DESC_CMDSTAT_L
1099 | ((intr) ? SDMA_DESC_CMDSTAT_EI : 0));
1100 wmb();
1101 dma_cache_sync(pi->port.dev, (void *)txre, MPSC_TXRE_SIZE,
1102 DMA_BIDIRECTIONAL);
1103 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1104 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1105 flush_dcache_range((ulong)txre,
1106 (ulong)txre + MPSC_TXRE_SIZE);
1107 #endif
1108 }
1109
1110 static void mpsc_copy_tx_data(struct mpsc_port_info *pi)
1111 {
1112 struct circ_buf *xmit = &pi->port.state->xmit;
1113 u8 *bp;
1114 u32 i;
1115
1116 /* Make sure the desc ring isn't full */
1117 while (CIRC_CNT(pi->txr_head, pi->txr_tail, MPSC_TXR_ENTRIES)
1118 < (MPSC_TXR_ENTRIES - 1)) {
1119 if (pi->port.x_char) {
1120 /*
1121 * Ideally, we should use the TCS field in
1122 * CHR_1 to put the x_char out immediately but
1123 * errata prevents us from being able to read
1124 * CHR_2 to know that its safe to write to
1125 * CHR_1. Instead, just put it in-band with
1126 * all the other Tx data.
1127 */
1128 bp = pi->txb + (pi->txr_head * MPSC_TXBE_SIZE);
1129 *bp = pi->port.x_char;
1130 pi->port.x_char = 0;
1131 i = 1;
1132 } else if (!uart_circ_empty(xmit)
1133 && !uart_tx_stopped(&pi->port)) {
1134 i = min((u32)MPSC_TXBE_SIZE,
1135 (u32)uart_circ_chars_pending(xmit));
1136 i = min(i, (u32)CIRC_CNT_TO_END(xmit->head, xmit->tail,
1137 UART_XMIT_SIZE));
1138 bp = pi->txb + (pi->txr_head * MPSC_TXBE_SIZE);
1139 memcpy(bp, &xmit->buf[xmit->tail], i);
1140 xmit->tail = (xmit->tail + i) & (UART_XMIT_SIZE - 1);
1141
1142 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1143 uart_write_wakeup(&pi->port);
1144 } else { /* All tx data copied into ring bufs */
1145 return;
1146 }
1147
1148 dma_cache_sync(pi->port.dev, (void *)bp, MPSC_TXBE_SIZE,
1149 DMA_BIDIRECTIONAL);
1150 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1151 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1152 flush_dcache_range((ulong)bp,
1153 (ulong)bp + MPSC_TXBE_SIZE);
1154 #endif
1155 mpsc_setup_tx_desc(pi, i, 1);
1156
1157 /* Advance to next descriptor */
1158 pi->txr_head = (pi->txr_head + 1) & (MPSC_TXR_ENTRIES - 1);
1159 }
1160 }
1161
1162 static int mpsc_tx_intr(struct mpsc_port_info *pi)
1163 {
1164 struct mpsc_tx_desc *txre;
1165 int rc = 0;
1166 unsigned long iflags;
1167
1168 spin_lock_irqsave(&pi->tx_lock, iflags);
1169
1170 if (!mpsc_sdma_tx_active(pi)) {
1171 txre = (struct mpsc_tx_desc *)(pi->txr
1172 + (pi->txr_tail * MPSC_TXRE_SIZE));
1173
1174 dma_cache_sync(pi->port.dev, (void *)txre, MPSC_TXRE_SIZE,
1175 DMA_FROM_DEVICE);
1176 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1177 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1178 invalidate_dcache_range((ulong)txre,
1179 (ulong)txre + MPSC_TXRE_SIZE);
1180 #endif
1181
1182 while (!(be32_to_cpu(txre->cmdstat) & SDMA_DESC_CMDSTAT_O)) {
1183 rc = 1;
1184 pi->port.icount.tx += be16_to_cpu(txre->bytecnt);
1185 pi->txr_tail = (pi->txr_tail+1) & (MPSC_TXR_ENTRIES-1);
1186
1187 /* If no more data to tx, fall out of loop */
1188 if (pi->txr_head == pi->txr_tail)
1189 break;
1190
1191 txre = (struct mpsc_tx_desc *)(pi->txr
1192 + (pi->txr_tail * MPSC_TXRE_SIZE));
1193 dma_cache_sync(pi->port.dev, (void *)txre,
1194 MPSC_TXRE_SIZE, DMA_FROM_DEVICE);
1195 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1196 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1197 invalidate_dcache_range((ulong)txre,
1198 (ulong)txre + MPSC_TXRE_SIZE);
1199 #endif
1200 }
1201
1202 mpsc_copy_tx_data(pi);
1203 mpsc_sdma_start_tx(pi); /* start next desc if ready */
1204 }
1205
1206 spin_unlock_irqrestore(&pi->tx_lock, iflags);
1207 return rc;
1208 }
1209
1210 /*
1211 * This is the driver's interrupt handler. To avoid a race, we first clear
1212 * the interrupt, then handle any completed Rx/Tx descriptors. When done
1213 * handling those descriptors, we restart the Rx/Tx engines if they're stopped.
1214 */
1215 static irqreturn_t mpsc_sdma_intr(int irq, void *dev_id)
1216 {
1217 struct mpsc_port_info *pi = dev_id;
1218 ulong iflags;
1219 int rc = IRQ_NONE;
1220
1221 pr_debug("mpsc_sdma_intr[%d]: SDMA Interrupt Received\n",pi->port.line);
1222
1223 spin_lock_irqsave(&pi->port.lock, iflags);
1224 mpsc_sdma_intr_ack(pi);
1225 if (mpsc_rx_intr(pi))
1226 rc = IRQ_HANDLED;
1227 if (mpsc_tx_intr(pi))
1228 rc = IRQ_HANDLED;
1229 spin_unlock_irqrestore(&pi->port.lock, iflags);
1230
1231 pr_debug("mpsc_sdma_intr[%d]: SDMA Interrupt Handled\n", pi->port.line);
1232 return rc;
1233 }
1234
1235 /*
1236 ******************************************************************************
1237 *
1238 * serial_core.c Interface routines
1239 *
1240 ******************************************************************************
1241 */
1242 static uint mpsc_tx_empty(struct uart_port *port)
1243 {
1244 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1245 ulong iflags;
1246 uint rc;
1247
1248 spin_lock_irqsave(&pi->port.lock, iflags);
1249 rc = mpsc_sdma_tx_active(pi) ? 0 : TIOCSER_TEMT;
1250 spin_unlock_irqrestore(&pi->port.lock, iflags);
1251
1252 return rc;
1253 }
1254
1255 static void mpsc_set_mctrl(struct uart_port *port, uint mctrl)
1256 {
1257 /* Have no way to set modem control lines AFAICT */
1258 }
1259
1260 static uint mpsc_get_mctrl(struct uart_port *port)
1261 {
1262 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1263 u32 mflags, status;
1264
1265 status = (pi->mirror_regs) ? pi->MPSC_CHR_10_m
1266 : readl(pi->mpsc_base + MPSC_CHR_10);
1267
1268 mflags = 0;
1269 if (status & 0x1)
1270 mflags |= TIOCM_CTS;
1271 if (status & 0x2)
1272 mflags |= TIOCM_CAR;
1273
1274 return mflags | TIOCM_DSR; /* No way to tell if DSR asserted */
1275 }
1276
1277 static void mpsc_stop_tx(struct uart_port *port)
1278 {
1279 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1280
1281 pr_debug("mpsc_stop_tx[%d]\n", port->line);
1282
1283 mpsc_freeze(pi);
1284 }
1285
1286 static void mpsc_start_tx(struct uart_port *port)
1287 {
1288 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1289 unsigned long iflags;
1290
1291 spin_lock_irqsave(&pi->tx_lock, iflags);
1292
1293 mpsc_unfreeze(pi);
1294 mpsc_copy_tx_data(pi);
1295 mpsc_sdma_start_tx(pi);
1296
1297 spin_unlock_irqrestore(&pi->tx_lock, iflags);
1298
1299 pr_debug("mpsc_start_tx[%d]\n", port->line);
1300 }
1301
1302 static void mpsc_start_rx(struct mpsc_port_info *pi)
1303 {
1304 pr_debug("mpsc_start_rx[%d]: Starting...\n", pi->port.line);
1305
1306 if (pi->rcv_data) {
1307 mpsc_enter_hunt(pi);
1308 mpsc_sdma_cmd(pi, SDMA_SDCM_ERD);
1309 }
1310 }
1311
1312 static void mpsc_stop_rx(struct uart_port *port)
1313 {
1314 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1315
1316 pr_debug("mpsc_stop_rx[%d]: Stopping...\n", port->line);
1317
1318 if (pi->mirror_regs) {
1319 writel(pi->MPSC_CHR_2_m | MPSC_CHR_2_RA,
1320 pi->mpsc_base + MPSC_CHR_2);
1321 /* Erratum prevents reading CHR_2 so just delay for a while */
1322 udelay(100);
1323 } else {
1324 writel(readl(pi->mpsc_base + MPSC_CHR_2) | MPSC_CHR_2_RA,
1325 pi->mpsc_base + MPSC_CHR_2);
1326
1327 while (readl(pi->mpsc_base + MPSC_CHR_2) & MPSC_CHR_2_RA)
1328 udelay(10);
1329 }
1330
1331 mpsc_sdma_cmd(pi, SDMA_SDCM_AR);
1332 }
1333
1334 static void mpsc_enable_ms(struct uart_port *port)
1335 {
1336 }
1337
1338 static void mpsc_break_ctl(struct uart_port *port, int ctl)
1339 {
1340 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1341 ulong flags;
1342 u32 v;
1343
1344 v = ctl ? 0x00ff0000 : 0;
1345
1346 spin_lock_irqsave(&pi->port.lock, flags);
1347 if (pi->mirror_regs)
1348 pi->MPSC_CHR_1_m = v;
1349 writel(v, pi->mpsc_base + MPSC_CHR_1);
1350 spin_unlock_irqrestore(&pi->port.lock, flags);
1351 }
1352
1353 static int mpsc_startup(struct uart_port *port)
1354 {
1355 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1356 u32 flag = 0;
1357 int rc;
1358
1359 pr_debug("mpsc_startup[%d]: Starting up MPSC, irq: %d\n",
1360 port->line, pi->port.irq);
1361
1362 if ((rc = mpsc_make_ready(pi)) == 0) {
1363 /* Setup IRQ handler */
1364 mpsc_sdma_intr_ack(pi);
1365
1366 /* If irq's are shared, need to set flag */
1367 if (mpsc_ports[0].port.irq == mpsc_ports[1].port.irq)
1368 flag = IRQF_SHARED;
1369
1370 if (request_irq(pi->port.irq, mpsc_sdma_intr, flag,
1371 "mpsc-sdma", pi))
1372 printk(KERN_ERR "MPSC: Can't get SDMA IRQ %d\n",
1373 pi->port.irq);
1374
1375 mpsc_sdma_intr_unmask(pi, 0xf);
1376 mpsc_sdma_set_rx_ring(pi, (struct mpsc_rx_desc *)(pi->rxr_p
1377 + (pi->rxr_posn * MPSC_RXRE_SIZE)));
1378 }
1379
1380 return rc;
1381 }
1382
1383 static void mpsc_shutdown(struct uart_port *port)
1384 {
1385 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1386
1387 pr_debug("mpsc_shutdown[%d]: Shutting down MPSC\n", port->line);
1388
1389 mpsc_sdma_stop(pi);
1390 free_irq(pi->port.irq, pi);
1391 }
1392
1393 static void mpsc_set_termios(struct uart_port *port, struct ktermios *termios,
1394 struct ktermios *old)
1395 {
1396 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1397 u32 baud;
1398 ulong flags;
1399 u32 chr_bits, stop_bits, par;
1400
1401 pi->c_iflag = termios->c_iflag;
1402 pi->c_cflag = termios->c_cflag;
1403
1404 switch (termios->c_cflag & CSIZE) {
1405 case CS5:
1406 chr_bits = MPSC_MPCR_CL_5;
1407 break;
1408 case CS6:
1409 chr_bits = MPSC_MPCR_CL_6;
1410 break;
1411 case CS7:
1412 chr_bits = MPSC_MPCR_CL_7;
1413 break;
1414 case CS8:
1415 default:
1416 chr_bits = MPSC_MPCR_CL_8;
1417 break;
1418 }
1419
1420 if (termios->c_cflag & CSTOPB)
1421 stop_bits = MPSC_MPCR_SBL_2;
1422 else
1423 stop_bits = MPSC_MPCR_SBL_1;
1424
1425 par = MPSC_CHR_2_PAR_EVEN;
1426 if (termios->c_cflag & PARENB)
1427 if (termios->c_cflag & PARODD)
1428 par = MPSC_CHR_2_PAR_ODD;
1429 #ifdef CMSPAR
1430 if (termios->c_cflag & CMSPAR) {
1431 if (termios->c_cflag & PARODD)
1432 par = MPSC_CHR_2_PAR_MARK;
1433 else
1434 par = MPSC_CHR_2_PAR_SPACE;
1435 }
1436 #endif
1437
1438 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk);
1439
1440 spin_lock_irqsave(&pi->port.lock, flags);
1441
1442 uart_update_timeout(port, termios->c_cflag, baud);
1443
1444 mpsc_set_char_length(pi, chr_bits);
1445 mpsc_set_stop_bit_length(pi, stop_bits);
1446 mpsc_set_parity(pi, par);
1447 mpsc_set_baudrate(pi, baud);
1448
1449 /* Characters/events to read */
1450 pi->port.read_status_mask = SDMA_DESC_CMDSTAT_OR;
1451
1452 if (termios->c_iflag & INPCK)
1453 pi->port.read_status_mask |= SDMA_DESC_CMDSTAT_PE
1454 | SDMA_DESC_CMDSTAT_FR;
1455
1456 if (termios->c_iflag & (BRKINT | PARMRK))
1457 pi->port.read_status_mask |= SDMA_DESC_CMDSTAT_BR;
1458
1459 /* Characters/events to ignore */
1460 pi->port.ignore_status_mask = 0;
1461
1462 if (termios->c_iflag & IGNPAR)
1463 pi->port.ignore_status_mask |= SDMA_DESC_CMDSTAT_PE
1464 | SDMA_DESC_CMDSTAT_FR;
1465
1466 if (termios->c_iflag & IGNBRK) {
1467 pi->port.ignore_status_mask |= SDMA_DESC_CMDSTAT_BR;
1468
1469 if (termios->c_iflag & IGNPAR)
1470 pi->port.ignore_status_mask |= SDMA_DESC_CMDSTAT_OR;
1471 }
1472
1473 if ((termios->c_cflag & CREAD)) {
1474 if (!pi->rcv_data) {
1475 pi->rcv_data = 1;
1476 mpsc_start_rx(pi);
1477 }
1478 } else if (pi->rcv_data) {
1479 mpsc_stop_rx(port);
1480 pi->rcv_data = 0;
1481 }
1482
1483 spin_unlock_irqrestore(&pi->port.lock, flags);
1484 }
1485
1486 static const char *mpsc_type(struct uart_port *port)
1487 {
1488 pr_debug("mpsc_type[%d]: port type: %s\n", port->line,MPSC_DRIVER_NAME);
1489 return MPSC_DRIVER_NAME;
1490 }
1491
1492 static int mpsc_request_port(struct uart_port *port)
1493 {
1494 /* Should make chip/platform specific call */
1495 return 0;
1496 }
1497
1498 static void mpsc_release_port(struct uart_port *port)
1499 {
1500 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1501
1502 if (pi->ready) {
1503 mpsc_uninit_rings(pi);
1504 mpsc_free_ring_mem(pi);
1505 pi->ready = 0;
1506 }
1507 }
1508
1509 static void mpsc_config_port(struct uart_port *port, int flags)
1510 {
1511 }
1512
1513 static int mpsc_verify_port(struct uart_port *port, struct serial_struct *ser)
1514 {
1515 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1516 int rc = 0;
1517
1518 pr_debug("mpsc_verify_port[%d]: Verifying port data\n", pi->port.line);
1519
1520 if (ser->type != PORT_UNKNOWN && ser->type != PORT_MPSC)
1521 rc = -EINVAL;
1522 else if (pi->port.irq != ser->irq)
1523 rc = -EINVAL;
1524 else if (ser->io_type != SERIAL_IO_MEM)
1525 rc = -EINVAL;
1526 else if (pi->port.uartclk / 16 != ser->baud_base) /* Not sure */
1527 rc = -EINVAL;
1528 else if ((void *)pi->port.mapbase != ser->iomem_base)
1529 rc = -EINVAL;
1530 else if (pi->port.iobase != ser->port)
1531 rc = -EINVAL;
1532 else if (ser->hub6 != 0)
1533 rc = -EINVAL;
1534
1535 return rc;
1536 }
1537 #ifdef CONFIG_CONSOLE_POLL
1538 /* Serial polling routines for writing and reading from the uart while
1539 * in an interrupt or debug context.
1540 */
1541
1542 static char poll_buf[2048];
1543 static int poll_ptr;
1544 static int poll_cnt;
1545 static void mpsc_put_poll_char(struct uart_port *port,
1546 unsigned char c);
1547
1548 static int mpsc_get_poll_char(struct uart_port *port)
1549 {
1550 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1551 struct mpsc_rx_desc *rxre;
1552 u32 cmdstat, bytes_in, i;
1553 u8 *bp;
1554
1555 if (!serial_polled)
1556 serial_polled = 1;
1557
1558 pr_debug("mpsc_rx_intr[%d]: Handling Rx intr\n", pi->port.line);
1559
1560 if (poll_cnt) {
1561 poll_cnt--;
1562 return poll_buf[poll_ptr++];
1563 }
1564 poll_ptr = 0;
1565 poll_cnt = 0;
1566
1567 while (poll_cnt == 0) {
1568 rxre = (struct mpsc_rx_desc *)(pi->rxr +
1569 (pi->rxr_posn*MPSC_RXRE_SIZE));
1570 dma_cache_sync(pi->port.dev, (void *)rxre,
1571 MPSC_RXRE_SIZE, DMA_FROM_DEVICE);
1572 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1573 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1574 invalidate_dcache_range((ulong)rxre,
1575 (ulong)rxre + MPSC_RXRE_SIZE);
1576 #endif
1577 /*
1578 * Loop through Rx descriptors handling ones that have
1579 * been completed.
1580 */
1581 while (poll_cnt == 0 &&
1582 !((cmdstat = be32_to_cpu(rxre->cmdstat)) &
1583 SDMA_DESC_CMDSTAT_O)){
1584 bytes_in = be16_to_cpu(rxre->bytecnt);
1585 bp = pi->rxb + (pi->rxr_posn * MPSC_RXBE_SIZE);
1586 dma_cache_sync(pi->port.dev, (void *) bp,
1587 MPSC_RXBE_SIZE, DMA_FROM_DEVICE);
1588 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1589 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1590 invalidate_dcache_range((ulong)bp,
1591 (ulong)bp + MPSC_RXBE_SIZE);
1592 #endif
1593 if ((unlikely(cmdstat & (SDMA_DESC_CMDSTAT_BR |
1594 SDMA_DESC_CMDSTAT_FR | SDMA_DESC_CMDSTAT_OR))) &&
1595 !(cmdstat & pi->port.ignore_status_mask)) {
1596 poll_buf[poll_cnt] = *bp;
1597 poll_cnt++;
1598 } else {
1599 for (i = 0; i < bytes_in; i++) {
1600 poll_buf[poll_cnt] = *bp++;
1601 poll_cnt++;
1602 }
1603 pi->port.icount.rx += bytes_in;
1604 }
1605 rxre->bytecnt = cpu_to_be16(0);
1606 wmb();
1607 rxre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O |
1608 SDMA_DESC_CMDSTAT_EI |
1609 SDMA_DESC_CMDSTAT_F |
1610 SDMA_DESC_CMDSTAT_L);
1611 wmb();
1612 dma_cache_sync(pi->port.dev, (void *)rxre,
1613 MPSC_RXRE_SIZE, DMA_BIDIRECTIONAL);
1614 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1615 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1616 flush_dcache_range((ulong)rxre,
1617 (ulong)rxre + MPSC_RXRE_SIZE);
1618 #endif
1619
1620 /* Advance to next descriptor */
1621 pi->rxr_posn = (pi->rxr_posn + 1) &
1622 (MPSC_RXR_ENTRIES - 1);
1623 rxre = (struct mpsc_rx_desc *)(pi->rxr +
1624 (pi->rxr_posn * MPSC_RXRE_SIZE));
1625 dma_cache_sync(pi->port.dev, (void *)rxre,
1626 MPSC_RXRE_SIZE, DMA_FROM_DEVICE);
1627 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1628 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1629 invalidate_dcache_range((ulong)rxre,
1630 (ulong)rxre + MPSC_RXRE_SIZE);
1631 #endif
1632 }
1633
1634 /* Restart rx engine, if its stopped */
1635 if ((readl(pi->sdma_base + SDMA_SDCM) & SDMA_SDCM_ERD) == 0)
1636 mpsc_start_rx(pi);
1637 }
1638 if (poll_cnt) {
1639 poll_cnt--;
1640 return poll_buf[poll_ptr++];
1641 }
1642
1643 return 0;
1644 }
1645
1646
1647 static void mpsc_put_poll_char(struct uart_port *port,
1648 unsigned char c)
1649 {
1650 struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
1651 u32 data;
1652
1653 data = readl(pi->mpsc_base + MPSC_MPCR);
1654 writeb(c, pi->mpsc_base + MPSC_CHR_1);
1655 mb();
1656 data = readl(pi->mpsc_base + MPSC_CHR_2);
1657 data |= MPSC_CHR_2_TTCS;
1658 writel(data, pi->mpsc_base + MPSC_CHR_2);
1659 mb();
1660
1661 while (readl(pi->mpsc_base + MPSC_CHR_2) & MPSC_CHR_2_TTCS);
1662 }
1663 #endif
1664
1665 static struct uart_ops mpsc_pops = {
1666 .tx_empty = mpsc_tx_empty,
1667 .set_mctrl = mpsc_set_mctrl,
1668 .get_mctrl = mpsc_get_mctrl,
1669 .stop_tx = mpsc_stop_tx,
1670 .start_tx = mpsc_start_tx,
1671 .stop_rx = mpsc_stop_rx,
1672 .enable_ms = mpsc_enable_ms,
1673 .break_ctl = mpsc_break_ctl,
1674 .startup = mpsc_startup,
1675 .shutdown = mpsc_shutdown,
1676 .set_termios = mpsc_set_termios,
1677 .type = mpsc_type,
1678 .release_port = mpsc_release_port,
1679 .request_port = mpsc_request_port,
1680 .config_port = mpsc_config_port,
1681 .verify_port = mpsc_verify_port,
1682 #ifdef CONFIG_CONSOLE_POLL
1683 .poll_get_char = mpsc_get_poll_char,
1684 .poll_put_char = mpsc_put_poll_char,
1685 #endif
1686 };
1687
1688 /*
1689 ******************************************************************************
1690 *
1691 * Console Interface Routines
1692 *
1693 ******************************************************************************
1694 */
1695
1696 #ifdef CONFIG_SERIAL_MPSC_CONSOLE
1697 static void mpsc_console_write(struct console *co, const char *s, uint count)
1698 {
1699 struct mpsc_port_info *pi = &mpsc_ports[co->index];
1700 u8 *bp, *dp, add_cr = 0;
1701 int i;
1702 unsigned long iflags;
1703
1704 spin_lock_irqsave(&pi->tx_lock, iflags);
1705
1706 while (pi->txr_head != pi->txr_tail) {
1707 while (mpsc_sdma_tx_active(pi))
1708 udelay(100);
1709 mpsc_sdma_intr_ack(pi);
1710 mpsc_tx_intr(pi);
1711 }
1712
1713 while (mpsc_sdma_tx_active(pi))
1714 udelay(100);
1715
1716 while (count > 0) {
1717 bp = dp = pi->txb + (pi->txr_head * MPSC_TXBE_SIZE);
1718
1719 for (i = 0; i < MPSC_TXBE_SIZE; i++) {
1720 if (count == 0)
1721 break;
1722
1723 if (add_cr) {
1724 *(dp++) = '\r';
1725 add_cr = 0;
1726 } else {
1727 *(dp++) = *s;
1728
1729 if (*(s++) == '\n') { /* add '\r' after '\n' */
1730 add_cr = 1;
1731 count++;
1732 }
1733 }
1734
1735 count--;
1736 }
1737
1738 dma_cache_sync(pi->port.dev, (void *)bp, MPSC_TXBE_SIZE,
1739 DMA_BIDIRECTIONAL);
1740 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1741 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1742 flush_dcache_range((ulong)bp,
1743 (ulong)bp + MPSC_TXBE_SIZE);
1744 #endif
1745 mpsc_setup_tx_desc(pi, i, 0);
1746 pi->txr_head = (pi->txr_head + 1) & (MPSC_TXR_ENTRIES - 1);
1747 mpsc_sdma_start_tx(pi);
1748
1749 while (mpsc_sdma_tx_active(pi))
1750 udelay(100);
1751
1752 pi->txr_tail = (pi->txr_tail + 1) & (MPSC_TXR_ENTRIES - 1);
1753 }
1754
1755 spin_unlock_irqrestore(&pi->tx_lock, iflags);
1756 }
1757
1758 static int __init mpsc_console_setup(struct console *co, char *options)
1759 {
1760 struct mpsc_port_info *pi;
1761 int baud, bits, parity, flow;
1762
1763 pr_debug("mpsc_console_setup[%d]: options: %s\n", co->index, options);
1764
1765 if (co->index >= MPSC_NUM_CTLRS)
1766 co->index = 0;
1767
1768 pi = &mpsc_ports[co->index];
1769
1770 baud = pi->default_baud;
1771 bits = pi->default_bits;
1772 parity = pi->default_parity;
1773 flow = pi->default_flow;
1774
1775 if (!pi->port.ops)
1776 return -ENODEV;
1777
1778 spin_lock_init(&pi->port.lock); /* Temporary fix--copied from 8250.c */
1779
1780 if (options)
1781 uart_parse_options(options, &baud, &parity, &bits, &flow);
1782
1783 return uart_set_options(&pi->port, co, baud, parity, bits, flow);
1784 }
1785
1786 static struct console mpsc_console = {
1787 .name = MPSC_DEV_NAME,
1788 .write = mpsc_console_write,
1789 .device = uart_console_device,
1790 .setup = mpsc_console_setup,
1791 .flags = CON_PRINTBUFFER,
1792 .index = -1,
1793 .data = &mpsc_reg,
1794 };
1795
1796 static int __init mpsc_late_console_init(void)
1797 {
1798 pr_debug("mpsc_late_console_init: Enter\n");
1799
1800 if (!(mpsc_console.flags & CON_ENABLED))
1801 register_console(&mpsc_console);
1802 return 0;
1803 }
1804
1805 late_initcall(mpsc_late_console_init);
1806
1807 #define MPSC_CONSOLE &mpsc_console
1808 #else
1809 #define MPSC_CONSOLE NULL
1810 #endif
1811 /*
1812 ******************************************************************************
1813 *
1814 * Dummy Platform Driver to extract & map shared register regions
1815 *
1816 ******************************************************************************
1817 */
1818 static void mpsc_resource_err(char *s)
1819 {
1820 printk(KERN_WARNING "MPSC: Platform device resource error in %s\n", s);
1821 }
1822
1823 static int mpsc_shared_map_regs(struct platform_device *pd)
1824 {
1825 struct resource *r;
1826
1827 if ((r = platform_get_resource(pd, IORESOURCE_MEM,
1828 MPSC_ROUTING_BASE_ORDER))
1829 && request_mem_region(r->start,
1830 MPSC_ROUTING_REG_BLOCK_SIZE,
1831 "mpsc_routing_regs")) {
1832 mpsc_shared_regs.mpsc_routing_base = ioremap(r->start,
1833 MPSC_ROUTING_REG_BLOCK_SIZE);
1834 mpsc_shared_regs.mpsc_routing_base_p = r->start;
1835 } else {
1836 mpsc_resource_err("MPSC routing base");
1837 return -ENOMEM;
1838 }
1839
1840 if ((r = platform_get_resource(pd, IORESOURCE_MEM,
1841 MPSC_SDMA_INTR_BASE_ORDER))
1842 && request_mem_region(r->start,
1843 MPSC_SDMA_INTR_REG_BLOCK_SIZE,
1844 "sdma_intr_regs")) {
1845 mpsc_shared_regs.sdma_intr_base = ioremap(r->start,
1846 MPSC_SDMA_INTR_REG_BLOCK_SIZE);
1847 mpsc_shared_regs.sdma_intr_base_p = r->start;
1848 } else {
1849 iounmap(mpsc_shared_regs.mpsc_routing_base);
1850 release_mem_region(mpsc_shared_regs.mpsc_routing_base_p,
1851 MPSC_ROUTING_REG_BLOCK_SIZE);
1852 mpsc_resource_err("SDMA intr base");
1853 return -ENOMEM;
1854 }
1855
1856 return 0;
1857 }
1858
1859 static void mpsc_shared_unmap_regs(void)
1860 {
1861 if (!mpsc_shared_regs.mpsc_routing_base) {
1862 iounmap(mpsc_shared_regs.mpsc_routing_base);
1863 release_mem_region(mpsc_shared_regs.mpsc_routing_base_p,
1864 MPSC_ROUTING_REG_BLOCK_SIZE);
1865 }
1866 if (!mpsc_shared_regs.sdma_intr_base) {
1867 iounmap(mpsc_shared_regs.sdma_intr_base);
1868 release_mem_region(mpsc_shared_regs.sdma_intr_base_p,
1869 MPSC_SDMA_INTR_REG_BLOCK_SIZE);
1870 }
1871
1872 mpsc_shared_regs.mpsc_routing_base = NULL;
1873 mpsc_shared_regs.sdma_intr_base = NULL;
1874
1875 mpsc_shared_regs.mpsc_routing_base_p = 0;
1876 mpsc_shared_regs.sdma_intr_base_p = 0;
1877 }
1878
1879 static int mpsc_shared_drv_probe(struct platform_device *dev)
1880 {
1881 struct mpsc_shared_pdata *pdata;
1882 int rc = -ENODEV;
1883
1884 if (dev->id == 0) {
1885 if (!(rc = mpsc_shared_map_regs(dev))) {
1886 pdata = (struct mpsc_shared_pdata *)
1887 dev->dev.platform_data;
1888
1889 mpsc_shared_regs.MPSC_MRR_m = pdata->mrr_val;
1890 mpsc_shared_regs.MPSC_RCRR_m= pdata->rcrr_val;
1891 mpsc_shared_regs.MPSC_TCRR_m= pdata->tcrr_val;
1892 mpsc_shared_regs.SDMA_INTR_CAUSE_m =
1893 pdata->intr_cause_val;
1894 mpsc_shared_regs.SDMA_INTR_MASK_m =
1895 pdata->intr_mask_val;
1896
1897 rc = 0;
1898 }
1899 }
1900
1901 return rc;
1902 }
1903
1904 static int mpsc_shared_drv_remove(struct platform_device *dev)
1905 {
1906 int rc = -ENODEV;
1907
1908 if (dev->id == 0) {
1909 mpsc_shared_unmap_regs();
1910 mpsc_shared_regs.MPSC_MRR_m = 0;
1911 mpsc_shared_regs.MPSC_RCRR_m = 0;
1912 mpsc_shared_regs.MPSC_TCRR_m = 0;
1913 mpsc_shared_regs.SDMA_INTR_CAUSE_m = 0;
1914 mpsc_shared_regs.SDMA_INTR_MASK_m = 0;
1915 rc = 0;
1916 }
1917
1918 return rc;
1919 }
1920
1921 static struct platform_driver mpsc_shared_driver = {
1922 .probe = mpsc_shared_drv_probe,
1923 .remove = mpsc_shared_drv_remove,
1924 .driver = {
1925 .name = MPSC_SHARED_NAME,
1926 },
1927 };
1928
1929 /*
1930 ******************************************************************************
1931 *
1932 * Driver Interface Routines
1933 *
1934 ******************************************************************************
1935 */
1936 static struct uart_driver mpsc_reg = {
1937 .owner = THIS_MODULE,
1938 .driver_name = MPSC_DRIVER_NAME,
1939 .dev_name = MPSC_DEV_NAME,
1940 .major = MPSC_MAJOR,
1941 .minor = MPSC_MINOR_START,
1942 .nr = MPSC_NUM_CTLRS,
1943 .cons = MPSC_CONSOLE,
1944 };
1945
1946 static int mpsc_drv_map_regs(struct mpsc_port_info *pi,
1947 struct platform_device *pd)
1948 {
1949 struct resource *r;
1950
1951 if ((r = platform_get_resource(pd, IORESOURCE_MEM, MPSC_BASE_ORDER))
1952 && request_mem_region(r->start, MPSC_REG_BLOCK_SIZE,
1953 "mpsc_regs")) {
1954 pi->mpsc_base = ioremap(r->start, MPSC_REG_BLOCK_SIZE);
1955 pi->mpsc_base_p = r->start;
1956 } else {
1957 mpsc_resource_err("MPSC base");
1958 goto err;
1959 }
1960
1961 if ((r = platform_get_resource(pd, IORESOURCE_MEM,
1962 MPSC_SDMA_BASE_ORDER))
1963 && request_mem_region(r->start,
1964 MPSC_SDMA_REG_BLOCK_SIZE, "sdma_regs")) {
1965 pi->sdma_base = ioremap(r->start,MPSC_SDMA_REG_BLOCK_SIZE);
1966 pi->sdma_base_p = r->start;
1967 } else {
1968 mpsc_resource_err("SDMA base");
1969 if (pi->mpsc_base) {
1970 iounmap(pi->mpsc_base);
1971 pi->mpsc_base = NULL;
1972 }
1973 goto err;
1974 }
1975
1976 if ((r = platform_get_resource(pd,IORESOURCE_MEM,MPSC_BRG_BASE_ORDER))
1977 && request_mem_region(r->start,
1978 MPSC_BRG_REG_BLOCK_SIZE, "brg_regs")) {
1979 pi->brg_base = ioremap(r->start, MPSC_BRG_REG_BLOCK_SIZE);
1980 pi->brg_base_p = r->start;
1981 } else {
1982 mpsc_resource_err("BRG base");
1983 if (pi->mpsc_base) {
1984 iounmap(pi->mpsc_base);
1985 pi->mpsc_base = NULL;
1986 }
1987 if (pi->sdma_base) {
1988 iounmap(pi->sdma_base);
1989 pi->sdma_base = NULL;
1990 }
1991 goto err;
1992 }
1993 return 0;
1994
1995 err:
1996 return -ENOMEM;
1997 }
1998
1999 static void mpsc_drv_unmap_regs(struct mpsc_port_info *pi)
2000 {
2001 if (!pi->mpsc_base) {
2002 iounmap(pi->mpsc_base);
2003 release_mem_region(pi->mpsc_base_p, MPSC_REG_BLOCK_SIZE);
2004 }
2005 if (!pi->sdma_base) {
2006 iounmap(pi->sdma_base);
2007 release_mem_region(pi->sdma_base_p, MPSC_SDMA_REG_BLOCK_SIZE);
2008 }
2009 if (!pi->brg_base) {
2010 iounmap(pi->brg_base);
2011 release_mem_region(pi->brg_base_p, MPSC_BRG_REG_BLOCK_SIZE);
2012 }
2013
2014 pi->mpsc_base = NULL;
2015 pi->sdma_base = NULL;
2016 pi->brg_base = NULL;
2017
2018 pi->mpsc_base_p = 0;
2019 pi->sdma_base_p = 0;
2020 pi->brg_base_p = 0;
2021 }
2022
2023 static void mpsc_drv_get_platform_data(struct mpsc_port_info *pi,
2024 struct platform_device *pd, int num)
2025 {
2026 struct mpsc_pdata *pdata;
2027
2028 pdata = (struct mpsc_pdata *)pd->dev.platform_data;
2029
2030 pi->port.uartclk = pdata->brg_clk_freq;
2031 pi->port.iotype = UPIO_MEM;
2032 pi->port.line = num;
2033 pi->port.type = PORT_MPSC;
2034 pi->port.fifosize = MPSC_TXBE_SIZE;
2035 pi->port.membase = pi->mpsc_base;
2036 pi->port.mapbase = (ulong)pi->mpsc_base;
2037 pi->port.ops = &mpsc_pops;
2038
2039 pi->mirror_regs = pdata->mirror_regs;
2040 pi->cache_mgmt = pdata->cache_mgmt;
2041 pi->brg_can_tune = pdata->brg_can_tune;
2042 pi->brg_clk_src = pdata->brg_clk_src;
2043 pi->mpsc_max_idle = pdata->max_idle;
2044 pi->default_baud = pdata->default_baud;
2045 pi->default_bits = pdata->default_bits;
2046 pi->default_parity = pdata->default_parity;
2047 pi->default_flow = pdata->default_flow;
2048
2049 /* Initial values of mirrored regs */
2050 pi->MPSC_CHR_1_m = pdata->chr_1_val;
2051 pi->MPSC_CHR_2_m = pdata->chr_2_val;
2052 pi->MPSC_CHR_10_m = pdata->chr_10_val;
2053 pi->MPSC_MPCR_m = pdata->mpcr_val;
2054 pi->BRG_BCR_m = pdata->bcr_val;
2055
2056 pi->shared_regs = &mpsc_shared_regs;
2057
2058 pi->port.irq = platform_get_irq(pd, 0);
2059 }
2060
2061 static int mpsc_drv_probe(struct platform_device *dev)
2062 {
2063 struct mpsc_port_info *pi;
2064 int rc = -ENODEV;
2065
2066 pr_debug("mpsc_drv_probe: Adding MPSC %d\n", dev->id);
2067
2068 if (dev->id < MPSC_NUM_CTLRS) {
2069 pi = &mpsc_ports[dev->id];
2070
2071 if (!(rc = mpsc_drv_map_regs(pi, dev))) {
2072 mpsc_drv_get_platform_data(pi, dev, dev->id);
2073 pi->port.dev = &dev->dev;
2074
2075 if (!(rc = mpsc_make_ready(pi))) {
2076 spin_lock_init(&pi->tx_lock);
2077 if (!(rc = uart_add_one_port(&mpsc_reg,
2078 &pi->port))) {
2079 rc = 0;
2080 } else {
2081 mpsc_release_port((struct uart_port *)
2082 pi);
2083 mpsc_drv_unmap_regs(pi);
2084 }
2085 } else {
2086 mpsc_drv_unmap_regs(pi);
2087 }
2088 }
2089 }
2090
2091 return rc;
2092 }
2093
2094 static int mpsc_drv_remove(struct platform_device *dev)
2095 {
2096 pr_debug("mpsc_drv_exit: Removing MPSC %d\n", dev->id);
2097
2098 if (dev->id < MPSC_NUM_CTLRS) {
2099 uart_remove_one_port(&mpsc_reg, &mpsc_ports[dev->id].port);
2100 mpsc_release_port((struct uart_port *)
2101 &mpsc_ports[dev->id].port);
2102 mpsc_drv_unmap_regs(&mpsc_ports[dev->id]);
2103 return 0;
2104 } else {
2105 return -ENODEV;
2106 }
2107 }
2108
2109 static struct platform_driver mpsc_driver = {
2110 .probe = mpsc_drv_probe,
2111 .remove = mpsc_drv_remove,
2112 .driver = {
2113 .name = MPSC_CTLR_NAME,
2114 .owner = THIS_MODULE,
2115 },
2116 };
2117
2118 static int __init mpsc_drv_init(void)
2119 {
2120 int rc;
2121
2122 printk(KERN_INFO "Serial: MPSC driver\n");
2123
2124 memset(mpsc_ports, 0, sizeof(mpsc_ports));
2125 memset(&mpsc_shared_regs, 0, sizeof(mpsc_shared_regs));
2126
2127 if (!(rc = uart_register_driver(&mpsc_reg))) {
2128 if (!(rc = platform_driver_register(&mpsc_shared_driver))) {
2129 if ((rc = platform_driver_register(&mpsc_driver))) {
2130 platform_driver_unregister(&mpsc_shared_driver);
2131 uart_unregister_driver(&mpsc_reg);
2132 }
2133 } else {
2134 uart_unregister_driver(&mpsc_reg);
2135 }
2136 }
2137
2138 return rc;
2139 }
2140
2141 static void __exit mpsc_drv_exit(void)
2142 {
2143 platform_driver_unregister(&mpsc_driver);
2144 platform_driver_unregister(&mpsc_shared_driver);
2145 uart_unregister_driver(&mpsc_reg);
2146 memset(mpsc_ports, 0, sizeof(mpsc_ports));
2147 memset(&mpsc_shared_regs, 0, sizeof(mpsc_shared_regs));
2148 }
2149
2150 module_init(mpsc_drv_init);
2151 module_exit(mpsc_drv_exit);
2152
2153 MODULE_AUTHOR("Mark A. Greer <mgreer@mvista.com>");
2154 MODULE_DESCRIPTION("Generic Marvell MPSC serial/UART driver");
2155 MODULE_VERSION(MPSC_VERSION);
2156 MODULE_LICENSE("GPL");
2157 MODULE_ALIAS_CHARDEV_MAJOR(MPSC_MAJOR);
2158 MODULE_ALIAS("platform:" MPSC_CTLR_NAME);
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