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Linux 3.11-rc3
[cris-mirror.git] / drivers / tty / serial / serial-tegra.c
blobee7c8123c374aa18b22a88a564d0f89008c07acb
1 /*
2 * serial_tegra.c
3 *
4 * High-speed serial driver for NVIDIA Tegra SoCs
5 *
6 * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved.
7 *
8 * Author: Laxman Dewangan <ldewangan@nvidia.com>
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms and conditions of the GNU General Public License,
12 * version 2, as published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #include <linux/clk.h>
24 #include <linux/debugfs.h>
25 #include <linux/delay.h>
26 #include <linux/dmaengine.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/dmapool.h>
29 #include <linux/err.h>
30 #include <linux/io.h>
31 #include <linux/irq.h>
32 #include <linux/module.h>
33 #include <linux/of.h>
34 #include <linux/of_device.h>
35 #include <linux/pagemap.h>
36 #include <linux/platform_device.h>
37 #include <linux/serial.h>
38 #include <linux/serial_8250.h>
39 #include <linux/serial_core.h>
40 #include <linux/serial_reg.h>
41 #include <linux/slab.h>
42 #include <linux/string.h>
43 #include <linux/termios.h>
44 #include <linux/tty.h>
45 #include <linux/tty_flip.h>
46
47 #include <linux/clk/tegra.h>
48
49 #define TEGRA_UART_TYPE "TEGRA_UART"
50 #define TX_EMPTY_STATUS (UART_LSR_TEMT | UART_LSR_THRE)
51 #define BYTES_TO_ALIGN(x) ((unsigned long)(x) & 0x3)
52
53 #define TEGRA_UART_RX_DMA_BUFFER_SIZE 4096
54 #define TEGRA_UART_LSR_TXFIFO_FULL 0x100
55 #define TEGRA_UART_IER_EORD 0x20
56 #define TEGRA_UART_MCR_RTS_EN 0x40
57 #define TEGRA_UART_MCR_CTS_EN 0x20
58 #define TEGRA_UART_LSR_ANY (UART_LSR_OE | UART_LSR_BI | \
59 UART_LSR_PE | UART_LSR_FE)
60 #define TEGRA_UART_IRDA_CSR 0x08
61 #define TEGRA_UART_SIR_ENABLED 0x80
62
63 #define TEGRA_UART_TX_PIO 1
64 #define TEGRA_UART_TX_DMA 2
65 #define TEGRA_UART_MIN_DMA 16
66 #define TEGRA_UART_FIFO_SIZE 32
67
68 /*
69 * Tx fifo trigger level setting in tegra uart is in
70 * reverse way then conventional uart.
71 */
72 #define TEGRA_UART_TX_TRIG_16B 0x00
73 #define TEGRA_UART_TX_TRIG_8B 0x10
74 #define TEGRA_UART_TX_TRIG_4B 0x20
75 #define TEGRA_UART_TX_TRIG_1B 0x30
76
77 #define TEGRA_UART_MAXIMUM 5
78
79 /* Default UART setting when started: 115200 no parity, stop, 8 data bits */
80 #define TEGRA_UART_DEFAULT_BAUD 115200
81 #define TEGRA_UART_DEFAULT_LSR UART_LCR_WLEN8
82
83 /* Tx transfer mode */
84 #define TEGRA_TX_PIO 1
85 #define TEGRA_TX_DMA 2
86
87 /**
88 * tegra_uart_chip_data: SOC specific data.
89 *
90 * @tx_fifo_full_status: Status flag available for checking tx fifo full.
91 * @allow_txfifo_reset_fifo_mode: allow_tx fifo reset with fifo mode or not.
92 * Tegra30 does not allow this.
93 * @support_clk_src_div: Clock source support the clock divider.
94 */
95 struct tegra_uart_chip_data {
96 bool tx_fifo_full_status;
97 bool allow_txfifo_reset_fifo_mode;
98 bool support_clk_src_div;
99 };
100
101 struct tegra_uart_port {
102 struct uart_port uport;
103 const struct tegra_uart_chip_data *cdata;
104
105 struct clk *uart_clk;
106 unsigned int current_baud;
107
108 /* Register shadow */
109 unsigned long fcr_shadow;
110 unsigned long mcr_shadow;
111 unsigned long lcr_shadow;
112 unsigned long ier_shadow;
113 bool rts_active;
114
115 int tx_in_progress;
116 unsigned int tx_bytes;
117
118 bool enable_modem_interrupt;
119
120 bool rx_timeout;
121 int rx_in_progress;
122 int symb_bit;
123 int dma_req_sel;
124
125 struct dma_chan *rx_dma_chan;
126 struct dma_chan *tx_dma_chan;
127 dma_addr_t rx_dma_buf_phys;
128 dma_addr_t tx_dma_buf_phys;
129 unsigned char *rx_dma_buf_virt;
130 unsigned char *tx_dma_buf_virt;
131 struct dma_async_tx_descriptor *tx_dma_desc;
132 struct dma_async_tx_descriptor *rx_dma_desc;
133 dma_cookie_t tx_cookie;
134 dma_cookie_t rx_cookie;
135 int tx_bytes_requested;
136 int rx_bytes_requested;
137 };
138
139 static void tegra_uart_start_next_tx(struct tegra_uart_port *tup);
140 static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup);
141
142 static inline unsigned long tegra_uart_read(struct tegra_uart_port *tup,
143 unsigned long reg)
144 {
145 return readl(tup->uport.membase + (reg << tup->uport.regshift));
146 }
147
148 static inline void tegra_uart_write(struct tegra_uart_port *tup, unsigned val,
149 unsigned long reg)
150 {
151 writel(val, tup->uport.membase + (reg << tup->uport.regshift));
152 }
153
154 static inline struct tegra_uart_port *to_tegra_uport(struct uart_port *u)
155 {
156 return container_of(u, struct tegra_uart_port, uport);
157 }
158
159 static unsigned int tegra_uart_get_mctrl(struct uart_port *u)
160 {
161 struct tegra_uart_port *tup = to_tegra_uport(u);
162
163 /*
164 * RI - Ring detector is active
165 * CD/DCD/CAR - Carrier detect is always active. For some reason
166 * linux has different names for carrier detect.
167 * DSR - Data Set ready is active as the hardware doesn't support it.
168 * Don't know if the linux support this yet?
169 * CTS - Clear to send. Always set to active, as the hardware handles
170 * CTS automatically.
171 */
172 if (tup->enable_modem_interrupt)
173 return TIOCM_RI | TIOCM_CD | TIOCM_DSR | TIOCM_CTS;
174 return TIOCM_CTS;
175 }
176
177 static void set_rts(struct tegra_uart_port *tup, bool active)
178 {
179 unsigned long mcr;
180
181 mcr = tup->mcr_shadow;
182 if (active)
183 mcr |= TEGRA_UART_MCR_RTS_EN;
184 else
185 mcr &= ~TEGRA_UART_MCR_RTS_EN;
186 if (mcr != tup->mcr_shadow) {
187 tegra_uart_write(tup, mcr, UART_MCR);
188 tup->mcr_shadow = mcr;
189 }
190 return;
191 }
192
193 static void set_dtr(struct tegra_uart_port *tup, bool active)
194 {
195 unsigned long mcr;
196
197 mcr = tup->mcr_shadow;
198 if (active)
199 mcr |= UART_MCR_DTR;
200 else
201 mcr &= ~UART_MCR_DTR;
202 if (mcr != tup->mcr_shadow) {
203 tegra_uart_write(tup, mcr, UART_MCR);
204 tup->mcr_shadow = mcr;
205 }
206 return;
207 }
208
209 static void tegra_uart_set_mctrl(struct uart_port *u, unsigned int mctrl)
210 {
211 struct tegra_uart_port *tup = to_tegra_uport(u);
212 unsigned long mcr;
213 int dtr_enable;
214
215 mcr = tup->mcr_shadow;
216 tup->rts_active = !!(mctrl & TIOCM_RTS);
217 set_rts(tup, tup->rts_active);
218
219 dtr_enable = !!(mctrl & TIOCM_DTR);
220 set_dtr(tup, dtr_enable);
221 return;
222 }
223
224 static void tegra_uart_break_ctl(struct uart_port *u, int break_ctl)
225 {
226 struct tegra_uart_port *tup = to_tegra_uport(u);
227 unsigned long lcr;
228
229 lcr = tup->lcr_shadow;
230 if (break_ctl)
231 lcr |= UART_LCR_SBC;
232 else
233 lcr &= ~UART_LCR_SBC;
234 tegra_uart_write(tup, lcr, UART_LCR);
235 tup->lcr_shadow = lcr;
236 }
237
238 /* Wait for a symbol-time. */
239 static void tegra_uart_wait_sym_time(struct tegra_uart_port *tup,
240 unsigned int syms)
241 {
242 if (tup->current_baud)
243 udelay(DIV_ROUND_UP(syms * tup->symb_bit * 1000000,
244 tup->current_baud));
245 }
246
247 static void tegra_uart_fifo_reset(struct tegra_uart_port *tup, u8 fcr_bits)
248 {
249 unsigned long fcr = tup->fcr_shadow;
250
251 if (tup->cdata->allow_txfifo_reset_fifo_mode) {
252 fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
253 tegra_uart_write(tup, fcr, UART_FCR);
254 } else {
255 fcr &= ~UART_FCR_ENABLE_FIFO;
256 tegra_uart_write(tup, fcr, UART_FCR);
257 udelay(60);
258 fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
259 tegra_uart_write(tup, fcr, UART_FCR);
260 fcr |= UART_FCR_ENABLE_FIFO;
261 tegra_uart_write(tup, fcr, UART_FCR);
262 }
263
264 /* Dummy read to ensure the write is posted */
265 tegra_uart_read(tup, UART_SCR);
266
267 /* Wait for the flush to propagate. */
268 tegra_uart_wait_sym_time(tup, 1);
269 }
270
271 static int tegra_set_baudrate(struct tegra_uart_port *tup, unsigned int baud)
272 {
273 unsigned long rate;
274 unsigned int divisor;
275 unsigned long lcr;
276 int ret;
277
278 if (tup->current_baud == baud)
279 return 0;
280
281 if (tup->cdata->support_clk_src_div) {
282 rate = baud * 16;
283 ret = clk_set_rate(tup->uart_clk, rate);
284 if (ret < 0) {
285 dev_err(tup->uport.dev,
286 "clk_set_rate() failed for rate %lu\n", rate);
287 return ret;
288 }
289 divisor = 1;
290 } else {
291 rate = clk_get_rate(tup->uart_clk);
292 divisor = DIV_ROUND_CLOSEST(rate, baud * 16);
293 }
294
295 lcr = tup->lcr_shadow;
296 lcr |= UART_LCR_DLAB;
297 tegra_uart_write(tup, lcr, UART_LCR);
298
299 tegra_uart_write(tup, divisor & 0xFF, UART_TX);
300 tegra_uart_write(tup, ((divisor >> 8) & 0xFF), UART_IER);
301
302 lcr &= ~UART_LCR_DLAB;
303 tegra_uart_write(tup, lcr, UART_LCR);
304
305 /* Dummy read to ensure the write is posted */
306 tegra_uart_read(tup, UART_SCR);
307
308 tup->current_baud = baud;
309
310 /* wait two character intervals at new rate */
311 tegra_uart_wait_sym_time(tup, 2);
312 return 0;
313 }
314
315 static char tegra_uart_decode_rx_error(struct tegra_uart_port *tup,
316 unsigned long lsr)
317 {
318 char flag = TTY_NORMAL;
319
320 if (unlikely(lsr & TEGRA_UART_LSR_ANY)) {
321 if (lsr & UART_LSR_OE) {
322 /* Overrrun error */
323 flag |= TTY_OVERRUN;
324 tup->uport.icount.overrun++;
325 dev_err(tup->uport.dev, "Got overrun errors\n");
326 } else if (lsr & UART_LSR_PE) {
327 /* Parity error */
328 flag |= TTY_PARITY;
329 tup->uport.icount.parity++;
330 dev_err(tup->uport.dev, "Got Parity errors\n");
331 } else if (lsr & UART_LSR_FE) {
332 flag |= TTY_FRAME;
333 tup->uport.icount.frame++;
334 dev_err(tup->uport.dev, "Got frame errors\n");
335 } else if (lsr & UART_LSR_BI) {
336 dev_err(tup->uport.dev, "Got Break\n");
337 tup->uport.icount.brk++;
338 /* If FIFO read error without any data, reset Rx FIFO */
339 if (!(lsr & UART_LSR_DR) && (lsr & UART_LSR_FIFOE))
340 tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_RCVR);
341 }
342 }
343 return flag;
344 }
345
346 static int tegra_uart_request_port(struct uart_port *u)
347 {
348 return 0;
349 }
350
351 static void tegra_uart_release_port(struct uart_port *u)
352 {
353 /* Nothing to do here */
354 }
355
356 static void tegra_uart_fill_tx_fifo(struct tegra_uart_port *tup, int max_bytes)
357 {
358 struct circ_buf *xmit = &tup->uport.state->xmit;
359 int i;
360
361 for (i = 0; i < max_bytes; i++) {
362 BUG_ON(uart_circ_empty(xmit));
363 if (tup->cdata->tx_fifo_full_status) {
364 unsigned long lsr = tegra_uart_read(tup, UART_LSR);
365 if ((lsr & TEGRA_UART_LSR_TXFIFO_FULL))
366 break;
367 }
368 tegra_uart_write(tup, xmit->buf[xmit->tail], UART_TX);
369 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
370 tup->uport.icount.tx++;
371 }
372 }
373
374 static void tegra_uart_start_pio_tx(struct tegra_uart_port *tup,
375 unsigned int bytes)
376 {
377 if (bytes > TEGRA_UART_MIN_DMA)
378 bytes = TEGRA_UART_MIN_DMA;
379
380 tup->tx_in_progress = TEGRA_UART_TX_PIO;
381 tup->tx_bytes = bytes;
382 tup->ier_shadow |= UART_IER_THRI;
383 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
384 }
385
386 static void tegra_uart_tx_dma_complete(void *args)
387 {
388 struct tegra_uart_port *tup = args;
389 struct circ_buf *xmit = &tup->uport.state->xmit;
390 struct dma_tx_state state;
391 unsigned long flags;
392 int count;
393
394 dmaengine_tx_status(tup->tx_dma_chan, tup->rx_cookie, &state);
395 count = tup->tx_bytes_requested - state.residue;
396 async_tx_ack(tup->tx_dma_desc);
397 spin_lock_irqsave(&tup->uport.lock, flags);
398 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
399 tup->tx_in_progress = 0;
400 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
401 uart_write_wakeup(&tup->uport);
402 tegra_uart_start_next_tx(tup);
403 spin_unlock_irqrestore(&tup->uport.lock, flags);
404 }
405
406 static int tegra_uart_start_tx_dma(struct tegra_uart_port *tup,
407 unsigned long count)
408 {
409 struct circ_buf *xmit = &tup->uport.state->xmit;
410 dma_addr_t tx_phys_addr;
411
412 dma_sync_single_for_device(tup->uport.dev, tup->tx_dma_buf_phys,
413 UART_XMIT_SIZE, DMA_TO_DEVICE);
414
415 tup->tx_bytes = count & ~(0xF);
416 tx_phys_addr = tup->tx_dma_buf_phys + xmit->tail;
417 tup->tx_dma_desc = dmaengine_prep_slave_single(tup->tx_dma_chan,
418 tx_phys_addr, tup->tx_bytes, DMA_MEM_TO_DEV,
419 DMA_PREP_INTERRUPT);
420 if (!tup->tx_dma_desc) {
421 dev_err(tup->uport.dev, "Not able to get desc for Tx\n");
422 return -EIO;
423 }
424
425 tup->tx_dma_desc->callback = tegra_uart_tx_dma_complete;
426 tup->tx_dma_desc->callback_param = tup;
427 tup->tx_in_progress = TEGRA_UART_TX_DMA;
428 tup->tx_bytes_requested = tup->tx_bytes;
429 tup->tx_cookie = dmaengine_submit(tup->tx_dma_desc);
430 dma_async_issue_pending(tup->tx_dma_chan);
431 return 0;
432 }
433
434 static void tegra_uart_start_next_tx(struct tegra_uart_port *tup)
435 {
436 unsigned long tail;
437 unsigned long count;
438 struct circ_buf *xmit = &tup->uport.state->xmit;
439
440 tail = (unsigned long)&xmit->buf[xmit->tail];
441 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
442 if (!count)
443 return;
444
445 if (count < TEGRA_UART_MIN_DMA)
446 tegra_uart_start_pio_tx(tup, count);
447 else if (BYTES_TO_ALIGN(tail) > 0)
448 tegra_uart_start_pio_tx(tup, BYTES_TO_ALIGN(tail));
449 else
450 tegra_uart_start_tx_dma(tup, count);
451 }
452
453 /* Called by serial core driver with u->lock taken. */
454 static void tegra_uart_start_tx(struct uart_port *u)
455 {
456 struct tegra_uart_port *tup = to_tegra_uport(u);
457 struct circ_buf *xmit = &u->state->xmit;
458
459 if (!uart_circ_empty(xmit) && !tup->tx_in_progress)
460 tegra_uart_start_next_tx(tup);
461 }
462
463 static unsigned int tegra_uart_tx_empty(struct uart_port *u)
464 {
465 struct tegra_uart_port *tup = to_tegra_uport(u);
466 unsigned int ret = 0;
467 unsigned long flags;
468
469 spin_lock_irqsave(&u->lock, flags);
470 if (!tup->tx_in_progress) {
471 unsigned long lsr = tegra_uart_read(tup, UART_LSR);
472 if ((lsr & TX_EMPTY_STATUS) == TX_EMPTY_STATUS)
473 ret = TIOCSER_TEMT;
474 }
475 spin_unlock_irqrestore(&u->lock, flags);
476 return ret;
477 }
478
479 static void tegra_uart_stop_tx(struct uart_port *u)
480 {
481 struct tegra_uart_port *tup = to_tegra_uport(u);
482 struct circ_buf *xmit = &tup->uport.state->xmit;
483 struct dma_tx_state state;
484 int count;
485
486 dmaengine_terminate_all(tup->tx_dma_chan);
487 dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state);
488 count = tup->tx_bytes_requested - state.residue;
489 async_tx_ack(tup->tx_dma_desc);
490 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
491 tup->tx_in_progress = 0;
492 return;
493 }
494
495 static void tegra_uart_handle_tx_pio(struct tegra_uart_port *tup)
496 {
497 struct circ_buf *xmit = &tup->uport.state->xmit;
498
499 tegra_uart_fill_tx_fifo(tup, tup->tx_bytes);
500 tup->tx_in_progress = 0;
501 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
502 uart_write_wakeup(&tup->uport);
503 tegra_uart_start_next_tx(tup);
504 return;
505 }
506
507 static void tegra_uart_handle_rx_pio(struct tegra_uart_port *tup,
508 struct tty_port *tty)
509 {
510 do {
511 char flag = TTY_NORMAL;
512 unsigned long lsr = 0;
513 unsigned char ch;
514
515 lsr = tegra_uart_read(tup, UART_LSR);
516 if (!(lsr & UART_LSR_DR))
517 break;
518
519 flag = tegra_uart_decode_rx_error(tup, lsr);
520 ch = (unsigned char) tegra_uart_read(tup, UART_RX);
521 tup->uport.icount.rx++;
522
523 if (!uart_handle_sysrq_char(&tup->uport, ch) && tty)
524 tty_insert_flip_char(tty, ch, flag);
525 } while (1);
526
527 return;
528 }
529
530 static void tegra_uart_copy_rx_to_tty(struct tegra_uart_port *tup,
531 struct tty_port *tty, int count)
532 {
533 int copied;
534
535 tup->uport.icount.rx += count;
536 if (!tty) {
537 dev_err(tup->uport.dev, "No tty port\n");
538 return;
539 }
540 dma_sync_single_for_cpu(tup->uport.dev, tup->rx_dma_buf_phys,
541 TEGRA_UART_RX_DMA_BUFFER_SIZE, DMA_FROM_DEVICE);
542 copied = tty_insert_flip_string(tty,
543 ((unsigned char *)(tup->rx_dma_buf_virt)), count);
544 if (copied != count) {
545 WARN_ON(1);
546 dev_err(tup->uport.dev, "RxData copy to tty layer failed\n");
547 }
548 dma_sync_single_for_device(tup->uport.dev, tup->rx_dma_buf_phys,
549 TEGRA_UART_RX_DMA_BUFFER_SIZE, DMA_TO_DEVICE);
550 }
551
552 static void tegra_uart_rx_dma_complete(void *args)
553 {
554 struct tegra_uart_port *tup = args;
555 struct uart_port *u = &tup->uport;
556 int count = tup->rx_bytes_requested;
557 struct tty_struct *tty = tty_port_tty_get(&tup->uport.state->port);
558 struct tty_port *port = &u->state->port;
559 unsigned long flags;
560
561 async_tx_ack(tup->rx_dma_desc);
562 spin_lock_irqsave(&u->lock, flags);
563
564 /* Deactivate flow control to stop sender */
565 if (tup->rts_active)
566 set_rts(tup, false);
567
568 /* If we are here, DMA is stopped */
569 if (count)
570 tegra_uart_copy_rx_to_tty(tup, port, count);
571
572 tegra_uart_handle_rx_pio(tup, port);
573 if (tty) {
574 tty_flip_buffer_push(port);
575 tty_kref_put(tty);
576 }
577 tegra_uart_start_rx_dma(tup);
578
579 /* Activate flow control to start transfer */
580 if (tup->rts_active)
581 set_rts(tup, true);
582
583 spin_unlock_irqrestore(&u->lock, flags);
584 }
585
586 static void tegra_uart_handle_rx_dma(struct tegra_uart_port *tup)
587 {
588 struct dma_tx_state state;
589 struct tty_struct *tty = tty_port_tty_get(&tup->uport.state->port);
590 struct tty_port *port = &tup->uport.state->port;
591 int count;
592
593 /* Deactivate flow control to stop sender */
594 if (tup->rts_active)
595 set_rts(tup, false);
596
597 dmaengine_terminate_all(tup->rx_dma_chan);
598 dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state);
599 count = tup->rx_bytes_requested - state.residue;
600
601 /* If we are here, DMA is stopped */
602 if (count)
603 tegra_uart_copy_rx_to_tty(tup, port, count);
604
605 tegra_uart_handle_rx_pio(tup, port);
606 if (tty) {
607 tty_flip_buffer_push(port);
608 tty_kref_put(tty);
609 }
610 tegra_uart_start_rx_dma(tup);
611
612 if (tup->rts_active)
613 set_rts(tup, true);
614 }
615
616 static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup)
617 {
618 unsigned int count = TEGRA_UART_RX_DMA_BUFFER_SIZE;
619
620 tup->rx_dma_desc = dmaengine_prep_slave_single(tup->rx_dma_chan,
621 tup->rx_dma_buf_phys, count, DMA_DEV_TO_MEM,
622 DMA_PREP_INTERRUPT);
623 if (!tup->rx_dma_desc) {
624 dev_err(tup->uport.dev, "Not able to get desc for Rx\n");
625 return -EIO;
626 }
627
628 tup->rx_dma_desc->callback = tegra_uart_rx_dma_complete;
629 tup->rx_dma_desc->callback_param = tup;
630 dma_sync_single_for_device(tup->uport.dev, tup->rx_dma_buf_phys,
631 count, DMA_TO_DEVICE);
632 tup->rx_bytes_requested = count;
633 tup->rx_cookie = dmaengine_submit(tup->rx_dma_desc);
634 dma_async_issue_pending(tup->rx_dma_chan);
635 return 0;
636 }
637
638 static void tegra_uart_handle_modem_signal_change(struct uart_port *u)
639 {
640 struct tegra_uart_port *tup = to_tegra_uport(u);
641 unsigned long msr;
642
643 msr = tegra_uart_read(tup, UART_MSR);
644 if (!(msr & UART_MSR_ANY_DELTA))
645 return;
646
647 if (msr & UART_MSR_TERI)
648 tup->uport.icount.rng++;
649 if (msr & UART_MSR_DDSR)
650 tup->uport.icount.dsr++;
651 /* We may only get DDCD when HW init and reset */
652 if (msr & UART_MSR_DDCD)
653 uart_handle_dcd_change(&tup->uport, msr & UART_MSR_DCD);
654 /* Will start/stop_tx accordingly */
655 if (msr & UART_MSR_DCTS)
656 uart_handle_cts_change(&tup->uport, msr & UART_MSR_CTS);
657 return;
658 }
659
660 static irqreturn_t tegra_uart_isr(int irq, void *data)
661 {
662 struct tegra_uart_port *tup = data;
663 struct uart_port *u = &tup->uport;
664 unsigned long iir;
665 unsigned long ier;
666 bool is_rx_int = false;
667 unsigned long flags;
668
669 spin_lock_irqsave(&u->lock, flags);
670 while (1) {
671 iir = tegra_uart_read(tup, UART_IIR);
672 if (iir & UART_IIR_NO_INT) {
673 if (is_rx_int) {
674 tegra_uart_handle_rx_dma(tup);
675 if (tup->rx_in_progress) {
676 ier = tup->ier_shadow;
677 ier |= (UART_IER_RLSI | UART_IER_RTOIE |
678 TEGRA_UART_IER_EORD);
679 tup->ier_shadow = ier;
680 tegra_uart_write(tup, ier, UART_IER);
681 }
682 }
683 spin_unlock_irqrestore(&u->lock, flags);
684 return IRQ_HANDLED;
685 }
686
687 switch ((iir >> 1) & 0x7) {
688 case 0: /* Modem signal change interrupt */
689 tegra_uart_handle_modem_signal_change(u);
690 break;
691
692 case 1: /* Transmit interrupt only triggered when using PIO */
693 tup->ier_shadow &= ~UART_IER_THRI;
694 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
695 tegra_uart_handle_tx_pio(tup);
696 break;
697
698 case 4: /* End of data */
699 case 6: /* Rx timeout */
700 case 2: /* Receive */
701 if (!is_rx_int) {
702 is_rx_int = true;
703 /* Disable Rx interrupts */
704 ier = tup->ier_shadow;
705 ier |= UART_IER_RDI;
706 tegra_uart_write(tup, ier, UART_IER);
707 ier &= ~(UART_IER_RDI | UART_IER_RLSI |
708 UART_IER_RTOIE | TEGRA_UART_IER_EORD);
709 tup->ier_shadow = ier;
710 tegra_uart_write(tup, ier, UART_IER);
711 }
712 break;
713
714 case 3: /* Receive error */
715 tegra_uart_decode_rx_error(tup,
716 tegra_uart_read(tup, UART_LSR));
717 break;
718
719 case 5: /* break nothing to handle */
720 case 7: /* break nothing to handle */
721 break;
722 }
723 }
724 }
725
726 static void tegra_uart_stop_rx(struct uart_port *u)
727 {
728 struct tegra_uart_port *tup = to_tegra_uport(u);
729 struct tty_struct *tty = tty_port_tty_get(&tup->uport.state->port);
730 struct tty_port *port = &u->state->port;
731 struct dma_tx_state state;
732 unsigned long ier;
733 int count;
734
735 if (tup->rts_active)
736 set_rts(tup, false);
737
738 if (!tup->rx_in_progress)
739 return;
740
741 tegra_uart_wait_sym_time(tup, 1); /* wait a character interval */
742
743 ier = tup->ier_shadow;
744 ier &= ~(UART_IER_RDI | UART_IER_RLSI | UART_IER_RTOIE |
745 TEGRA_UART_IER_EORD);
746 tup->ier_shadow = ier;
747 tegra_uart_write(tup, ier, UART_IER);
748 tup->rx_in_progress = 0;
749 if (tup->rx_dma_chan) {
750 dmaengine_terminate_all(tup->rx_dma_chan);
751 dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state);
752 async_tx_ack(tup->rx_dma_desc);
753 count = tup->rx_bytes_requested - state.residue;
754 tegra_uart_copy_rx_to_tty(tup, port, count);
755 tegra_uart_handle_rx_pio(tup, port);
756 } else {
757 tegra_uart_handle_rx_pio(tup, port);
758 }
759 if (tty) {
760 tty_flip_buffer_push(port);
761 tty_kref_put(tty);
762 }
763 return;
764 }
765
766 static void tegra_uart_hw_deinit(struct tegra_uart_port *tup)
767 {
768 unsigned long flags;
769 unsigned long char_time = DIV_ROUND_UP(10000000, tup->current_baud);
770 unsigned long fifo_empty_time = tup->uport.fifosize * char_time;
771 unsigned long wait_time;
772 unsigned long lsr;
773 unsigned long msr;
774 unsigned long mcr;
775
776 /* Disable interrupts */
777 tegra_uart_write(tup, 0, UART_IER);
778
779 lsr = tegra_uart_read(tup, UART_LSR);
780 if ((lsr & UART_LSR_TEMT) != UART_LSR_TEMT) {
781 msr = tegra_uart_read(tup, UART_MSR);
782 mcr = tegra_uart_read(tup, UART_MCR);
783 if ((mcr & TEGRA_UART_MCR_CTS_EN) && (msr & UART_MSR_CTS))
784 dev_err(tup->uport.dev,
785 "Tx Fifo not empty, CTS disabled, waiting\n");
786
787 /* Wait for Tx fifo to be empty */
788 while ((lsr & UART_LSR_TEMT) != UART_LSR_TEMT) {
789 wait_time = min(fifo_empty_time, 100lu);
790 udelay(wait_time);
791 fifo_empty_time -= wait_time;
792 if (!fifo_empty_time) {
793 msr = tegra_uart_read(tup, UART_MSR);
794 mcr = tegra_uart_read(tup, UART_MCR);
795 if ((mcr & TEGRA_UART_MCR_CTS_EN) &&
796 (msr & UART_MSR_CTS))
797 dev_err(tup->uport.dev,
798 "Slave not ready\n");
799 break;
800 }
801 lsr = tegra_uart_read(tup, UART_LSR);
802 }
803 }
804
805 spin_lock_irqsave(&tup->uport.lock, flags);
806 /* Reset the Rx and Tx FIFOs */
807 tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_XMIT | UART_FCR_CLEAR_RCVR);
808 tup->current_baud = 0;
809 spin_unlock_irqrestore(&tup->uport.lock, flags);
810
811 clk_disable_unprepare(tup->uart_clk);
812 }
813
814 static int tegra_uart_hw_init(struct tegra_uart_port *tup)
815 {
816 int ret;
817
818 tup->fcr_shadow = 0;
819 tup->mcr_shadow = 0;
820 tup->lcr_shadow = 0;
821 tup->ier_shadow = 0;
822 tup->current_baud = 0;
823
824 clk_prepare_enable(tup->uart_clk);
825
826 /* Reset the UART controller to clear all previous status.*/
827 tegra_periph_reset_assert(tup->uart_clk);
828 udelay(10);
829 tegra_periph_reset_deassert(tup->uart_clk);
830
831 tup->rx_in_progress = 0;
832 tup->tx_in_progress = 0;
833
834 /*
835 * Set the trigger level
836 *
837 * For PIO mode:
838 *
839 * For receive, this will interrupt the CPU after that many number of
840 * bytes are received, for the remaining bytes the receive timeout
841 * interrupt is received. Rx high watermark is set to 4.
842 *
843 * For transmit, if the trasnmit interrupt is enabled, this will
844 * interrupt the CPU when the number of entries in the FIFO reaches the
845 * low watermark. Tx low watermark is set to 16 bytes.
846 *
847 * For DMA mode:
848 *
849 * Set the Tx trigger to 16. This should match the DMA burst size that
850 * programmed in the DMA registers.
851 */
852 tup->fcr_shadow = UART_FCR_ENABLE_FIFO;
853 tup->fcr_shadow |= UART_FCR_R_TRIG_01;
854 tup->fcr_shadow |= TEGRA_UART_TX_TRIG_16B;
855 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);
856
857 /*
858 * Initialize the UART with default configuration
859 * (115200, N, 8, 1) so that the receive DMA buffer may be
860 * enqueued
861 */
862 tup->lcr_shadow = TEGRA_UART_DEFAULT_LSR;
863 tegra_set_baudrate(tup, TEGRA_UART_DEFAULT_BAUD);
864 tup->fcr_shadow |= UART_FCR_DMA_SELECT;
865 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);
866
867 ret = tegra_uart_start_rx_dma(tup);
868 if (ret < 0) {
869 dev_err(tup->uport.dev, "Not able to start Rx DMA\n");
870 return ret;
871 }
872 tup->rx_in_progress = 1;
873
874 /*
875 * Enable IE_RXS for the receive status interrupts like line errros.
876 * Enable IE_RX_TIMEOUT to get the bytes which cannot be DMA'd.
877 *
878 * If using DMA mode, enable EORD instead of receive interrupt which
879 * will interrupt after the UART is done with the receive instead of
880 * the interrupt when the FIFO "threshold" is reached.
881 *
882 * EORD is different interrupt than RX_TIMEOUT - RX_TIMEOUT occurs when
883 * the DATA is sitting in the FIFO and couldn't be transferred to the
884 * DMA as the DMA size alignment(4 bytes) is not met. EORD will be
885 * triggered when there is a pause of the incomming data stream for 4
886 * characters long.
887 *
888 * For pauses in the data which is not aligned to 4 bytes, we get
889 * both the EORD as well as RX_TIMEOUT - SW sees RX_TIMEOUT first
890 * then the EORD.
891 */
892 tup->ier_shadow = UART_IER_RLSI | UART_IER_RTOIE | TEGRA_UART_IER_EORD;
893 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
894 return 0;
895 }
896
897 static int tegra_uart_dma_channel_allocate(struct tegra_uart_port *tup,
898 bool dma_to_memory)
899 {
900 struct dma_chan *dma_chan;
901 unsigned char *dma_buf;
902 dma_addr_t dma_phys;
903 int ret;
904 struct dma_slave_config dma_sconfig;
905 dma_cap_mask_t mask;
906
907 dma_cap_zero(mask);
908 dma_cap_set(DMA_SLAVE, mask);
909 dma_chan = dma_request_channel(mask, NULL, NULL);
910 if (!dma_chan) {
911 dev_err(tup->uport.dev,
912 "Dma channel is not available, will try later\n");
913 return -EPROBE_DEFER;
914 }
915
916 if (dma_to_memory) {
917 dma_buf = dma_alloc_coherent(tup->uport.dev,
918 TEGRA_UART_RX_DMA_BUFFER_SIZE,
919 &dma_phys, GFP_KERNEL);
920 if (!dma_buf) {
921 dev_err(tup->uport.dev,
922 "Not able to allocate the dma buffer\n");
923 dma_release_channel(dma_chan);
924 return -ENOMEM;
925 }
926 } else {
927 dma_phys = dma_map_single(tup->uport.dev,
928 tup->uport.state->xmit.buf, UART_XMIT_SIZE,
929 DMA_TO_DEVICE);
930 dma_buf = tup->uport.state->xmit.buf;
931 }
932
933 dma_sconfig.slave_id = tup->dma_req_sel;
934 if (dma_to_memory) {
935 dma_sconfig.src_addr = tup->uport.mapbase;
936 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
937 dma_sconfig.src_maxburst = 4;
938 } else {
939 dma_sconfig.dst_addr = tup->uport.mapbase;
940 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
941 dma_sconfig.dst_maxburst = 16;
942 }
943
944 ret = dmaengine_slave_config(dma_chan, &dma_sconfig);
945 if (ret < 0) {
946 dev_err(tup->uport.dev,
947 "Dma slave config failed, err = %d\n", ret);
948 goto scrub;
949 }
950
951 if (dma_to_memory) {
952 tup->rx_dma_chan = dma_chan;
953 tup->rx_dma_buf_virt = dma_buf;
954 tup->rx_dma_buf_phys = dma_phys;
955 } else {
956 tup->tx_dma_chan = dma_chan;
957 tup->tx_dma_buf_virt = dma_buf;
958 tup->tx_dma_buf_phys = dma_phys;
959 }
960 return 0;
961
962 scrub:
963 dma_release_channel(dma_chan);
964 return ret;
965 }
966
967 static void tegra_uart_dma_channel_free(struct tegra_uart_port *tup,
968 bool dma_to_memory)
969 {
970 struct dma_chan *dma_chan;
971
972 if (dma_to_memory) {
973 dma_free_coherent(tup->uport.dev, TEGRA_UART_RX_DMA_BUFFER_SIZE,
974 tup->rx_dma_buf_virt, tup->rx_dma_buf_phys);
975 dma_chan = tup->rx_dma_chan;
976 tup->rx_dma_chan = NULL;
977 tup->rx_dma_buf_phys = 0;
978 tup->rx_dma_buf_virt = NULL;
979 } else {
980 dma_unmap_single(tup->uport.dev, tup->tx_dma_buf_phys,
981 UART_XMIT_SIZE, DMA_TO_DEVICE);
982 dma_chan = tup->tx_dma_chan;
983 tup->tx_dma_chan = NULL;
984 tup->tx_dma_buf_phys = 0;
985 tup->tx_dma_buf_virt = NULL;
986 }
987 dma_release_channel(dma_chan);
988 }
989
990 static int tegra_uart_startup(struct uart_port *u)
991 {
992 struct tegra_uart_port *tup = to_tegra_uport(u);
993 int ret;
994
995 ret = tegra_uart_dma_channel_allocate(tup, false);
996 if (ret < 0) {
997 dev_err(u->dev, "Tx Dma allocation failed, err = %d\n", ret);
998 return ret;
999 }
1000
1001 ret = tegra_uart_dma_channel_allocate(tup, true);
1002 if (ret < 0) {
1003 dev_err(u->dev, "Rx Dma allocation failed, err = %d\n", ret);
1004 goto fail_rx_dma;
1005 }
1006
1007 ret = tegra_uart_hw_init(tup);
1008 if (ret < 0) {
1009 dev_err(u->dev, "Uart HW init failed, err = %d\n", ret);
1010 goto fail_hw_init;
1011 }
1012
1013 ret = request_irq(u->irq, tegra_uart_isr, IRQF_DISABLED,
1014 dev_name(u->dev), tup);
1015 if (ret < 0) {
1016 dev_err(u->dev, "Failed to register ISR for IRQ %d\n", u->irq);
1017 goto fail_hw_init;
1018 }
1019 return 0;
1020
1021 fail_hw_init:
1022 tegra_uart_dma_channel_free(tup, true);
1023 fail_rx_dma:
1024 tegra_uart_dma_channel_free(tup, false);
1025 return ret;
1026 }
1027
1028 static void tegra_uart_shutdown(struct uart_port *u)
1029 {
1030 struct tegra_uart_port *tup = to_tegra_uport(u);
1031
1032 tegra_uart_hw_deinit(tup);
1033
1034 tup->rx_in_progress = 0;
1035 tup->tx_in_progress = 0;
1036
1037 tegra_uart_dma_channel_free(tup, true);
1038 tegra_uart_dma_channel_free(tup, false);
1039 free_irq(u->irq, tup);
1040 }
1041
1042 static void tegra_uart_enable_ms(struct uart_port *u)
1043 {
1044 struct tegra_uart_port *tup = to_tegra_uport(u);
1045
1046 if (tup->enable_modem_interrupt) {
1047 tup->ier_shadow |= UART_IER_MSI;
1048 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
1049 }
1050 }
1051
1052 static void tegra_uart_set_termios(struct uart_port *u,
1053 struct ktermios *termios, struct ktermios *oldtermios)
1054 {
1055 struct tegra_uart_port *tup = to_tegra_uport(u);
1056 unsigned int baud;
1057 unsigned long flags;
1058 unsigned int lcr;
1059 int symb_bit = 1;
1060 struct clk *parent_clk = clk_get_parent(tup->uart_clk);
1061 unsigned long parent_clk_rate = clk_get_rate(parent_clk);
1062 int max_divider = (tup->cdata->support_clk_src_div) ? 0x7FFF : 0xFFFF;
1063
1064 max_divider *= 16;
1065 spin_lock_irqsave(&u->lock, flags);
1066
1067 /* Changing configuration, it is safe to stop any rx now */
1068 if (tup->rts_active)
1069 set_rts(tup, false);
1070
1071 /* Clear all interrupts as configuration is going to be change */
1072 tegra_uart_write(tup, tup->ier_shadow | UART_IER_RDI, UART_IER);
1073 tegra_uart_read(tup, UART_IER);
1074 tegra_uart_write(tup, 0, UART_IER);
1075 tegra_uart_read(tup, UART_IER);
1076
1077 /* Parity */
1078 lcr = tup->lcr_shadow;
1079 lcr &= ~UART_LCR_PARITY;
1080
1081 /* CMSPAR isn't supported by this driver */
1082 termios->c_cflag &= ~CMSPAR;
1083
1084 if ((termios->c_cflag & PARENB) == PARENB) {
1085 symb_bit++;
1086 if (termios->c_cflag & PARODD) {
1087 lcr |= UART_LCR_PARITY;
1088 lcr &= ~UART_LCR_EPAR;
1089 lcr &= ~UART_LCR_SPAR;
1090 } else {
1091 lcr |= UART_LCR_PARITY;
1092 lcr |= UART_LCR_EPAR;
1093 lcr &= ~UART_LCR_SPAR;
1094 }
1095 }
1096
1097 lcr &= ~UART_LCR_WLEN8;
1098 switch (termios->c_cflag & CSIZE) {
1099 case CS5:
1100 lcr |= UART_LCR_WLEN5;
1101 symb_bit += 5;
1102 break;
1103 case CS6:
1104 lcr |= UART_LCR_WLEN6;
1105 symb_bit += 6;
1106 break;
1107 case CS7:
1108 lcr |= UART_LCR_WLEN7;
1109 symb_bit += 7;
1110 break;
1111 default:
1112 lcr |= UART_LCR_WLEN8;
1113 symb_bit += 8;
1114 break;
1115 }
1116
1117 /* Stop bits */
1118 if (termios->c_cflag & CSTOPB) {
1119 lcr |= UART_LCR_STOP;
1120 symb_bit += 2;
1121 } else {
1122 lcr &= ~UART_LCR_STOP;
1123 symb_bit++;
1124 }
1125
1126 tegra_uart_write(tup, lcr, UART_LCR);
1127 tup->lcr_shadow = lcr;
1128 tup->symb_bit = symb_bit;
1129
1130 /* Baud rate. */
1131 baud = uart_get_baud_rate(u, termios, oldtermios,
1132 parent_clk_rate/max_divider,
1133 parent_clk_rate/16);
1134 spin_unlock_irqrestore(&u->lock, flags);
1135 tegra_set_baudrate(tup, baud);
1136 if (tty_termios_baud_rate(termios))
1137 tty_termios_encode_baud_rate(termios, baud, baud);
1138 spin_lock_irqsave(&u->lock, flags);
1139
1140 /* Flow control */
1141 if (termios->c_cflag & CRTSCTS) {
1142 tup->mcr_shadow |= TEGRA_UART_MCR_CTS_EN;
1143 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN;
1144 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR);
1145 /* if top layer has asked to set rts active then do so here */
1146 if (tup->rts_active)
1147 set_rts(tup, true);
1148 } else {
1149 tup->mcr_shadow &= ~TEGRA_UART_MCR_CTS_EN;
1150 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN;
1151 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR);
1152 }
1153
1154 /* update the port timeout based on new settings */
1155 uart_update_timeout(u, termios->c_cflag, baud);
1156
1157 /* Make sure all write has completed */
1158 tegra_uart_read(tup, UART_IER);
1159
1160 /* Reenable interrupt */
1161 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
1162 tegra_uart_read(tup, UART_IER);
1163
1164 spin_unlock_irqrestore(&u->lock, flags);
1165 return;
1166 }
1167
1168 /*
1169 * Flush any TX data submitted for DMA and PIO. Called when the
1170 * TX circular buffer is reset.
1171 */
1172 static void tegra_uart_flush_buffer(struct uart_port *u)
1173 {
1174 struct tegra_uart_port *tup = to_tegra_uport(u);
1175
1176 tup->tx_bytes = 0;
1177 if (tup->tx_dma_chan)
1178 dmaengine_terminate_all(tup->tx_dma_chan);
1179 return;
1180 }
1181
1182 static const char *tegra_uart_type(struct uart_port *u)
1183 {
1184 return TEGRA_UART_TYPE;
1185 }
1186
1187 static struct uart_ops tegra_uart_ops = {
1188 .tx_empty = tegra_uart_tx_empty,
1189 .set_mctrl = tegra_uart_set_mctrl,
1190 .get_mctrl = tegra_uart_get_mctrl,
1191 .stop_tx = tegra_uart_stop_tx,
1192 .start_tx = tegra_uart_start_tx,
1193 .stop_rx = tegra_uart_stop_rx,
1194 .flush_buffer = tegra_uart_flush_buffer,
1195 .enable_ms = tegra_uart_enable_ms,
1196 .break_ctl = tegra_uart_break_ctl,
1197 .startup = tegra_uart_startup,
1198 .shutdown = tegra_uart_shutdown,
1199 .set_termios = tegra_uart_set_termios,
1200 .type = tegra_uart_type,
1201 .request_port = tegra_uart_request_port,
1202 .release_port = tegra_uart_release_port,
1203 };
1204
1205 static struct uart_driver tegra_uart_driver = {
1206 .owner = THIS_MODULE,
1207 .driver_name = "tegra_hsuart",
1208 .dev_name = "ttyTHS",
1209 .cons = 0,
1210 .nr = TEGRA_UART_MAXIMUM,
1211 };
1212
1213 static int tegra_uart_parse_dt(struct platform_device *pdev,
1214 struct tegra_uart_port *tup)
1215 {
1216 struct device_node *np = pdev->dev.of_node;
1217 u32 of_dma[2];
1218 int port;
1219
1220 if (of_property_read_u32_array(np, "nvidia,dma-request-selector",
1221 of_dma, 2) >= 0) {
1222 tup->dma_req_sel = of_dma[1];
1223 } else {
1224 dev_err(&pdev->dev, "missing dma requestor in device tree\n");
1225 return -EINVAL;
1226 }
1227
1228 port = of_alias_get_id(np, "serial");
1229 if (port < 0) {
1230 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", port);
1231 return port;
1232 }
1233 tup->uport.line = port;
1234
1235 tup->enable_modem_interrupt = of_property_read_bool(np,
1236 "nvidia,enable-modem-interrupt");
1237 return 0;
1238 }
1239
1240 struct tegra_uart_chip_data tegra20_uart_chip_data = {
1241 .tx_fifo_full_status = false,
1242 .allow_txfifo_reset_fifo_mode = true,
1243 .support_clk_src_div = false,
1244 };
1245
1246 struct tegra_uart_chip_data tegra30_uart_chip_data = {
1247 .tx_fifo_full_status = true,
1248 .allow_txfifo_reset_fifo_mode = false,
1249 .support_clk_src_div = true,
1250 };
1251
1252 static struct of_device_id tegra_uart_of_match[] = {
1253 {
1254 .compatible = "nvidia,tegra30-hsuart",
1255 .data = &tegra30_uart_chip_data,
1256 }, {
1257 .compatible = "nvidia,tegra20-hsuart",
1258 .data = &tegra20_uart_chip_data,
1259 }, {
1260 },
1261 };
1262 MODULE_DEVICE_TABLE(of, tegra_uart_of_match);
1263
1264 static int tegra_uart_probe(struct platform_device *pdev)
1265 {
1266 struct tegra_uart_port *tup;
1267 struct uart_port *u;
1268 struct resource *resource;
1269 int ret;
1270 const struct tegra_uart_chip_data *cdata;
1271 const struct of_device_id *match;
1272
1273 match = of_match_device(tegra_uart_of_match, &pdev->dev);
1274 if (!match) {
1275 dev_err(&pdev->dev, "Error: No device match found\n");
1276 return -ENODEV;
1277 }
1278 cdata = match->data;
1279
1280 tup = devm_kzalloc(&pdev->dev, sizeof(*tup), GFP_KERNEL);
1281 if (!tup) {
1282 dev_err(&pdev->dev, "Failed to allocate memory for tup\n");
1283 return -ENOMEM;
1284 }
1285
1286 ret = tegra_uart_parse_dt(pdev, tup);
1287 if (ret < 0)
1288 return ret;
1289
1290 u = &tup->uport;
1291 u->dev = &pdev->dev;
1292 u->ops = &tegra_uart_ops;
1293 u->type = PORT_TEGRA;
1294 u->fifosize = 32;
1295 tup->cdata = cdata;
1296
1297 platform_set_drvdata(pdev, tup);
1298 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1299 if (!resource) {
1300 dev_err(&pdev->dev, "No IO memory resource\n");
1301 return -ENODEV;
1302 }
1303
1304 u->mapbase = resource->start;
1305 u->membase = devm_ioremap_resource(&pdev->dev, resource);
1306 if (IS_ERR(u->membase))
1307 return PTR_ERR(u->membase);
1308
1309 tup->uart_clk = devm_clk_get(&pdev->dev, NULL);
1310 if (IS_ERR(tup->uart_clk)) {
1311 dev_err(&pdev->dev, "Couldn't get the clock\n");
1312 return PTR_ERR(tup->uart_clk);
1313 }
1314
1315 u->iotype = UPIO_MEM32;
1316 u->irq = platform_get_irq(pdev, 0);
1317 u->regshift = 2;
1318 ret = uart_add_one_port(&tegra_uart_driver, u);
1319 if (ret < 0) {
1320 dev_err(&pdev->dev, "Failed to add uart port, err %d\n", ret);
1321 return ret;
1322 }
1323 return ret;
1324 }
1325
1326 static int tegra_uart_remove(struct platform_device *pdev)
1327 {
1328 struct tegra_uart_port *tup = platform_get_drvdata(pdev);
1329 struct uart_port *u = &tup->uport;
1330
1331 uart_remove_one_port(&tegra_uart_driver, u);
1332 return 0;
1333 }
1334
1335 #ifdef CONFIG_PM_SLEEP
1336 static int tegra_uart_suspend(struct device *dev)
1337 {
1338 struct tegra_uart_port *tup = dev_get_drvdata(dev);
1339 struct uart_port *u = &tup->uport;
1340
1341 return uart_suspend_port(&tegra_uart_driver, u);
1342 }
1343
1344 static int tegra_uart_resume(struct device *dev)
1345 {
1346 struct tegra_uart_port *tup = dev_get_drvdata(dev);
1347 struct uart_port *u = &tup->uport;
1348
1349 return uart_resume_port(&tegra_uart_driver, u);
1350 }
1351 #endif
1352
1353 static const struct dev_pm_ops tegra_uart_pm_ops = {
1354 SET_SYSTEM_SLEEP_PM_OPS(tegra_uart_suspend, tegra_uart_resume)
1355 };
1356
1357 static struct platform_driver tegra_uart_platform_driver = {
1358 .probe = tegra_uart_probe,
1359 .remove = tegra_uart_remove,
1360 .driver = {
1361 .name = "serial-tegra",
1362 .of_match_table = tegra_uart_of_match,
1363 .pm = &tegra_uart_pm_ops,
1364 },
1365 };
1366
1367 static int __init tegra_uart_init(void)
1368 {
1369 int ret;
1370
1371 ret = uart_register_driver(&tegra_uart_driver);
1372 if (ret < 0) {
1373 pr_err("Could not register %s driver\n",
1374 tegra_uart_driver.driver_name);
1375 return ret;
1376 }
1377
1378 ret = platform_driver_register(&tegra_uart_platform_driver);
1379 if (ret < 0) {
1380 pr_err("Uart platform driver register failed, e = %d\n", ret);
1381 uart_unregister_driver(&tegra_uart_driver);
1382 return ret;
1383 }
1384 return 0;
1385 }
1386
1387 static void __exit tegra_uart_exit(void)
1388 {
1389 pr_info("Unloading tegra uart driver\n");
1390 platform_driver_unregister(&tegra_uart_platform_driver);
1391 uart_unregister_driver(&tegra_uart_driver);
1392 }
1393
1394 module_init(tegra_uart_init);
1395 module_exit(tegra_uart_exit);
1396
1397 MODULE_ALIAS("platform:serial-tegra");
1398 MODULE_DESCRIPTION("High speed UART driver for tegra chipset");
1399 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
1400 MODULE_LICENSE("GPL v2");
CRIS linux kernel tree