2 * Xilinx TFT frame buffer driver
4 * Author: MontaVista Software, Inc.
7 * 2002-2007 (c) MontaVista Software, Inc.
8 * 2007 (c) Secret Lab Technologies, Ltd.
11 * This file is licensed under the terms of the GNU General Public License
12 * version 2. This program is licensed "as is" without any warranty of any
13 * kind, whether express or implied.
17 * This driver was based on au1100fb.c by MontaVista rewritten for 2.6
18 * by Embedded Alley Solutions <source@embeddedalley.com>, which in turn
19 * was based on skeletonfb.c, Skeleton for a frame buffer device by
23 #include <linux/device.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/errno.h>
27 #include <linux/string.h>
30 #include <linux/init.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/of_device.h>
33 #include <linux/of_platform.h>
34 #include <linux/of_address.h>
36 #include <linux/xilinxfb.h>
37 #include <linux/slab.h>
43 #define DRIVER_NAME "xilinxfb"
47 * Xilinx calls it "TFT LCD Controller" though it can also be used for
48 * the VGA port on the Xilinx ML40x board. This is a hardware display
49 * controller for a 640x480 resolution TFT or VGA screen.
51 * The interface to the framebuffer is nice and simple. There are two
52 * control registers. The first tells the LCD interface where in memory
53 * the frame buffer is (only the 11 most significant bits are used, so
54 * don't start thinking about scrolling). The second allows the LCD to
55 * be turned on or off as well as rotated 180 degrees.
57 * In case of direct BUS access the second control register will be at
58 * an offset of 4 as compared to the DCR access where the offset is 1
59 * i.e. REG_CTRL. So this is taken care in the function
60 * xilinx_fb_out32 where it left shifts the offset 2 times in case of
66 #define REG_CTRL_ENABLE 0x0001
67 #define REG_CTRL_ROTATE 0x0002
70 * The hardware only handles a single mode: 640x480 24 bit true
71 * color. Each pixel gets a word (32 bits) of memory. Within each word,
72 * the 8 most significant bits are ignored, the next 8 bits are the red
73 * level, the next 8 bits are the green level and the 8 least
74 * significant bits are the blue level. Each row of the LCD uses 1024
75 * words, but only the first 640 pixels are displayed with the other 384
76 * words being ignored. There are 480 rows.
78 #define BYTES_PER_PIXEL 4
79 #define BITS_PER_PIXEL (BYTES_PER_PIXEL * 8)
85 #define PALETTE_ENTRIES_NO 16 /* passed to fb_alloc_cmap() */
88 * Default xilinxfb configuration
90 static struct xilinxfb_platform_data xilinx_fb_default_pdata
= {
98 * Here are the default fb_fix_screeninfo and fb_var_screeninfo structures
100 static struct fb_fix_screeninfo xilinx_fb_fix
= {
102 .type
= FB_TYPE_PACKED_PIXELS
,
103 .visual
= FB_VISUAL_TRUECOLOR
,
104 .accel
= FB_ACCEL_NONE
107 static struct fb_var_screeninfo xilinx_fb_var
= {
108 .bits_per_pixel
= BITS_PER_PIXEL
,
110 .red
= { RED_SHIFT
, 8, 0 },
111 .green
= { GREEN_SHIFT
, 8, 0 },
112 .blue
= { BLUE_SHIFT
, 8, 0 },
113 .transp
= { 0, 0, 0 },
115 .activate
= FB_ACTIVATE_NOW
119 #define BUS_ACCESS_FLAG 0x1 /* 1 = BUS, 0 = DCR */
120 #define LITTLE_ENDIAN_ACCESS 0x2 /* LITTLE ENDIAN IO functions */
122 struct xilinxfb_drvdata
{
124 struct fb_info info
; /* FB driver info record */
126 phys_addr_t regs_phys
; /* phys. address of the control
128 void __iomem
*regs
; /* virt. address of the control
130 #ifdef CONFIG_PPC_DCR
132 unsigned int dcr_len
;
134 void *fb_virt
; /* virt. address of the frame buffer */
135 dma_addr_t fb_phys
; /* phys. address of the frame buffer */
136 int fb_alloced
; /* Flag, was the fb memory alloced? */
138 u8 flags
; /* features of the driver */
140 u32 reg_ctrl_default
;
142 u32 pseudo_palette
[PALETTE_ENTRIES_NO
];
143 /* Fake palette of 16 colors */
146 #define to_xilinxfb_drvdata(_info) \
147 container_of(_info, struct xilinxfb_drvdata, info)
150 * The XPS TFT Controller can be accessed through BUS or DCR interface.
151 * To perform the read/write on the registers we need to check on
152 * which bus its connected and call the appropriate write API.
154 static void xilinx_fb_out32(struct xilinxfb_drvdata
*drvdata
, u32 offset
,
157 if (drvdata
->flags
& BUS_ACCESS_FLAG
) {
158 if (drvdata
->flags
& LITTLE_ENDIAN_ACCESS
)
159 iowrite32(val
, drvdata
->regs
+ (offset
<< 2));
161 iowrite32be(val
, drvdata
->regs
+ (offset
<< 2));
163 #ifdef CONFIG_PPC_DCR
165 dcr_write(drvdata
->dcr_host
, offset
, val
);
169 static u32
xilinx_fb_in32(struct xilinxfb_drvdata
*drvdata
, u32 offset
)
171 if (drvdata
->flags
& BUS_ACCESS_FLAG
) {
172 if (drvdata
->flags
& LITTLE_ENDIAN_ACCESS
)
173 return ioread32(drvdata
->regs
+ (offset
<< 2));
175 return ioread32be(drvdata
->regs
+ (offset
<< 2));
177 #ifdef CONFIG_PPC_DCR
179 return dcr_read(drvdata
->dcr_host
, offset
);
185 xilinx_fb_setcolreg(unsigned regno
, unsigned red
, unsigned green
, unsigned blue
,
186 unsigned transp
, struct fb_info
*fbi
)
188 u32
*palette
= fbi
->pseudo_palette
;
190 if (regno
>= PALETTE_ENTRIES_NO
)
193 if (fbi
->var
.grayscale
) {
194 /* Convert color to grayscale.
195 * grayscale = 0.30*R + 0.59*G + 0.11*B */
197 (red
* 77 + green
* 151 + blue
* 28 + 127) >> 8;
200 /* fbi->fix.visual is always FB_VISUAL_TRUECOLOR */
202 /* We only handle 8 bits of each color. */
206 palette
[regno
] = (red
<< RED_SHIFT
) | (green
<< GREEN_SHIFT
) |
207 (blue
<< BLUE_SHIFT
);
213 xilinx_fb_blank(int blank_mode
, struct fb_info
*fbi
)
215 struct xilinxfb_drvdata
*drvdata
= to_xilinxfb_drvdata(fbi
);
217 switch (blank_mode
) {
218 case FB_BLANK_UNBLANK
:
220 xilinx_fb_out32(drvdata
, REG_CTRL
, drvdata
->reg_ctrl_default
);
223 case FB_BLANK_NORMAL
:
224 case FB_BLANK_VSYNC_SUSPEND
:
225 case FB_BLANK_HSYNC_SUSPEND
:
226 case FB_BLANK_POWERDOWN
:
228 xilinx_fb_out32(drvdata
, REG_CTRL
, 0);
233 return 0; /* success */
236 static struct fb_ops xilinxfb_ops
=
238 .owner
= THIS_MODULE
,
239 .fb_setcolreg
= xilinx_fb_setcolreg
,
240 .fb_blank
= xilinx_fb_blank
,
241 .fb_fillrect
= cfb_fillrect
,
242 .fb_copyarea
= cfb_copyarea
,
243 .fb_imageblit
= cfb_imageblit
,
246 /* ---------------------------------------------------------------------
247 * Bus independent setup/teardown
250 static int xilinxfb_assign(struct platform_device
*pdev
,
251 struct xilinxfb_drvdata
*drvdata
,
252 struct xilinxfb_platform_data
*pdata
)
255 struct device
*dev
= &pdev
->dev
;
256 int fbsize
= pdata
->xvirt
* pdata
->yvirt
* BYTES_PER_PIXEL
;
258 if (drvdata
->flags
& BUS_ACCESS_FLAG
) {
259 struct resource
*res
;
261 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
262 drvdata
->regs_phys
= res
->start
;
263 drvdata
->regs
= devm_request_and_ioremap(&pdev
->dev
, res
);
264 if (!drvdata
->regs
) {
270 /* Allocate the framebuffer memory */
271 if (pdata
->fb_phys
) {
272 drvdata
->fb_phys
= pdata
->fb_phys
;
273 drvdata
->fb_virt
= ioremap(pdata
->fb_phys
, fbsize
);
275 drvdata
->fb_alloced
= 1;
276 drvdata
->fb_virt
= dma_alloc_coherent(dev
, PAGE_ALIGN(fbsize
),
277 &drvdata
->fb_phys
, GFP_KERNEL
);
280 if (!drvdata
->fb_virt
) {
281 dev_err(dev
, "Could not allocate frame buffer memory\n");
283 if (drvdata
->flags
& BUS_ACCESS_FLAG
)
289 /* Clear (turn to black) the framebuffer */
290 memset_io((void __iomem
*)drvdata
->fb_virt
, 0, fbsize
);
292 /* Tell the hardware where the frame buffer is */
293 xilinx_fb_out32(drvdata
, REG_FB_ADDR
, drvdata
->fb_phys
);
294 rc
= xilinx_fb_in32(drvdata
, REG_FB_ADDR
);
295 /* Endianess detection */
296 if (rc
!= drvdata
->fb_phys
) {
297 drvdata
->flags
|= LITTLE_ENDIAN_ACCESS
;
298 xilinx_fb_out32(drvdata
, REG_FB_ADDR
, drvdata
->fb_phys
);
301 /* Turn on the display */
302 drvdata
->reg_ctrl_default
= REG_CTRL_ENABLE
;
303 if (pdata
->rotate_screen
)
304 drvdata
->reg_ctrl_default
|= REG_CTRL_ROTATE
;
305 xilinx_fb_out32(drvdata
, REG_CTRL
,
306 drvdata
->reg_ctrl_default
);
308 /* Fill struct fb_info */
309 drvdata
->info
.device
= dev
;
310 drvdata
->info
.screen_base
= (void __iomem
*)drvdata
->fb_virt
;
311 drvdata
->info
.fbops
= &xilinxfb_ops
;
312 drvdata
->info
.fix
= xilinx_fb_fix
;
313 drvdata
->info
.fix
.smem_start
= drvdata
->fb_phys
;
314 drvdata
->info
.fix
.smem_len
= fbsize
;
315 drvdata
->info
.fix
.line_length
= pdata
->xvirt
* BYTES_PER_PIXEL
;
317 drvdata
->info
.pseudo_palette
= drvdata
->pseudo_palette
;
318 drvdata
->info
.flags
= FBINFO_DEFAULT
;
319 drvdata
->info
.var
= xilinx_fb_var
;
320 drvdata
->info
.var
.height
= pdata
->screen_height_mm
;
321 drvdata
->info
.var
.width
= pdata
->screen_width_mm
;
322 drvdata
->info
.var
.xres
= pdata
->xres
;
323 drvdata
->info
.var
.yres
= pdata
->yres
;
324 drvdata
->info
.var
.xres_virtual
= pdata
->xvirt
;
325 drvdata
->info
.var
.yres_virtual
= pdata
->yvirt
;
327 /* Allocate a colour map */
328 rc
= fb_alloc_cmap(&drvdata
->info
.cmap
, PALETTE_ENTRIES_NO
, 0);
330 dev_err(dev
, "Fail to allocate colormap (%d entries)\n",
335 /* Register new frame buffer */
336 rc
= register_framebuffer(&drvdata
->info
);
338 dev_err(dev
, "Could not register frame buffer\n");
342 if (drvdata
->flags
& BUS_ACCESS_FLAG
) {
343 /* Put a banner in the log (for DEBUG) */
344 dev_dbg(dev
, "regs: phys=%x, virt=%p\n", drvdata
->regs_phys
,
347 /* Put a banner in the log (for DEBUG) */
348 dev_dbg(dev
, "fb: phys=%llx, virt=%p, size=%x\n",
349 (unsigned long long)drvdata
->fb_phys
, drvdata
->fb_virt
, fbsize
);
351 return 0; /* success */
354 fb_dealloc_cmap(&drvdata
->info
.cmap
);
357 if (drvdata
->fb_alloced
)
358 dma_free_coherent(dev
, PAGE_ALIGN(fbsize
), drvdata
->fb_virt
,
361 iounmap(drvdata
->fb_virt
);
363 /* Turn off the display */
364 xilinx_fb_out32(drvdata
, REG_CTRL
, 0);
367 if (drvdata
->flags
& BUS_ACCESS_FLAG
)
368 devm_iounmap(dev
, drvdata
->regs
);
372 dev_set_drvdata(dev
, NULL
);
377 static int xilinxfb_release(struct device
*dev
)
379 struct xilinxfb_drvdata
*drvdata
= dev_get_drvdata(dev
);
381 #if !defined(CONFIG_FRAMEBUFFER_CONSOLE) && defined(CONFIG_LOGO)
382 xilinx_fb_blank(VESA_POWERDOWN
, &drvdata
->info
);
385 unregister_framebuffer(&drvdata
->info
);
387 fb_dealloc_cmap(&drvdata
->info
.cmap
);
389 if (drvdata
->fb_alloced
)
390 dma_free_coherent(dev
, PAGE_ALIGN(drvdata
->info
.fix
.smem_len
),
391 drvdata
->fb_virt
, drvdata
->fb_phys
);
393 iounmap(drvdata
->fb_virt
);
395 /* Turn off the display */
396 xilinx_fb_out32(drvdata
, REG_CTRL
, 0);
398 /* Release the resources, as allocated based on interface */
399 if (drvdata
->flags
& BUS_ACCESS_FLAG
)
400 devm_iounmap(dev
, drvdata
->regs
);
401 #ifdef CONFIG_PPC_DCR
403 dcr_unmap(drvdata
->dcr_host
, drvdata
->dcr_len
);
407 dev_set_drvdata(dev
, NULL
);
412 /* ---------------------------------------------------------------------
416 static int xilinxfb_of_probe(struct platform_device
*op
)
420 struct xilinxfb_platform_data pdata
;
422 struct xilinxfb_drvdata
*drvdata
;
424 /* Copy with the default pdata (not a ptr reference!) */
425 pdata
= xilinx_fb_default_pdata
;
427 /* Allocate the driver data region */
428 drvdata
= kzalloc(sizeof(*drvdata
), GFP_KERNEL
);
430 dev_err(&op
->dev
, "Couldn't allocate device private record\n");
435 * To check whether the core is connected directly to DCR or BUS
436 * interface and initialize the tft_access accordingly.
438 of_property_read_u32(op
->dev
.of_node
, "xlnx,dcr-splb-slave-if",
442 * Fill the resource structure if its direct BUS interface
443 * otherwise fill the dcr_host structure.
446 drvdata
->flags
|= BUS_ACCESS_FLAG
;
448 #ifdef CONFIG_PPC_DCR
451 start
= dcr_resource_start(op
->dev
.of_node
, 0);
452 drvdata
->dcr_len
= dcr_resource_len(op
->dev
.of_node
, 0);
453 drvdata
->dcr_host
= dcr_map(op
->dev
.of_node
, start
, drvdata
->dcr_len
);
454 if (!DCR_MAP_OK(drvdata
->dcr_host
)) {
455 dev_err(&op
->dev
, "invalid DCR address\n");
462 prop
= of_get_property(op
->dev
.of_node
, "phys-size", &size
);
463 if ((prop
) && (size
>= sizeof(u32
)*2)) {
464 pdata
.screen_width_mm
= prop
[0];
465 pdata
.screen_height_mm
= prop
[1];
468 prop
= of_get_property(op
->dev
.of_node
, "resolution", &size
);
469 if ((prop
) && (size
>= sizeof(u32
)*2)) {
470 pdata
.xres
= prop
[0];
471 pdata
.yres
= prop
[1];
474 prop
= of_get_property(op
->dev
.of_node
, "virtual-resolution", &size
);
475 if ((prop
) && (size
>= sizeof(u32
)*2)) {
476 pdata
.xvirt
= prop
[0];
477 pdata
.yvirt
= prop
[1];
480 if (of_find_property(op
->dev
.of_node
, "rotate-display", NULL
))
481 pdata
.rotate_screen
= 1;
483 dev_set_drvdata(&op
->dev
, drvdata
);
484 return xilinxfb_assign(op
, drvdata
, &pdata
);
487 static int xilinxfb_of_remove(struct platform_device
*op
)
489 return xilinxfb_release(&op
->dev
);
492 /* Match table for of_platform binding */
493 static struct of_device_id xilinxfb_of_match
[] = {
494 { .compatible
= "xlnx,xps-tft-1.00.a", },
495 { .compatible
= "xlnx,xps-tft-2.00.a", },
496 { .compatible
= "xlnx,xps-tft-2.01.a", },
497 { .compatible
= "xlnx,plb-tft-cntlr-ref-1.00.a", },
498 { .compatible
= "xlnx,plb-dvi-cntlr-ref-1.00.c", },
501 MODULE_DEVICE_TABLE(of
, xilinxfb_of_match
);
503 static struct platform_driver xilinxfb_of_driver
= {
504 .probe
= xilinxfb_of_probe
,
505 .remove
= xilinxfb_of_remove
,
508 .owner
= THIS_MODULE
,
509 .of_match_table
= xilinxfb_of_match
,
513 module_platform_driver(xilinxfb_of_driver
);
515 MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
516 MODULE_DESCRIPTION("Xilinx TFT frame buffer driver");
517 MODULE_LICENSE("GPL");