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Linux 2.6.12-rc6
[cris-mirror.git] / include / sound / cs4231.h
blobd7f90823778aa812fea65515c86aea2eea348d31
1 #ifndef __SOUND_CS4231_H
2 #define __SOUND_CS4231_H
3
4 /*
5 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
6 * Definitions for CS4231 & InterWave chips & compatible chips
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24
25 #include "control.h"
26 #include "pcm.h"
27 #include "timer.h"
28
29 #ifdef CONFIG_SBUS
30 #define SBUS_SUPPORT
31 #include <asm/sbus.h>
32 #endif
33
34 #if defined(CONFIG_PCI) && defined(CONFIG_SPARC64)
35 #define EBUS_SUPPORT
36 #include <linux/pci.h>
37 #include <asm/ebus.h>
38 #endif
39
40 #if !defined(SBUS_SUPPORT) && !defined(EBUS_SUPPORT)
41 #define LEGACY_SUPPORT
42 #endif
43
44 /* IO ports */
45
46 #define CS4231P(x) (c_d_c_CS4231##x)
47
48 #define c_d_c_CS4231REGSEL 0
49 #define c_d_c_CS4231REG 1
50 #define c_d_c_CS4231STATUS 2
51 #define c_d_c_CS4231PIO 3
52
53 /* codec registers */
54
55 #define CS4231_LEFT_INPUT 0x00 /* left input control */
56 #define CS4231_RIGHT_INPUT 0x01 /* right input control */
57 #define CS4231_AUX1_LEFT_INPUT 0x02 /* left AUX1 input control */
58 #define CS4231_AUX1_RIGHT_INPUT 0x03 /* right AUX1 input control */
59 #define CS4231_AUX2_LEFT_INPUT 0x04 /* left AUX2 input control */
60 #define CS4231_AUX2_RIGHT_INPUT 0x05 /* right AUX2 input control */
61 #define CS4231_LEFT_OUTPUT 0x06 /* left output control register */
62 #define CS4231_RIGHT_OUTPUT 0x07 /* right output control register */
63 #define CS4231_PLAYBK_FORMAT 0x08 /* clock and data format - playback - bits 7-0 MCE */
64 #define CS4231_IFACE_CTRL 0x09 /* interface control - bits 7-2 MCE */
65 #define CS4231_PIN_CTRL 0x0a /* pin control */
66 #define CS4231_TEST_INIT 0x0b /* test and initialization */
67 #define CS4231_MISC_INFO 0x0c /* miscellaneaous information */
68 #define CS4231_LOOPBACK 0x0d /* loopback control */
69 #define CS4231_PLY_UPR_CNT 0x0e /* playback upper base count */
70 #define CS4231_PLY_LWR_CNT 0x0f /* playback lower base count */
71 #define CS4231_ALT_FEATURE_1 0x10 /* alternate #1 feature enable */
72 #define AD1845_AF1_MIC_LEFT 0x10 /* alternate #1 feature + MIC left */
73 #define CS4231_ALT_FEATURE_2 0x11 /* alternate #2 feature enable */
74 #define AD1845_AF2_MIC_RIGHT 0x11 /* alternate #2 feature + MIC right */
75 #define CS4231_LEFT_LINE_IN 0x12 /* left line input control */
76 #define CS4231_RIGHT_LINE_IN 0x13 /* right line input control */
77 #define CS4231_TIMER_LOW 0x14 /* timer low byte */
78 #define CS4231_TIMER_HIGH 0x15 /* timer high byte */
79 #define CS4231_LEFT_MIC_INPUT 0x16 /* left MIC input control register (InterWave only) */
80 #define AD1845_UPR_FREQ_SEL 0x16 /* upper byte of frequency select */
81 #define CS4231_RIGHT_MIC_INPUT 0x17 /* right MIC input control register (InterWave only) */
82 #define AD1845_LWR_FREQ_SEL 0x17 /* lower byte of frequency select */
83 #define CS4236_EXT_REG 0x17 /* extended register access */
84 #define CS4231_IRQ_STATUS 0x18 /* irq status register */
85 #define CS4231_LINE_LEFT_OUTPUT 0x19 /* left line output control register (InterWave only) */
86 #define CS4231_VERSION 0x19 /* CS4231(A) - version values */
87 #define CS4231_MONO_CTRL 0x1a /* mono input/output control */
88 #define CS4231_LINE_RIGHT_OUTPUT 0x1b /* right line output control register (InterWave only) */
89 #define AD1845_PWR_DOWN 0x1b /* power down control */
90 #define CS4235_LEFT_MASTER 0x1b /* left master output control */
91 #define CS4231_REC_FORMAT 0x1c /* clock and data format - record - bits 7-0 MCE */
92 #define CS4231_PLY_VAR_FREQ 0x1d /* playback variable frequency */
93 #define AD1845_CLOCK 0x1d /* crystal clock select and total power down */
94 #define CS4235_RIGHT_MASTER 0x1d /* right master output control */
95 #define CS4231_REC_UPR_CNT 0x1e /* record upper count */
96 #define CS4231_REC_LWR_CNT 0x1f /* record lower count */
97
98 /* definitions for codec register select port - CODECP( REGSEL ) */
99
100 #define CS4231_INIT 0x80 /* CODEC is initializing */
101 #define CS4231_MCE 0x40 /* mode change enable */
102 #define CS4231_TRD 0x20 /* transfer request disable */
103
104 /* definitions for codec status register - CODECP( STATUS ) */
105
106 #define CS4231_GLOBALIRQ 0x01 /* IRQ is active */
107
108 /* definitions for codec irq status */
109
110 #define CS4231_PLAYBACK_IRQ 0x10
111 #define CS4231_RECORD_IRQ 0x20
112 #define CS4231_TIMER_IRQ 0x40
113 #define CS4231_ALL_IRQS 0x70
114 #define CS4231_REC_UNDERRUN 0x08
115 #define CS4231_REC_OVERRUN 0x04
116 #define CS4231_PLY_OVERRUN 0x02
117 #define CS4231_PLY_UNDERRUN 0x01
118
119 /* definitions for CS4231_LEFT_INPUT and CS4231_RIGHT_INPUT registers */
120
121 #define CS4231_ENABLE_MIC_GAIN 0x20
122
123 #define CS4231_MIXS_LINE 0x00
124 #define CS4231_MIXS_AUX1 0x40
125 #define CS4231_MIXS_MIC 0x80
126 #define CS4231_MIXS_ALL 0xc0
127
128 /* definitions for clock and data format register - CS4231_PLAYBK_FORMAT */
129
130 #define CS4231_LINEAR_8 0x00 /* 8-bit unsigned data */
131 #define CS4231_ALAW_8 0x60 /* 8-bit A-law companded */
132 #define CS4231_ULAW_8 0x20 /* 8-bit U-law companded */
133 #define CS4231_LINEAR_16 0x40 /* 16-bit twos complement data - little endian */
134 #define CS4231_LINEAR_16_BIG 0xc0 /* 16-bit twos complement data - big endian */
135 #define CS4231_ADPCM_16 0xa0 /* 16-bit ADPCM */
136 #define CS4231_STEREO 0x10 /* stereo mode */
137 /* bits 3-1 define frequency divisor */
138 #define CS4231_XTAL1 0x00 /* 24.576 crystal */
139 #define CS4231_XTAL2 0x01 /* 16.9344 crystal */
140
141 /* definitions for interface control register - CS4231_IFACE_CTRL */
142
143 #define CS4231_RECORD_PIO 0x80 /* record PIO enable */
144 #define CS4231_PLAYBACK_PIO 0x40 /* playback PIO enable */
145 #define CS4231_CALIB_MODE 0x18 /* calibration mode bits */
146 #define CS4231_AUTOCALIB 0x08 /* auto calibrate */
147 #define CS4231_SINGLE_DMA 0x04 /* use single DMA channel */
148 #define CS4231_RECORD_ENABLE 0x02 /* record enable */
149 #define CS4231_PLAYBACK_ENABLE 0x01 /* playback enable */
150
151 /* definitions for pin control register - CS4231_PIN_CTRL */
152
153 #define CS4231_IRQ_ENABLE 0x02 /* enable IRQ */
154 #define CS4231_XCTL1 0x40 /* external control #1 */
155 #define CS4231_XCTL0 0x80 /* external control #0 */
156
157 /* definitions for test and init register - CS4231_TEST_INIT */
158
159 #define CS4231_CALIB_IN_PROGRESS 0x20 /* auto calibrate in progress */
160 #define CS4231_DMA_REQUEST 0x10 /* DMA request in progress */
161
162 /* definitions for misc control register - CS4231_MISC_INFO */
163
164 #define CS4231_MODE2 0x40 /* MODE 2 */
165 #define CS4231_IW_MODE3 0x6c /* MODE 3 - InterWave enhanced mode */
166 #define CS4231_4236_MODE3 0xe0 /* MODE 3 - CS4236+ enhanced mode */
167
168 /* definitions for alternate feature 1 register - CS4231_ALT_FEATURE_1 */
169
170 #define CS4231_DACZ 0x01 /* zero DAC when underrun */
171 #define CS4231_TIMER_ENABLE 0x40 /* codec timer enable */
172 #define CS4231_OLB 0x80 /* output level bit */
173
174 /* definitions for Extended Registers - CS4236+ */
175
176 #define CS4236_REG(i23val) (((i23val << 2) & 0x10) | ((i23val >> 4) & 0x0f))
177 #define CS4236_I23VAL(reg) ((((reg)&0xf) << 4) | (((reg)&0x10) >> 2) | 0x8)
178
179 #define CS4236_LEFT_LINE 0x08 /* left LINE alternate volume */
180 #define CS4236_RIGHT_LINE 0x18 /* right LINE alternate volume */
181 #define CS4236_LEFT_MIC 0x28 /* left MIC volume */
182 #define CS4236_RIGHT_MIC 0x38 /* right MIC volume */
183 #define CS4236_LEFT_MIX_CTRL 0x48 /* synthesis and left input mixer control */
184 #define CS4236_RIGHT_MIX_CTRL 0x58 /* right input mixer control */
185 #define CS4236_LEFT_FM 0x68 /* left FM volume */
186 #define CS4236_RIGHT_FM 0x78 /* right FM volume */
187 #define CS4236_LEFT_DSP 0x88 /* left DSP serial port volume */
188 #define CS4236_RIGHT_DSP 0x98 /* right DSP serial port volume */
189 #define CS4236_RIGHT_LOOPBACK 0xa8 /* right loopback monitor volume */
190 #define CS4236_DAC_MUTE 0xb8 /* DAC mute and IFSE enable */
191 #define CS4236_ADC_RATE 0xc8 /* indenpendent ADC sample frequency */
192 #define CS4236_DAC_RATE 0xd8 /* indenpendent DAC sample frequency */
193 #define CS4236_LEFT_MASTER 0xe8 /* left master digital audio volume */
194 #define CS4236_RIGHT_MASTER 0xf8 /* right master digital audio volume */
195 #define CS4236_LEFT_WAVE 0x0c /* left wavetable serial port volume */
196 #define CS4236_RIGHT_WAVE 0x1c /* right wavetable serial port volume */
197 #define CS4236_VERSION 0x9c /* chip version and ID */
198
199 /* defines for codec.mode */
200
201 #define CS4231_MODE_NONE 0x0000
202 #define CS4231_MODE_PLAY 0x0001
203 #define CS4231_MODE_RECORD 0x0002
204 #define CS4231_MODE_TIMER 0x0004
205 #define CS4231_MODE_OPEN (CS4231_MODE_PLAY|CS4231_MODE_RECORD|CS4231_MODE_TIMER)
206
207 /* defines for codec.hardware */
208
209 #define CS4231_HW_DETECT 0x0000 /* let CS4231 driver detect chip */
210 #define CS4231_HW_DETECT3 0x0001 /* allow mode 3 */
211 #define CS4231_HW_TYPE_MASK 0xff00 /* type mask */
212 #define CS4231_HW_CS4231_MASK 0x0100 /* CS4231 serie */
213 #define CS4231_HW_CS4231 0x0100 /* CS4231 chip */
214 #define CS4231_HW_CS4231A 0x0101 /* CS4231A chip */
215 #define CS4231_HW_AD1845 0x0102 /* AD1845 chip */
216 #define CS4231_HW_CS4232_MASK 0x0200 /* CS4232 serie (has control ports) */
217 #define CS4231_HW_CS4232 0x0200 /* CS4232 */
218 #define CS4231_HW_CS4232A 0x0201 /* CS4232A */
219 #define CS4231_HW_CS4236 0x0202 /* CS4236 */
220 #define CS4231_HW_CS4236B_MASK 0x0400 /* CS4236B serie (has extended control regs) */
221 #define CS4231_HW_CS4235 0x0400 /* CS4235 - Crystal Clear (tm) stereo enhancement */
222 #define CS4231_HW_CS4236B 0x0401 /* CS4236B */
223 #define CS4231_HW_CS4237B 0x0402 /* CS4237B - SRS 3D */
224 #define CS4231_HW_CS4238B 0x0403 /* CS4238B - QSOUND 3D */
225 #define CS4231_HW_CS4239 0x0404 /* CS4239 - Crystal Clear (tm) stereo enhancement */
226 /* compatible, but clones */
227 #define CS4231_HW_INTERWAVE 0x1000 /* InterWave chip */
228 #define CS4231_HW_OPL3SA2 0x1001 /* OPL3-SA2 chip */
229
230 /* defines for codec.hwshare */
231 #define CS4231_HWSHARE_IRQ (1<<0)
232 #define CS4231_HWSHARE_DMA1 (1<<1)
233 #define CS4231_HWSHARE_DMA2 (1<<2)
234
235 typedef struct _snd_cs4231 cs4231_t;
236
237 struct _snd_cs4231 {
238 unsigned long port; /* base i/o port */
239 #ifdef LEGACY_SUPPORT
240 struct resource *res_port;
241 unsigned long cport; /* control base i/o port (CS4236) */
242 struct resource *res_cport;
243 int irq; /* IRQ line */
244 int dma1; /* playback DMA */
245 int dma2; /* record DMA */
246 #endif
247 unsigned short version; /* version of CODEC chip */
248 unsigned short mode; /* see to CS4231_MODE_XXXX */
249 unsigned short hardware; /* see to CS4231_HW_XXXX */
250 unsigned short hwshare; /* shared resources */
251 unsigned short single_dma:1, /* forced single DMA mode (GUS 16-bit daughter board) or dma1 == dma2 */
252 ebus_flag:1; /* SPARC: EBUS present */
253
254 #ifdef EBUS_SUPPORT
255 struct ebus_dma_info eb2c;
256 struct ebus_dma_info eb2p;
257 #endif
258
259 #if defined(SBUS_SUPPORT) || defined(EBUS_SUPPORT)
260 union {
261 #ifdef SBUS_SUPPORT
262 struct sbus_dev *sdev;
263 #endif
264 #ifdef EBUS_SUPPORT
265 struct pci_dev *pdev;
266 #endif
267 } dev_u;
268 unsigned int p_periods_sent;
269 unsigned int c_periods_sent;
270 #endif
271
272 snd_card_t *card;
273 snd_pcm_t *pcm;
274 snd_pcm_substream_t *playback_substream;
275 snd_pcm_substream_t *capture_substream;
276 snd_timer_t *timer;
277
278 unsigned char image[32]; /* registers image */
279 unsigned char eimage[32]; /* extended registers image */
280 unsigned char cimage[16]; /* control registers image */
281 int mce_bit;
282 int calibrate_mute;
283 int sw_3d_bit;
284 #ifdef LEGACY_SUPPORT
285 unsigned int p_dma_size;
286 unsigned int c_dma_size;
287 #endif
288
289 spinlock_t reg_lock;
290 struct semaphore mce_mutex;
291 struct semaphore open_mutex;
292
293 int (*rate_constraint) (snd_pcm_runtime_t *runtime);
294 void (*set_playback_format) (cs4231_t *chip, snd_pcm_hw_params_t *hw_params, unsigned char pdfr);
295 void (*set_capture_format) (cs4231_t *chip, snd_pcm_hw_params_t *hw_params, unsigned char cdfr);
296 void (*trigger) (cs4231_t *chip, unsigned int what, int start);
297 #ifdef CONFIG_PM
298 void (*suspend) (cs4231_t *chip);
299 void (*resume) (cs4231_t *chip);
300 #endif
301 void *dma_private_data;
302 #ifdef LEGACY_SUPPORT
303 int (*claim_dma) (cs4231_t *chip, void *dma_private_data, int dma);
304 int (*release_dma) (cs4231_t *chip, void *dma_private_data, int dma);
305 #endif
306 };
307
308 /* exported functions */
309
310 void snd_cs4231_out(cs4231_t *chip, unsigned char reg, unsigned char val);
311 unsigned char snd_cs4231_in(cs4231_t *chip, unsigned char reg);
312 void snd_cs4236_ext_out(cs4231_t *chip, unsigned char reg, unsigned char val);
313 unsigned char snd_cs4236_ext_in(cs4231_t *chip, unsigned char reg);
314 void snd_cs4231_mce_up(cs4231_t *chip);
315 void snd_cs4231_mce_down(cs4231_t *chip);
316
317 irqreturn_t snd_cs4231_interrupt(int irq, void *dev_id, struct pt_regs *regs);
318
319 const char *snd_cs4231_chip_id(cs4231_t *chip);
320
321 int snd_cs4231_create(snd_card_t * card,
322 unsigned long port,
323 unsigned long cport,
324 int irq, int dma1, int dma2,
325 unsigned short hardware,
326 unsigned short hwshare,
327 cs4231_t ** rchip);
328 int snd_cs4231_pcm(cs4231_t * chip, int device, snd_pcm_t **rpcm);
329 int snd_cs4231_timer(cs4231_t * chip, int device, snd_timer_t **rtimer);
330 int snd_cs4231_mixer(cs4231_t * chip);
331
332 int snd_cs4236_create(snd_card_t * card,
333 unsigned long port,
334 unsigned long cport,
335 int irq, int dma1, int dma2,
336 unsigned short hardware,
337 unsigned short hwshare,
338 cs4231_t ** rchip);
339 int snd_cs4236_pcm(cs4231_t * chip, int device, snd_pcm_t **rpcm);
340 int snd_cs4236_mixer(cs4231_t * chip);
341
342 /*
343 * mixer library
344 */
345
346 #define CS4231_SINGLE(xname, xindex, reg, shift, mask, invert) \
347 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
348 .info = snd_cs4231_info_single, \
349 .get = snd_cs4231_get_single, .put = snd_cs4231_put_single, \
350 .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24) }
351
352 int snd_cs4231_info_single(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo);
353 int snd_cs4231_get_single(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol);
354 int snd_cs4231_put_single(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol);
355
356 #define CS4231_DOUBLE(xname, xindex, left_reg, right_reg, shift_left, shift_right, mask, invert) \
357 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
358 .info = snd_cs4231_info_double, \
359 .get = snd_cs4231_get_double, .put = snd_cs4231_put_double, \
360 .private_value = left_reg | (right_reg << 8) | (shift_left << 16) | (shift_right << 19) | (mask << 24) | (invert << 22) }
361
362 int snd_cs4231_info_double(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo);
363 int snd_cs4231_get_double(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol);
364 int snd_cs4231_put_double(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol);
365
366 #endif /* __SOUND_CS4231_H */
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