arch/parisc/kernel/irq.c

   1 /*
   2  * Code to handle x86 style IRQs plus some generic interrupt stuff.
   3  *
   4  * Copyright (C) 1992 Linus Torvalds
   5  * Copyright (C) 1994, 1995, 1996, 1997, 1998 Ralf Baechle
   6  * Copyright (C) 1999 SuSE GmbH (Philipp Rumpf, prumpf@tux.org)
   7  * Copyright (C) 1999-2000 Grant Grundler
   8  * Copyright (c) 2005 Matthew Wilcox
   9  *
  10  *    This program is free software; you can redistribute it and/or modify
  11  *    it under the terms of the GNU General Public License as published by
  12  *    the Free Software Foundation; either version 2, or (at your option)
  13  *    any later version.
  14  *
  15  *    This program is distributed in the hope that it will be useful,
  16  *    but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *    GNU General Public License for more details.
  19  *
  20  *    You should have received a copy of the GNU General Public License
  21  *    along with this program; if not, write to the Free Software
  22  *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  23  */
  24 #include <linux/bitops.h>
  25 #include <linux/errno.h>
  26 #include <linux/init.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/kernel_stat.h>
  29 #include <linux/seq_file.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/types.h>
  32 #include <asm/io.h>
  33
  34 #include <asm/smp.h>
  35
  36 #undef PARISC_IRQ_CR16_COUNTS
  37
  38 extern irqreturn_t timer_interrupt(int, void *);
  39 extern irqreturn_t ipi_interrupt(int, void *);
  40
  41 #define EIEM_MASK(irq)       (1UL<<(CPU_IRQ_MAX - irq))
  42
  43 /* Bits in EIEM correlate with cpu_irq_action[].
  44 ** Numbered *Big Endian*! (ie bit 0 is MSB)
  45 */
  46 static volatile unsigned long cpu_eiem = 0;
  47
  48 /*
  49 ** local ACK bitmap ... habitually set to 1, but reset to zero
  50 ** between ->ack() and ->end() of the interrupt to prevent
  51 ** re-interruption of a processing interrupt.
  52 */
  53 static DEFINE_PER_CPU(unsigned long, local_ack_eiem) = ~0UL;
  54
  55 static void cpu_mask_irq(struct irq_data *d)
  56 {
  57         unsigned long eirr_bit = EIEM_MASK(d->irq);
  58
  59         cpu_eiem &= ~eirr_bit;
  60         /* Do nothing on the other CPUs.  If they get this interrupt,
  61          * The & cpu_eiem in the do_cpu_irq_mask() ensures they won't
  62          * handle it, and the set_eiem() at the bottom will ensure it
  63          * then gets disabled */
  64 }
  65
  66 static void __cpu_unmask_irq(unsigned int irq)
  67 {
  68         unsigned long eirr_bit = EIEM_MASK(irq);
  69
  70         cpu_eiem |= eirr_bit;
  71
  72         /* This is just a simple NOP IPI.  But what it does is cause
  73          * all the other CPUs to do a set_eiem(cpu_eiem) at the end
  74          * of the interrupt handler */
  75         smp_send_all_nop();
  76 }
  77
  78 static void cpu_unmask_irq(struct irq_data *d)
  79 {
  80         __cpu_unmask_irq(d->irq);
  81 }
  82
  83 void cpu_ack_irq(struct irq_data *d)
  84 {
  85         unsigned long mask = EIEM_MASK(d->irq);
  86         int cpu = smp_processor_id();
  87
  88         /* Clear in EIEM so we can no longer process */
  89         per_cpu(local_ack_eiem, cpu) &= ~mask;
  90
  91         /* disable the interrupt */
  92         set_eiem(cpu_eiem & per_cpu(local_ack_eiem, cpu));
  93
  94         /* and now ack it */
  95         mtctl(mask, 23);
  96 }
  97
  98 void cpu_eoi_irq(struct irq_data *d)
  99 {
 100         unsigned long mask = EIEM_MASK(d->irq);
 101         int cpu = smp_processor_id();
 102
 103         /* set it in the eiems---it's no longer in process */
 104         per_cpu(local_ack_eiem, cpu) |= mask;
 105
 106         /* enable the interrupt */
 107         set_eiem(cpu_eiem & per_cpu(local_ack_eiem, cpu));
 108 }
 109
 110 #ifdef CONFIG_SMP
 111 int cpu_check_affinity(struct irq_data *d, const struct cpumask *dest)
 112 {
 113         int cpu_dest;
 114
 115         /* timer and ipi have to always be received on all CPUs */
 116         if (irqd_is_per_cpu(d))
 117                 return -EINVAL;
 118
 119         /* whatever mask they set, we just allow one CPU */
 120         cpu_dest = first_cpu(*dest);
 121
 122         return cpu_dest;
 123 }
 124
 125 static int cpu_set_affinity_irq(struct irq_data *d, const struct cpumask *dest,
 126                                 bool force)
 127 {
 128         int cpu_dest;
 129
 130         cpu_dest = cpu_check_affinity(d, dest);
 131         if (cpu_dest < 0)
 132                 return -1;
 133
 134         cpumask_copy(d->affinity, dest);
 135
 136         return 0;
 137 }
 138 #endif
 139
 140 static struct irq_chip cpu_interrupt_type = {
 141         .name                   = "CPU",
 142         .irq_mask               = cpu_mask_irq,
 143         .irq_unmask             = cpu_unmask_irq,
 144         .irq_ack                = cpu_ack_irq,
 145         .irq_eoi                = cpu_eoi_irq,
 146 #ifdef CONFIG_SMP
 147         .irq_set_affinity       = cpu_set_affinity_irq,
 148 #endif
 149         /* XXX: Needs to be written.  We managed without it so far, but
 150          * we really ought to write it.
 151          */
 152         .irq_retrigger  = NULL,
 153 };
 154
 155 int show_interrupts(struct seq_file *p, void *v)
 156 {
 157         int i = *(loff_t *) v, j;
 158         unsigned long flags;
 159
 160         if (i == 0) {
 161                 seq_puts(p, "    ");
 162                 for_each_online_cpu(j)
 163                         seq_printf(p, "       CPU%d", j);
 164
 165 #ifdef PARISC_IRQ_CR16_COUNTS
 166                 seq_printf(p, " [min/avg/max] (CPU cycle counts)");
 167 #endif
 168                 seq_putc(p, '\n');
 169         }
 170
 171         if (i < NR_IRQS) {
 172                 struct irq_desc *desc = irq_to_desc(i);
 173                 struct irqaction *action;
 174
 175                 raw_spin_lock_irqsave(&desc->lock, flags);
 176                 action = desc->action;
 177                 if (!action)
 178                         goto skip;
 179                 seq_printf(p, "%3d: ", i);
 180 #ifdef CONFIG_SMP
 181                 for_each_online_cpu(j)
 182                         seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
 183 #else
 184                 seq_printf(p, "%10u ", kstat_irqs(i));
 185 #endif
 186
 187                 seq_printf(p, " %14s", irq_desc_get_chip(desc)->name);
 188 #ifndef PARISC_IRQ_CR16_COUNTS
 189                 seq_printf(p, "  %s", action->name);
 190
 191                 while ((action = action->next))
 192                         seq_printf(p, ", %s", action->name);
 193 #else
 194                 for ( ;action; action = action->next) {
 195                         unsigned int k, avg, min, max;
 196
 197                         min = max = action->cr16_hist[0];
 198
 199                         for (avg = k = 0; k < PARISC_CR16_HIST_SIZE; k++) {
 200                                 int hist = action->cr16_hist[k];
 201
 202                                 if (hist) {
 203                                         avg += hist;
 204                                 } else
 205                                         break;
 206
 207                                 if (hist > max) max = hist;
 208                                 if (hist < min) min = hist;
 209                         }
 210
 211                         avg /= k;
 212                         seq_printf(p, " %s[%d/%d/%d]", action->name,
 213                                         min,avg,max);
 214                 }
 215 #endif
 216
 217                 seq_putc(p, '\n');
 218  skip:
 219                 raw_spin_unlock_irqrestore(&desc->lock, flags);
 220         }
 221
 222         return 0;
 223 }
 224
 225
 226
 227 /*
 228 ** The following form a "set": Virtual IRQ, Transaction Address, Trans Data.
 229 ** Respectively, these map to IRQ region+EIRR, Processor HPA, EIRR bit.
 230 **
 231 ** To use txn_XXX() interfaces, get a Virtual IRQ first.
 232 ** Then use that to get the Transaction address and data.
 233 */
 234
 235 int cpu_claim_irq(unsigned int irq, struct irq_chip *type, void *data)
 236 {
 237         if (irq_has_action(irq))
 238                 return -EBUSY;
 239         if (irq_get_chip(irq) != &cpu_interrupt_type)
 240                 return -EBUSY;
 241
 242         /* for iosapic interrupts */
 243         if (type) {
 244                 irq_set_chip_and_handler(irq, type, handle_percpu_irq);
 245                 irq_set_chip_data(irq, data);
 246                 __cpu_unmask_irq(irq);
 247         }
 248         return 0;
 249 }
 250
 251 int txn_claim_irq(int irq)
 252 {
 253         return cpu_claim_irq(irq, NULL, NULL) ? -1 : irq;
 254 }
 255
 256 /*
 257  * The bits_wide parameter accommodates the limitations of the HW/SW which
 258  * use these bits:
 259  * Legacy PA I/O (GSC/NIO): 5 bits (architected EIM register)
 260  * V-class (EPIC):          6 bits
 261  * N/L/A-class (iosapic):   8 bits
 262  * PCI 2.2 MSI:            16 bits
 263  * Some PCI devices:       32 bits (Symbios SCSI/ATM/HyperFabric)
 264  *
 265  * On the service provider side:
 266  * o PA 1.1 (and PA2.0 narrow mode)     5-bits (width of EIR register)
 267  * o PA 2.0 wide mode                   6-bits (per processor)
 268  * o IA64                               8-bits (0-256 total)
 269  *
 270  * So a Legacy PA I/O device on a PA 2.0 box can't use all the bits supported
 271  * by the processor...and the N/L-class I/O subsystem supports more bits than
 272  * PA2.0 has. The first case is the problem.
 273  */
 274 int txn_alloc_irq(unsigned int bits_wide)
 275 {
 276         int irq;
 277
 278         /* never return irq 0 cause that's the interval timer */
 279         for (irq = CPU_IRQ_BASE + 1; irq <= CPU_IRQ_MAX; irq++) {
 280                 if (cpu_claim_irq(irq, NULL, NULL) < 0)
 281                         continue;
 282                 if ((irq - CPU_IRQ_BASE) >= (1 << bits_wide))
 283                         continue;
 284                 return irq;
 285         }
 286
 287         /* unlikely, but be prepared */
 288         return -1;
 289 }
 290
 291
 292 unsigned long txn_affinity_addr(unsigned int irq, int cpu)
 293 {
 294 #ifdef CONFIG_SMP
 295         struct irq_data *d = irq_get_irq_data(irq);
 296         cpumask_copy(d->affinity, cpumask_of(cpu));
 297 #endif
 298
 299         return per_cpu(cpu_data, cpu).txn_addr;
 300 }
 301
 302
 303 unsigned long txn_alloc_addr(unsigned int virt_irq)
 304 {
 305         static int next_cpu = -1;
 306
 307         next_cpu++; /* assign to "next" CPU we want this bugger on */
 308
 309         /* validate entry */
 310         while ((next_cpu < nr_cpu_ids) &&
 311                 (!per_cpu(cpu_data, next_cpu).txn_addr ||
 312                  !cpu_online(next_cpu)))
 313                 next_cpu++;
 314
 315         if (next_cpu >= nr_cpu_ids)
 316                 next_cpu = 0;   /* nothing else, assign monarch */
 317
 318         return txn_affinity_addr(virt_irq, next_cpu);
 319 }
 320
 321
 322 unsigned int txn_alloc_data(unsigned int virt_irq)
 323 {
 324         return virt_irq - CPU_IRQ_BASE;
 325 }
 326
 327 static inline int eirr_to_irq(unsigned long eirr)
 328 {
 329         int bit = fls_long(eirr);
 330         return (BITS_PER_LONG - bit) + TIMER_IRQ;
 331 }
 332
 333 /* ONLY called from entry.S:intr_extint() */
 334 void do_cpu_irq_mask(struct pt_regs *regs)
 335 {
 336         struct pt_regs *old_regs;
 337         unsigned long eirr_val;
 338         int irq, cpu = smp_processor_id();
 339 #ifdef CONFIG_SMP
 340         struct irq_desc *desc;
 341         cpumask_t dest;
 342 #endif
 343
 344         old_regs = set_irq_regs(regs);
 345         local_irq_disable();
 346         irq_enter();
 347
 348         eirr_val = mfctl(23) & cpu_eiem & per_cpu(local_ack_eiem, cpu);
 349         if (!eirr_val)
 350                 goto set_out;
 351         irq = eirr_to_irq(eirr_val);
 352
 353 #ifdef CONFIG_SMP
 354         desc = irq_to_desc(irq);
 355         cpumask_copy(&dest, desc->irq_data.affinity);
 356         if (irqd_is_per_cpu(&desc->irq_data) &&
 357             !cpu_isset(smp_processor_id(), dest)) {
 358                 int cpu = first_cpu(dest);
 359
 360                 printk(KERN_DEBUG "redirecting irq %d from CPU %d to %d\n",
 361                        irq, smp_processor_id(), cpu);
 362                 gsc_writel(irq + CPU_IRQ_BASE,
 363                            per_cpu(cpu_data, cpu).hpa);
 364                 goto set_out;
 365         }
 366 #endif
 367         generic_handle_irq(irq);
 368
 369  out:
 370         irq_exit();
 371         set_irq_regs(old_regs);
 372         return;
 373
 374  set_out:
 375         set_eiem(cpu_eiem & per_cpu(local_ack_eiem, cpu));
 376         goto out;
 377 }
 378
 379 static struct irqaction timer_action = {
 380         .handler = timer_interrupt,
 381         .name = "timer",
 382         .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_PERCPU | IRQF_IRQPOLL,
 383 };
 384
 385 #ifdef CONFIG_SMP
 386 static struct irqaction ipi_action = {
 387         .handler = ipi_interrupt,
 388         .name = "IPI",
 389         .flags = IRQF_DISABLED | IRQF_PERCPU,
 390 };
 391 #endif
 392
 393 static void claim_cpu_irqs(void)
 394 {
 395         int i;
 396         for (i = CPU_IRQ_BASE; i <= CPU_IRQ_MAX; i++) {
 397                 irq_set_chip_and_handler(i, &cpu_interrupt_type,
 398                                          handle_percpu_irq);
 399         }
 400
 401         irq_set_handler(TIMER_IRQ, handle_percpu_irq);
 402         setup_irq(TIMER_IRQ, &timer_action);
 403 #ifdef CONFIG_SMP
 404         irq_set_handler(IPI_IRQ, handle_percpu_irq);
 405         setup_irq(IPI_IRQ, &ipi_action);
 406 #endif
 407 }
 408
 409 void __init init_IRQ(void)
 410 {
 411         local_irq_disable();    /* PARANOID - should already be disabled */
 412         mtctl(~0UL, 23);        /* EIRR : clear all pending external intr */
 413 #ifdef CONFIG_SMP
 414         if (!cpu_eiem) {
 415                 claim_cpu_irqs();
 416                 cpu_eiem = EIEM_MASK(IPI_IRQ) | EIEM_MASK(TIMER_IRQ);
 417         }
 418 #else
 419         claim_cpu_irqs();
 420         cpu_eiem = EIEM_MASK(TIMER_IRQ);
 421 #endif
 422         set_eiem(cpu_eiem);     /* EIEM : enable all external intr */
 423
 424 }
 425