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Linux 3.8-rc7
[cris-mirror.git] / arch / x86 / kernel / cpu / perf_event_intel.c
blob4914e94ad6e86a9565420dcac8d014ff679ab6fa
1 /*
2 * Per core/cpu state
3 *
4 * Used to coordinate shared registers between HT threads or
5 * among events on a single PMU.
6 */
7
8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9
10 #include <linux/stddef.h>
11 #include <linux/types.h>
12 #include <linux/init.h>
13 #include <linux/slab.h>
14 #include <linux/export.h>
15
16 #include <asm/hardirq.h>
17 #include <asm/apic.h>
18
19 #include "perf_event.h"
20
21 /*
22 * Intel PerfMon, used on Core and later.
23 */
24 static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =
25 {
26 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c,
27 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
28 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e,
29 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e,
30 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
31 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
32 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c,
33 [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */
34 };
35
36 static struct event_constraint intel_core_event_constraints[] __read_mostly =
37 {
38 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
39 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
40 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
41 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
42 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
43 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
44 EVENT_CONSTRAINT_END
45 };
46
47 static struct event_constraint intel_core2_event_constraints[] __read_mostly =
48 {
49 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
50 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
51 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
52 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
53 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
54 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
55 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
56 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
57 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
58 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
59 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
60 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
61 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
62 EVENT_CONSTRAINT_END
63 };
64
65 static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
66 {
67 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
68 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
69 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
70 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
71 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
72 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
73 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
74 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
75 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
76 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
77 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
78 EVENT_CONSTRAINT_END
79 };
80
81 static struct extra_reg intel_nehalem_extra_regs[] __read_mostly =
82 {
83 INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
84 EVENT_EXTRA_END
85 };
86
87 static struct event_constraint intel_westmere_event_constraints[] __read_mostly =
88 {
89 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
90 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
91 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
92 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
93 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
94 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
95 INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */
96 EVENT_CONSTRAINT_END
97 };
98
99 static struct event_constraint intel_snb_event_constraints[] __read_mostly =
100 {
101 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
102 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
103 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
104 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
105 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
106 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
107 EVENT_CONSTRAINT_END
108 };
109
110 static struct extra_reg intel_westmere_extra_regs[] __read_mostly =
111 {
112 INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
113 INTEL_EVENT_EXTRA_REG(0xbb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1),
114 EVENT_EXTRA_END
115 };
116
117 static struct event_constraint intel_v1_event_constraints[] __read_mostly =
118 {
119 EVENT_CONSTRAINT_END
120 };
121
122 static struct event_constraint intel_gen_event_constraints[] __read_mostly =
123 {
124 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
125 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
126 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
127 EVENT_CONSTRAINT_END
128 };
129
130 static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
131 INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0),
132 INTEL_EVENT_EXTRA_REG(0xbb, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1),
133 EVENT_EXTRA_END
134 };
135
136 static u64 intel_pmu_event_map(int hw_event)
137 {
138 return intel_perfmon_event_map[hw_event];
139 }
140
141 #define SNB_DMND_DATA_RD (1ULL << 0)
142 #define SNB_DMND_RFO (1ULL << 1)
143 #define SNB_DMND_IFETCH (1ULL << 2)
144 #define SNB_DMND_WB (1ULL << 3)
145 #define SNB_PF_DATA_RD (1ULL << 4)
146 #define SNB_PF_RFO (1ULL << 5)
147 #define SNB_PF_IFETCH (1ULL << 6)
148 #define SNB_LLC_DATA_RD (1ULL << 7)
149 #define SNB_LLC_RFO (1ULL << 8)
150 #define SNB_LLC_IFETCH (1ULL << 9)
151 #define SNB_BUS_LOCKS (1ULL << 10)
152 #define SNB_STRM_ST (1ULL << 11)
153 #define SNB_OTHER (1ULL << 15)
154 #define SNB_RESP_ANY (1ULL << 16)
155 #define SNB_NO_SUPP (1ULL << 17)
156 #define SNB_LLC_HITM (1ULL << 18)
157 #define SNB_LLC_HITE (1ULL << 19)
158 #define SNB_LLC_HITS (1ULL << 20)
159 #define SNB_LLC_HITF (1ULL << 21)
160 #define SNB_LOCAL (1ULL << 22)
161 #define SNB_REMOTE (0xffULL << 23)
162 #define SNB_SNP_NONE (1ULL << 31)
163 #define SNB_SNP_NOT_NEEDED (1ULL << 32)
164 #define SNB_SNP_MISS (1ULL << 33)
165 #define SNB_NO_FWD (1ULL << 34)
166 #define SNB_SNP_FWD (1ULL << 35)
167 #define SNB_HITM (1ULL << 36)
168 #define SNB_NON_DRAM (1ULL << 37)
169
170 #define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD)
171 #define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO)
172 #define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
173
174 #define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \
175 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \
176 SNB_HITM)
177
178 #define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY)
179 #define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY)
180
181 #define SNB_L3_ACCESS SNB_RESP_ANY
182 #define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM)
183
184 static __initconst const u64 snb_hw_cache_extra_regs
185 [PERF_COUNT_HW_CACHE_MAX]
186 [PERF_COUNT_HW_CACHE_OP_MAX]
187 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
188 {
189 [ C(LL ) ] = {
190 [ C(OP_READ) ] = {
191 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
192 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS,
193 },
194 [ C(OP_WRITE) ] = {
195 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
196 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS,
197 },
198 [ C(OP_PREFETCH) ] = {
199 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
200 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
201 },
202 },
203 [ C(NODE) ] = {
204 [ C(OP_READ) ] = {
205 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY,
206 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE,
207 },
208 [ C(OP_WRITE) ] = {
209 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY,
210 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE,
211 },
212 [ C(OP_PREFETCH) ] = {
213 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY,
214 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE,
215 },
216 },
217 };
218
219 static __initconst const u64 snb_hw_cache_event_ids
220 [PERF_COUNT_HW_CACHE_MAX]
221 [PERF_COUNT_HW_CACHE_OP_MAX]
222 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
223 {
224 [ C(L1D) ] = {
225 [ C(OP_READ) ] = {
226 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */
227 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */
228 },
229 [ C(OP_WRITE) ] = {
230 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */
231 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */
232 },
233 [ C(OP_PREFETCH) ] = {
234 [ C(RESULT_ACCESS) ] = 0x0,
235 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */
236 },
237 },
238 [ C(L1I ) ] = {
239 [ C(OP_READ) ] = {
240 [ C(RESULT_ACCESS) ] = 0x0,
241 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */
242 },
243 [ C(OP_WRITE) ] = {
244 [ C(RESULT_ACCESS) ] = -1,
245 [ C(RESULT_MISS) ] = -1,
246 },
247 [ C(OP_PREFETCH) ] = {
248 [ C(RESULT_ACCESS) ] = 0x0,
249 [ C(RESULT_MISS) ] = 0x0,
250 },
251 },
252 [ C(LL ) ] = {
253 [ C(OP_READ) ] = {
254 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
255 [ C(RESULT_ACCESS) ] = 0x01b7,
256 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
257 [ C(RESULT_MISS) ] = 0x01b7,
258 },
259 [ C(OP_WRITE) ] = {
260 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
261 [ C(RESULT_ACCESS) ] = 0x01b7,
262 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
263 [ C(RESULT_MISS) ] = 0x01b7,
264 },
265 [ C(OP_PREFETCH) ] = {
266 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
267 [ C(RESULT_ACCESS) ] = 0x01b7,
268 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
269 [ C(RESULT_MISS) ] = 0x01b7,
270 },
271 },
272 [ C(DTLB) ] = {
273 [ C(OP_READ) ] = {
274 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
275 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
276 },
277 [ C(OP_WRITE) ] = {
278 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
279 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
280 },
281 [ C(OP_PREFETCH) ] = {
282 [ C(RESULT_ACCESS) ] = 0x0,
283 [ C(RESULT_MISS) ] = 0x0,
284 },
285 },
286 [ C(ITLB) ] = {
287 [ C(OP_READ) ] = {
288 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */
289 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */
290 },
291 [ C(OP_WRITE) ] = {
292 [ C(RESULT_ACCESS) ] = -1,
293 [ C(RESULT_MISS) ] = -1,
294 },
295 [ C(OP_PREFETCH) ] = {
296 [ C(RESULT_ACCESS) ] = -1,
297 [ C(RESULT_MISS) ] = -1,
298 },
299 },
300 [ C(BPU ) ] = {
301 [ C(OP_READ) ] = {
302 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
303 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
304 },
305 [ C(OP_WRITE) ] = {
306 [ C(RESULT_ACCESS) ] = -1,
307 [ C(RESULT_MISS) ] = -1,
308 },
309 [ C(OP_PREFETCH) ] = {
310 [ C(RESULT_ACCESS) ] = -1,
311 [ C(RESULT_MISS) ] = -1,
312 },
313 },
314 [ C(NODE) ] = {
315 [ C(OP_READ) ] = {
316 [ C(RESULT_ACCESS) ] = 0x01b7,
317 [ C(RESULT_MISS) ] = 0x01b7,
318 },
319 [ C(OP_WRITE) ] = {
320 [ C(RESULT_ACCESS) ] = 0x01b7,
321 [ C(RESULT_MISS) ] = 0x01b7,
322 },
323 [ C(OP_PREFETCH) ] = {
324 [ C(RESULT_ACCESS) ] = 0x01b7,
325 [ C(RESULT_MISS) ] = 0x01b7,
326 },
327 },
328
329 };
330
331 static __initconst const u64 westmere_hw_cache_event_ids
332 [PERF_COUNT_HW_CACHE_MAX]
333 [PERF_COUNT_HW_CACHE_OP_MAX]
334 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
335 {
336 [ C(L1D) ] = {
337 [ C(OP_READ) ] = {
338 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
339 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
340 },
341 [ C(OP_WRITE) ] = {
342 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
343 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
344 },
345 [ C(OP_PREFETCH) ] = {
346 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
347 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
348 },
349 },
350 [ C(L1I ) ] = {
351 [ C(OP_READ) ] = {
352 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
353 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
354 },
355 [ C(OP_WRITE) ] = {
356 [ C(RESULT_ACCESS) ] = -1,
357 [ C(RESULT_MISS) ] = -1,
358 },
359 [ C(OP_PREFETCH) ] = {
360 [ C(RESULT_ACCESS) ] = 0x0,
361 [ C(RESULT_MISS) ] = 0x0,
362 },
363 },
364 [ C(LL ) ] = {
365 [ C(OP_READ) ] = {
366 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
367 [ C(RESULT_ACCESS) ] = 0x01b7,
368 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
369 [ C(RESULT_MISS) ] = 0x01b7,
370 },
371 /*
372 * Use RFO, not WRITEBACK, because a write miss would typically occur
373 * on RFO.
374 */
375 [ C(OP_WRITE) ] = {
376 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
377 [ C(RESULT_ACCESS) ] = 0x01b7,
378 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
379 [ C(RESULT_MISS) ] = 0x01b7,
380 },
381 [ C(OP_PREFETCH) ] = {
382 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
383 [ C(RESULT_ACCESS) ] = 0x01b7,
384 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
385 [ C(RESULT_MISS) ] = 0x01b7,
386 },
387 },
388 [ C(DTLB) ] = {
389 [ C(OP_READ) ] = {
390 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
391 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
392 },
393 [ C(OP_WRITE) ] = {
394 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
395 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
396 },
397 [ C(OP_PREFETCH) ] = {
398 [ C(RESULT_ACCESS) ] = 0x0,
399 [ C(RESULT_MISS) ] = 0x0,
400 },
401 },
402 [ C(ITLB) ] = {
403 [ C(OP_READ) ] = {
404 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
405 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */
406 },
407 [ C(OP_WRITE) ] = {
408 [ C(RESULT_ACCESS) ] = -1,
409 [ C(RESULT_MISS) ] = -1,
410 },
411 [ C(OP_PREFETCH) ] = {
412 [ C(RESULT_ACCESS) ] = -1,
413 [ C(RESULT_MISS) ] = -1,
414 },
415 },
416 [ C(BPU ) ] = {
417 [ C(OP_READ) ] = {
418 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
419 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
420 },
421 [ C(OP_WRITE) ] = {
422 [ C(RESULT_ACCESS) ] = -1,
423 [ C(RESULT_MISS) ] = -1,
424 },
425 [ C(OP_PREFETCH) ] = {
426 [ C(RESULT_ACCESS) ] = -1,
427 [ C(RESULT_MISS) ] = -1,
428 },
429 },
430 [ C(NODE) ] = {
431 [ C(OP_READ) ] = {
432 [ C(RESULT_ACCESS) ] = 0x01b7,
433 [ C(RESULT_MISS) ] = 0x01b7,
434 },
435 [ C(OP_WRITE) ] = {
436 [ C(RESULT_ACCESS) ] = 0x01b7,
437 [ C(RESULT_MISS) ] = 0x01b7,
438 },
439 [ C(OP_PREFETCH) ] = {
440 [ C(RESULT_ACCESS) ] = 0x01b7,
441 [ C(RESULT_MISS) ] = 0x01b7,
442 },
443 },
444 };
445
446 /*
447 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits;
448 * See IA32 SDM Vol 3B 30.6.1.3
449 */
450
451 #define NHM_DMND_DATA_RD (1 << 0)
452 #define NHM_DMND_RFO (1 << 1)
453 #define NHM_DMND_IFETCH (1 << 2)
454 #define NHM_DMND_WB (1 << 3)
455 #define NHM_PF_DATA_RD (1 << 4)
456 #define NHM_PF_DATA_RFO (1 << 5)
457 #define NHM_PF_IFETCH (1 << 6)
458 #define NHM_OFFCORE_OTHER (1 << 7)
459 #define NHM_UNCORE_HIT (1 << 8)
460 #define NHM_OTHER_CORE_HIT_SNP (1 << 9)
461 #define NHM_OTHER_CORE_HITM (1 << 10)
462 /* reserved */
463 #define NHM_REMOTE_CACHE_FWD (1 << 12)
464 #define NHM_REMOTE_DRAM (1 << 13)
465 #define NHM_LOCAL_DRAM (1 << 14)
466 #define NHM_NON_DRAM (1 << 15)
467
468 #define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD)
469 #define NHM_REMOTE (NHM_REMOTE_DRAM)
470
471 #define NHM_DMND_READ (NHM_DMND_DATA_RD)
472 #define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB)
473 #define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
474
475 #define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
476 #define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD)
477 #define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS)
478
479 static __initconst const u64 nehalem_hw_cache_extra_regs
480 [PERF_COUNT_HW_CACHE_MAX]
481 [PERF_COUNT_HW_CACHE_OP_MAX]
482 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
483 {
484 [ C(LL ) ] = {
485 [ C(OP_READ) ] = {
486 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
487 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS,
488 },
489 [ C(OP_WRITE) ] = {
490 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
491 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS,
492 },
493 [ C(OP_PREFETCH) ] = {
494 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
495 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
496 },
497 },
498 [ C(NODE) ] = {
499 [ C(OP_READ) ] = {
500 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE,
501 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE,
502 },
503 [ C(OP_WRITE) ] = {
504 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE,
505 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE,
506 },
507 [ C(OP_PREFETCH) ] = {
508 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE,
509 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE,
510 },
511 },
512 };
513
514 static __initconst const u64 nehalem_hw_cache_event_ids
515 [PERF_COUNT_HW_CACHE_MAX]
516 [PERF_COUNT_HW_CACHE_OP_MAX]
517 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
518 {
519 [ C(L1D) ] = {
520 [ C(OP_READ) ] = {
521 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
522 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
523 },
524 [ C(OP_WRITE) ] = {
525 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
526 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
527 },
528 [ C(OP_PREFETCH) ] = {
529 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
530 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
531 },
532 },
533 [ C(L1I ) ] = {
534 [ C(OP_READ) ] = {
535 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
536 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
537 },
538 [ C(OP_WRITE) ] = {
539 [ C(RESULT_ACCESS) ] = -1,
540 [ C(RESULT_MISS) ] = -1,
541 },
542 [ C(OP_PREFETCH) ] = {
543 [ C(RESULT_ACCESS) ] = 0x0,
544 [ C(RESULT_MISS) ] = 0x0,
545 },
546 },
547 [ C(LL ) ] = {
548 [ C(OP_READ) ] = {
549 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
550 [ C(RESULT_ACCESS) ] = 0x01b7,
551 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
552 [ C(RESULT_MISS) ] = 0x01b7,
553 },
554 /*
555 * Use RFO, not WRITEBACK, because a write miss would typically occur
556 * on RFO.
557 */
558 [ C(OP_WRITE) ] = {
559 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
560 [ C(RESULT_ACCESS) ] = 0x01b7,
561 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
562 [ C(RESULT_MISS) ] = 0x01b7,
563 },
564 [ C(OP_PREFETCH) ] = {
565 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
566 [ C(RESULT_ACCESS) ] = 0x01b7,
567 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
568 [ C(RESULT_MISS) ] = 0x01b7,
569 },
570 },
571 [ C(DTLB) ] = {
572 [ C(OP_READ) ] = {
573 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
574 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
575 },
576 [ C(OP_WRITE) ] = {
577 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
578 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
579 },
580 [ C(OP_PREFETCH) ] = {
581 [ C(RESULT_ACCESS) ] = 0x0,
582 [ C(RESULT_MISS) ] = 0x0,
583 },
584 },
585 [ C(ITLB) ] = {
586 [ C(OP_READ) ] = {
587 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
588 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */
589 },
590 [ C(OP_WRITE) ] = {
591 [ C(RESULT_ACCESS) ] = -1,
592 [ C(RESULT_MISS) ] = -1,
593 },
594 [ C(OP_PREFETCH) ] = {
595 [ C(RESULT_ACCESS) ] = -1,
596 [ C(RESULT_MISS) ] = -1,
597 },
598 },
599 [ C(BPU ) ] = {
600 [ C(OP_READ) ] = {
601 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
602 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
603 },
604 [ C(OP_WRITE) ] = {
605 [ C(RESULT_ACCESS) ] = -1,
606 [ C(RESULT_MISS) ] = -1,
607 },
608 [ C(OP_PREFETCH) ] = {
609 [ C(RESULT_ACCESS) ] = -1,
610 [ C(RESULT_MISS) ] = -1,
611 },
612 },
613 [ C(NODE) ] = {
614 [ C(OP_READ) ] = {
615 [ C(RESULT_ACCESS) ] = 0x01b7,
616 [ C(RESULT_MISS) ] = 0x01b7,
617 },
618 [ C(OP_WRITE) ] = {
619 [ C(RESULT_ACCESS) ] = 0x01b7,
620 [ C(RESULT_MISS) ] = 0x01b7,
621 },
622 [ C(OP_PREFETCH) ] = {
623 [ C(RESULT_ACCESS) ] = 0x01b7,
624 [ C(RESULT_MISS) ] = 0x01b7,
625 },
626 },
627 };
628
629 static __initconst const u64 core2_hw_cache_event_ids
630 [PERF_COUNT_HW_CACHE_MAX]
631 [PERF_COUNT_HW_CACHE_OP_MAX]
632 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
633 {
634 [ C(L1D) ] = {
635 [ C(OP_READ) ] = {
636 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
637 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
638 },
639 [ C(OP_WRITE) ] = {
640 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
641 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
642 },
643 [ C(OP_PREFETCH) ] = {
644 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
645 [ C(RESULT_MISS) ] = 0,
646 },
647 },
648 [ C(L1I ) ] = {
649 [ C(OP_READ) ] = {
650 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */
651 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */
652 },
653 [ C(OP_WRITE) ] = {
654 [ C(RESULT_ACCESS) ] = -1,
655 [ C(RESULT_MISS) ] = -1,
656 },
657 [ C(OP_PREFETCH) ] = {
658 [ C(RESULT_ACCESS) ] = 0,
659 [ C(RESULT_MISS) ] = 0,
660 },
661 },
662 [ C(LL ) ] = {
663 [ C(OP_READ) ] = {
664 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
665 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
666 },
667 [ C(OP_WRITE) ] = {
668 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
669 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
670 },
671 [ C(OP_PREFETCH) ] = {
672 [ C(RESULT_ACCESS) ] = 0,
673 [ C(RESULT_MISS) ] = 0,
674 },
675 },
676 [ C(DTLB) ] = {
677 [ C(OP_READ) ] = {
678 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
679 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
680 },
681 [ C(OP_WRITE) ] = {
682 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
683 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
684 },
685 [ C(OP_PREFETCH) ] = {
686 [ C(RESULT_ACCESS) ] = 0,
687 [ C(RESULT_MISS) ] = 0,
688 },
689 },
690 [ C(ITLB) ] = {
691 [ C(OP_READ) ] = {
692 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
693 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */
694 },
695 [ C(OP_WRITE) ] = {
696 [ C(RESULT_ACCESS) ] = -1,
697 [ C(RESULT_MISS) ] = -1,
698 },
699 [ C(OP_PREFETCH) ] = {
700 [ C(RESULT_ACCESS) ] = -1,
701 [ C(RESULT_MISS) ] = -1,
702 },
703 },
704 [ C(BPU ) ] = {
705 [ C(OP_READ) ] = {
706 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
707 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
708 },
709 [ C(OP_WRITE) ] = {
710 [ C(RESULT_ACCESS) ] = -1,
711 [ C(RESULT_MISS) ] = -1,
712 },
713 [ C(OP_PREFETCH) ] = {
714 [ C(RESULT_ACCESS) ] = -1,
715 [ C(RESULT_MISS) ] = -1,
716 },
717 },
718 };
719
720 static __initconst const u64 atom_hw_cache_event_ids
721 [PERF_COUNT_HW_CACHE_MAX]
722 [PERF_COUNT_HW_CACHE_OP_MAX]
723 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
724 {
725 [ C(L1D) ] = {
726 [ C(OP_READ) ] = {
727 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */
728 [ C(RESULT_MISS) ] = 0,
729 },
730 [ C(OP_WRITE) ] = {
731 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */
732 [ C(RESULT_MISS) ] = 0,
733 },
734 [ C(OP_PREFETCH) ] = {
735 [ C(RESULT_ACCESS) ] = 0x0,
736 [ C(RESULT_MISS) ] = 0,
737 },
738 },
739 [ C(L1I ) ] = {
740 [ C(OP_READ) ] = {
741 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
742 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
743 },
744 [ C(OP_WRITE) ] = {
745 [ C(RESULT_ACCESS) ] = -1,
746 [ C(RESULT_MISS) ] = -1,
747 },
748 [ C(OP_PREFETCH) ] = {
749 [ C(RESULT_ACCESS) ] = 0,
750 [ C(RESULT_MISS) ] = 0,
751 },
752 },
753 [ C(LL ) ] = {
754 [ C(OP_READ) ] = {
755 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
756 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
757 },
758 [ C(OP_WRITE) ] = {
759 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
760 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
761 },
762 [ C(OP_PREFETCH) ] = {
763 [ C(RESULT_ACCESS) ] = 0,
764 [ C(RESULT_MISS) ] = 0,
765 },
766 },
767 [ C(DTLB) ] = {
768 [ C(OP_READ) ] = {
769 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
770 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
771 },
772 [ C(OP_WRITE) ] = {
773 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
774 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
775 },
776 [ C(OP_PREFETCH) ] = {
777 [ C(RESULT_ACCESS) ] = 0,
778 [ C(RESULT_MISS) ] = 0,
779 },
780 },
781 [ C(ITLB) ] = {
782 [ C(OP_READ) ] = {
783 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
784 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
785 },
786 [ C(OP_WRITE) ] = {
787 [ C(RESULT_ACCESS) ] = -1,
788 [ C(RESULT_MISS) ] = -1,
789 },
790 [ C(OP_PREFETCH) ] = {
791 [ C(RESULT_ACCESS) ] = -1,
792 [ C(RESULT_MISS) ] = -1,
793 },
794 },
795 [ C(BPU ) ] = {
796 [ C(OP_READ) ] = {
797 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
798 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
799 },
800 [ C(OP_WRITE) ] = {
801 [ C(RESULT_ACCESS) ] = -1,
802 [ C(RESULT_MISS) ] = -1,
803 },
804 [ C(OP_PREFETCH) ] = {
805 [ C(RESULT_ACCESS) ] = -1,
806 [ C(RESULT_MISS) ] = -1,
807 },
808 },
809 };
810
811 static inline bool intel_pmu_needs_lbr_smpl(struct perf_event *event)
812 {
813 /* user explicitly requested branch sampling */
814 if (has_branch_stack(event))
815 return true;
816
817 /* implicit branch sampling to correct PEBS skid */
818 if (x86_pmu.intel_cap.pebs_trap && event->attr.precise_ip > 1)
819 return true;
820
821 return false;
822 }
823
824 static void intel_pmu_disable_all(void)
825 {
826 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
827
828 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
829
830 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask))
831 intel_pmu_disable_bts();
832
833 intel_pmu_pebs_disable_all();
834 intel_pmu_lbr_disable_all();
835 }
836
837 static void intel_pmu_enable_all(int added)
838 {
839 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
840
841 intel_pmu_pebs_enable_all();
842 intel_pmu_lbr_enable_all();
843 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL,
844 x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask);
845
846 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
847 struct perf_event *event =
848 cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
849
850 if (WARN_ON_ONCE(!event))
851 return;
852
853 intel_pmu_enable_bts(event->hw.config);
854 }
855 }
856
857 /*
858 * Workaround for:
859 * Intel Errata AAK100 (model 26)
860 * Intel Errata AAP53 (model 30)
861 * Intel Errata BD53 (model 44)
862 *
863 * The official story:
864 * These chips need to be 'reset' when adding counters by programming the
865 * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either
866 * in sequence on the same PMC or on different PMCs.
867 *
868 * In practise it appears some of these events do in fact count, and
869 * we need to programm all 4 events.
870 */
871 static void intel_pmu_nhm_workaround(void)
872 {
873 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
874 static const unsigned long nhm_magic[4] = {
875 0x4300B5,
876 0x4300D2,
877 0x4300B1,
878 0x4300B1
879 };
880 struct perf_event *event;
881 int i;
882
883 /*
884 * The Errata requires below steps:
885 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL;
886 * 2) Configure 4 PERFEVTSELx with the magic events and clear
887 * the corresponding PMCx;
888 * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL;
889 * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL;
890 * 5) Clear 4 pairs of ERFEVTSELx and PMCx;
891 */
892
893 /*
894 * The real steps we choose are a little different from above.
895 * A) To reduce MSR operations, we don't run step 1) as they
896 * are already cleared before this function is called;
897 * B) Call x86_perf_event_update to save PMCx before configuring
898 * PERFEVTSELx with magic number;
899 * C) With step 5), we do clear only when the PERFEVTSELx is
900 * not used currently.
901 * D) Call x86_perf_event_set_period to restore PMCx;
902 */
903
904 /* We always operate 4 pairs of PERF Counters */
905 for (i = 0; i < 4; i++) {
906 event = cpuc->events[i];
907 if (event)
908 x86_perf_event_update(event);
909 }
910
911 for (i = 0; i < 4; i++) {
912 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]);
913 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0);
914 }
915
916 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf);
917 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0);
918
919 for (i = 0; i < 4; i++) {
920 event = cpuc->events[i];
921
922 if (event) {
923 x86_perf_event_set_period(event);
924 __x86_pmu_enable_event(&event->hw,
925 ARCH_PERFMON_EVENTSEL_ENABLE);
926 } else
927 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0);
928 }
929 }
930
931 static void intel_pmu_nhm_enable_all(int added)
932 {
933 if (added)
934 intel_pmu_nhm_workaround();
935 intel_pmu_enable_all(added);
936 }
937
938 static inline u64 intel_pmu_get_status(void)
939 {
940 u64 status;
941
942 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
943
944 return status;
945 }
946
947 static inline void intel_pmu_ack_status(u64 ack)
948 {
949 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
950 }
951
952 static void intel_pmu_disable_fixed(struct hw_perf_event *hwc)
953 {
954 int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
955 u64 ctrl_val, mask;
956
957 mask = 0xfULL << (idx * 4);
958
959 rdmsrl(hwc->config_base, ctrl_val);
960 ctrl_val &= ~mask;
961 wrmsrl(hwc->config_base, ctrl_val);
962 }
963
964 static void intel_pmu_disable_event(struct perf_event *event)
965 {
966 struct hw_perf_event *hwc = &event->hw;
967 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
968
969 if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
970 intel_pmu_disable_bts();
971 intel_pmu_drain_bts_buffer();
972 return;
973 }
974
975 cpuc->intel_ctrl_guest_mask &= ~(1ull << hwc->idx);
976 cpuc->intel_ctrl_host_mask &= ~(1ull << hwc->idx);
977
978 /*
979 * must disable before any actual event
980 * because any event may be combined with LBR
981 */
982 if (intel_pmu_needs_lbr_smpl(event))
983 intel_pmu_lbr_disable(event);
984
985 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
986 intel_pmu_disable_fixed(hwc);
987 return;
988 }
989
990 x86_pmu_disable_event(event);
991
992 if (unlikely(event->attr.precise_ip))
993 intel_pmu_pebs_disable(event);
994 }
995
996 static void intel_pmu_enable_fixed(struct hw_perf_event *hwc)
997 {
998 int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
999 u64 ctrl_val, bits, mask;
1000
1001 /*
1002 * Enable IRQ generation (0x8),
1003 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
1004 * if requested:
1005 */
1006 bits = 0x8ULL;
1007 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
1008 bits |= 0x2;
1009 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
1010 bits |= 0x1;
1011
1012 /*
1013 * ANY bit is supported in v3 and up
1014 */
1015 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
1016 bits |= 0x4;
1017
1018 bits <<= (idx * 4);
1019 mask = 0xfULL << (idx * 4);
1020
1021 rdmsrl(hwc->config_base, ctrl_val);
1022 ctrl_val &= ~mask;
1023 ctrl_val |= bits;
1024 wrmsrl(hwc->config_base, ctrl_val);
1025 }
1026
1027 static void intel_pmu_enable_event(struct perf_event *event)
1028 {
1029 struct hw_perf_event *hwc = &event->hw;
1030 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1031
1032 if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
1033 if (!__this_cpu_read(cpu_hw_events.enabled))
1034 return;
1035
1036 intel_pmu_enable_bts(hwc->config);
1037 return;
1038 }
1039 /*
1040 * must enabled before any actual event
1041 * because any event may be combined with LBR
1042 */
1043 if (intel_pmu_needs_lbr_smpl(event))
1044 intel_pmu_lbr_enable(event);
1045
1046 if (event->attr.exclude_host)
1047 cpuc->intel_ctrl_guest_mask |= (1ull << hwc->idx);
1048 if (event->attr.exclude_guest)
1049 cpuc->intel_ctrl_host_mask |= (1ull << hwc->idx);
1050
1051 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
1052 intel_pmu_enable_fixed(hwc);
1053 return;
1054 }
1055
1056 if (unlikely(event->attr.precise_ip))
1057 intel_pmu_pebs_enable(event);
1058
1059 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
1060 }
1061
1062 /*
1063 * Save and restart an expired event. Called by NMI contexts,
1064 * so it has to be careful about preempting normal event ops:
1065 */
1066 int intel_pmu_save_and_restart(struct perf_event *event)
1067 {
1068 x86_perf_event_update(event);
1069 return x86_perf_event_set_period(event);
1070 }
1071
1072 static void intel_pmu_reset(void)
1073 {
1074 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
1075 unsigned long flags;
1076 int idx;
1077
1078 if (!x86_pmu.num_counters)
1079 return;
1080
1081 local_irq_save(flags);
1082
1083 pr_info("clearing PMU state on CPU#%d\n", smp_processor_id());
1084
1085 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1086 wrmsrl_safe(x86_pmu_config_addr(idx), 0ull);
1087 wrmsrl_safe(x86_pmu_event_addr(idx), 0ull);
1088 }
1089 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++)
1090 wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
1091
1092 if (ds)
1093 ds->bts_index = ds->bts_buffer_base;
1094
1095 local_irq_restore(flags);
1096 }
1097
1098 /*
1099 * This handler is triggered by the local APIC, so the APIC IRQ handling
1100 * rules apply:
1101 */
1102 static int intel_pmu_handle_irq(struct pt_regs *regs)
1103 {
1104 struct perf_sample_data data;
1105 struct cpu_hw_events *cpuc;
1106 int bit, loops;
1107 u64 status;
1108 int handled;
1109
1110 cpuc = &__get_cpu_var(cpu_hw_events);
1111
1112 /*
1113 * Some chipsets need to unmask the LVTPC in a particular spot
1114 * inside the nmi handler. As a result, the unmasking was pushed
1115 * into all the nmi handlers.
1116 *
1117 * This handler doesn't seem to have any issues with the unmasking
1118 * so it was left at the top.
1119 */
1120 apic_write(APIC_LVTPC, APIC_DM_NMI);
1121
1122 intel_pmu_disable_all();
1123 handled = intel_pmu_drain_bts_buffer();
1124 status = intel_pmu_get_status();
1125 if (!status) {
1126 intel_pmu_enable_all(0);
1127 return handled;
1128 }
1129
1130 loops = 0;
1131 again:
1132 intel_pmu_ack_status(status);
1133 if (++loops > 100) {
1134 WARN_ONCE(1, "perfevents: irq loop stuck!\n");
1135 perf_event_print_debug();
1136 intel_pmu_reset();
1137 goto done;
1138 }
1139
1140 inc_irq_stat(apic_perf_irqs);
1141
1142 intel_pmu_lbr_read();
1143
1144 /*
1145 * PEBS overflow sets bit 62 in the global status register
1146 */
1147 if (__test_and_clear_bit(62, (unsigned long *)&status)) {
1148 handled++;
1149 x86_pmu.drain_pebs(regs);
1150 }
1151
1152 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
1153 struct perf_event *event = cpuc->events[bit];
1154
1155 handled++;
1156
1157 if (!test_bit(bit, cpuc->active_mask))
1158 continue;
1159
1160 if (!intel_pmu_save_and_restart(event))
1161 continue;
1162
1163 perf_sample_data_init(&data, 0, event->hw.last_period);
1164
1165 if (has_branch_stack(event))
1166 data.br_stack = &cpuc->lbr_stack;
1167
1168 if (perf_event_overflow(event, &data, regs))
1169 x86_pmu_stop(event, 0);
1170 }
1171
1172 /*
1173 * Repeat if there is more work to be done:
1174 */
1175 status = intel_pmu_get_status();
1176 if (status)
1177 goto again;
1178
1179 done:
1180 intel_pmu_enable_all(0);
1181 return handled;
1182 }
1183
1184 static struct event_constraint *
1185 intel_bts_constraints(struct perf_event *event)
1186 {
1187 struct hw_perf_event *hwc = &event->hw;
1188 unsigned int hw_event, bts_event;
1189
1190 if (event->attr.freq)
1191 return NULL;
1192
1193 hw_event = hwc->config & INTEL_ARCH_EVENT_MASK;
1194 bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
1195
1196 if (unlikely(hw_event == bts_event && hwc->sample_period == 1))
1197 return &bts_constraint;
1198
1199 return NULL;
1200 }
1201
1202 static int intel_alt_er(int idx)
1203 {
1204 if (!(x86_pmu.er_flags & ERF_HAS_RSP_1))
1205 return idx;
1206
1207 if (idx == EXTRA_REG_RSP_0)
1208 return EXTRA_REG_RSP_1;
1209
1210 if (idx == EXTRA_REG_RSP_1)
1211 return EXTRA_REG_RSP_0;
1212
1213 return idx;
1214 }
1215
1216 static void intel_fixup_er(struct perf_event *event, int idx)
1217 {
1218 event->hw.extra_reg.idx = idx;
1219
1220 if (idx == EXTRA_REG_RSP_0) {
1221 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
1222 event->hw.config |= 0x01b7;
1223 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0;
1224 } else if (idx == EXTRA_REG_RSP_1) {
1225 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
1226 event->hw.config |= 0x01bb;
1227 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1;
1228 }
1229 }
1230
1231 /*
1232 * manage allocation of shared extra msr for certain events
1233 *
1234 * sharing can be:
1235 * per-cpu: to be shared between the various events on a single PMU
1236 * per-core: per-cpu + shared by HT threads
1237 */
1238 static struct event_constraint *
1239 __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc,
1240 struct perf_event *event,
1241 struct hw_perf_event_extra *reg)
1242 {
1243 struct event_constraint *c = &emptyconstraint;
1244 struct er_account *era;
1245 unsigned long flags;
1246 int idx = reg->idx;
1247
1248 /*
1249 * reg->alloc can be set due to existing state, so for fake cpuc we
1250 * need to ignore this, otherwise we might fail to allocate proper fake
1251 * state for this extra reg constraint. Also see the comment below.
1252 */
1253 if (reg->alloc && !cpuc->is_fake)
1254 return NULL; /* call x86_get_event_constraint() */
1255
1256 again:
1257 era = &cpuc->shared_regs->regs[idx];
1258 /*
1259 * we use spin_lock_irqsave() to avoid lockdep issues when
1260 * passing a fake cpuc
1261 */
1262 raw_spin_lock_irqsave(&era->lock, flags);
1263
1264 if (!atomic_read(&era->ref) || era->config == reg->config) {
1265
1266 /*
1267 * If its a fake cpuc -- as per validate_{group,event}() we
1268 * shouldn't touch event state and we can avoid doing so
1269 * since both will only call get_event_constraints() once
1270 * on each event, this avoids the need for reg->alloc.
1271 *
1272 * Not doing the ER fixup will only result in era->reg being
1273 * wrong, but since we won't actually try and program hardware
1274 * this isn't a problem either.
1275 */
1276 if (!cpuc->is_fake) {
1277 if (idx != reg->idx)
1278 intel_fixup_er(event, idx);
1279
1280 /*
1281 * x86_schedule_events() can call get_event_constraints()
1282 * multiple times on events in the case of incremental
1283 * scheduling(). reg->alloc ensures we only do the ER
1284 * allocation once.
1285 */
1286 reg->alloc = 1;
1287 }
1288
1289 /* lock in msr value */
1290 era->config = reg->config;
1291 era->reg = reg->reg;
1292
1293 /* one more user */
1294 atomic_inc(&era->ref);
1295
1296 /*
1297 * need to call x86_get_event_constraint()
1298 * to check if associated event has constraints
1299 */
1300 c = NULL;
1301 } else {
1302 idx = intel_alt_er(idx);
1303 if (idx != reg->idx) {
1304 raw_spin_unlock_irqrestore(&era->lock, flags);
1305 goto again;
1306 }
1307 }
1308 raw_spin_unlock_irqrestore(&era->lock, flags);
1309
1310 return c;
1311 }
1312
1313 static void
1314 __intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc,
1315 struct hw_perf_event_extra *reg)
1316 {
1317 struct er_account *era;
1318
1319 /*
1320 * Only put constraint if extra reg was actually allocated. Also takes
1321 * care of event which do not use an extra shared reg.
1322 *
1323 * Also, if this is a fake cpuc we shouldn't touch any event state
1324 * (reg->alloc) and we don't care about leaving inconsistent cpuc state
1325 * either since it'll be thrown out.
1326 */
1327 if (!reg->alloc || cpuc->is_fake)
1328 return;
1329
1330 era = &cpuc->shared_regs->regs[reg->idx];
1331
1332 /* one fewer user */
1333 atomic_dec(&era->ref);
1334
1335 /* allocate again next time */
1336 reg->alloc = 0;
1337 }
1338
1339 static struct event_constraint *
1340 intel_shared_regs_constraints(struct cpu_hw_events *cpuc,
1341 struct perf_event *event)
1342 {
1343 struct event_constraint *c = NULL, *d;
1344 struct hw_perf_event_extra *xreg, *breg;
1345
1346 xreg = &event->hw.extra_reg;
1347 if (xreg->idx != EXTRA_REG_NONE) {
1348 c = __intel_shared_reg_get_constraints(cpuc, event, xreg);
1349 if (c == &emptyconstraint)
1350 return c;
1351 }
1352 breg = &event->hw.branch_reg;
1353 if (breg->idx != EXTRA_REG_NONE) {
1354 d = __intel_shared_reg_get_constraints(cpuc, event, breg);
1355 if (d == &emptyconstraint) {
1356 __intel_shared_reg_put_constraints(cpuc, xreg);
1357 c = d;
1358 }
1359 }
1360 return c;
1361 }
1362
1363 struct event_constraint *
1364 x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1365 {
1366 struct event_constraint *c;
1367
1368 if (x86_pmu.event_constraints) {
1369 for_each_event_constraint(c, x86_pmu.event_constraints) {
1370 if ((event->hw.config & c->cmask) == c->code)
1371 return c;
1372 }
1373 }
1374
1375 return &unconstrained;
1376 }
1377
1378 static struct event_constraint *
1379 intel_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1380 {
1381 struct event_constraint *c;
1382
1383 c = intel_bts_constraints(event);
1384 if (c)
1385 return c;
1386
1387 c = intel_pebs_constraints(event);
1388 if (c)
1389 return c;
1390
1391 c = intel_shared_regs_constraints(cpuc, event);
1392 if (c)
1393 return c;
1394
1395 return x86_get_event_constraints(cpuc, event);
1396 }
1397
1398 static void
1399 intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc,
1400 struct perf_event *event)
1401 {
1402 struct hw_perf_event_extra *reg;
1403
1404 reg = &event->hw.extra_reg;
1405 if (reg->idx != EXTRA_REG_NONE)
1406 __intel_shared_reg_put_constraints(cpuc, reg);
1407
1408 reg = &event->hw.branch_reg;
1409 if (reg->idx != EXTRA_REG_NONE)
1410 __intel_shared_reg_put_constraints(cpuc, reg);
1411 }
1412
1413 static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
1414 struct perf_event *event)
1415 {
1416 intel_put_shared_regs_event_constraints(cpuc, event);
1417 }
1418
1419 static void intel_pebs_aliases_core2(struct perf_event *event)
1420 {
1421 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
1422 /*
1423 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
1424 * (0x003c) so that we can use it with PEBS.
1425 *
1426 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
1427 * PEBS capable. However we can use INST_RETIRED.ANY_P
1428 * (0x00c0), which is a PEBS capable event, to get the same
1429 * count.
1430 *
1431 * INST_RETIRED.ANY_P counts the number of cycles that retires
1432 * CNTMASK instructions. By setting CNTMASK to a value (16)
1433 * larger than the maximum number of instructions that can be
1434 * retired per cycle (4) and then inverting the condition, we
1435 * count all cycles that retire 16 or less instructions, which
1436 * is every cycle.
1437 *
1438 * Thereby we gain a PEBS capable cycle counter.
1439 */
1440 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16);
1441
1442 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
1443 event->hw.config = alt_config;
1444 }
1445 }
1446
1447 static void intel_pebs_aliases_snb(struct perf_event *event)
1448 {
1449 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
1450 /*
1451 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
1452 * (0x003c) so that we can use it with PEBS.
1453 *
1454 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
1455 * PEBS capable. However we can use UOPS_RETIRED.ALL
1456 * (0x01c2), which is a PEBS capable event, to get the same
1457 * count.
1458 *
1459 * UOPS_RETIRED.ALL counts the number of cycles that retires
1460 * CNTMASK micro-ops. By setting CNTMASK to a value (16)
1461 * larger than the maximum number of micro-ops that can be
1462 * retired per cycle (4) and then inverting the condition, we
1463 * count all cycles that retire 16 or less micro-ops, which
1464 * is every cycle.
1465 *
1466 * Thereby we gain a PEBS capable cycle counter.
1467 */
1468 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16);
1469
1470 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
1471 event->hw.config = alt_config;
1472 }
1473 }
1474
1475 static int intel_pmu_hw_config(struct perf_event *event)
1476 {
1477 int ret = x86_pmu_hw_config(event);
1478
1479 if (ret)
1480 return ret;
1481
1482 if (event->attr.precise_ip && x86_pmu.pebs_aliases)
1483 x86_pmu.pebs_aliases(event);
1484
1485 if (intel_pmu_needs_lbr_smpl(event)) {
1486 ret = intel_pmu_setup_lbr_filter(event);
1487 if (ret)
1488 return ret;
1489 }
1490
1491 if (event->attr.type != PERF_TYPE_RAW)
1492 return 0;
1493
1494 if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY))
1495 return 0;
1496
1497 if (x86_pmu.version < 3)
1498 return -EINVAL;
1499
1500 if (perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN))
1501 return -EACCES;
1502
1503 event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY;
1504
1505 return 0;
1506 }
1507
1508 struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
1509 {
1510 if (x86_pmu.guest_get_msrs)
1511 return x86_pmu.guest_get_msrs(nr);
1512 *nr = 0;
1513 return NULL;
1514 }
1515 EXPORT_SYMBOL_GPL(perf_guest_get_msrs);
1516
1517 static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr)
1518 {
1519 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1520 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
1521
1522 arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL;
1523 arr[0].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask;
1524 arr[0].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask;
1525 /*
1526 * If PMU counter has PEBS enabled it is not enough to disable counter
1527 * on a guest entry since PEBS memory write can overshoot guest entry
1528 * and corrupt guest memory. Disabling PEBS solves the problem.
1529 */
1530 arr[1].msr = MSR_IA32_PEBS_ENABLE;
1531 arr[1].host = cpuc->pebs_enabled;
1532 arr[1].guest = 0;
1533
1534 *nr = 2;
1535 return arr;
1536 }
1537
1538 static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr)
1539 {
1540 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1541 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
1542 int idx;
1543
1544 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1545 struct perf_event *event = cpuc->events[idx];
1546
1547 arr[idx].msr = x86_pmu_config_addr(idx);
1548 arr[idx].host = arr[idx].guest = 0;
1549
1550 if (!test_bit(idx, cpuc->active_mask))
1551 continue;
1552
1553 arr[idx].host = arr[idx].guest =
1554 event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE;
1555
1556 if (event->attr.exclude_host)
1557 arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
1558 else if (event->attr.exclude_guest)
1559 arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
1560 }
1561
1562 *nr = x86_pmu.num_counters;
1563 return arr;
1564 }
1565
1566 static void core_pmu_enable_event(struct perf_event *event)
1567 {
1568 if (!event->attr.exclude_host)
1569 x86_pmu_enable_event(event);
1570 }
1571
1572 static void core_pmu_enable_all(int added)
1573 {
1574 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1575 int idx;
1576
1577 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1578 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
1579
1580 if (!test_bit(idx, cpuc->active_mask) ||
1581 cpuc->events[idx]->attr.exclude_host)
1582 continue;
1583
1584 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
1585 }
1586 }
1587
1588 PMU_FORMAT_ATTR(event, "config:0-7" );
1589 PMU_FORMAT_ATTR(umask, "config:8-15" );
1590 PMU_FORMAT_ATTR(edge, "config:18" );
1591 PMU_FORMAT_ATTR(pc, "config:19" );
1592 PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */
1593 PMU_FORMAT_ATTR(inv, "config:23" );
1594 PMU_FORMAT_ATTR(cmask, "config:24-31" );
1595
1596 static struct attribute *intel_arch_formats_attr[] = {
1597 &format_attr_event.attr,
1598 &format_attr_umask.attr,
1599 &format_attr_edge.attr,
1600 &format_attr_pc.attr,
1601 &format_attr_inv.attr,
1602 &format_attr_cmask.attr,
1603 NULL,
1604 };
1605
1606 ssize_t intel_event_sysfs_show(char *page, u64 config)
1607 {
1608 u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT);
1609
1610 return x86_event_sysfs_show(page, config, event);
1611 }
1612
1613 static __initconst const struct x86_pmu core_pmu = {
1614 .name = "core",
1615 .handle_irq = x86_pmu_handle_irq,
1616 .disable_all = x86_pmu_disable_all,
1617 .enable_all = core_pmu_enable_all,
1618 .enable = core_pmu_enable_event,
1619 .disable = x86_pmu_disable_event,
1620 .hw_config = x86_pmu_hw_config,
1621 .schedule_events = x86_schedule_events,
1622 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
1623 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
1624 .event_map = intel_pmu_event_map,
1625 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
1626 .apic = 1,
1627 /*
1628 * Intel PMCs cannot be accessed sanely above 32 bit width,
1629 * so we install an artificial 1<<31 period regardless of
1630 * the generic event period:
1631 */
1632 .max_period = (1ULL << 31) - 1,
1633 .get_event_constraints = intel_get_event_constraints,
1634 .put_event_constraints = intel_put_event_constraints,
1635 .event_constraints = intel_core_event_constraints,
1636 .guest_get_msrs = core_guest_get_msrs,
1637 .format_attrs = intel_arch_formats_attr,
1638 .events_sysfs_show = intel_event_sysfs_show,
1639 };
1640
1641 struct intel_shared_regs *allocate_shared_regs(int cpu)
1642 {
1643 struct intel_shared_regs *regs;
1644 int i;
1645
1646 regs = kzalloc_node(sizeof(struct intel_shared_regs),
1647 GFP_KERNEL, cpu_to_node(cpu));
1648 if (regs) {
1649 /*
1650 * initialize the locks to keep lockdep happy
1651 */
1652 for (i = 0; i < EXTRA_REG_MAX; i++)
1653 raw_spin_lock_init(&regs->regs[i].lock);
1654
1655 regs->core_id = -1;
1656 }
1657 return regs;
1658 }
1659
1660 static int intel_pmu_cpu_prepare(int cpu)
1661 {
1662 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1663
1664 if (!(x86_pmu.extra_regs || x86_pmu.lbr_sel_map))
1665 return NOTIFY_OK;
1666
1667 cpuc->shared_regs = allocate_shared_regs(cpu);
1668 if (!cpuc->shared_regs)
1669 return NOTIFY_BAD;
1670
1671 return NOTIFY_OK;
1672 }
1673
1674 static void intel_pmu_cpu_starting(int cpu)
1675 {
1676 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1677 int core_id = topology_core_id(cpu);
1678 int i;
1679
1680 init_debug_store_on_cpu(cpu);
1681 /*
1682 * Deal with CPUs that don't clear their LBRs on power-up.
1683 */
1684 intel_pmu_lbr_reset();
1685
1686 cpuc->lbr_sel = NULL;
1687
1688 if (!cpuc->shared_regs)
1689 return;
1690
1691 if (!(x86_pmu.er_flags & ERF_NO_HT_SHARING)) {
1692 for_each_cpu(i, topology_thread_cpumask(cpu)) {
1693 struct intel_shared_regs *pc;
1694
1695 pc = per_cpu(cpu_hw_events, i).shared_regs;
1696 if (pc && pc->core_id == core_id) {
1697 cpuc->kfree_on_online = cpuc->shared_regs;
1698 cpuc->shared_regs = pc;
1699 break;
1700 }
1701 }
1702 cpuc->shared_regs->core_id = core_id;
1703 cpuc->shared_regs->refcnt++;
1704 }
1705
1706 if (x86_pmu.lbr_sel_map)
1707 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR];
1708 }
1709
1710 static void intel_pmu_cpu_dying(int cpu)
1711 {
1712 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1713 struct intel_shared_regs *pc;
1714
1715 pc = cpuc->shared_regs;
1716 if (pc) {
1717 if (pc->core_id == -1 || --pc->refcnt == 0)
1718 kfree(pc);
1719 cpuc->shared_regs = NULL;
1720 }
1721
1722 fini_debug_store_on_cpu(cpu);
1723 }
1724
1725 static void intel_pmu_flush_branch_stack(void)
1726 {
1727 /*
1728 * Intel LBR does not tag entries with the
1729 * PID of the current task, then we need to
1730 * flush it on ctxsw
1731 * For now, we simply reset it
1732 */
1733 if (x86_pmu.lbr_nr)
1734 intel_pmu_lbr_reset();
1735 }
1736
1737 PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");
1738
1739 static struct attribute *intel_arch3_formats_attr[] = {
1740 &format_attr_event.attr,
1741 &format_attr_umask.attr,
1742 &format_attr_edge.attr,
1743 &format_attr_pc.attr,
1744 &format_attr_any.attr,
1745 &format_attr_inv.attr,
1746 &format_attr_cmask.attr,
1747
1748 &format_attr_offcore_rsp.attr, /* XXX do NHM/WSM + SNB breakout */
1749 NULL,
1750 };
1751
1752 static __initconst const struct x86_pmu intel_pmu = {
1753 .name = "Intel",
1754 .handle_irq = intel_pmu_handle_irq,
1755 .disable_all = intel_pmu_disable_all,
1756 .enable_all = intel_pmu_enable_all,
1757 .enable = intel_pmu_enable_event,
1758 .disable = intel_pmu_disable_event,
1759 .hw_config = intel_pmu_hw_config,
1760 .schedule_events = x86_schedule_events,
1761 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
1762 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
1763 .event_map = intel_pmu_event_map,
1764 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
1765 .apic = 1,
1766 /*
1767 * Intel PMCs cannot be accessed sanely above 32 bit width,
1768 * so we install an artificial 1<<31 period regardless of
1769 * the generic event period:
1770 */
1771 .max_period = (1ULL << 31) - 1,
1772 .get_event_constraints = intel_get_event_constraints,
1773 .put_event_constraints = intel_put_event_constraints,
1774 .pebs_aliases = intel_pebs_aliases_core2,
1775
1776 .format_attrs = intel_arch3_formats_attr,
1777 .events_sysfs_show = intel_event_sysfs_show,
1778
1779 .cpu_prepare = intel_pmu_cpu_prepare,
1780 .cpu_starting = intel_pmu_cpu_starting,
1781 .cpu_dying = intel_pmu_cpu_dying,
1782 .guest_get_msrs = intel_guest_get_msrs,
1783 .flush_branch_stack = intel_pmu_flush_branch_stack,
1784 };
1785
1786 static __init void intel_clovertown_quirk(void)
1787 {
1788 /*
1789 * PEBS is unreliable due to:
1790 *
1791 * AJ67 - PEBS may experience CPL leaks
1792 * AJ68 - PEBS PMI may be delayed by one event
1793 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]
1794 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS
1795 *
1796 * AJ67 could be worked around by restricting the OS/USR flags.
1797 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.
1798 *
1799 * AJ106 could possibly be worked around by not allowing LBR
1800 * usage from PEBS, including the fixup.
1801 * AJ68 could possibly be worked around by always programming
1802 * a pebs_event_reset[0] value and coping with the lost events.
1803 *
1804 * But taken together it might just make sense to not enable PEBS on
1805 * these chips.
1806 */
1807 pr_warn("PEBS disabled due to CPU errata\n");
1808 x86_pmu.pebs = 0;
1809 x86_pmu.pebs_constraints = NULL;
1810 }
1811
1812 static int intel_snb_pebs_broken(int cpu)
1813 {
1814 u32 rev = UINT_MAX; /* default to broken for unknown models */
1815
1816 switch (cpu_data(cpu).x86_model) {
1817 case 42: /* SNB */
1818 rev = 0x28;
1819 break;
1820
1821 case 45: /* SNB-EP */
1822 switch (cpu_data(cpu).x86_mask) {
1823 case 6: rev = 0x618; break;
1824 case 7: rev = 0x70c; break;
1825 }
1826 }
1827
1828 return (cpu_data(cpu).microcode < rev);
1829 }
1830
1831 static void intel_snb_check_microcode(void)
1832 {
1833 int pebs_broken = 0;
1834 int cpu;
1835
1836 get_online_cpus();
1837 for_each_online_cpu(cpu) {
1838 if ((pebs_broken = intel_snb_pebs_broken(cpu)))
1839 break;
1840 }
1841 put_online_cpus();
1842
1843 if (pebs_broken == x86_pmu.pebs_broken)
1844 return;
1845
1846 /*
1847 * Serialized by the microcode lock..
1848 */
1849 if (x86_pmu.pebs_broken) {
1850 pr_info("PEBS enabled due to microcode update\n");
1851 x86_pmu.pebs_broken = 0;
1852 } else {
1853 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n");
1854 x86_pmu.pebs_broken = 1;
1855 }
1856 }
1857
1858 static __init void intel_sandybridge_quirk(void)
1859 {
1860 x86_pmu.check_microcode = intel_snb_check_microcode;
1861 intel_snb_check_microcode();
1862 }
1863
1864 static const struct { int id; char *name; } intel_arch_events_map[] __initconst = {
1865 { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" },
1866 { PERF_COUNT_HW_INSTRUCTIONS, "instructions" },
1867 { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" },
1868 { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" },
1869 { PERF_COUNT_HW_CACHE_MISSES, "cache misses" },
1870 { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" },
1871 { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" },
1872 };
1873
1874 static __init void intel_arch_events_quirk(void)
1875 {
1876 int bit;
1877
1878 /* disable event that reported as not presend by cpuid */
1879 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) {
1880 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0;
1881 pr_warn("CPUID marked event: \'%s\' unavailable\n",
1882 intel_arch_events_map[bit].name);
1883 }
1884 }
1885
1886 static __init void intel_nehalem_quirk(void)
1887 {
1888 union cpuid10_ebx ebx;
1889
1890 ebx.full = x86_pmu.events_maskl;
1891 if (ebx.split.no_branch_misses_retired) {
1892 /*
1893 * Erratum AAJ80 detected, we work it around by using
1894 * the BR_MISP_EXEC.ANY event. This will over-count
1895 * branch-misses, but it's still much better than the
1896 * architectural event which is often completely bogus:
1897 */
1898 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
1899 ebx.split.no_branch_misses_retired = 0;
1900 x86_pmu.events_maskl = ebx.full;
1901 pr_info("CPU erratum AAJ80 worked around\n");
1902 }
1903 }
1904
1905 __init int intel_pmu_init(void)
1906 {
1907 union cpuid10_edx edx;
1908 union cpuid10_eax eax;
1909 union cpuid10_ebx ebx;
1910 struct event_constraint *c;
1911 unsigned int unused;
1912 int version;
1913
1914 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
1915 switch (boot_cpu_data.x86) {
1916 case 0x6:
1917 return p6_pmu_init();
1918 case 0xb:
1919 return knc_pmu_init();
1920 case 0xf:
1921 return p4_pmu_init();
1922 }
1923 return -ENODEV;
1924 }
1925
1926 /*
1927 * Check whether the Architectural PerfMon supports
1928 * Branch Misses Retired hw_event or not.
1929 */
1930 cpuid(10, &eax.full, &ebx.full, &unused, &edx.full);
1931 if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT)
1932 return -ENODEV;
1933
1934 version = eax.split.version_id;
1935 if (version < 2)
1936 x86_pmu = core_pmu;
1937 else
1938 x86_pmu = intel_pmu;
1939
1940 x86_pmu.version = version;
1941 x86_pmu.num_counters = eax.split.num_counters;
1942 x86_pmu.cntval_bits = eax.split.bit_width;
1943 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1;
1944
1945 x86_pmu.events_maskl = ebx.full;
1946 x86_pmu.events_mask_len = eax.split.mask_length;
1947
1948 x86_pmu.max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters);
1949
1950 /*
1951 * Quirk: v2 perfmon does not report fixed-purpose events, so
1952 * assume at least 3 events:
1953 */
1954 if (version > 1)
1955 x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3);
1956
1957 /*
1958 * v2 and above have a perf capabilities MSR
1959 */
1960 if (version > 1) {
1961 u64 capabilities;
1962
1963 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities);
1964 x86_pmu.intel_cap.capabilities = capabilities;
1965 }
1966
1967 intel_ds_init();
1968
1969 x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */
1970
1971 /*
1972 * Install the hw-cache-events table:
1973 */
1974 switch (boot_cpu_data.x86_model) {
1975 case 14: /* 65 nm core solo/duo, "Yonah" */
1976 pr_cont("Core events, ");
1977 break;
1978
1979 case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
1980 x86_add_quirk(intel_clovertown_quirk);
1981 case 22: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */
1982 case 23: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */
1983 case 29: /* six-core 45 nm xeon "Dunnington" */
1984 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
1985 sizeof(hw_cache_event_ids));
1986
1987 intel_pmu_lbr_init_core();
1988
1989 x86_pmu.event_constraints = intel_core2_event_constraints;
1990 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
1991 pr_cont("Core2 events, ");
1992 break;
1993
1994 case 26: /* 45 nm nehalem, "Bloomfield" */
1995 case 30: /* 45 nm nehalem, "Lynnfield" */
1996 case 46: /* 45 nm nehalem-ex, "Beckton" */
1997 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
1998 sizeof(hw_cache_event_ids));
1999 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
2000 sizeof(hw_cache_extra_regs));
2001
2002 intel_pmu_lbr_init_nhm();
2003
2004 x86_pmu.event_constraints = intel_nehalem_event_constraints;
2005 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
2006 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
2007 x86_pmu.extra_regs = intel_nehalem_extra_regs;
2008
2009 /* UOPS_ISSUED.STALLED_CYCLES */
2010 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
2011 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
2012 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
2013 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
2014 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
2015
2016 x86_add_quirk(intel_nehalem_quirk);
2017
2018 pr_cont("Nehalem events, ");
2019 break;
2020
2021 case 28: /* Atom */
2022 case 38: /* Lincroft */
2023 case 39: /* Penwell */
2024 case 53: /* Cloverview */
2025 case 54: /* Cedarview */
2026 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
2027 sizeof(hw_cache_event_ids));
2028
2029 intel_pmu_lbr_init_atom();
2030
2031 x86_pmu.event_constraints = intel_gen_event_constraints;
2032 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
2033 pr_cont("Atom events, ");
2034 break;
2035
2036 case 37: /* 32 nm nehalem, "Clarkdale" */
2037 case 44: /* 32 nm nehalem, "Gulftown" */
2038 case 47: /* 32 nm Xeon E7 */
2039 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
2040 sizeof(hw_cache_event_ids));
2041 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
2042 sizeof(hw_cache_extra_regs));
2043
2044 intel_pmu_lbr_init_nhm();
2045
2046 x86_pmu.event_constraints = intel_westmere_event_constraints;
2047 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
2048 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;
2049 x86_pmu.extra_regs = intel_westmere_extra_regs;
2050 x86_pmu.er_flags |= ERF_HAS_RSP_1;
2051
2052 /* UOPS_ISSUED.STALLED_CYCLES */
2053 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
2054 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
2055 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
2056 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
2057 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
2058
2059 pr_cont("Westmere events, ");
2060 break;
2061
2062 case 42: /* SandyBridge */
2063 case 45: /* SandyBridge, "Romely-EP" */
2064 x86_add_quirk(intel_sandybridge_quirk);
2065 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
2066 sizeof(hw_cache_event_ids));
2067 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
2068 sizeof(hw_cache_extra_regs));
2069
2070 intel_pmu_lbr_init_snb();
2071
2072 x86_pmu.event_constraints = intel_snb_event_constraints;
2073 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
2074 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
2075 x86_pmu.extra_regs = intel_snb_extra_regs;
2076 /* all extra regs are per-cpu when HT is on */
2077 x86_pmu.er_flags |= ERF_HAS_RSP_1;
2078 x86_pmu.er_flags |= ERF_NO_HT_SHARING;
2079
2080 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
2081 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
2082 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
2083 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
2084 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
2085 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1);
2086
2087 pr_cont("SandyBridge events, ");
2088 break;
2089 case 58: /* IvyBridge */
2090 case 62: /* IvyBridge EP */
2091 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
2092 sizeof(hw_cache_event_ids));
2093 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
2094 sizeof(hw_cache_extra_regs));
2095
2096 intel_pmu_lbr_init_snb();
2097
2098 x86_pmu.event_constraints = intel_snb_event_constraints;
2099 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints;
2100 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
2101 x86_pmu.extra_regs = intel_snb_extra_regs;
2102 /* all extra regs are per-cpu when HT is on */
2103 x86_pmu.er_flags |= ERF_HAS_RSP_1;
2104 x86_pmu.er_flags |= ERF_NO_HT_SHARING;
2105
2106 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
2107 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
2108 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
2109
2110 pr_cont("IvyBridge events, ");
2111 break;
2112
2113
2114 default:
2115 switch (x86_pmu.version) {
2116 case 1:
2117 x86_pmu.event_constraints = intel_v1_event_constraints;
2118 pr_cont("generic architected perfmon v1, ");
2119 break;
2120 default:
2121 /*
2122 * default constraints for v2 and up
2123 */
2124 x86_pmu.event_constraints = intel_gen_event_constraints;
2125 pr_cont("generic architected perfmon, ");
2126 break;
2127 }
2128 }
2129
2130 if (x86_pmu.num_counters > INTEL_PMC_MAX_GENERIC) {
2131 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
2132 x86_pmu.num_counters, INTEL_PMC_MAX_GENERIC);
2133 x86_pmu.num_counters = INTEL_PMC_MAX_GENERIC;
2134 }
2135 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
2136
2137 if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED) {
2138 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
2139 x86_pmu.num_counters_fixed, INTEL_PMC_MAX_FIXED);
2140 x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED;
2141 }
2142
2143 x86_pmu.intel_ctrl |=
2144 ((1LL << x86_pmu.num_counters_fixed)-1) << INTEL_PMC_IDX_FIXED;
2145
2146 if (x86_pmu.event_constraints) {
2147 /*
2148 * event on fixed counter2 (REF_CYCLES) only works on this
2149 * counter, so do not extend mask to generic counters
2150 */
2151 for_each_event_constraint(c, x86_pmu.event_constraints) {
2152 if (c->cmask != X86_RAW_EVENT_MASK
2153 || c->idxmsk64 == INTEL_PMC_MSK_FIXED_REF_CYCLES) {
2154 continue;
2155 }
2156
2157 c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
2158 c->weight += x86_pmu.num_counters;
2159 }
2160 }
2161
2162 return 0;
2163 }
CRIS linux kernel tree