2 * Copyright (C) 1991, 1992 Linus Torvalds
3 * Copyright (C) 2000, 2001, 2002 Andi Kleen, SuSE Labs
4 * Copyright (C) 2011 Don Zickus Red Hat, Inc.
6 * Pentium III FXSR, SSE support
7 * Gareth Hughes <gareth@valinux.com>, May 2000
11 * Handle hardware traps and faults.
13 #include <linux/spinlock.h>
14 #include <linux/kprobes.h>
15 #include <linux/kdebug.h>
16 #include <linux/nmi.h>
17 #include <linux/delay.h>
18 #include <linux/hardirq.h>
19 #include <linux/slab.h>
20 #include <linux/export.h>
22 #if defined(CONFIG_EDAC)
23 #include <linux/edac.h>
26 #include <linux/atomic.h>
27 #include <asm/traps.h>
28 #include <asm/mach_traps.h>
30 #include <asm/x86_init.h>
34 struct list_head head
;
37 static struct nmi_desc nmi_desc
[NMI_MAX
] =
40 .lock
= __SPIN_LOCK_UNLOCKED(&nmi_desc
[0].lock
),
41 .head
= LIST_HEAD_INIT(nmi_desc
[0].head
),
44 .lock
= __SPIN_LOCK_UNLOCKED(&nmi_desc
[1].lock
),
45 .head
= LIST_HEAD_INIT(nmi_desc
[1].head
),
48 .lock
= __SPIN_LOCK_UNLOCKED(&nmi_desc
[2].lock
),
49 .head
= LIST_HEAD_INIT(nmi_desc
[2].head
),
52 .lock
= __SPIN_LOCK_UNLOCKED(&nmi_desc
[3].lock
),
53 .head
= LIST_HEAD_INIT(nmi_desc
[3].head
),
61 unsigned int external
;
65 static DEFINE_PER_CPU(struct nmi_stats
, nmi_stats
);
67 static int ignore_nmis
;
69 int unknown_nmi_panic
;
71 * Prevent NMI reason port (0x61) being accessed simultaneously, can
72 * only be used in NMI handler.
74 static DEFINE_RAW_SPINLOCK(nmi_reason_lock
);
76 static int __init
setup_unknown_nmi_panic(char *str
)
78 unknown_nmi_panic
= 1;
81 __setup("unknown_nmi_panic", setup_unknown_nmi_panic
);
83 #define nmi_to_desc(type) (&nmi_desc[type])
85 static int __kprobes
nmi_handle(unsigned int type
, struct pt_regs
*regs
, bool b2b
)
87 struct nmi_desc
*desc
= nmi_to_desc(type
);
94 * NMIs are edge-triggered, which means if you have enough
95 * of them concurrently, you can lose some because only one
96 * can be latched at any given time. Walk the whole list
97 * to handle those situations.
99 list_for_each_entry_rcu(a
, &desc
->head
, list
)
100 handled
+= a
->handler(type
, regs
);
104 /* return total number of NMI events handled */
108 int __register_nmi_handler(unsigned int type
, struct nmiaction
*action
)
110 struct nmi_desc
*desc
= nmi_to_desc(type
);
113 if (!action
->handler
)
116 spin_lock_irqsave(&desc
->lock
, flags
);
119 * most handlers of type NMI_UNKNOWN never return because
120 * they just assume the NMI is theirs. Just a sanity check
121 * to manage expectations
123 WARN_ON_ONCE(type
== NMI_UNKNOWN
&& !list_empty(&desc
->head
));
124 WARN_ON_ONCE(type
== NMI_SERR
&& !list_empty(&desc
->head
));
125 WARN_ON_ONCE(type
== NMI_IO_CHECK
&& !list_empty(&desc
->head
));
128 * some handlers need to be executed first otherwise a fake
129 * event confuses some handlers (kdump uses this flag)
131 if (action
->flags
& NMI_FLAG_FIRST
)
132 list_add_rcu(&action
->list
, &desc
->head
);
134 list_add_tail_rcu(&action
->list
, &desc
->head
);
136 spin_unlock_irqrestore(&desc
->lock
, flags
);
139 EXPORT_SYMBOL(__register_nmi_handler
);
141 void unregister_nmi_handler(unsigned int type
, const char *name
)
143 struct nmi_desc
*desc
= nmi_to_desc(type
);
147 spin_lock_irqsave(&desc
->lock
, flags
);
149 list_for_each_entry_rcu(n
, &desc
->head
, list
) {
151 * the name passed in to describe the nmi handler
152 * is used as the lookup key
154 if (!strcmp(n
->name
, name
)) {
156 "Trying to free NMI (%s) from NMI context!\n", n
->name
);
157 list_del_rcu(&n
->list
);
162 spin_unlock_irqrestore(&desc
->lock
, flags
);
165 EXPORT_SYMBOL_GPL(unregister_nmi_handler
);
167 static __kprobes
void
168 pci_serr_error(unsigned char reason
, struct pt_regs
*regs
)
170 /* check to see if anyone registered against these types of errors */
171 if (nmi_handle(NMI_SERR
, regs
, false))
174 pr_emerg("NMI: PCI system error (SERR) for reason %02x on CPU %d.\n",
175 reason
, smp_processor_id());
178 * On some machines, PCI SERR line is used to report memory
179 * errors. EDAC makes use of it.
181 #if defined(CONFIG_EDAC)
182 if (edac_handler_set()) {
183 edac_atomic_assert_error();
188 if (panic_on_unrecovered_nmi
)
189 panic("NMI: Not continuing");
191 pr_emerg("Dazed and confused, but trying to continue\n");
193 /* Clear and disable the PCI SERR error line. */
194 reason
= (reason
& NMI_REASON_CLEAR_MASK
) | NMI_REASON_CLEAR_SERR
;
195 outb(reason
, NMI_REASON_PORT
);
198 static __kprobes
void
199 io_check_error(unsigned char reason
, struct pt_regs
*regs
)
203 /* check to see if anyone registered against these types of errors */
204 if (nmi_handle(NMI_IO_CHECK
, regs
, false))
208 "NMI: IOCK error (debug interrupt?) for reason %02x on CPU %d.\n",
209 reason
, smp_processor_id());
213 panic("NMI IOCK error: Not continuing");
215 /* Re-enable the IOCK line, wait for a few seconds */
216 reason
= (reason
& NMI_REASON_CLEAR_MASK
) | NMI_REASON_CLEAR_IOCHK
;
217 outb(reason
, NMI_REASON_PORT
);
221 touch_nmi_watchdog();
225 reason
&= ~NMI_REASON_CLEAR_IOCHK
;
226 outb(reason
, NMI_REASON_PORT
);
229 static __kprobes
void
230 unknown_nmi_error(unsigned char reason
, struct pt_regs
*regs
)
235 * Use 'false' as back-to-back NMIs are dealt with one level up.
236 * Of course this makes having multiple 'unknown' handlers useless
237 * as only the first one is ever run (unless it can actually determine
238 * if it caused the NMI)
240 handled
= nmi_handle(NMI_UNKNOWN
, regs
, false);
242 __this_cpu_add(nmi_stats
.unknown
, handled
);
246 __this_cpu_add(nmi_stats
.unknown
, 1);
248 pr_emerg("Uhhuh. NMI received for unknown reason %02x on CPU %d.\n",
249 reason
, smp_processor_id());
251 pr_emerg("Do you have a strange power saving mode enabled?\n");
252 if (unknown_nmi_panic
|| panic_on_unrecovered_nmi
)
253 panic("NMI: Not continuing");
255 pr_emerg("Dazed and confused, but trying to continue\n");
258 static DEFINE_PER_CPU(bool, swallow_nmi
);
259 static DEFINE_PER_CPU(unsigned long, last_nmi_rip
);
261 static __kprobes
void default_do_nmi(struct pt_regs
*regs
)
263 unsigned char reason
= 0;
268 * CPU-specific NMI must be processed before non-CPU-specific
269 * NMI, otherwise we may lose it, because the CPU-specific
270 * NMI can not be detected/processed on other CPUs.
274 * Back-to-back NMIs are interesting because they can either
275 * be two NMI or more than two NMIs (any thing over two is dropped
276 * due to NMI being edge-triggered). If this is the second half
277 * of the back-to-back NMI, assume we dropped things and process
278 * more handlers. Otherwise reset the 'swallow' NMI behaviour
280 if (regs
->ip
== __this_cpu_read(last_nmi_rip
))
283 __this_cpu_write(swallow_nmi
, false);
285 __this_cpu_write(last_nmi_rip
, regs
->ip
);
287 handled
= nmi_handle(NMI_LOCAL
, regs
, b2b
);
288 __this_cpu_add(nmi_stats
.normal
, handled
);
291 * There are cases when a NMI handler handles multiple
292 * events in the current NMI. One of these events may
293 * be queued for in the next NMI. Because the event is
294 * already handled, the next NMI will result in an unknown
295 * NMI. Instead lets flag this for a potential NMI to
299 __this_cpu_write(swallow_nmi
, true);
303 /* Non-CPU-specific NMI: NMI sources can be processed on any CPU */
304 raw_spin_lock(&nmi_reason_lock
);
305 reason
= x86_platform
.get_nmi_reason();
307 if (reason
& NMI_REASON_MASK
) {
308 if (reason
& NMI_REASON_SERR
)
309 pci_serr_error(reason
, regs
);
310 else if (reason
& NMI_REASON_IOCHK
)
311 io_check_error(reason
, regs
);
314 * Reassert NMI in case it became active
315 * meanwhile as it's edge-triggered:
319 __this_cpu_add(nmi_stats
.external
, 1);
320 raw_spin_unlock(&nmi_reason_lock
);
323 raw_spin_unlock(&nmi_reason_lock
);
326 * Only one NMI can be latched at a time. To handle
327 * this we may process multiple nmi handlers at once to
328 * cover the case where an NMI is dropped. The downside
329 * to this approach is we may process an NMI prematurely,
330 * while its real NMI is sitting latched. This will cause
331 * an unknown NMI on the next run of the NMI processing.
333 * We tried to flag that condition above, by setting the
334 * swallow_nmi flag when we process more than one event.
335 * This condition is also only present on the second half
336 * of a back-to-back NMI, so we flag that condition too.
338 * If both are true, we assume we already processed this
339 * NMI previously and we swallow it. Otherwise we reset
342 * There are scenarios where we may accidentally swallow
343 * a 'real' unknown NMI. For example, while processing
344 * a perf NMI another perf NMI comes in along with a
345 * 'real' unknown NMI. These two NMIs get combined into
346 * one (as descibed above). When the next NMI gets
347 * processed, it will be flagged by perf as handled, but
348 * noone will know that there was a 'real' unknown NMI sent
349 * also. As a result it gets swallowed. Or if the first
350 * perf NMI returns two events handled then the second
351 * NMI will get eaten by the logic below, again losing a
352 * 'real' unknown NMI. But this is the best we can do
355 if (b2b
&& __this_cpu_read(swallow_nmi
))
356 __this_cpu_add(nmi_stats
.swallow
, 1);
358 unknown_nmi_error(reason
, regs
);
362 * NMIs can hit breakpoints which will cause it to lose its
363 * NMI context with the CPU when the breakpoint does an iret.
367 * For i386, NMIs use the same stack as the kernel, and we can
368 * add a workaround to the iret problem in C (preventing nested
369 * NMIs if an NMI takes a trap). Simply have 3 states the NMI
376 * When no NMI is in progress, it is in the "not running" state.
377 * When an NMI comes in, it goes into the "executing" state.
378 * Normally, if another NMI is triggered, it does not interrupt
379 * the running NMI and the HW will simply latch it so that when
380 * the first NMI finishes, it will restart the second NMI.
381 * (Note, the latch is binary, thus multiple NMIs triggering,
382 * when one is running, are ignored. Only one NMI is restarted.)
384 * If an NMI hits a breakpoint that executes an iret, another
385 * NMI can preempt it. We do not want to allow this new NMI
386 * to run, but we want to execute it when the first one finishes.
387 * We set the state to "latched", and the exit of the first NMI will
388 * perform a dec_return, if the result is zero (NOT_RUNNING), then
389 * it will simply exit the NMI handler. If not, the dec_return
390 * would have set the state to NMI_EXECUTING (what we want it to
391 * be when we are running). In this case, we simply jump back
392 * to rerun the NMI handler again, and restart the 'latched' NMI.
394 * No trap (breakpoint or page fault) should be hit before nmi_restart,
395 * thus there is no race between the first check of state for NOT_RUNNING
396 * and setting it to NMI_EXECUTING. The HW will prevent nested NMIs
399 * In case the NMI takes a page fault, we need to save off the CR2
400 * because the NMI could have preempted another page fault and corrupt
401 * the CR2 that is about to be read. As nested NMIs must be restarted
402 * and they can not take breakpoints or page faults, the update of the
403 * CR2 must be done before converting the nmi state back to NOT_RUNNING.
404 * Otherwise, there would be a race of another nested NMI coming in
405 * after setting state to NOT_RUNNING but before updating the nmi_cr2.
412 static DEFINE_PER_CPU(enum nmi_states
, nmi_state
);
413 static DEFINE_PER_CPU(unsigned long, nmi_cr2
);
415 #define nmi_nesting_preprocess(regs) \
417 if (this_cpu_read(nmi_state) != NMI_NOT_RUNNING) { \
418 this_cpu_write(nmi_state, NMI_LATCHED); \
421 this_cpu_write(nmi_state, NMI_EXECUTING); \
422 this_cpu_write(nmi_cr2, read_cr2()); \
426 #define nmi_nesting_postprocess() \
428 if (unlikely(this_cpu_read(nmi_cr2) != read_cr2())) \
429 write_cr2(this_cpu_read(nmi_cr2)); \
430 if (this_cpu_dec_return(nmi_state)) \
435 * In x86_64 things are a bit more difficult. This has the same problem
436 * where an NMI hitting a breakpoint that calls iret will remove the
437 * NMI context, allowing a nested NMI to enter. What makes this more
438 * difficult is that both NMIs and breakpoints have their own stack.
439 * When a new NMI or breakpoint is executed, the stack is set to a fixed
440 * point. If an NMI is nested, it will have its stack set at that same
441 * fixed address that the first NMI had, and will start corrupting the
442 * stack. This is handled in entry_64.S, but the same problem exists with
443 * the breakpoint stack.
445 * If a breakpoint is being processed, and the debug stack is being used,
446 * if an NMI comes in and also hits a breakpoint, the stack pointer
447 * will be set to the same fixed address as the breakpoint that was
448 * interrupted, causing that stack to be corrupted. To handle this case,
449 * check if the stack that was interrupted is the debug stack, and if
450 * so, change the IDT so that new breakpoints will use the current stack
451 * and not switch to the fixed address. On return of the NMI, switch back
452 * to the original IDT.
454 static DEFINE_PER_CPU(int, update_debug_stack
);
456 static inline void nmi_nesting_preprocess(struct pt_regs
*regs
)
459 * If we interrupted a breakpoint, it is possible that
460 * the nmi handler will have breakpoints too. We need to
461 * change the IDT such that breakpoints that happen here
462 * continue to use the NMI stack.
464 if (unlikely(is_debug_stack(regs
->sp
))) {
465 debug_stack_set_zero();
466 this_cpu_write(update_debug_stack
, 1);
470 static inline void nmi_nesting_postprocess(void)
472 if (unlikely(this_cpu_read(update_debug_stack
))) {
474 this_cpu_write(update_debug_stack
, 0);
479 dotraplinkage notrace __kprobes
void
480 do_nmi(struct pt_regs
*regs
, long error_code
)
482 nmi_nesting_preprocess(regs
);
486 inc_irq_stat(__nmi_count
);
489 default_do_nmi(regs
);
493 /* On i386, may loop back to preprocess */
494 nmi_nesting_postprocess();
502 void restart_nmi(void)
507 /* reset the back-to-back NMI logic */
508 void local_touch_nmi(void)
510 __this_cpu_write(last_nmi_rip
, 0);