arch/x86/kernel/process.c

   1 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
   2
   3 #include <linux/errno.h>
   4 #include <linux/kernel.h>
   5 #include <linux/mm.h>
   6 #include <linux/smp.h>
   7 #include <linux/prctl.h>
   8 #include <linux/slab.h>
   9 #include <linux/sched.h>
  10 #include <linux/module.h>
  11 #include <linux/pm.h>
  12 #include <linux/clockchips.h>
  13 #include <linux/random.h>
  14 #include <linux/user-return-notifier.h>
  15 #include <linux/dmi.h>
  16 #include <linux/utsname.h>
  17 #include <linux/stackprotector.h>
  18 #include <linux/tick.h>
  19 #include <linux/cpuidle.h>
  20 #include <trace/events/power.h>
  21 #include <linux/hw_breakpoint.h>
  22 #include <asm/cpu.h>
  23 #include <asm/apic.h>
  24 #include <asm/syscalls.h>
  25 #include <asm/idle.h>
  26 #include <asm/uaccess.h>
  27 #include <asm/i387.h>
  28 #include <asm/fpu-internal.h>
  29 #include <asm/debugreg.h>
  30 #include <asm/nmi.h>
  31
  32 /*
  33  * per-CPU TSS segments. Threads are completely 'soft' on Linux,
  34  * no more per-task TSS's. The TSS size is kept cacheline-aligned
  35  * so they are allowed to end up in the .data..cacheline_aligned
  36  * section. Since TSS's are completely CPU-local, we want them
  37  * on exact cacheline boundaries, to eliminate cacheline ping-pong.
  38  */
  39 DEFINE_PER_CPU_SHARED_ALIGNED(struct tss_struct, init_tss) = INIT_TSS;
  40
  41 #ifdef CONFIG_X86_64
  42 static DEFINE_PER_CPU(unsigned char, is_idle);
  43 static ATOMIC_NOTIFIER_HEAD(idle_notifier);
  44
  45 void idle_notifier_register(struct notifier_block *n)
  46 {
  47         atomic_notifier_chain_register(&idle_notifier, n);
  48 }
  49 EXPORT_SYMBOL_GPL(idle_notifier_register);
  50
  51 void idle_notifier_unregister(struct notifier_block *n)
  52 {
  53         atomic_notifier_chain_unregister(&idle_notifier, n);
  54 }
  55 EXPORT_SYMBOL_GPL(idle_notifier_unregister);
  56 #endif
  57
  58 struct kmem_cache *task_xstate_cachep;
  59 EXPORT_SYMBOL_GPL(task_xstate_cachep);
  60
  61 /*
  62  * this gets called so that we can store lazy state into memory and copy the
  63  * current task into the new thread.
  64  */
  65 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
  66 {
  67         int ret;
  68
  69         *dst = *src;
  70         if (fpu_allocated(&src->thread.fpu)) {
  71                 memset(&dst->thread.fpu, 0, sizeof(dst->thread.fpu));
  72                 ret = fpu_alloc(&dst->thread.fpu);
  73                 if (ret)
  74                         return ret;
  75                 fpu_copy(dst, src);
  76         }
  77         return 0;
  78 }
  79
  80 void free_thread_xstate(struct task_struct *tsk)
  81 {
  82         fpu_free(&tsk->thread.fpu);
  83 }
  84
  85 void arch_release_task_struct(struct task_struct *tsk)
  86 {
  87         free_thread_xstate(tsk);
  88 }
  89
  90 void arch_task_cache_init(void)
  91 {
  92         task_xstate_cachep =
  93                 kmem_cache_create("task_xstate", xstate_size,
  94                                   __alignof__(union thread_xstate),
  95                                   SLAB_PANIC | SLAB_NOTRACK, NULL);
  96 }
  97
  98 /*
  99  * Free current thread data structures etc..
 100  */
 101 void exit_thread(void)
 102 {
 103         struct task_struct *me = current;
 104         struct thread_struct *t = &me->thread;
 105         unsigned long *bp = t->io_bitmap_ptr;
 106
 107         if (bp) {
 108                 struct tss_struct *tss = &per_cpu(init_tss, get_cpu());
 109
 110                 t->io_bitmap_ptr = NULL;
 111                 clear_thread_flag(TIF_IO_BITMAP);
 112                 /*
 113                  * Careful, clear this in the TSS too:
 114                  */
 115                 memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
 116                 t->io_bitmap_max = 0;
 117                 put_cpu();
 118                 kfree(bp);
 119         }
 120
 121         drop_fpu(me);
 122 }
 123
 124 void show_regs_common(void)
 125 {
 126         const char *vendor, *product, *board;
 127
 128         vendor = dmi_get_system_info(DMI_SYS_VENDOR);
 129         if (!vendor)
 130                 vendor = "";
 131         product = dmi_get_system_info(DMI_PRODUCT_NAME);
 132         if (!product)
 133                 product = "";
 134
 135         /* Board Name is optional */
 136         board = dmi_get_system_info(DMI_BOARD_NAME);
 137
 138         printk(KERN_DEFAULT "Pid: %d, comm: %.20s %s %s %.*s %s %s%s%s\n",
 139                current->pid, current->comm, print_tainted(),
 140                init_utsname()->release,
 141                (int)strcspn(init_utsname()->version, " "),
 142                init_utsname()->version,
 143                vendor, product,
 144                board ? "/" : "",
 145                board ? board : "");
 146 }
 147
 148 void flush_thread(void)
 149 {
 150         struct task_struct *tsk = current;
 151
 152         flush_ptrace_hw_breakpoint(tsk);
 153         memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
 154         drop_init_fpu(tsk);
 155         /*
 156          * Free the FPU state for non xsave platforms. They get reallocated
 157          * lazily at the first use.
 158          */
 159         if (!use_eager_fpu())
 160                 free_thread_xstate(tsk);
 161 }
 162
 163 static void hard_disable_TSC(void)
 164 {
 165         write_cr4(read_cr4() | X86_CR4_TSD);
 166 }
 167
 168 void disable_TSC(void)
 169 {
 170         preempt_disable();
 171         if (!test_and_set_thread_flag(TIF_NOTSC))
 172                 /*
 173                  * Must flip the CPU state synchronously with
 174                  * TIF_NOTSC in the current running context.
 175                  */
 176                 hard_disable_TSC();
 177         preempt_enable();
 178 }
 179
 180 static void hard_enable_TSC(void)
 181 {
 182         write_cr4(read_cr4() & ~X86_CR4_TSD);
 183 }
 184
 185 static void enable_TSC(void)
 186 {
 187         preempt_disable();
 188         if (test_and_clear_thread_flag(TIF_NOTSC))
 189                 /*
 190                  * Must flip the CPU state synchronously with
 191                  * TIF_NOTSC in the current running context.
 192                  */
 193                 hard_enable_TSC();
 194         preempt_enable();
 195 }
 196
 197 int get_tsc_mode(unsigned long adr)
 198 {
 199         unsigned int val;
 200
 201         if (test_thread_flag(TIF_NOTSC))
 202                 val = PR_TSC_SIGSEGV;
 203         else
 204                 val = PR_TSC_ENABLE;
 205
 206         return put_user(val, (unsigned int __user *)adr);
 207 }
 208
 209 int set_tsc_mode(unsigned int val)
 210 {
 211         if (val == PR_TSC_SIGSEGV)
 212                 disable_TSC();
 213         else if (val == PR_TSC_ENABLE)
 214                 enable_TSC();
 215         else
 216                 return -EINVAL;
 217
 218         return 0;
 219 }
 220
 221 void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
 222                       struct tss_struct *tss)
 223 {
 224         struct thread_struct *prev, *next;
 225
 226         prev = &prev_p->thread;
 227         next = &next_p->thread;
 228
 229         if (test_tsk_thread_flag(prev_p, TIF_BLOCKSTEP) ^
 230             test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) {
 231                 unsigned long debugctl = get_debugctlmsr();
 232
 233                 debugctl &= ~DEBUGCTLMSR_BTF;
 234                 if (test_tsk_thread_flag(next_p, TIF_BLOCKSTEP))
 235                         debugctl |= DEBUGCTLMSR_BTF;
 236
 237                 update_debugctlmsr(debugctl);
 238         }
 239
 240         if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^
 241             test_tsk_thread_flag(next_p, TIF_NOTSC)) {
 242                 /* prev and next are different */
 243                 if (test_tsk_thread_flag(next_p, TIF_NOTSC))
 244                         hard_disable_TSC();
 245                 else
 246                         hard_enable_TSC();
 247         }
 248
 249         if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) {
 250                 /*
 251                  * Copy the relevant range of the IO bitmap.
 252                  * Normally this is 128 bytes or less:
 253                  */
 254                 memcpy(tss->io_bitmap, next->io_bitmap_ptr,
 255                        max(prev->io_bitmap_max, next->io_bitmap_max));
 256         } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) {
 257                 /*
 258                  * Clear any possible leftover bits:
 259                  */
 260                 memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
 261         }
 262         propagate_user_return_notify(prev_p, next_p);
 263 }
 264
 265 /*
 266  * Idle related variables and functions
 267  */
 268 unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE;
 269 EXPORT_SYMBOL(boot_option_idle_override);
 270
 271 /*
 272  * Powermanagement idle function, if any..
 273  */
 274 void (*pm_idle)(void);
 275 #ifdef CONFIG_APM_MODULE
 276 EXPORT_SYMBOL(pm_idle);
 277 #endif
 278
 279 #ifndef CONFIG_SMP
 280 static inline void play_dead(void)
 281 {
 282         BUG();
 283 }
 284 #endif
 285
 286 #ifdef CONFIG_X86_64
 287 void enter_idle(void)
 288 {
 289         this_cpu_write(is_idle, 1);
 290         atomic_notifier_call_chain(&idle_notifier, IDLE_START, NULL);
 291 }
 292
 293 static void __exit_idle(void)
 294 {
 295         if (x86_test_and_clear_bit_percpu(0, is_idle) == 0)
 296                 return;
 297         atomic_notifier_call_chain(&idle_notifier, IDLE_END, NULL);
 298 }
 299
 300 /* Called from interrupts to signify idle end */
 301 void exit_idle(void)
 302 {
 303         /* idle loop has pid 0 */
 304         if (current->pid)
 305                 return;
 306         __exit_idle();
 307 }
 308 #endif
 309
 310 /*
 311  * The idle thread. There's no useful work to be
 312  * done, so just try to conserve power and have a
 313  * low exit latency (ie sit in a loop waiting for
 314  * somebody to say that they'd like to reschedule)
 315  */
 316 void cpu_idle(void)
 317 {
 318         /*
 319          * If we're the non-boot CPU, nothing set the stack canary up
 320          * for us.  CPU0 already has it initialized but no harm in
 321          * doing it again.  This is a good place for updating it, as
 322          * we wont ever return from this function (so the invalid
 323          * canaries already on the stack wont ever trigger).
 324          */
 325         boot_init_stack_canary();
 326         current_thread_info()->status |= TS_POLLING;
 327
 328         while (1) {
 329                 tick_nohz_idle_enter();
 330
 331                 while (!need_resched()) {
 332                         rmb();
 333
 334                         if (cpu_is_offline(smp_processor_id()))
 335                                 play_dead();
 336
 337                         /*
 338                          * Idle routines should keep interrupts disabled
 339                          * from here on, until they go to idle.
 340                          * Otherwise, idle callbacks can misfire.
 341                          */
 342                         local_touch_nmi();
 343                         local_irq_disable();
 344
 345                         enter_idle();
 346
 347                         /* Don't trace irqs off for idle */
 348                         stop_critical_timings();
 349
 350                         /* enter_idle() needs rcu for notifiers */
 351                         rcu_idle_enter();
 352
 353                         if (cpuidle_idle_call())
 354                                 pm_idle();
 355
 356                         rcu_idle_exit();
 357                         start_critical_timings();
 358
 359                         /* In many cases the interrupt that ended idle
 360                            has already called exit_idle. But some idle
 361                            loops can be woken up without interrupt. */
 362                         __exit_idle();
 363                 }
 364
 365                 tick_nohz_idle_exit();
 366                 preempt_enable_no_resched();
 367                 schedule();
 368                 preempt_disable();
 369         }
 370 }
 371
 372 /*
 373  * We use this if we don't have any better
 374  * idle routine..
 375  */
 376 void default_idle(void)
 377 {
 378         trace_power_start_rcuidle(POWER_CSTATE, 1, smp_processor_id());
 379         trace_cpu_idle_rcuidle(1, smp_processor_id());
 380         current_thread_info()->status &= ~TS_POLLING;
 381         /*
 382          * TS_POLLING-cleared state must be visible before we
 383          * test NEED_RESCHED:
 384          */
 385         smp_mb();
 386
 387         if (!need_resched())
 388                 safe_halt();    /* enables interrupts racelessly */
 389         else
 390                 local_irq_enable();
 391         current_thread_info()->status |= TS_POLLING;
 392         trace_power_end_rcuidle(smp_processor_id());
 393         trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
 394 }
 395 #ifdef CONFIG_APM_MODULE
 396 EXPORT_SYMBOL(default_idle);
 397 #endif
 398
 399 bool set_pm_idle_to_default(void)
 400 {
 401         bool ret = !!pm_idle;
 402
 403         pm_idle = default_idle;
 404
 405         return ret;
 406 }
 407 void stop_this_cpu(void *dummy)
 408 {
 409         local_irq_disable();
 410         /*
 411          * Remove this CPU:
 412          */
 413         set_cpu_online(smp_processor_id(), false);
 414         disable_local_APIC();
 415
 416         for (;;) {
 417                 if (hlt_works(smp_processor_id()))
 418                         halt();
 419         }
 420 }
 421
 422 /* Default MONITOR/MWAIT with no hints, used for default C1 state */
 423 static void mwait_idle(void)
 424 {
 425         if (!need_resched()) {
 426                 trace_power_start_rcuidle(POWER_CSTATE, 1, smp_processor_id());
 427                 trace_cpu_idle_rcuidle(1, smp_processor_id());
 428                 if (this_cpu_has(X86_FEATURE_CLFLUSH_MONITOR))
 429                         clflush((void *)&current_thread_info()->flags);
 430
 431                 __monitor((void *)&current_thread_info()->flags, 0, 0);
 432                 smp_mb();
 433                 if (!need_resched())
 434                         __sti_mwait(0, 0);
 435                 else
 436                         local_irq_enable();
 437                 trace_power_end_rcuidle(smp_processor_id());
 438                 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
 439         } else
 440                 local_irq_enable();
 441 }
 442
 443 /*
 444  * On SMP it's slightly faster (but much more power-consuming!)
 445  * to poll the ->work.need_resched flag instead of waiting for the
 446  * cross-CPU IPI to arrive. Use this option with caution.
 447  */
 448 static void poll_idle(void)
 449 {
 450         trace_power_start_rcuidle(POWER_CSTATE, 0, smp_processor_id());
 451         trace_cpu_idle_rcuidle(0, smp_processor_id());
 452         local_irq_enable();
 453         while (!need_resched())
 454                 cpu_relax();
 455         trace_power_end_rcuidle(smp_processor_id());
 456         trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
 457 }
 458
 459 /*
 460  * mwait selection logic:
 461  *
 462  * It depends on the CPU. For AMD CPUs that support MWAIT this is
 463  * wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings
 464  * then depend on a clock divisor and current Pstate of the core. If
 465  * all cores of a processor are in halt state (C1) the processor can
 466  * enter the C1E (C1 enhanced) state. If mwait is used this will never
 467  * happen.
 468  *
 469  * idle=mwait overrides this decision and forces the usage of mwait.
 470  */
 471
 472 #define MWAIT_INFO                      0x05
 473 #define MWAIT_ECX_EXTENDED_INFO         0x01
 474 #define MWAIT_EDX_C1                    0xf0
 475
 476 int mwait_usable(const struct cpuinfo_x86 *c)
 477 {
 478         u32 eax, ebx, ecx, edx;
 479
 480         /* Use mwait if idle=mwait boot option is given */
 481         if (boot_option_idle_override == IDLE_FORCE_MWAIT)
 482                 return 1;
 483
 484         /*
 485          * Any idle= boot option other than idle=mwait means that we must not
 486          * use mwait. Eg: idle=halt or idle=poll or idle=nomwait
 487          */
 488         if (boot_option_idle_override != IDLE_NO_OVERRIDE)
 489                 return 0;
 490
 491         if (c->cpuid_level < MWAIT_INFO)
 492                 return 0;
 493
 494         cpuid(MWAIT_INFO, &eax, &ebx, &ecx, &edx);
 495         /* Check, whether EDX has extended info about MWAIT */
 496         if (!(ecx & MWAIT_ECX_EXTENDED_INFO))
 497                 return 1;
 498
 499         /*
 500          * edx enumeratios MONITOR/MWAIT extensions. Check, whether
 501          * C1  supports MWAIT
 502          */
 503         return (edx & MWAIT_EDX_C1);
 504 }
 505
 506 bool amd_e400_c1e_detected;
 507 EXPORT_SYMBOL(amd_e400_c1e_detected);
 508
 509 static cpumask_var_t amd_e400_c1e_mask;
 510
 511 void amd_e400_remove_cpu(int cpu)
 512 {
 513         if (amd_e400_c1e_mask != NULL)
 514                 cpumask_clear_cpu(cpu, amd_e400_c1e_mask);
 515 }
 516
 517 /*
 518  * AMD Erratum 400 aware idle routine. We check for C1E active in the interrupt
 519  * pending message MSR. If we detect C1E, then we handle it the same
 520  * way as C3 power states (local apic timer and TSC stop)
 521  */
 522 static void amd_e400_idle(void)
 523 {
 524         if (need_resched())
 525                 return;
 526
 527         if (!amd_e400_c1e_detected) {
 528                 u32 lo, hi;
 529
 530                 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
 531
 532                 if (lo & K8_INTP_C1E_ACTIVE_MASK) {
 533                         amd_e400_c1e_detected = true;
 534                         if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
 535                                 mark_tsc_unstable("TSC halt in AMD C1E");
 536                         pr_info("System has AMD C1E enabled\n");
 537                 }
 538         }
 539
 540         if (amd_e400_c1e_detected) {
 541                 int cpu = smp_processor_id();
 542
 543                 if (!cpumask_test_cpu(cpu, amd_e400_c1e_mask)) {
 544                         cpumask_set_cpu(cpu, amd_e400_c1e_mask);
 545                         /*
 546                          * Force broadcast so ACPI can not interfere.
 547                          */
 548                         clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
 549                                            &cpu);
 550                         pr_info("Switch to broadcast mode on CPU%d\n", cpu);
 551                 }
 552                 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
 553
 554                 default_idle();
 555
 556                 /*
 557                  * The switch back from broadcast mode needs to be
 558                  * called with interrupts disabled.
 559                  */
 560                  local_irq_disable();
 561                  clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
 562                  local_irq_enable();
 563         } else
 564                 default_idle();
 565 }
 566
 567 void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c)
 568 {
 569 #ifdef CONFIG_SMP
 570         if (pm_idle == poll_idle && smp_num_siblings > 1) {
 571                 pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n");
 572         }
 573 #endif
 574         if (pm_idle)
 575                 return;
 576
 577         if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) {
 578                 /*
 579                  * One CPU supports mwait => All CPUs supports mwait
 580                  */
 581                 pr_info("using mwait in idle threads\n");
 582                 pm_idle = mwait_idle;
 583         } else if (cpu_has_amd_erratum(amd_erratum_400)) {
 584                 /* E400: APIC timer interrupt does not wake up CPU from C1e */
 585                 pr_info("using AMD E400 aware idle routine\n");
 586                 pm_idle = amd_e400_idle;
 587         } else
 588                 pm_idle = default_idle;
 589 }
 590
 591 void __init init_amd_e400_c1e_mask(void)
 592 {
 593         /* If we're using amd_e400_idle, we need to allocate amd_e400_c1e_mask. */
 594         if (pm_idle == amd_e400_idle)
 595                 zalloc_cpumask_var(&amd_e400_c1e_mask, GFP_KERNEL);
 596 }
 597
 598 static int __init idle_setup(char *str)
 599 {
 600         if (!str)
 601                 return -EINVAL;
 602
 603         if (!strcmp(str, "poll")) {
 604                 pr_info("using polling idle threads\n");
 605                 pm_idle = poll_idle;
 606                 boot_option_idle_override = IDLE_POLL;
 607         } else if (!strcmp(str, "mwait")) {
 608                 boot_option_idle_override = IDLE_FORCE_MWAIT;
 609                 WARN_ONCE(1, "\"idle=mwait\" will be removed in 2012\n");
 610         } else if (!strcmp(str, "halt")) {
 611                 /*
 612                  * When the boot option of idle=halt is added, halt is
 613                  * forced to be used for CPU idle. In such case CPU C2/C3
 614                  * won't be used again.
 615                  * To continue to load the CPU idle driver, don't touch
 616                  * the boot_option_idle_override.
 617                  */
 618                 pm_idle = default_idle;
 619                 boot_option_idle_override = IDLE_HALT;
 620         } else if (!strcmp(str, "nomwait")) {
 621                 /*
 622                  * If the boot option of "idle=nomwait" is added,
 623                  * it means that mwait will be disabled for CPU C2/C3
 624                  * states. In such case it won't touch the variable
 625                  * of boot_option_idle_override.
 626                  */
 627                 boot_option_idle_override = IDLE_NOMWAIT;
 628         } else
 629                 return -1;
 630
 631         return 0;
 632 }
 633 early_param("idle", idle_setup);
 634
 635 unsigned long arch_align_stack(unsigned long sp)
 636 {
 637         if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
 638                 sp -= get_random_int() % 8192;
 639         return sp & ~0xf;
 640 }
 641
 642 unsigned long arch_randomize_brk(struct mm_struct *mm)
 643 {
 644         unsigned long range_end = mm->brk + 0x02000000;
 645         return randomize_range(mm->brk, range_end, 0) ? : mm->brk;
 646 }
 647