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Linux 3.8-rc7
[cris-mirror.git] / arch / x86 / kvm / vmx.c
blob9120ae1901e42804828dbde5db41707c113b0cbc
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
19 #include "irq.h"
20 #include "mmu.h"
21 #include "cpuid.h"
22
23 #include <linux/kvm_host.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/mm.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/moduleparam.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/ftrace_event.h>
32 #include <linux/slab.h>
33 #include <linux/tboot.h>
34 #include "kvm_cache_regs.h"
35 #include "x86.h"
36
37 #include <asm/io.h>
38 #include <asm/desc.h>
39 #include <asm/vmx.h>
40 #include <asm/virtext.h>
41 #include <asm/mce.h>
42 #include <asm/i387.h>
43 #include <asm/xcr.h>
44 #include <asm/perf_event.h>
45 #include <asm/kexec.h>
46
47 #include "trace.h"
48
49 #define __ex(x) __kvm_handle_fault_on_reboot(x)
50 #define __ex_clear(x, reg) \
51 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
52
53 MODULE_AUTHOR("Qumranet");
54 MODULE_LICENSE("GPL");
55
56 static const struct x86_cpu_id vmx_cpu_id[] = {
57 X86_FEATURE_MATCH(X86_FEATURE_VMX),
58 {}
59 };
60 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
61
62 static bool __read_mostly enable_vpid = 1;
63 module_param_named(vpid, enable_vpid, bool, 0444);
64
65 static bool __read_mostly flexpriority_enabled = 1;
66 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
67
68 static bool __read_mostly enable_ept = 1;
69 module_param_named(ept, enable_ept, bool, S_IRUGO);
70
71 static bool __read_mostly enable_unrestricted_guest = 1;
72 module_param_named(unrestricted_guest,
73 enable_unrestricted_guest, bool, S_IRUGO);
74
75 static bool __read_mostly enable_ept_ad_bits = 1;
76 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
77
78 static bool __read_mostly emulate_invalid_guest_state = true;
79 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
80
81 static bool __read_mostly vmm_exclusive = 1;
82 module_param(vmm_exclusive, bool, S_IRUGO);
83
84 static bool __read_mostly fasteoi = 1;
85 module_param(fasteoi, bool, S_IRUGO);
86
87 /*
88 * If nested=1, nested virtualization is supported, i.e., guests may use
89 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
90 * use VMX instructions.
91 */
92 static bool __read_mostly nested = 0;
93 module_param(nested, bool, S_IRUGO);
94
95 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
96 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
97 #define KVM_GUEST_CR0_MASK \
98 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
99 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
100 (X86_CR0_WP | X86_CR0_NE)
101 #define KVM_VM_CR0_ALWAYS_ON \
102 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
103 #define KVM_CR4_GUEST_OWNED_BITS \
104 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
105 | X86_CR4_OSXMMEXCPT)
106
107 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
108 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
109
110 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
111
112 /*
113 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
114 * ple_gap: upper bound on the amount of time between two successive
115 * executions of PAUSE in a loop. Also indicate if ple enabled.
116 * According to test, this time is usually smaller than 128 cycles.
117 * ple_window: upper bound on the amount of time a guest is allowed to execute
118 * in a PAUSE loop. Tests indicate that most spinlocks are held for
119 * less than 2^12 cycles
120 * Time is measured based on a counter that runs at the same rate as the TSC,
121 * refer SDM volume 3b section 21.6.13 & 22.1.3.
122 */
123 #define KVM_VMX_DEFAULT_PLE_GAP 128
124 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
125 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
126 module_param(ple_gap, int, S_IRUGO);
127
128 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
129 module_param(ple_window, int, S_IRUGO);
130
131 extern const ulong vmx_return;
132
133 #define NR_AUTOLOAD_MSRS 8
134 #define VMCS02_POOL_SIZE 1
135
136 struct vmcs {
137 u32 revision_id;
138 u32 abort;
139 char data[0];
140 };
141
142 /*
143 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
144 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
145 * loaded on this CPU (so we can clear them if the CPU goes down).
146 */
147 struct loaded_vmcs {
148 struct vmcs *vmcs;
149 int cpu;
150 int launched;
151 struct list_head loaded_vmcss_on_cpu_link;
152 };
153
154 struct shared_msr_entry {
155 unsigned index;
156 u64 data;
157 u64 mask;
158 };
159
160 /*
161 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
162 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
163 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
164 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
165 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
166 * More than one of these structures may exist, if L1 runs multiple L2 guests.
167 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
168 * underlying hardware which will be used to run L2.
169 * This structure is packed to ensure that its layout is identical across
170 * machines (necessary for live migration).
171 * If there are changes in this struct, VMCS12_REVISION must be changed.
172 */
173 typedef u64 natural_width;
174 struct __packed vmcs12 {
175 /* According to the Intel spec, a VMCS region must start with the
176 * following two fields. Then follow implementation-specific data.
177 */
178 u32 revision_id;
179 u32 abort;
180
181 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
182 u32 padding[7]; /* room for future expansion */
183
184 u64 io_bitmap_a;
185 u64 io_bitmap_b;
186 u64 msr_bitmap;
187 u64 vm_exit_msr_store_addr;
188 u64 vm_exit_msr_load_addr;
189 u64 vm_entry_msr_load_addr;
190 u64 tsc_offset;
191 u64 virtual_apic_page_addr;
192 u64 apic_access_addr;
193 u64 ept_pointer;
194 u64 guest_physical_address;
195 u64 vmcs_link_pointer;
196 u64 guest_ia32_debugctl;
197 u64 guest_ia32_pat;
198 u64 guest_ia32_efer;
199 u64 guest_ia32_perf_global_ctrl;
200 u64 guest_pdptr0;
201 u64 guest_pdptr1;
202 u64 guest_pdptr2;
203 u64 guest_pdptr3;
204 u64 host_ia32_pat;
205 u64 host_ia32_efer;
206 u64 host_ia32_perf_global_ctrl;
207 u64 padding64[8]; /* room for future expansion */
208 /*
209 * To allow migration of L1 (complete with its L2 guests) between
210 * machines of different natural widths (32 or 64 bit), we cannot have
211 * unsigned long fields with no explict size. We use u64 (aliased
212 * natural_width) instead. Luckily, x86 is little-endian.
213 */
214 natural_width cr0_guest_host_mask;
215 natural_width cr4_guest_host_mask;
216 natural_width cr0_read_shadow;
217 natural_width cr4_read_shadow;
218 natural_width cr3_target_value0;
219 natural_width cr3_target_value1;
220 natural_width cr3_target_value2;
221 natural_width cr3_target_value3;
222 natural_width exit_qualification;
223 natural_width guest_linear_address;
224 natural_width guest_cr0;
225 natural_width guest_cr3;
226 natural_width guest_cr4;
227 natural_width guest_es_base;
228 natural_width guest_cs_base;
229 natural_width guest_ss_base;
230 natural_width guest_ds_base;
231 natural_width guest_fs_base;
232 natural_width guest_gs_base;
233 natural_width guest_ldtr_base;
234 natural_width guest_tr_base;
235 natural_width guest_gdtr_base;
236 natural_width guest_idtr_base;
237 natural_width guest_dr7;
238 natural_width guest_rsp;
239 natural_width guest_rip;
240 natural_width guest_rflags;
241 natural_width guest_pending_dbg_exceptions;
242 natural_width guest_sysenter_esp;
243 natural_width guest_sysenter_eip;
244 natural_width host_cr0;
245 natural_width host_cr3;
246 natural_width host_cr4;
247 natural_width host_fs_base;
248 natural_width host_gs_base;
249 natural_width host_tr_base;
250 natural_width host_gdtr_base;
251 natural_width host_idtr_base;
252 natural_width host_ia32_sysenter_esp;
253 natural_width host_ia32_sysenter_eip;
254 natural_width host_rsp;
255 natural_width host_rip;
256 natural_width paddingl[8]; /* room for future expansion */
257 u32 pin_based_vm_exec_control;
258 u32 cpu_based_vm_exec_control;
259 u32 exception_bitmap;
260 u32 page_fault_error_code_mask;
261 u32 page_fault_error_code_match;
262 u32 cr3_target_count;
263 u32 vm_exit_controls;
264 u32 vm_exit_msr_store_count;
265 u32 vm_exit_msr_load_count;
266 u32 vm_entry_controls;
267 u32 vm_entry_msr_load_count;
268 u32 vm_entry_intr_info_field;
269 u32 vm_entry_exception_error_code;
270 u32 vm_entry_instruction_len;
271 u32 tpr_threshold;
272 u32 secondary_vm_exec_control;
273 u32 vm_instruction_error;
274 u32 vm_exit_reason;
275 u32 vm_exit_intr_info;
276 u32 vm_exit_intr_error_code;
277 u32 idt_vectoring_info_field;
278 u32 idt_vectoring_error_code;
279 u32 vm_exit_instruction_len;
280 u32 vmx_instruction_info;
281 u32 guest_es_limit;
282 u32 guest_cs_limit;
283 u32 guest_ss_limit;
284 u32 guest_ds_limit;
285 u32 guest_fs_limit;
286 u32 guest_gs_limit;
287 u32 guest_ldtr_limit;
288 u32 guest_tr_limit;
289 u32 guest_gdtr_limit;
290 u32 guest_idtr_limit;
291 u32 guest_es_ar_bytes;
292 u32 guest_cs_ar_bytes;
293 u32 guest_ss_ar_bytes;
294 u32 guest_ds_ar_bytes;
295 u32 guest_fs_ar_bytes;
296 u32 guest_gs_ar_bytes;
297 u32 guest_ldtr_ar_bytes;
298 u32 guest_tr_ar_bytes;
299 u32 guest_interruptibility_info;
300 u32 guest_activity_state;
301 u32 guest_sysenter_cs;
302 u32 host_ia32_sysenter_cs;
303 u32 padding32[8]; /* room for future expansion */
304 u16 virtual_processor_id;
305 u16 guest_es_selector;
306 u16 guest_cs_selector;
307 u16 guest_ss_selector;
308 u16 guest_ds_selector;
309 u16 guest_fs_selector;
310 u16 guest_gs_selector;
311 u16 guest_ldtr_selector;
312 u16 guest_tr_selector;
313 u16 host_es_selector;
314 u16 host_cs_selector;
315 u16 host_ss_selector;
316 u16 host_ds_selector;
317 u16 host_fs_selector;
318 u16 host_gs_selector;
319 u16 host_tr_selector;
320 };
321
322 /*
323 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
324 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
325 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
326 */
327 #define VMCS12_REVISION 0x11e57ed0
328
329 /*
330 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
331 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
332 * current implementation, 4K are reserved to avoid future complications.
333 */
334 #define VMCS12_SIZE 0x1000
335
336 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
337 struct vmcs02_list {
338 struct list_head list;
339 gpa_t vmptr;
340 struct loaded_vmcs vmcs02;
341 };
342
343 /*
344 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
345 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
346 */
347 struct nested_vmx {
348 /* Has the level1 guest done vmxon? */
349 bool vmxon;
350
351 /* The guest-physical address of the current VMCS L1 keeps for L2 */
352 gpa_t current_vmptr;
353 /* The host-usable pointer to the above */
354 struct page *current_vmcs12_page;
355 struct vmcs12 *current_vmcs12;
356
357 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
358 struct list_head vmcs02_pool;
359 int vmcs02_num;
360 u64 vmcs01_tsc_offset;
361 /* L2 must run next, and mustn't decide to exit to L1. */
362 bool nested_run_pending;
363 /*
364 * Guest pages referred to in vmcs02 with host-physical pointers, so
365 * we must keep them pinned while L2 runs.
366 */
367 struct page *apic_access_page;
368 };
369
370 struct vcpu_vmx {
371 struct kvm_vcpu vcpu;
372 unsigned long host_rsp;
373 u8 fail;
374 u8 cpl;
375 bool nmi_known_unmasked;
376 u32 exit_intr_info;
377 u32 idt_vectoring_info;
378 ulong rflags;
379 struct shared_msr_entry *guest_msrs;
380 int nmsrs;
381 int save_nmsrs;
382 #ifdef CONFIG_X86_64
383 u64 msr_host_kernel_gs_base;
384 u64 msr_guest_kernel_gs_base;
385 #endif
386 /*
387 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
388 * non-nested (L1) guest, it always points to vmcs01. For a nested
389 * guest (L2), it points to a different VMCS.
390 */
391 struct loaded_vmcs vmcs01;
392 struct loaded_vmcs *loaded_vmcs;
393 bool __launched; /* temporary, used in vmx_vcpu_run */
394 struct msr_autoload {
395 unsigned nr;
396 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
397 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
398 } msr_autoload;
399 struct {
400 int loaded;
401 u16 fs_sel, gs_sel, ldt_sel;
402 #ifdef CONFIG_X86_64
403 u16 ds_sel, es_sel;
404 #endif
405 int gs_ldt_reload_needed;
406 int fs_reload_needed;
407 } host_state;
408 struct {
409 int vm86_active;
410 ulong save_rflags;
411 struct kvm_segment segs[8];
412 } rmode;
413 struct {
414 u32 bitmask; /* 4 bits per segment (1 bit per field) */
415 struct kvm_save_segment {
416 u16 selector;
417 unsigned long base;
418 u32 limit;
419 u32 ar;
420 } seg[8];
421 } segment_cache;
422 int vpid;
423 bool emulation_required;
424
425 /* Support for vnmi-less CPUs */
426 int soft_vnmi_blocked;
427 ktime_t entry_time;
428 s64 vnmi_blocked_time;
429 u32 exit_reason;
430
431 bool rdtscp_enabled;
432
433 /* Support for a guest hypervisor (nested VMX) */
434 struct nested_vmx nested;
435 };
436
437 enum segment_cache_field {
438 SEG_FIELD_SEL = 0,
439 SEG_FIELD_BASE = 1,
440 SEG_FIELD_LIMIT = 2,
441 SEG_FIELD_AR = 3,
442
443 SEG_FIELD_NR = 4
444 };
445
446 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
447 {
448 return container_of(vcpu, struct vcpu_vmx, vcpu);
449 }
450
451 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
452 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
453 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
454 [number##_HIGH] = VMCS12_OFFSET(name)+4
455
456 static const unsigned short vmcs_field_to_offset_table[] = {
457 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
458 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
459 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
460 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
461 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
462 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
463 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
464 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
465 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
466 FIELD(HOST_ES_SELECTOR, host_es_selector),
467 FIELD(HOST_CS_SELECTOR, host_cs_selector),
468 FIELD(HOST_SS_SELECTOR, host_ss_selector),
469 FIELD(HOST_DS_SELECTOR, host_ds_selector),
470 FIELD(HOST_FS_SELECTOR, host_fs_selector),
471 FIELD(HOST_GS_SELECTOR, host_gs_selector),
472 FIELD(HOST_TR_SELECTOR, host_tr_selector),
473 FIELD64(IO_BITMAP_A, io_bitmap_a),
474 FIELD64(IO_BITMAP_B, io_bitmap_b),
475 FIELD64(MSR_BITMAP, msr_bitmap),
476 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
477 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
478 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
479 FIELD64(TSC_OFFSET, tsc_offset),
480 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
481 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
482 FIELD64(EPT_POINTER, ept_pointer),
483 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
484 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
485 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
486 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
487 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
488 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
489 FIELD64(GUEST_PDPTR0, guest_pdptr0),
490 FIELD64(GUEST_PDPTR1, guest_pdptr1),
491 FIELD64(GUEST_PDPTR2, guest_pdptr2),
492 FIELD64(GUEST_PDPTR3, guest_pdptr3),
493 FIELD64(HOST_IA32_PAT, host_ia32_pat),
494 FIELD64(HOST_IA32_EFER, host_ia32_efer),
495 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
496 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
497 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
498 FIELD(EXCEPTION_BITMAP, exception_bitmap),
499 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
500 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
501 FIELD(CR3_TARGET_COUNT, cr3_target_count),
502 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
503 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
504 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
505 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
506 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
507 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
508 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
509 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
510 FIELD(TPR_THRESHOLD, tpr_threshold),
511 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
512 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
513 FIELD(VM_EXIT_REASON, vm_exit_reason),
514 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
515 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
516 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
517 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
518 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
519 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
520 FIELD(GUEST_ES_LIMIT, guest_es_limit),
521 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
522 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
523 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
524 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
525 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
526 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
527 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
528 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
529 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
530 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
531 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
532 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
533 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
534 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
535 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
536 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
537 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
538 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
539 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
540 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
541 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
542 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
543 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
544 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
545 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
546 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
547 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
548 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
549 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
550 FIELD(EXIT_QUALIFICATION, exit_qualification),
551 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
552 FIELD(GUEST_CR0, guest_cr0),
553 FIELD(GUEST_CR3, guest_cr3),
554 FIELD(GUEST_CR4, guest_cr4),
555 FIELD(GUEST_ES_BASE, guest_es_base),
556 FIELD(GUEST_CS_BASE, guest_cs_base),
557 FIELD(GUEST_SS_BASE, guest_ss_base),
558 FIELD(GUEST_DS_BASE, guest_ds_base),
559 FIELD(GUEST_FS_BASE, guest_fs_base),
560 FIELD(GUEST_GS_BASE, guest_gs_base),
561 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
562 FIELD(GUEST_TR_BASE, guest_tr_base),
563 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
564 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
565 FIELD(GUEST_DR7, guest_dr7),
566 FIELD(GUEST_RSP, guest_rsp),
567 FIELD(GUEST_RIP, guest_rip),
568 FIELD(GUEST_RFLAGS, guest_rflags),
569 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
570 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
571 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
572 FIELD(HOST_CR0, host_cr0),
573 FIELD(HOST_CR3, host_cr3),
574 FIELD(HOST_CR4, host_cr4),
575 FIELD(HOST_FS_BASE, host_fs_base),
576 FIELD(HOST_GS_BASE, host_gs_base),
577 FIELD(HOST_TR_BASE, host_tr_base),
578 FIELD(HOST_GDTR_BASE, host_gdtr_base),
579 FIELD(HOST_IDTR_BASE, host_idtr_base),
580 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
581 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
582 FIELD(HOST_RSP, host_rsp),
583 FIELD(HOST_RIP, host_rip),
584 };
585 static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
586
587 static inline short vmcs_field_to_offset(unsigned long field)
588 {
589 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
590 return -1;
591 return vmcs_field_to_offset_table[field];
592 }
593
594 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
595 {
596 return to_vmx(vcpu)->nested.current_vmcs12;
597 }
598
599 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
600 {
601 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
602 if (is_error_page(page))
603 return NULL;
604
605 return page;
606 }
607
608 static void nested_release_page(struct page *page)
609 {
610 kvm_release_page_dirty(page);
611 }
612
613 static void nested_release_page_clean(struct page *page)
614 {
615 kvm_release_page_clean(page);
616 }
617
618 static u64 construct_eptp(unsigned long root_hpa);
619 static void kvm_cpu_vmxon(u64 addr);
620 static void kvm_cpu_vmxoff(void);
621 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
622 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
623 static void vmx_set_segment(struct kvm_vcpu *vcpu,
624 struct kvm_segment *var, int seg);
625 static void vmx_get_segment(struct kvm_vcpu *vcpu,
626 struct kvm_segment *var, int seg);
627
628 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
629 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
630 /*
631 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
632 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
633 */
634 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
635 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
636
637 static unsigned long *vmx_io_bitmap_a;
638 static unsigned long *vmx_io_bitmap_b;
639 static unsigned long *vmx_msr_bitmap_legacy;
640 static unsigned long *vmx_msr_bitmap_longmode;
641
642 static bool cpu_has_load_ia32_efer;
643 static bool cpu_has_load_perf_global_ctrl;
644
645 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
646 static DEFINE_SPINLOCK(vmx_vpid_lock);
647
648 static struct vmcs_config {
649 int size;
650 int order;
651 u32 revision_id;
652 u32 pin_based_exec_ctrl;
653 u32 cpu_based_exec_ctrl;
654 u32 cpu_based_2nd_exec_ctrl;
655 u32 vmexit_ctrl;
656 u32 vmentry_ctrl;
657 } vmcs_config;
658
659 static struct vmx_capability {
660 u32 ept;
661 u32 vpid;
662 } vmx_capability;
663
664 #define VMX_SEGMENT_FIELD(seg) \
665 [VCPU_SREG_##seg] = { \
666 .selector = GUEST_##seg##_SELECTOR, \
667 .base = GUEST_##seg##_BASE, \
668 .limit = GUEST_##seg##_LIMIT, \
669 .ar_bytes = GUEST_##seg##_AR_BYTES, \
670 }
671
672 static const struct kvm_vmx_segment_field {
673 unsigned selector;
674 unsigned base;
675 unsigned limit;
676 unsigned ar_bytes;
677 } kvm_vmx_segment_fields[] = {
678 VMX_SEGMENT_FIELD(CS),
679 VMX_SEGMENT_FIELD(DS),
680 VMX_SEGMENT_FIELD(ES),
681 VMX_SEGMENT_FIELD(FS),
682 VMX_SEGMENT_FIELD(GS),
683 VMX_SEGMENT_FIELD(SS),
684 VMX_SEGMENT_FIELD(TR),
685 VMX_SEGMENT_FIELD(LDTR),
686 };
687
688 static u64 host_efer;
689
690 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
691
692 /*
693 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
694 * away by decrementing the array size.
695 */
696 static const u32 vmx_msr_index[] = {
697 #ifdef CONFIG_X86_64
698 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
699 #endif
700 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
701 };
702 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
703
704 static inline bool is_page_fault(u32 intr_info)
705 {
706 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
707 INTR_INFO_VALID_MASK)) ==
708 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
709 }
710
711 static inline bool is_no_device(u32 intr_info)
712 {
713 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
714 INTR_INFO_VALID_MASK)) ==
715 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
716 }
717
718 static inline bool is_invalid_opcode(u32 intr_info)
719 {
720 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
721 INTR_INFO_VALID_MASK)) ==
722 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
723 }
724
725 static inline bool is_external_interrupt(u32 intr_info)
726 {
727 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
728 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
729 }
730
731 static inline bool is_machine_check(u32 intr_info)
732 {
733 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
734 INTR_INFO_VALID_MASK)) ==
735 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
736 }
737
738 static inline bool cpu_has_vmx_msr_bitmap(void)
739 {
740 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
741 }
742
743 static inline bool cpu_has_vmx_tpr_shadow(void)
744 {
745 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
746 }
747
748 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
749 {
750 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
751 }
752
753 static inline bool cpu_has_secondary_exec_ctrls(void)
754 {
755 return vmcs_config.cpu_based_exec_ctrl &
756 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
757 }
758
759 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
760 {
761 return vmcs_config.cpu_based_2nd_exec_ctrl &
762 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
763 }
764
765 static inline bool cpu_has_vmx_flexpriority(void)
766 {
767 return cpu_has_vmx_tpr_shadow() &&
768 cpu_has_vmx_virtualize_apic_accesses();
769 }
770
771 static inline bool cpu_has_vmx_ept_execute_only(void)
772 {
773 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
774 }
775
776 static inline bool cpu_has_vmx_eptp_uncacheable(void)
777 {
778 return vmx_capability.ept & VMX_EPTP_UC_BIT;
779 }
780
781 static inline bool cpu_has_vmx_eptp_writeback(void)
782 {
783 return vmx_capability.ept & VMX_EPTP_WB_BIT;
784 }
785
786 static inline bool cpu_has_vmx_ept_2m_page(void)
787 {
788 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
789 }
790
791 static inline bool cpu_has_vmx_ept_1g_page(void)
792 {
793 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
794 }
795
796 static inline bool cpu_has_vmx_ept_4levels(void)
797 {
798 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
799 }
800
801 static inline bool cpu_has_vmx_ept_ad_bits(void)
802 {
803 return vmx_capability.ept & VMX_EPT_AD_BIT;
804 }
805
806 static inline bool cpu_has_vmx_invept_context(void)
807 {
808 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
809 }
810
811 static inline bool cpu_has_vmx_invept_global(void)
812 {
813 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
814 }
815
816 static inline bool cpu_has_vmx_invvpid_single(void)
817 {
818 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
819 }
820
821 static inline bool cpu_has_vmx_invvpid_global(void)
822 {
823 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
824 }
825
826 static inline bool cpu_has_vmx_ept(void)
827 {
828 return vmcs_config.cpu_based_2nd_exec_ctrl &
829 SECONDARY_EXEC_ENABLE_EPT;
830 }
831
832 static inline bool cpu_has_vmx_unrestricted_guest(void)
833 {
834 return vmcs_config.cpu_based_2nd_exec_ctrl &
835 SECONDARY_EXEC_UNRESTRICTED_GUEST;
836 }
837
838 static inline bool cpu_has_vmx_ple(void)
839 {
840 return vmcs_config.cpu_based_2nd_exec_ctrl &
841 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
842 }
843
844 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
845 {
846 return flexpriority_enabled && irqchip_in_kernel(kvm);
847 }
848
849 static inline bool cpu_has_vmx_vpid(void)
850 {
851 return vmcs_config.cpu_based_2nd_exec_ctrl &
852 SECONDARY_EXEC_ENABLE_VPID;
853 }
854
855 static inline bool cpu_has_vmx_rdtscp(void)
856 {
857 return vmcs_config.cpu_based_2nd_exec_ctrl &
858 SECONDARY_EXEC_RDTSCP;
859 }
860
861 static inline bool cpu_has_vmx_invpcid(void)
862 {
863 return vmcs_config.cpu_based_2nd_exec_ctrl &
864 SECONDARY_EXEC_ENABLE_INVPCID;
865 }
866
867 static inline bool cpu_has_virtual_nmis(void)
868 {
869 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
870 }
871
872 static inline bool cpu_has_vmx_wbinvd_exit(void)
873 {
874 return vmcs_config.cpu_based_2nd_exec_ctrl &
875 SECONDARY_EXEC_WBINVD_EXITING;
876 }
877
878 static inline bool report_flexpriority(void)
879 {
880 return flexpriority_enabled;
881 }
882
883 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
884 {
885 return vmcs12->cpu_based_vm_exec_control & bit;
886 }
887
888 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
889 {
890 return (vmcs12->cpu_based_vm_exec_control &
891 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
892 (vmcs12->secondary_vm_exec_control & bit);
893 }
894
895 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
896 struct kvm_vcpu *vcpu)
897 {
898 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
899 }
900
901 static inline bool is_exception(u32 intr_info)
902 {
903 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
904 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
905 }
906
907 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
908 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
909 struct vmcs12 *vmcs12,
910 u32 reason, unsigned long qualification);
911
912 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
913 {
914 int i;
915
916 for (i = 0; i < vmx->nmsrs; ++i)
917 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
918 return i;
919 return -1;
920 }
921
922 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
923 {
924 struct {
925 u64 vpid : 16;
926 u64 rsvd : 48;
927 u64 gva;
928 } operand = { vpid, 0, gva };
929
930 asm volatile (__ex(ASM_VMX_INVVPID)
931 /* CF==1 or ZF==1 --> rc = -1 */
932 "; ja 1f ; ud2 ; 1:"
933 : : "a"(&operand), "c"(ext) : "cc", "memory");
934 }
935
936 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
937 {
938 struct {
939 u64 eptp, gpa;
940 } operand = {eptp, gpa};
941
942 asm volatile (__ex(ASM_VMX_INVEPT)
943 /* CF==1 or ZF==1 --> rc = -1 */
944 "; ja 1f ; ud2 ; 1:\n"
945 : : "a" (&operand), "c" (ext) : "cc", "memory");
946 }
947
948 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
949 {
950 int i;
951
952 i = __find_msr_index(vmx, msr);
953 if (i >= 0)
954 return &vmx->guest_msrs[i];
955 return NULL;
956 }
957
958 static void vmcs_clear(struct vmcs *vmcs)
959 {
960 u64 phys_addr = __pa(vmcs);
961 u8 error;
962
963 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
964 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
965 : "cc", "memory");
966 if (error)
967 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
968 vmcs, phys_addr);
969 }
970
971 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
972 {
973 vmcs_clear(loaded_vmcs->vmcs);
974 loaded_vmcs->cpu = -1;
975 loaded_vmcs->launched = 0;
976 }
977
978 static void vmcs_load(struct vmcs *vmcs)
979 {
980 u64 phys_addr = __pa(vmcs);
981 u8 error;
982
983 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
984 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
985 : "cc", "memory");
986 if (error)
987 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
988 vmcs, phys_addr);
989 }
990
991 #ifdef CONFIG_KEXEC
992 /*
993 * This bitmap is used to indicate whether the vmclear
994 * operation is enabled on all cpus. All disabled by
995 * default.
996 */
997 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
998
999 static inline void crash_enable_local_vmclear(int cpu)
1000 {
1001 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1002 }
1003
1004 static inline void crash_disable_local_vmclear(int cpu)
1005 {
1006 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1007 }
1008
1009 static inline int crash_local_vmclear_enabled(int cpu)
1010 {
1011 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1012 }
1013
1014 static void crash_vmclear_local_loaded_vmcss(void)
1015 {
1016 int cpu = raw_smp_processor_id();
1017 struct loaded_vmcs *v;
1018
1019 if (!crash_local_vmclear_enabled(cpu))
1020 return;
1021
1022 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1023 loaded_vmcss_on_cpu_link)
1024 vmcs_clear(v->vmcs);
1025 }
1026 #else
1027 static inline void crash_enable_local_vmclear(int cpu) { }
1028 static inline void crash_disable_local_vmclear(int cpu) { }
1029 #endif /* CONFIG_KEXEC */
1030
1031 static void __loaded_vmcs_clear(void *arg)
1032 {
1033 struct loaded_vmcs *loaded_vmcs = arg;
1034 int cpu = raw_smp_processor_id();
1035
1036 if (loaded_vmcs->cpu != cpu)
1037 return; /* vcpu migration can race with cpu offline */
1038 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1039 per_cpu(current_vmcs, cpu) = NULL;
1040 crash_disable_local_vmclear(cpu);
1041 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1042
1043 /*
1044 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1045 * is before setting loaded_vmcs->vcpu to -1 which is done in
1046 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1047 * then adds the vmcs into percpu list before it is deleted.
1048 */
1049 smp_wmb();
1050
1051 loaded_vmcs_init(loaded_vmcs);
1052 crash_enable_local_vmclear(cpu);
1053 }
1054
1055 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1056 {
1057 int cpu = loaded_vmcs->cpu;
1058
1059 if (cpu != -1)
1060 smp_call_function_single(cpu,
1061 __loaded_vmcs_clear, loaded_vmcs, 1);
1062 }
1063
1064 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
1065 {
1066 if (vmx->vpid == 0)
1067 return;
1068
1069 if (cpu_has_vmx_invvpid_single())
1070 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
1071 }
1072
1073 static inline void vpid_sync_vcpu_global(void)
1074 {
1075 if (cpu_has_vmx_invvpid_global())
1076 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1077 }
1078
1079 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1080 {
1081 if (cpu_has_vmx_invvpid_single())
1082 vpid_sync_vcpu_single(vmx);
1083 else
1084 vpid_sync_vcpu_global();
1085 }
1086
1087 static inline void ept_sync_global(void)
1088 {
1089 if (cpu_has_vmx_invept_global())
1090 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1091 }
1092
1093 static inline void ept_sync_context(u64 eptp)
1094 {
1095 if (enable_ept) {
1096 if (cpu_has_vmx_invept_context())
1097 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1098 else
1099 ept_sync_global();
1100 }
1101 }
1102
1103 static __always_inline unsigned long vmcs_readl(unsigned long field)
1104 {
1105 unsigned long value;
1106
1107 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1108 : "=a"(value) : "d"(field) : "cc");
1109 return value;
1110 }
1111
1112 static __always_inline u16 vmcs_read16(unsigned long field)
1113 {
1114 return vmcs_readl(field);
1115 }
1116
1117 static __always_inline u32 vmcs_read32(unsigned long field)
1118 {
1119 return vmcs_readl(field);
1120 }
1121
1122 static __always_inline u64 vmcs_read64(unsigned long field)
1123 {
1124 #ifdef CONFIG_X86_64
1125 return vmcs_readl(field);
1126 #else
1127 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1128 #endif
1129 }
1130
1131 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1132 {
1133 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1134 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1135 dump_stack();
1136 }
1137
1138 static void vmcs_writel(unsigned long field, unsigned long value)
1139 {
1140 u8 error;
1141
1142 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1143 : "=q"(error) : "a"(value), "d"(field) : "cc");
1144 if (unlikely(error))
1145 vmwrite_error(field, value);
1146 }
1147
1148 static void vmcs_write16(unsigned long field, u16 value)
1149 {
1150 vmcs_writel(field, value);
1151 }
1152
1153 static void vmcs_write32(unsigned long field, u32 value)
1154 {
1155 vmcs_writel(field, value);
1156 }
1157
1158 static void vmcs_write64(unsigned long field, u64 value)
1159 {
1160 vmcs_writel(field, value);
1161 #ifndef CONFIG_X86_64
1162 asm volatile ("");
1163 vmcs_writel(field+1, value >> 32);
1164 #endif
1165 }
1166
1167 static void vmcs_clear_bits(unsigned long field, u32 mask)
1168 {
1169 vmcs_writel(field, vmcs_readl(field) & ~mask);
1170 }
1171
1172 static void vmcs_set_bits(unsigned long field, u32 mask)
1173 {
1174 vmcs_writel(field, vmcs_readl(field) | mask);
1175 }
1176
1177 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1178 {
1179 vmx->segment_cache.bitmask = 0;
1180 }
1181
1182 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1183 unsigned field)
1184 {
1185 bool ret;
1186 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1187
1188 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1189 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1190 vmx->segment_cache.bitmask = 0;
1191 }
1192 ret = vmx->segment_cache.bitmask & mask;
1193 vmx->segment_cache.bitmask |= mask;
1194 return ret;
1195 }
1196
1197 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1198 {
1199 u16 *p = &vmx->segment_cache.seg[seg].selector;
1200
1201 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1202 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1203 return *p;
1204 }
1205
1206 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1207 {
1208 ulong *p = &vmx->segment_cache.seg[seg].base;
1209
1210 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1211 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1212 return *p;
1213 }
1214
1215 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1216 {
1217 u32 *p = &vmx->segment_cache.seg[seg].limit;
1218
1219 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1220 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1221 return *p;
1222 }
1223
1224 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1225 {
1226 u32 *p = &vmx->segment_cache.seg[seg].ar;
1227
1228 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1229 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1230 return *p;
1231 }
1232
1233 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1234 {
1235 u32 eb;
1236
1237 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1238 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1239 if ((vcpu->guest_debug &
1240 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1241 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1242 eb |= 1u << BP_VECTOR;
1243 if (to_vmx(vcpu)->rmode.vm86_active)
1244 eb = ~0;
1245 if (enable_ept)
1246 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1247 if (vcpu->fpu_active)
1248 eb &= ~(1u << NM_VECTOR);
1249
1250 /* When we are running a nested L2 guest and L1 specified for it a
1251 * certain exception bitmap, we must trap the same exceptions and pass
1252 * them to L1. When running L2, we will only handle the exceptions
1253 * specified above if L1 did not want them.
1254 */
1255 if (is_guest_mode(vcpu))
1256 eb |= get_vmcs12(vcpu)->exception_bitmap;
1257
1258 vmcs_write32(EXCEPTION_BITMAP, eb);
1259 }
1260
1261 static void clear_atomic_switch_msr_special(unsigned long entry,
1262 unsigned long exit)
1263 {
1264 vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1265 vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1266 }
1267
1268 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1269 {
1270 unsigned i;
1271 struct msr_autoload *m = &vmx->msr_autoload;
1272
1273 switch (msr) {
1274 case MSR_EFER:
1275 if (cpu_has_load_ia32_efer) {
1276 clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1277 VM_EXIT_LOAD_IA32_EFER);
1278 return;
1279 }
1280 break;
1281 case MSR_CORE_PERF_GLOBAL_CTRL:
1282 if (cpu_has_load_perf_global_ctrl) {
1283 clear_atomic_switch_msr_special(
1284 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1285 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1286 return;
1287 }
1288 break;
1289 }
1290
1291 for (i = 0; i < m->nr; ++i)
1292 if (m->guest[i].index == msr)
1293 break;
1294
1295 if (i == m->nr)
1296 return;
1297 --m->nr;
1298 m->guest[i] = m->guest[m->nr];
1299 m->host[i] = m->host[m->nr];
1300 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1301 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1302 }
1303
1304 static void add_atomic_switch_msr_special(unsigned long entry,
1305 unsigned long exit, unsigned long guest_val_vmcs,
1306 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1307 {
1308 vmcs_write64(guest_val_vmcs, guest_val);
1309 vmcs_write64(host_val_vmcs, host_val);
1310 vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1311 vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1312 }
1313
1314 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1315 u64 guest_val, u64 host_val)
1316 {
1317 unsigned i;
1318 struct msr_autoload *m = &vmx->msr_autoload;
1319
1320 switch (msr) {
1321 case MSR_EFER:
1322 if (cpu_has_load_ia32_efer) {
1323 add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1324 VM_EXIT_LOAD_IA32_EFER,
1325 GUEST_IA32_EFER,
1326 HOST_IA32_EFER,
1327 guest_val, host_val);
1328 return;
1329 }
1330 break;
1331 case MSR_CORE_PERF_GLOBAL_CTRL:
1332 if (cpu_has_load_perf_global_ctrl) {
1333 add_atomic_switch_msr_special(
1334 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1335 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1336 GUEST_IA32_PERF_GLOBAL_CTRL,
1337 HOST_IA32_PERF_GLOBAL_CTRL,
1338 guest_val, host_val);
1339 return;
1340 }
1341 break;
1342 }
1343
1344 for (i = 0; i < m->nr; ++i)
1345 if (m->guest[i].index == msr)
1346 break;
1347
1348 if (i == NR_AUTOLOAD_MSRS) {
1349 printk_once(KERN_WARNING"Not enough mst switch entries. "
1350 "Can't add msr %x\n", msr);
1351 return;
1352 } else if (i == m->nr) {
1353 ++m->nr;
1354 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1355 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1356 }
1357
1358 m->guest[i].index = msr;
1359 m->guest[i].value = guest_val;
1360 m->host[i].index = msr;
1361 m->host[i].value = host_val;
1362 }
1363
1364 static void reload_tss(void)
1365 {
1366 /*
1367 * VT restores TR but not its size. Useless.
1368 */
1369 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1370 struct desc_struct *descs;
1371
1372 descs = (void *)gdt->address;
1373 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1374 load_TR_desc();
1375 }
1376
1377 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1378 {
1379 u64 guest_efer;
1380 u64 ignore_bits;
1381
1382 guest_efer = vmx->vcpu.arch.efer;
1383
1384 /*
1385 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1386 * outside long mode
1387 */
1388 ignore_bits = EFER_NX | EFER_SCE;
1389 #ifdef CONFIG_X86_64
1390 ignore_bits |= EFER_LMA | EFER_LME;
1391 /* SCE is meaningful only in long mode on Intel */
1392 if (guest_efer & EFER_LMA)
1393 ignore_bits &= ~(u64)EFER_SCE;
1394 #endif
1395 guest_efer &= ~ignore_bits;
1396 guest_efer |= host_efer & ignore_bits;
1397 vmx->guest_msrs[efer_offset].data = guest_efer;
1398 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1399
1400 clear_atomic_switch_msr(vmx, MSR_EFER);
1401 /* On ept, can't emulate nx, and must switch nx atomically */
1402 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1403 guest_efer = vmx->vcpu.arch.efer;
1404 if (!(guest_efer & EFER_LMA))
1405 guest_efer &= ~EFER_LME;
1406 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1407 return false;
1408 }
1409
1410 return true;
1411 }
1412
1413 static unsigned long segment_base(u16 selector)
1414 {
1415 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1416 struct desc_struct *d;
1417 unsigned long table_base;
1418 unsigned long v;
1419
1420 if (!(selector & ~3))
1421 return 0;
1422
1423 table_base = gdt->address;
1424
1425 if (selector & 4) { /* from ldt */
1426 u16 ldt_selector = kvm_read_ldt();
1427
1428 if (!(ldt_selector & ~3))
1429 return 0;
1430
1431 table_base = segment_base(ldt_selector);
1432 }
1433 d = (struct desc_struct *)(table_base + (selector & ~7));
1434 v = get_desc_base(d);
1435 #ifdef CONFIG_X86_64
1436 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1437 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1438 #endif
1439 return v;
1440 }
1441
1442 static inline unsigned long kvm_read_tr_base(void)
1443 {
1444 u16 tr;
1445 asm("str %0" : "=g"(tr));
1446 return segment_base(tr);
1447 }
1448
1449 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1450 {
1451 struct vcpu_vmx *vmx = to_vmx(vcpu);
1452 int i;
1453
1454 if (vmx->host_state.loaded)
1455 return;
1456
1457 vmx->host_state.loaded = 1;
1458 /*
1459 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1460 * allow segment selectors with cpl > 0 or ti == 1.
1461 */
1462 vmx->host_state.ldt_sel = kvm_read_ldt();
1463 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1464 savesegment(fs, vmx->host_state.fs_sel);
1465 if (!(vmx->host_state.fs_sel & 7)) {
1466 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1467 vmx->host_state.fs_reload_needed = 0;
1468 } else {
1469 vmcs_write16(HOST_FS_SELECTOR, 0);
1470 vmx->host_state.fs_reload_needed = 1;
1471 }
1472 savesegment(gs, vmx->host_state.gs_sel);
1473 if (!(vmx->host_state.gs_sel & 7))
1474 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1475 else {
1476 vmcs_write16(HOST_GS_SELECTOR, 0);
1477 vmx->host_state.gs_ldt_reload_needed = 1;
1478 }
1479
1480 #ifdef CONFIG_X86_64
1481 savesegment(ds, vmx->host_state.ds_sel);
1482 savesegment(es, vmx->host_state.es_sel);
1483 #endif
1484
1485 #ifdef CONFIG_X86_64
1486 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1487 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1488 #else
1489 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1490 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1491 #endif
1492
1493 #ifdef CONFIG_X86_64
1494 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1495 if (is_long_mode(&vmx->vcpu))
1496 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1497 #endif
1498 for (i = 0; i < vmx->save_nmsrs; ++i)
1499 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1500 vmx->guest_msrs[i].data,
1501 vmx->guest_msrs[i].mask);
1502 }
1503
1504 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1505 {
1506 if (!vmx->host_state.loaded)
1507 return;
1508
1509 ++vmx->vcpu.stat.host_state_reload;
1510 vmx->host_state.loaded = 0;
1511 #ifdef CONFIG_X86_64
1512 if (is_long_mode(&vmx->vcpu))
1513 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1514 #endif
1515 if (vmx->host_state.gs_ldt_reload_needed) {
1516 kvm_load_ldt(vmx->host_state.ldt_sel);
1517 #ifdef CONFIG_X86_64
1518 load_gs_index(vmx->host_state.gs_sel);
1519 #else
1520 loadsegment(gs, vmx->host_state.gs_sel);
1521 #endif
1522 }
1523 if (vmx->host_state.fs_reload_needed)
1524 loadsegment(fs, vmx->host_state.fs_sel);
1525 #ifdef CONFIG_X86_64
1526 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1527 loadsegment(ds, vmx->host_state.ds_sel);
1528 loadsegment(es, vmx->host_state.es_sel);
1529 }
1530 #endif
1531 reload_tss();
1532 #ifdef CONFIG_X86_64
1533 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1534 #endif
1535 /*
1536 * If the FPU is not active (through the host task or
1537 * the guest vcpu), then restore the cr0.TS bit.
1538 */
1539 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1540 stts();
1541 load_gdt(&__get_cpu_var(host_gdt));
1542 }
1543
1544 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1545 {
1546 preempt_disable();
1547 __vmx_load_host_state(vmx);
1548 preempt_enable();
1549 }
1550
1551 /*
1552 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1553 * vcpu mutex is already taken.
1554 */
1555 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1556 {
1557 struct vcpu_vmx *vmx = to_vmx(vcpu);
1558 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1559
1560 if (!vmm_exclusive)
1561 kvm_cpu_vmxon(phys_addr);
1562 else if (vmx->loaded_vmcs->cpu != cpu)
1563 loaded_vmcs_clear(vmx->loaded_vmcs);
1564
1565 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1566 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1567 vmcs_load(vmx->loaded_vmcs->vmcs);
1568 }
1569
1570 if (vmx->loaded_vmcs->cpu != cpu) {
1571 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1572 unsigned long sysenter_esp;
1573
1574 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1575 local_irq_disable();
1576 crash_disable_local_vmclear(cpu);
1577
1578 /*
1579 * Read loaded_vmcs->cpu should be before fetching
1580 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1581 * See the comments in __loaded_vmcs_clear().
1582 */
1583 smp_rmb();
1584
1585 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1586 &per_cpu(loaded_vmcss_on_cpu, cpu));
1587 crash_enable_local_vmclear(cpu);
1588 local_irq_enable();
1589
1590 /*
1591 * Linux uses per-cpu TSS and GDT, so set these when switching
1592 * processors.
1593 */
1594 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1595 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
1596
1597 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1598 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1599 vmx->loaded_vmcs->cpu = cpu;
1600 }
1601 }
1602
1603 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1604 {
1605 __vmx_load_host_state(to_vmx(vcpu));
1606 if (!vmm_exclusive) {
1607 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1608 vcpu->cpu = -1;
1609 kvm_cpu_vmxoff();
1610 }
1611 }
1612
1613 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1614 {
1615 ulong cr0;
1616
1617 if (vcpu->fpu_active)
1618 return;
1619 vcpu->fpu_active = 1;
1620 cr0 = vmcs_readl(GUEST_CR0);
1621 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1622 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1623 vmcs_writel(GUEST_CR0, cr0);
1624 update_exception_bitmap(vcpu);
1625 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1626 if (is_guest_mode(vcpu))
1627 vcpu->arch.cr0_guest_owned_bits &=
1628 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1629 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1630 }
1631
1632 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1633
1634 /*
1635 * Return the cr0 value that a nested guest would read. This is a combination
1636 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1637 * its hypervisor (cr0_read_shadow).
1638 */
1639 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1640 {
1641 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1642 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1643 }
1644 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1645 {
1646 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1647 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1648 }
1649
1650 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1651 {
1652 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1653 * set this *before* calling this function.
1654 */
1655 vmx_decache_cr0_guest_bits(vcpu);
1656 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1657 update_exception_bitmap(vcpu);
1658 vcpu->arch.cr0_guest_owned_bits = 0;
1659 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1660 if (is_guest_mode(vcpu)) {
1661 /*
1662 * L1's specified read shadow might not contain the TS bit,
1663 * so now that we turned on shadowing of this bit, we need to
1664 * set this bit of the shadow. Like in nested_vmx_run we need
1665 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1666 * up-to-date here because we just decached cr0.TS (and we'll
1667 * only update vmcs12->guest_cr0 on nested exit).
1668 */
1669 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1670 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1671 (vcpu->arch.cr0 & X86_CR0_TS);
1672 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1673 } else
1674 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1675 }
1676
1677 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1678 {
1679 unsigned long rflags, save_rflags;
1680
1681 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1682 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1683 rflags = vmcs_readl(GUEST_RFLAGS);
1684 if (to_vmx(vcpu)->rmode.vm86_active) {
1685 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1686 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1687 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1688 }
1689 to_vmx(vcpu)->rflags = rflags;
1690 }
1691 return to_vmx(vcpu)->rflags;
1692 }
1693
1694 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1695 {
1696 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1697 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
1698 to_vmx(vcpu)->rflags = rflags;
1699 if (to_vmx(vcpu)->rmode.vm86_active) {
1700 to_vmx(vcpu)->rmode.save_rflags = rflags;
1701 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1702 }
1703 vmcs_writel(GUEST_RFLAGS, rflags);
1704 }
1705
1706 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1707 {
1708 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1709 int ret = 0;
1710
1711 if (interruptibility & GUEST_INTR_STATE_STI)
1712 ret |= KVM_X86_SHADOW_INT_STI;
1713 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1714 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1715
1716 return ret & mask;
1717 }
1718
1719 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1720 {
1721 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1722 u32 interruptibility = interruptibility_old;
1723
1724 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1725
1726 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1727 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1728 else if (mask & KVM_X86_SHADOW_INT_STI)
1729 interruptibility |= GUEST_INTR_STATE_STI;
1730
1731 if ((interruptibility != interruptibility_old))
1732 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1733 }
1734
1735 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1736 {
1737 unsigned long rip;
1738
1739 rip = kvm_rip_read(vcpu);
1740 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1741 kvm_rip_write(vcpu, rip);
1742
1743 /* skipping an emulated instruction also counts */
1744 vmx_set_interrupt_shadow(vcpu, 0);
1745 }
1746
1747 /*
1748 * KVM wants to inject page-faults which it got to the guest. This function
1749 * checks whether in a nested guest, we need to inject them to L1 or L2.
1750 * This function assumes it is called with the exit reason in vmcs02 being
1751 * a #PF exception (this is the only case in which KVM injects a #PF when L2
1752 * is running).
1753 */
1754 static int nested_pf_handled(struct kvm_vcpu *vcpu)
1755 {
1756 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1757
1758 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
1759 if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
1760 return 0;
1761
1762 nested_vmx_vmexit(vcpu);
1763 return 1;
1764 }
1765
1766 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1767 bool has_error_code, u32 error_code,
1768 bool reinject)
1769 {
1770 struct vcpu_vmx *vmx = to_vmx(vcpu);
1771 u32 intr_info = nr | INTR_INFO_VALID_MASK;
1772
1773 if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1774 nested_pf_handled(vcpu))
1775 return;
1776
1777 if (has_error_code) {
1778 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1779 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1780 }
1781
1782 if (vmx->rmode.vm86_active) {
1783 int inc_eip = 0;
1784 if (kvm_exception_is_soft(nr))
1785 inc_eip = vcpu->arch.event_exit_inst_len;
1786 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
1787 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1788 return;
1789 }
1790
1791 if (kvm_exception_is_soft(nr)) {
1792 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1793 vmx->vcpu.arch.event_exit_inst_len);
1794 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1795 } else
1796 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1797
1798 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1799 }
1800
1801 static bool vmx_rdtscp_supported(void)
1802 {
1803 return cpu_has_vmx_rdtscp();
1804 }
1805
1806 static bool vmx_invpcid_supported(void)
1807 {
1808 return cpu_has_vmx_invpcid() && enable_ept;
1809 }
1810
1811 /*
1812 * Swap MSR entry in host/guest MSR entry array.
1813 */
1814 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1815 {
1816 struct shared_msr_entry tmp;
1817
1818 tmp = vmx->guest_msrs[to];
1819 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1820 vmx->guest_msrs[from] = tmp;
1821 }
1822
1823 /*
1824 * Set up the vmcs to automatically save and restore system
1825 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1826 * mode, as fiddling with msrs is very expensive.
1827 */
1828 static void setup_msrs(struct vcpu_vmx *vmx)
1829 {
1830 int save_nmsrs, index;
1831 unsigned long *msr_bitmap;
1832
1833 save_nmsrs = 0;
1834 #ifdef CONFIG_X86_64
1835 if (is_long_mode(&vmx->vcpu)) {
1836 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1837 if (index >= 0)
1838 move_msr_up(vmx, index, save_nmsrs++);
1839 index = __find_msr_index(vmx, MSR_LSTAR);
1840 if (index >= 0)
1841 move_msr_up(vmx, index, save_nmsrs++);
1842 index = __find_msr_index(vmx, MSR_CSTAR);
1843 if (index >= 0)
1844 move_msr_up(vmx, index, save_nmsrs++);
1845 index = __find_msr_index(vmx, MSR_TSC_AUX);
1846 if (index >= 0 && vmx->rdtscp_enabled)
1847 move_msr_up(vmx, index, save_nmsrs++);
1848 /*
1849 * MSR_STAR is only needed on long mode guests, and only
1850 * if efer.sce is enabled.
1851 */
1852 index = __find_msr_index(vmx, MSR_STAR);
1853 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1854 move_msr_up(vmx, index, save_nmsrs++);
1855 }
1856 #endif
1857 index = __find_msr_index(vmx, MSR_EFER);
1858 if (index >= 0 && update_transition_efer(vmx, index))
1859 move_msr_up(vmx, index, save_nmsrs++);
1860
1861 vmx->save_nmsrs = save_nmsrs;
1862
1863 if (cpu_has_vmx_msr_bitmap()) {
1864 if (is_long_mode(&vmx->vcpu))
1865 msr_bitmap = vmx_msr_bitmap_longmode;
1866 else
1867 msr_bitmap = vmx_msr_bitmap_legacy;
1868
1869 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1870 }
1871 }
1872
1873 /*
1874 * reads and returns guest's timestamp counter "register"
1875 * guest_tsc = host_tsc + tsc_offset -- 21.3
1876 */
1877 static u64 guest_read_tsc(void)
1878 {
1879 u64 host_tsc, tsc_offset;
1880
1881 rdtscll(host_tsc);
1882 tsc_offset = vmcs_read64(TSC_OFFSET);
1883 return host_tsc + tsc_offset;
1884 }
1885
1886 /*
1887 * Like guest_read_tsc, but always returns L1's notion of the timestamp
1888 * counter, even if a nested guest (L2) is currently running.
1889 */
1890 u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1891 {
1892 u64 tsc_offset;
1893
1894 tsc_offset = is_guest_mode(vcpu) ?
1895 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
1896 vmcs_read64(TSC_OFFSET);
1897 return host_tsc + tsc_offset;
1898 }
1899
1900 /*
1901 * Engage any workarounds for mis-matched TSC rates. Currently limited to
1902 * software catchup for faster rates on slower CPUs.
1903 */
1904 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1905 {
1906 if (!scale)
1907 return;
1908
1909 if (user_tsc_khz > tsc_khz) {
1910 vcpu->arch.tsc_catchup = 1;
1911 vcpu->arch.tsc_always_catchup = 1;
1912 } else
1913 WARN(1, "user requested TSC rate below hardware speed\n");
1914 }
1915
1916 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
1917 {
1918 return vmcs_read64(TSC_OFFSET);
1919 }
1920
1921 /*
1922 * writes 'offset' into guest's timestamp counter offset register
1923 */
1924 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1925 {
1926 if (is_guest_mode(vcpu)) {
1927 /*
1928 * We're here if L1 chose not to trap WRMSR to TSC. According
1929 * to the spec, this should set L1's TSC; The offset that L1
1930 * set for L2 remains unchanged, and still needs to be added
1931 * to the newly set TSC to get L2's TSC.
1932 */
1933 struct vmcs12 *vmcs12;
1934 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
1935 /* recalculate vmcs02.TSC_OFFSET: */
1936 vmcs12 = get_vmcs12(vcpu);
1937 vmcs_write64(TSC_OFFSET, offset +
1938 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
1939 vmcs12->tsc_offset : 0));
1940 } else {
1941 vmcs_write64(TSC_OFFSET, offset);
1942 }
1943 }
1944
1945 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
1946 {
1947 u64 offset = vmcs_read64(TSC_OFFSET);
1948 vmcs_write64(TSC_OFFSET, offset + adjustment);
1949 if (is_guest_mode(vcpu)) {
1950 /* Even when running L2, the adjustment needs to apply to L1 */
1951 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
1952 }
1953 }
1954
1955 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1956 {
1957 return target_tsc - native_read_tsc();
1958 }
1959
1960 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1961 {
1962 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1963 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1964 }
1965
1966 /*
1967 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1968 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1969 * all guests if the "nested" module option is off, and can also be disabled
1970 * for a single guest by disabling its VMX cpuid bit.
1971 */
1972 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1973 {
1974 return nested && guest_cpuid_has_vmx(vcpu);
1975 }
1976
1977 /*
1978 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1979 * returned for the various VMX controls MSRs when nested VMX is enabled.
1980 * The same values should also be used to verify that vmcs12 control fields are
1981 * valid during nested entry from L1 to L2.
1982 * Each of these control msrs has a low and high 32-bit half: A low bit is on
1983 * if the corresponding bit in the (32-bit) control field *must* be on, and a
1984 * bit in the high half is on if the corresponding bit in the control field
1985 * may be on. See also vmx_control_verify().
1986 * TODO: allow these variables to be modified (downgraded) by module options
1987 * or other means.
1988 */
1989 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
1990 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
1991 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
1992 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
1993 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
1994 static __init void nested_vmx_setup_ctls_msrs(void)
1995 {
1996 /*
1997 * Note that as a general rule, the high half of the MSRs (bits in
1998 * the control fields which may be 1) should be initialized by the
1999 * intersection of the underlying hardware's MSR (i.e., features which
2000 * can be supported) and the list of features we want to expose -
2001 * because they are known to be properly supported in our code.
2002 * Also, usually, the low half of the MSRs (bits which must be 1) can
2003 * be set to 0, meaning that L1 may turn off any of these bits. The
2004 * reason is that if one of these bits is necessary, it will appear
2005 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2006 * fields of vmcs01 and vmcs02, will turn these bits off - and
2007 * nested_vmx_exit_handled() will not pass related exits to L1.
2008 * These rules have exceptions below.
2009 */
2010
2011 /* pin-based controls */
2012 /*
2013 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2014 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2015 */
2016 nested_vmx_pinbased_ctls_low = 0x16 ;
2017 nested_vmx_pinbased_ctls_high = 0x16 |
2018 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
2019 PIN_BASED_VIRTUAL_NMIS;
2020
2021 /* exit controls */
2022 nested_vmx_exit_ctls_low = 0;
2023 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
2024 #ifdef CONFIG_X86_64
2025 nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
2026 #else
2027 nested_vmx_exit_ctls_high = 0;
2028 #endif
2029
2030 /* entry controls */
2031 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2032 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
2033 nested_vmx_entry_ctls_low = 0;
2034 nested_vmx_entry_ctls_high &=
2035 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
2036
2037 /* cpu-based controls */
2038 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2039 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2040 nested_vmx_procbased_ctls_low = 0;
2041 nested_vmx_procbased_ctls_high &=
2042 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2043 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2044 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2045 CPU_BASED_CR3_STORE_EXITING |
2046 #ifdef CONFIG_X86_64
2047 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2048 #endif
2049 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2050 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
2051 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
2052 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2053 /*
2054 * We can allow some features even when not supported by the
2055 * hardware. For example, L1 can specify an MSR bitmap - and we
2056 * can use it to avoid exits to L1 - even when L0 runs L2
2057 * without MSR bitmaps.
2058 */
2059 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2060
2061 /* secondary cpu-based controls */
2062 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2063 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2064 nested_vmx_secondary_ctls_low = 0;
2065 nested_vmx_secondary_ctls_high &=
2066 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2067 }
2068
2069 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2070 {
2071 /*
2072 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2073 */
2074 return ((control & high) | low) == control;
2075 }
2076
2077 static inline u64 vmx_control_msr(u32 low, u32 high)
2078 {
2079 return low | ((u64)high << 32);
2080 }
2081
2082 /*
2083 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2084 * also let it use VMX-specific MSRs.
2085 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2086 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2087 * like all other MSRs).
2088 */
2089 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2090 {
2091 if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2092 msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2093 /*
2094 * According to the spec, processors which do not support VMX
2095 * should throw a #GP(0) when VMX capability MSRs are read.
2096 */
2097 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2098 return 1;
2099 }
2100
2101 switch (msr_index) {
2102 case MSR_IA32_FEATURE_CONTROL:
2103 *pdata = 0;
2104 break;
2105 case MSR_IA32_VMX_BASIC:
2106 /*
2107 * This MSR reports some information about VMX support. We
2108 * should return information about the VMX we emulate for the
2109 * guest, and the VMCS structure we give it - not about the
2110 * VMX support of the underlying hardware.
2111 */
2112 *pdata = VMCS12_REVISION |
2113 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2114 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2115 break;
2116 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2117 case MSR_IA32_VMX_PINBASED_CTLS:
2118 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2119 nested_vmx_pinbased_ctls_high);
2120 break;
2121 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2122 case MSR_IA32_VMX_PROCBASED_CTLS:
2123 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2124 nested_vmx_procbased_ctls_high);
2125 break;
2126 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2127 case MSR_IA32_VMX_EXIT_CTLS:
2128 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2129 nested_vmx_exit_ctls_high);
2130 break;
2131 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2132 case MSR_IA32_VMX_ENTRY_CTLS:
2133 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2134 nested_vmx_entry_ctls_high);
2135 break;
2136 case MSR_IA32_VMX_MISC:
2137 *pdata = 0;
2138 break;
2139 /*
2140 * These MSRs specify bits which the guest must keep fixed (on or off)
2141 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2142 * We picked the standard core2 setting.
2143 */
2144 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2145 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2146 case MSR_IA32_VMX_CR0_FIXED0:
2147 *pdata = VMXON_CR0_ALWAYSON;
2148 break;
2149 case MSR_IA32_VMX_CR0_FIXED1:
2150 *pdata = -1ULL;
2151 break;
2152 case MSR_IA32_VMX_CR4_FIXED0:
2153 *pdata = VMXON_CR4_ALWAYSON;
2154 break;
2155 case MSR_IA32_VMX_CR4_FIXED1:
2156 *pdata = -1ULL;
2157 break;
2158 case MSR_IA32_VMX_VMCS_ENUM:
2159 *pdata = 0x1f;
2160 break;
2161 case MSR_IA32_VMX_PROCBASED_CTLS2:
2162 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2163 nested_vmx_secondary_ctls_high);
2164 break;
2165 case MSR_IA32_VMX_EPT_VPID_CAP:
2166 /* Currently, no nested ept or nested vpid */
2167 *pdata = 0;
2168 break;
2169 default:
2170 return 0;
2171 }
2172
2173 return 1;
2174 }
2175
2176 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2177 {
2178 if (!nested_vmx_allowed(vcpu))
2179 return 0;
2180
2181 if (msr_index == MSR_IA32_FEATURE_CONTROL)
2182 /* TODO: the right thing. */
2183 return 1;
2184 /*
2185 * No need to treat VMX capability MSRs specially: If we don't handle
2186 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2187 */
2188 return 0;
2189 }
2190
2191 /*
2192 * Reads an msr value (of 'msr_index') into 'pdata'.
2193 * Returns 0 on success, non-0 otherwise.
2194 * Assumes vcpu_load() was already called.
2195 */
2196 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2197 {
2198 u64 data;
2199 struct shared_msr_entry *msr;
2200
2201 if (!pdata) {
2202 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2203 return -EINVAL;
2204 }
2205
2206 switch (msr_index) {
2207 #ifdef CONFIG_X86_64
2208 case MSR_FS_BASE:
2209 data = vmcs_readl(GUEST_FS_BASE);
2210 break;
2211 case MSR_GS_BASE:
2212 data = vmcs_readl(GUEST_GS_BASE);
2213 break;
2214 case MSR_KERNEL_GS_BASE:
2215 vmx_load_host_state(to_vmx(vcpu));
2216 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2217 break;
2218 #endif
2219 case MSR_EFER:
2220 return kvm_get_msr_common(vcpu, msr_index, pdata);
2221 case MSR_IA32_TSC:
2222 data = guest_read_tsc();
2223 break;
2224 case MSR_IA32_SYSENTER_CS:
2225 data = vmcs_read32(GUEST_SYSENTER_CS);
2226 break;
2227 case MSR_IA32_SYSENTER_EIP:
2228 data = vmcs_readl(GUEST_SYSENTER_EIP);
2229 break;
2230 case MSR_IA32_SYSENTER_ESP:
2231 data = vmcs_readl(GUEST_SYSENTER_ESP);
2232 break;
2233 case MSR_TSC_AUX:
2234 if (!to_vmx(vcpu)->rdtscp_enabled)
2235 return 1;
2236 /* Otherwise falls through */
2237 default:
2238 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2239 return 0;
2240 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2241 if (msr) {
2242 data = msr->data;
2243 break;
2244 }
2245 return kvm_get_msr_common(vcpu, msr_index, pdata);
2246 }
2247
2248 *pdata = data;
2249 return 0;
2250 }
2251
2252 /*
2253 * Writes msr value into into the appropriate "register".
2254 * Returns 0 on success, non-0 otherwise.
2255 * Assumes vcpu_load() was already called.
2256 */
2257 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2258 {
2259 struct vcpu_vmx *vmx = to_vmx(vcpu);
2260 struct shared_msr_entry *msr;
2261 int ret = 0;
2262 u32 msr_index = msr_info->index;
2263 u64 data = msr_info->data;
2264
2265 switch (msr_index) {
2266 case MSR_EFER:
2267 ret = kvm_set_msr_common(vcpu, msr_info);
2268 break;
2269 #ifdef CONFIG_X86_64
2270 case MSR_FS_BASE:
2271 vmx_segment_cache_clear(vmx);
2272 vmcs_writel(GUEST_FS_BASE, data);
2273 break;
2274 case MSR_GS_BASE:
2275 vmx_segment_cache_clear(vmx);
2276 vmcs_writel(GUEST_GS_BASE, data);
2277 break;
2278 case MSR_KERNEL_GS_BASE:
2279 vmx_load_host_state(vmx);
2280 vmx->msr_guest_kernel_gs_base = data;
2281 break;
2282 #endif
2283 case MSR_IA32_SYSENTER_CS:
2284 vmcs_write32(GUEST_SYSENTER_CS, data);
2285 break;
2286 case MSR_IA32_SYSENTER_EIP:
2287 vmcs_writel(GUEST_SYSENTER_EIP, data);
2288 break;
2289 case MSR_IA32_SYSENTER_ESP:
2290 vmcs_writel(GUEST_SYSENTER_ESP, data);
2291 break;
2292 case MSR_IA32_TSC:
2293 kvm_write_tsc(vcpu, msr_info);
2294 break;
2295 case MSR_IA32_CR_PAT:
2296 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2297 vmcs_write64(GUEST_IA32_PAT, data);
2298 vcpu->arch.pat = data;
2299 break;
2300 }
2301 ret = kvm_set_msr_common(vcpu, msr_info);
2302 break;
2303 case MSR_IA32_TSC_ADJUST:
2304 ret = kvm_set_msr_common(vcpu, msr_info);
2305 break;
2306 case MSR_TSC_AUX:
2307 if (!vmx->rdtscp_enabled)
2308 return 1;
2309 /* Check reserved bit, higher 32 bits should be zero */
2310 if ((data >> 32) != 0)
2311 return 1;
2312 /* Otherwise falls through */
2313 default:
2314 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2315 break;
2316 msr = find_msr_entry(vmx, msr_index);
2317 if (msr) {
2318 msr->data = data;
2319 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2320 preempt_disable();
2321 kvm_set_shared_msr(msr->index, msr->data,
2322 msr->mask);
2323 preempt_enable();
2324 }
2325 break;
2326 }
2327 ret = kvm_set_msr_common(vcpu, msr_info);
2328 }
2329
2330 return ret;
2331 }
2332
2333 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2334 {
2335 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2336 switch (reg) {
2337 case VCPU_REGS_RSP:
2338 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2339 break;
2340 case VCPU_REGS_RIP:
2341 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2342 break;
2343 case VCPU_EXREG_PDPTR:
2344 if (enable_ept)
2345 ept_save_pdptrs(vcpu);
2346 break;
2347 default:
2348 break;
2349 }
2350 }
2351
2352 static __init int cpu_has_kvm_support(void)
2353 {
2354 return cpu_has_vmx();
2355 }
2356
2357 static __init int vmx_disabled_by_bios(void)
2358 {
2359 u64 msr;
2360
2361 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2362 if (msr & FEATURE_CONTROL_LOCKED) {
2363 /* launched w/ TXT and VMX disabled */
2364 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2365 && tboot_enabled())
2366 return 1;
2367 /* launched w/o TXT and VMX only enabled w/ TXT */
2368 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2369 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2370 && !tboot_enabled()) {
2371 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2372 "activate TXT before enabling KVM\n");
2373 return 1;
2374 }
2375 /* launched w/o TXT and VMX disabled */
2376 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2377 && !tboot_enabled())
2378 return 1;
2379 }
2380
2381 return 0;
2382 }
2383
2384 static void kvm_cpu_vmxon(u64 addr)
2385 {
2386 asm volatile (ASM_VMX_VMXON_RAX
2387 : : "a"(&addr), "m"(addr)
2388 : "memory", "cc");
2389 }
2390
2391 static int hardware_enable(void *garbage)
2392 {
2393 int cpu = raw_smp_processor_id();
2394 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2395 u64 old, test_bits;
2396
2397 if (read_cr4() & X86_CR4_VMXE)
2398 return -EBUSY;
2399
2400 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2401
2402 /*
2403 * Now we can enable the vmclear operation in kdump
2404 * since the loaded_vmcss_on_cpu list on this cpu
2405 * has been initialized.
2406 *
2407 * Though the cpu is not in VMX operation now, there
2408 * is no problem to enable the vmclear operation
2409 * for the loaded_vmcss_on_cpu list is empty!
2410 */
2411 crash_enable_local_vmclear(cpu);
2412
2413 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2414
2415 test_bits = FEATURE_CONTROL_LOCKED;
2416 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2417 if (tboot_enabled())
2418 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2419
2420 if ((old & test_bits) != test_bits) {
2421 /* enable and lock */
2422 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2423 }
2424 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2425
2426 if (vmm_exclusive) {
2427 kvm_cpu_vmxon(phys_addr);
2428 ept_sync_global();
2429 }
2430
2431 store_gdt(&__get_cpu_var(host_gdt));
2432
2433 return 0;
2434 }
2435
2436 static void vmclear_local_loaded_vmcss(void)
2437 {
2438 int cpu = raw_smp_processor_id();
2439 struct loaded_vmcs *v, *n;
2440
2441 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2442 loaded_vmcss_on_cpu_link)
2443 __loaded_vmcs_clear(v);
2444 }
2445
2446
2447 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2448 * tricks.
2449 */
2450 static void kvm_cpu_vmxoff(void)
2451 {
2452 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2453 }
2454
2455 static void hardware_disable(void *garbage)
2456 {
2457 if (vmm_exclusive) {
2458 vmclear_local_loaded_vmcss();
2459 kvm_cpu_vmxoff();
2460 }
2461 write_cr4(read_cr4() & ~X86_CR4_VMXE);
2462 }
2463
2464 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2465 u32 msr, u32 *result)
2466 {
2467 u32 vmx_msr_low, vmx_msr_high;
2468 u32 ctl = ctl_min | ctl_opt;
2469
2470 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2471
2472 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2473 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2474
2475 /* Ensure minimum (required) set of control bits are supported. */
2476 if (ctl_min & ~ctl)
2477 return -EIO;
2478
2479 *result = ctl;
2480 return 0;
2481 }
2482
2483 static __init bool allow_1_setting(u32 msr, u32 ctl)
2484 {
2485 u32 vmx_msr_low, vmx_msr_high;
2486
2487 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2488 return vmx_msr_high & ctl;
2489 }
2490
2491 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2492 {
2493 u32 vmx_msr_low, vmx_msr_high;
2494 u32 min, opt, min2, opt2;
2495 u32 _pin_based_exec_control = 0;
2496 u32 _cpu_based_exec_control = 0;
2497 u32 _cpu_based_2nd_exec_control = 0;
2498 u32 _vmexit_control = 0;
2499 u32 _vmentry_control = 0;
2500
2501 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2502 opt = PIN_BASED_VIRTUAL_NMIS;
2503 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2504 &_pin_based_exec_control) < 0)
2505 return -EIO;
2506
2507 min = CPU_BASED_HLT_EXITING |
2508 #ifdef CONFIG_X86_64
2509 CPU_BASED_CR8_LOAD_EXITING |
2510 CPU_BASED_CR8_STORE_EXITING |
2511 #endif
2512 CPU_BASED_CR3_LOAD_EXITING |
2513 CPU_BASED_CR3_STORE_EXITING |
2514 CPU_BASED_USE_IO_BITMAPS |
2515 CPU_BASED_MOV_DR_EXITING |
2516 CPU_BASED_USE_TSC_OFFSETING |
2517 CPU_BASED_MWAIT_EXITING |
2518 CPU_BASED_MONITOR_EXITING |
2519 CPU_BASED_INVLPG_EXITING |
2520 CPU_BASED_RDPMC_EXITING;
2521
2522 opt = CPU_BASED_TPR_SHADOW |
2523 CPU_BASED_USE_MSR_BITMAPS |
2524 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2525 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2526 &_cpu_based_exec_control) < 0)
2527 return -EIO;
2528 #ifdef CONFIG_X86_64
2529 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2530 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2531 ~CPU_BASED_CR8_STORE_EXITING;
2532 #endif
2533 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2534 min2 = 0;
2535 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2536 SECONDARY_EXEC_WBINVD_EXITING |
2537 SECONDARY_EXEC_ENABLE_VPID |
2538 SECONDARY_EXEC_ENABLE_EPT |
2539 SECONDARY_EXEC_UNRESTRICTED_GUEST |
2540 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2541 SECONDARY_EXEC_RDTSCP |
2542 SECONDARY_EXEC_ENABLE_INVPCID;
2543 if (adjust_vmx_controls(min2, opt2,
2544 MSR_IA32_VMX_PROCBASED_CTLS2,
2545 &_cpu_based_2nd_exec_control) < 0)
2546 return -EIO;
2547 }
2548 #ifndef CONFIG_X86_64
2549 if (!(_cpu_based_2nd_exec_control &
2550 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2551 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2552 #endif
2553 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2554 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2555 enabled */
2556 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2557 CPU_BASED_CR3_STORE_EXITING |
2558 CPU_BASED_INVLPG_EXITING);
2559 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2560 vmx_capability.ept, vmx_capability.vpid);
2561 }
2562
2563 min = 0;
2564 #ifdef CONFIG_X86_64
2565 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2566 #endif
2567 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
2568 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2569 &_vmexit_control) < 0)
2570 return -EIO;
2571
2572 min = 0;
2573 opt = VM_ENTRY_LOAD_IA32_PAT;
2574 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2575 &_vmentry_control) < 0)
2576 return -EIO;
2577
2578 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2579
2580 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2581 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2582 return -EIO;
2583
2584 #ifdef CONFIG_X86_64
2585 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2586 if (vmx_msr_high & (1u<<16))
2587 return -EIO;
2588 #endif
2589
2590 /* Require Write-Back (WB) memory type for VMCS accesses. */
2591 if (((vmx_msr_high >> 18) & 15) != 6)
2592 return -EIO;
2593
2594 vmcs_conf->size = vmx_msr_high & 0x1fff;
2595 vmcs_conf->order = get_order(vmcs_config.size);
2596 vmcs_conf->revision_id = vmx_msr_low;
2597
2598 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2599 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2600 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2601 vmcs_conf->vmexit_ctrl = _vmexit_control;
2602 vmcs_conf->vmentry_ctrl = _vmentry_control;
2603
2604 cpu_has_load_ia32_efer =
2605 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2606 VM_ENTRY_LOAD_IA32_EFER)
2607 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2608 VM_EXIT_LOAD_IA32_EFER);
2609
2610 cpu_has_load_perf_global_ctrl =
2611 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2612 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2613 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2614 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2615
2616 /*
2617 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2618 * but due to arrata below it can't be used. Workaround is to use
2619 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2620 *
2621 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2622 *
2623 * AAK155 (model 26)
2624 * AAP115 (model 30)
2625 * AAT100 (model 37)
2626 * BC86,AAY89,BD102 (model 44)
2627 * BA97 (model 46)
2628 *
2629 */
2630 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2631 switch (boot_cpu_data.x86_model) {
2632 case 26:
2633 case 30:
2634 case 37:
2635 case 44:
2636 case 46:
2637 cpu_has_load_perf_global_ctrl = false;
2638 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2639 "does not work properly. Using workaround\n");
2640 break;
2641 default:
2642 break;
2643 }
2644 }
2645
2646 return 0;
2647 }
2648
2649 static struct vmcs *alloc_vmcs_cpu(int cpu)
2650 {
2651 int node = cpu_to_node(cpu);
2652 struct page *pages;
2653 struct vmcs *vmcs;
2654
2655 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
2656 if (!pages)
2657 return NULL;
2658 vmcs = page_address(pages);
2659 memset(vmcs, 0, vmcs_config.size);
2660 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
2661 return vmcs;
2662 }
2663
2664 static struct vmcs *alloc_vmcs(void)
2665 {
2666 return alloc_vmcs_cpu(raw_smp_processor_id());
2667 }
2668
2669 static void free_vmcs(struct vmcs *vmcs)
2670 {
2671 free_pages((unsigned long)vmcs, vmcs_config.order);
2672 }
2673
2674 /*
2675 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2676 */
2677 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2678 {
2679 if (!loaded_vmcs->vmcs)
2680 return;
2681 loaded_vmcs_clear(loaded_vmcs);
2682 free_vmcs(loaded_vmcs->vmcs);
2683 loaded_vmcs->vmcs = NULL;
2684 }
2685
2686 static void free_kvm_area(void)
2687 {
2688 int cpu;
2689
2690 for_each_possible_cpu(cpu) {
2691 free_vmcs(per_cpu(vmxarea, cpu));
2692 per_cpu(vmxarea, cpu) = NULL;
2693 }
2694 }
2695
2696 static __init int alloc_kvm_area(void)
2697 {
2698 int cpu;
2699
2700 for_each_possible_cpu(cpu) {
2701 struct vmcs *vmcs;
2702
2703 vmcs = alloc_vmcs_cpu(cpu);
2704 if (!vmcs) {
2705 free_kvm_area();
2706 return -ENOMEM;
2707 }
2708
2709 per_cpu(vmxarea, cpu) = vmcs;
2710 }
2711 return 0;
2712 }
2713
2714 static __init int hardware_setup(void)
2715 {
2716 if (setup_vmcs_config(&vmcs_config) < 0)
2717 return -EIO;
2718
2719 if (boot_cpu_has(X86_FEATURE_NX))
2720 kvm_enable_efer_bits(EFER_NX);
2721
2722 if (!cpu_has_vmx_vpid())
2723 enable_vpid = 0;
2724
2725 if (!cpu_has_vmx_ept() ||
2726 !cpu_has_vmx_ept_4levels()) {
2727 enable_ept = 0;
2728 enable_unrestricted_guest = 0;
2729 enable_ept_ad_bits = 0;
2730 }
2731
2732 if (!cpu_has_vmx_ept_ad_bits())
2733 enable_ept_ad_bits = 0;
2734
2735 if (!cpu_has_vmx_unrestricted_guest())
2736 enable_unrestricted_guest = 0;
2737
2738 if (!cpu_has_vmx_flexpriority())
2739 flexpriority_enabled = 0;
2740
2741 if (!cpu_has_vmx_tpr_shadow())
2742 kvm_x86_ops->update_cr8_intercept = NULL;
2743
2744 if (enable_ept && !cpu_has_vmx_ept_2m_page())
2745 kvm_disable_largepages();
2746
2747 if (!cpu_has_vmx_ple())
2748 ple_gap = 0;
2749
2750 if (nested)
2751 nested_vmx_setup_ctls_msrs();
2752
2753 return alloc_kvm_area();
2754 }
2755
2756 static __exit void hardware_unsetup(void)
2757 {
2758 free_kvm_area();
2759 }
2760
2761 static void fix_pmode_dataseg(struct kvm_vcpu *vcpu, int seg, struct kvm_segment *save)
2762 {
2763 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2764 struct kvm_segment tmp = *save;
2765
2766 if (!(vmcs_readl(sf->base) == tmp.base && tmp.s)) {
2767 tmp.base = vmcs_readl(sf->base);
2768 tmp.selector = vmcs_read16(sf->selector);
2769 tmp.dpl = tmp.selector & SELECTOR_RPL_MASK;
2770 tmp.s = 1;
2771 }
2772 vmx_set_segment(vcpu, &tmp, seg);
2773 }
2774
2775 static void enter_pmode(struct kvm_vcpu *vcpu)
2776 {
2777 unsigned long flags;
2778 struct vcpu_vmx *vmx = to_vmx(vcpu);
2779
2780 vmx->emulation_required = 1;
2781 vmx->rmode.vm86_active = 0;
2782
2783 vmx_segment_cache_clear(vmx);
2784
2785 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2786
2787 flags = vmcs_readl(GUEST_RFLAGS);
2788 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2789 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2790 vmcs_writel(GUEST_RFLAGS, flags);
2791
2792 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2793 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2794
2795 update_exception_bitmap(vcpu);
2796
2797 if (emulate_invalid_guest_state)
2798 return;
2799
2800 fix_pmode_dataseg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2801 fix_pmode_dataseg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2802 fix_pmode_dataseg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2803 fix_pmode_dataseg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2804
2805 vmx_segment_cache_clear(vmx);
2806
2807 vmcs_write16(GUEST_SS_SELECTOR, 0);
2808 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
2809
2810 vmcs_write16(GUEST_CS_SELECTOR,
2811 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
2812 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2813 }
2814
2815 static gva_t rmode_tss_base(struct kvm *kvm)
2816 {
2817 if (!kvm->arch.tss_addr) {
2818 struct kvm_memslots *slots;
2819 struct kvm_memory_slot *slot;
2820 gfn_t base_gfn;
2821
2822 slots = kvm_memslots(kvm);
2823 slot = id_to_memslot(slots, 0);
2824 base_gfn = slot->base_gfn + slot->npages - 3;
2825
2826 return base_gfn << PAGE_SHIFT;
2827 }
2828 return kvm->arch.tss_addr;
2829 }
2830
2831 static void fix_rmode_seg(int seg, struct kvm_segment *save)
2832 {
2833 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2834
2835 vmcs_write16(sf->selector, save->base >> 4);
2836 vmcs_write32(sf->base, save->base & 0xffff0);
2837 vmcs_write32(sf->limit, 0xffff);
2838 vmcs_write32(sf->ar_bytes, 0xf3);
2839 if (save->base & 0xf)
2840 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
2841 " aligned when entering protected mode (seg=%d)",
2842 seg);
2843 }
2844
2845 static void enter_rmode(struct kvm_vcpu *vcpu)
2846 {
2847 unsigned long flags;
2848 struct vcpu_vmx *vmx = to_vmx(vcpu);
2849 struct kvm_segment var;
2850
2851 if (enable_unrestricted_guest)
2852 return;
2853
2854 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2855 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2856 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2857 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2858 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2859
2860 vmx->emulation_required = 1;
2861 vmx->rmode.vm86_active = 1;
2862
2863
2864 /*
2865 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2866 * vcpu. Call it here with phys address pointing 16M below 4G.
2867 */
2868 if (!vcpu->kvm->arch.tss_addr) {
2869 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2870 "called before entering vcpu\n");
2871 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2872 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2873 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2874 }
2875
2876 vmx_segment_cache_clear(vmx);
2877
2878 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
2879 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2880 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2881
2882 flags = vmcs_readl(GUEST_RFLAGS);
2883 vmx->rmode.save_rflags = flags;
2884
2885 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2886
2887 vmcs_writel(GUEST_RFLAGS, flags);
2888 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2889 update_exception_bitmap(vcpu);
2890
2891 if (emulate_invalid_guest_state)
2892 goto continue_rmode;
2893
2894 vmx_get_segment(vcpu, &var, VCPU_SREG_SS);
2895 vmx_set_segment(vcpu, &var, VCPU_SREG_SS);
2896
2897 vmx_get_segment(vcpu, &var, VCPU_SREG_CS);
2898 vmx_set_segment(vcpu, &var, VCPU_SREG_CS);
2899
2900 vmx_get_segment(vcpu, &var, VCPU_SREG_ES);
2901 vmx_set_segment(vcpu, &var, VCPU_SREG_ES);
2902
2903 vmx_get_segment(vcpu, &var, VCPU_SREG_DS);
2904 vmx_set_segment(vcpu, &var, VCPU_SREG_DS);
2905
2906 vmx_get_segment(vcpu, &var, VCPU_SREG_GS);
2907 vmx_set_segment(vcpu, &var, VCPU_SREG_GS);
2908
2909 vmx_get_segment(vcpu, &var, VCPU_SREG_FS);
2910 vmx_set_segment(vcpu, &var, VCPU_SREG_FS);
2911
2912 continue_rmode:
2913 kvm_mmu_reset_context(vcpu);
2914 }
2915
2916 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2917 {
2918 struct vcpu_vmx *vmx = to_vmx(vcpu);
2919 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2920
2921 if (!msr)
2922 return;
2923
2924 /*
2925 * Force kernel_gs_base reloading before EFER changes, as control
2926 * of this msr depends on is_long_mode().
2927 */
2928 vmx_load_host_state(to_vmx(vcpu));
2929 vcpu->arch.efer = efer;
2930 if (efer & EFER_LMA) {
2931 vmcs_write32(VM_ENTRY_CONTROLS,
2932 vmcs_read32(VM_ENTRY_CONTROLS) |
2933 VM_ENTRY_IA32E_MODE);
2934 msr->data = efer;
2935 } else {
2936 vmcs_write32(VM_ENTRY_CONTROLS,
2937 vmcs_read32(VM_ENTRY_CONTROLS) &
2938 ~VM_ENTRY_IA32E_MODE);
2939
2940 msr->data = efer & ~EFER_LME;
2941 }
2942 setup_msrs(vmx);
2943 }
2944
2945 #ifdef CONFIG_X86_64
2946
2947 static void enter_lmode(struct kvm_vcpu *vcpu)
2948 {
2949 u32 guest_tr_ar;
2950
2951 vmx_segment_cache_clear(to_vmx(vcpu));
2952
2953 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2954 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
2955 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2956 __func__);
2957 vmcs_write32(GUEST_TR_AR_BYTES,
2958 (guest_tr_ar & ~AR_TYPE_MASK)
2959 | AR_TYPE_BUSY_64_TSS);
2960 }
2961 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2962 }
2963
2964 static void exit_lmode(struct kvm_vcpu *vcpu)
2965 {
2966 vmcs_write32(VM_ENTRY_CONTROLS,
2967 vmcs_read32(VM_ENTRY_CONTROLS)
2968 & ~VM_ENTRY_IA32E_MODE);
2969 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2970 }
2971
2972 #endif
2973
2974 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2975 {
2976 vpid_sync_context(to_vmx(vcpu));
2977 if (enable_ept) {
2978 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2979 return;
2980 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2981 }
2982 }
2983
2984 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2985 {
2986 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2987
2988 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2989 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2990 }
2991
2992 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2993 {
2994 if (enable_ept && is_paging(vcpu))
2995 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2996 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2997 }
2998
2999 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3000 {
3001 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3002
3003 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3004 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3005 }
3006
3007 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3008 {
3009 if (!test_bit(VCPU_EXREG_PDPTR,
3010 (unsigned long *)&vcpu->arch.regs_dirty))
3011 return;
3012
3013 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3014 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
3015 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
3016 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
3017 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
3018 }
3019 }
3020
3021 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3022 {
3023 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3024 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3025 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3026 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3027 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3028 }
3029
3030 __set_bit(VCPU_EXREG_PDPTR,
3031 (unsigned long *)&vcpu->arch.regs_avail);
3032 __set_bit(VCPU_EXREG_PDPTR,
3033 (unsigned long *)&vcpu->arch.regs_dirty);
3034 }
3035
3036 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3037
3038 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3039 unsigned long cr0,
3040 struct kvm_vcpu *vcpu)
3041 {
3042 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3043 vmx_decache_cr3(vcpu);
3044 if (!(cr0 & X86_CR0_PG)) {
3045 /* From paging/starting to nonpaging */
3046 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3047 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3048 (CPU_BASED_CR3_LOAD_EXITING |
3049 CPU_BASED_CR3_STORE_EXITING));
3050 vcpu->arch.cr0 = cr0;
3051 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3052 } else if (!is_paging(vcpu)) {
3053 /* From nonpaging to paging */
3054 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3055 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3056 ~(CPU_BASED_CR3_LOAD_EXITING |
3057 CPU_BASED_CR3_STORE_EXITING));
3058 vcpu->arch.cr0 = cr0;
3059 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3060 }
3061
3062 if (!(cr0 & X86_CR0_WP))
3063 *hw_cr0 &= ~X86_CR0_WP;
3064 }
3065
3066 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3067 {
3068 struct vcpu_vmx *vmx = to_vmx(vcpu);
3069 unsigned long hw_cr0;
3070
3071 if (enable_unrestricted_guest)
3072 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
3073 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3074 else
3075 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
3076
3077 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3078 enter_pmode(vcpu);
3079
3080 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3081 enter_rmode(vcpu);
3082
3083 #ifdef CONFIG_X86_64
3084 if (vcpu->arch.efer & EFER_LME) {
3085 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3086 enter_lmode(vcpu);
3087 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3088 exit_lmode(vcpu);
3089 }
3090 #endif
3091
3092 if (enable_ept)
3093 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3094
3095 if (!vcpu->fpu_active)
3096 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3097
3098 vmcs_writel(CR0_READ_SHADOW, cr0);
3099 vmcs_writel(GUEST_CR0, hw_cr0);
3100 vcpu->arch.cr0 = cr0;
3101 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3102 }
3103
3104 static u64 construct_eptp(unsigned long root_hpa)
3105 {
3106 u64 eptp;
3107
3108 /* TODO write the value reading from MSR */
3109 eptp = VMX_EPT_DEFAULT_MT |
3110 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3111 if (enable_ept_ad_bits)
3112 eptp |= VMX_EPT_AD_ENABLE_BIT;
3113 eptp |= (root_hpa & PAGE_MASK);
3114
3115 return eptp;
3116 }
3117
3118 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3119 {
3120 unsigned long guest_cr3;
3121 u64 eptp;
3122
3123 guest_cr3 = cr3;
3124 if (enable_ept) {
3125 eptp = construct_eptp(cr3);
3126 vmcs_write64(EPT_POINTER, eptp);
3127 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
3128 vcpu->kvm->arch.ept_identity_map_addr;
3129 ept_load_pdptrs(vcpu);
3130 }
3131
3132 vmx_flush_tlb(vcpu);
3133 vmcs_writel(GUEST_CR3, guest_cr3);
3134 }
3135
3136 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3137 {
3138 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
3139 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3140
3141 if (cr4 & X86_CR4_VMXE) {
3142 /*
3143 * To use VMXON (and later other VMX instructions), a guest
3144 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3145 * So basically the check on whether to allow nested VMX
3146 * is here.
3147 */
3148 if (!nested_vmx_allowed(vcpu))
3149 return 1;
3150 } else if (to_vmx(vcpu)->nested.vmxon)
3151 return 1;
3152
3153 vcpu->arch.cr4 = cr4;
3154 if (enable_ept) {
3155 if (!is_paging(vcpu)) {
3156 hw_cr4 &= ~X86_CR4_PAE;
3157 hw_cr4 |= X86_CR4_PSE;
3158 } else if (!(cr4 & X86_CR4_PAE)) {
3159 hw_cr4 &= ~X86_CR4_PAE;
3160 }
3161 }
3162
3163 vmcs_writel(CR4_READ_SHADOW, cr4);
3164 vmcs_writel(GUEST_CR4, hw_cr4);
3165 return 0;
3166 }
3167
3168 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3169 struct kvm_segment *var, int seg)
3170 {
3171 struct vcpu_vmx *vmx = to_vmx(vcpu);
3172 u32 ar;
3173
3174 if (vmx->rmode.vm86_active
3175 && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
3176 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
3177 || seg == VCPU_SREG_GS)) {
3178 *var = vmx->rmode.segs[seg];
3179 if (seg == VCPU_SREG_TR
3180 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3181 return;
3182 var->base = vmx_read_guest_seg_base(vmx, seg);
3183 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3184 return;
3185 }
3186 var->base = vmx_read_guest_seg_base(vmx, seg);
3187 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3188 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3189 ar = vmx_read_guest_seg_ar(vmx, seg);
3190 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
3191 ar = 0;
3192 var->type = ar & 15;
3193 var->s = (ar >> 4) & 1;
3194 var->dpl = (ar >> 5) & 3;
3195 var->present = (ar >> 7) & 1;
3196 var->avl = (ar >> 12) & 1;
3197 var->l = (ar >> 13) & 1;
3198 var->db = (ar >> 14) & 1;
3199 var->g = (ar >> 15) & 1;
3200 var->unusable = (ar >> 16) & 1;
3201 }
3202
3203 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3204 {
3205 struct kvm_segment s;
3206
3207 if (to_vmx(vcpu)->rmode.vm86_active) {
3208 vmx_get_segment(vcpu, &s, seg);
3209 return s.base;
3210 }
3211 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3212 }
3213
3214 static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
3215 {
3216 if (!is_protmode(vcpu))
3217 return 0;
3218
3219 if (!is_long_mode(vcpu)
3220 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
3221 return 3;
3222
3223 return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3;
3224 }
3225
3226 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3227 {
3228 struct vcpu_vmx *vmx = to_vmx(vcpu);
3229
3230 /*
3231 * If we enter real mode with cs.sel & 3 != 0, the normal CPL calculations
3232 * fail; use the cache instead.
3233 */
3234 if (unlikely(vmx->emulation_required && emulate_invalid_guest_state)) {
3235 return vmx->cpl;
3236 }
3237
3238 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3239 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3240 vmx->cpl = __vmx_get_cpl(vcpu);
3241 }
3242
3243 return vmx->cpl;
3244 }
3245
3246
3247 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3248 {
3249 u32 ar;
3250
3251 if (var->unusable || !var->present)
3252 ar = 1 << 16;
3253 else {
3254 ar = var->type & 15;
3255 ar |= (var->s & 1) << 4;
3256 ar |= (var->dpl & 3) << 5;
3257 ar |= (var->present & 1) << 7;
3258 ar |= (var->avl & 1) << 12;
3259 ar |= (var->l & 1) << 13;
3260 ar |= (var->db & 1) << 14;
3261 ar |= (var->g & 1) << 15;
3262 }
3263
3264 return ar;
3265 }
3266
3267 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3268 struct kvm_segment *var, int seg)
3269 {
3270 struct vcpu_vmx *vmx = to_vmx(vcpu);
3271 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3272 u32 ar;
3273
3274 vmx_segment_cache_clear(vmx);
3275
3276 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
3277 vmcs_write16(sf->selector, var->selector);
3278 vmx->rmode.segs[VCPU_SREG_TR] = *var;
3279 return;
3280 }
3281 vmcs_writel(sf->base, var->base);
3282 vmcs_write32(sf->limit, var->limit);
3283 vmcs_write16(sf->selector, var->selector);
3284 if (vmx->rmode.vm86_active && var->s) {
3285 vmx->rmode.segs[seg] = *var;
3286 /*
3287 * Hack real-mode segments into vm86 compatibility.
3288 */
3289 if (var->base == 0xffff0000 && var->selector == 0xf000)
3290 vmcs_writel(sf->base, 0xf0000);
3291 ar = 0xf3;
3292 } else
3293 ar = vmx_segment_access_rights(var);
3294
3295 /*
3296 * Fix the "Accessed" bit in AR field of segment registers for older
3297 * qemu binaries.
3298 * IA32 arch specifies that at the time of processor reset the
3299 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3300 * is setting it to 0 in the userland code. This causes invalid guest
3301 * state vmexit when "unrestricted guest" mode is turned on.
3302 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3303 * tree. Newer qemu binaries with that qemu fix would not need this
3304 * kvm hack.
3305 */
3306 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3307 ar |= 0x1; /* Accessed */
3308
3309 vmcs_write32(sf->ar_bytes, ar);
3310 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3311
3312 /*
3313 * Fix segments for real mode guest in hosts that don't have
3314 * "unrestricted_mode" or it was disabled.
3315 * This is done to allow migration of the guests from hosts with
3316 * unrestricted guest like Westmere to older host that don't have
3317 * unrestricted guest like Nehelem.
3318 */
3319 if (vmx->rmode.vm86_active) {
3320 switch (seg) {
3321 case VCPU_SREG_CS:
3322 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
3323 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
3324 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
3325 vmcs_writel(GUEST_CS_BASE, 0xf0000);
3326 vmcs_write16(GUEST_CS_SELECTOR,
3327 vmcs_readl(GUEST_CS_BASE) >> 4);
3328 break;
3329 case VCPU_SREG_ES:
3330 case VCPU_SREG_DS:
3331 case VCPU_SREG_GS:
3332 case VCPU_SREG_FS:
3333 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3334 break;
3335 case VCPU_SREG_SS:
3336 vmcs_write16(GUEST_SS_SELECTOR,
3337 vmcs_readl(GUEST_SS_BASE) >> 4);
3338 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
3339 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
3340 break;
3341 }
3342 }
3343 }
3344
3345 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3346 {
3347 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3348
3349 *db = (ar >> 14) & 1;
3350 *l = (ar >> 13) & 1;
3351 }
3352
3353 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3354 {
3355 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3356 dt->address = vmcs_readl(GUEST_IDTR_BASE);
3357 }
3358
3359 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3360 {
3361 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3362 vmcs_writel(GUEST_IDTR_BASE, dt->address);
3363 }
3364
3365 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3366 {
3367 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3368 dt->address = vmcs_readl(GUEST_GDTR_BASE);
3369 }
3370
3371 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3372 {
3373 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3374 vmcs_writel(GUEST_GDTR_BASE, dt->address);
3375 }
3376
3377 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3378 {
3379 struct kvm_segment var;
3380 u32 ar;
3381
3382 vmx_get_segment(vcpu, &var, seg);
3383 ar = vmx_segment_access_rights(&var);
3384
3385 if (var.base != (var.selector << 4))
3386 return false;
3387 if (var.limit < 0xffff)
3388 return false;
3389 if (((ar | (3 << AR_DPL_SHIFT)) & ~(AR_G_MASK | AR_DB_MASK)) != 0xf3)
3390 return false;
3391
3392 return true;
3393 }
3394
3395 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3396 {
3397 struct kvm_segment cs;
3398 unsigned int cs_rpl;
3399
3400 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3401 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3402
3403 if (cs.unusable)
3404 return false;
3405 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3406 return false;
3407 if (!cs.s)
3408 return false;
3409 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3410 if (cs.dpl > cs_rpl)
3411 return false;
3412 } else {
3413 if (cs.dpl != cs_rpl)
3414 return false;
3415 }
3416 if (!cs.present)
3417 return false;
3418
3419 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3420 return true;
3421 }
3422
3423 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3424 {
3425 struct kvm_segment ss;
3426 unsigned int ss_rpl;
3427
3428 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3429 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3430
3431 if (ss.unusable)
3432 return true;
3433 if (ss.type != 3 && ss.type != 7)
3434 return false;
3435 if (!ss.s)
3436 return false;
3437 if (ss.dpl != ss_rpl) /* DPL != RPL */
3438 return false;
3439 if (!ss.present)
3440 return false;
3441
3442 return true;
3443 }
3444
3445 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3446 {
3447 struct kvm_segment var;
3448 unsigned int rpl;
3449
3450 vmx_get_segment(vcpu, &var, seg);
3451 rpl = var.selector & SELECTOR_RPL_MASK;
3452
3453 if (var.unusable)
3454 return true;
3455 if (!var.s)
3456 return false;
3457 if (!var.present)
3458 return false;
3459 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3460 if (var.dpl < rpl) /* DPL < RPL */
3461 return false;
3462 }
3463
3464 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3465 * rights flags
3466 */
3467 return true;
3468 }
3469
3470 static bool tr_valid(struct kvm_vcpu *vcpu)
3471 {
3472 struct kvm_segment tr;
3473
3474 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3475
3476 if (tr.unusable)
3477 return false;
3478 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3479 return false;
3480 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3481 return false;
3482 if (!tr.present)
3483 return false;
3484
3485 return true;
3486 }
3487
3488 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3489 {
3490 struct kvm_segment ldtr;
3491
3492 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3493
3494 if (ldtr.unusable)
3495 return true;
3496 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3497 return false;
3498 if (ldtr.type != 2)
3499 return false;
3500 if (!ldtr.present)
3501 return false;
3502
3503 return true;
3504 }
3505
3506 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3507 {
3508 struct kvm_segment cs, ss;
3509
3510 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3511 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3512
3513 return ((cs.selector & SELECTOR_RPL_MASK) ==
3514 (ss.selector & SELECTOR_RPL_MASK));
3515 }
3516
3517 /*
3518 * Check if guest state is valid. Returns true if valid, false if
3519 * not.
3520 * We assume that registers are always usable
3521 */
3522 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3523 {
3524 /* real mode guest state checks */
3525 if (!is_protmode(vcpu)) {
3526 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3527 return false;
3528 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3529 return false;
3530 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3531 return false;
3532 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3533 return false;
3534 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3535 return false;
3536 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3537 return false;
3538 } else {
3539 /* protected mode guest state checks */
3540 if (!cs_ss_rpl_check(vcpu))
3541 return false;
3542 if (!code_segment_valid(vcpu))
3543 return false;
3544 if (!stack_segment_valid(vcpu))
3545 return false;
3546 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3547 return false;
3548 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3549 return false;
3550 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3551 return false;
3552 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3553 return false;
3554 if (!tr_valid(vcpu))
3555 return false;
3556 if (!ldtr_valid(vcpu))
3557 return false;
3558 }
3559 /* TODO:
3560 * - Add checks on RIP
3561 * - Add checks on RFLAGS
3562 */
3563
3564 return true;
3565 }
3566
3567 static int init_rmode_tss(struct kvm *kvm)
3568 {
3569 gfn_t fn;
3570 u16 data = 0;
3571 int r, idx, ret = 0;
3572
3573 idx = srcu_read_lock(&kvm->srcu);
3574 fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
3575 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3576 if (r < 0)
3577 goto out;
3578 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3579 r = kvm_write_guest_page(kvm, fn++, &data,
3580 TSS_IOPB_BASE_OFFSET, sizeof(u16));
3581 if (r < 0)
3582 goto out;
3583 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3584 if (r < 0)
3585 goto out;
3586 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3587 if (r < 0)
3588 goto out;
3589 data = ~0;
3590 r = kvm_write_guest_page(kvm, fn, &data,
3591 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3592 sizeof(u8));
3593 if (r < 0)
3594 goto out;
3595
3596 ret = 1;
3597 out:
3598 srcu_read_unlock(&kvm->srcu, idx);
3599 return ret;
3600 }
3601
3602 static int init_rmode_identity_map(struct kvm *kvm)
3603 {
3604 int i, idx, r, ret;
3605 pfn_t identity_map_pfn;
3606 u32 tmp;
3607
3608 if (!enable_ept)
3609 return 1;
3610 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3611 printk(KERN_ERR "EPT: identity-mapping pagetable "
3612 "haven't been allocated!\n");
3613 return 0;
3614 }
3615 if (likely(kvm->arch.ept_identity_pagetable_done))
3616 return 1;
3617 ret = 0;
3618 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3619 idx = srcu_read_lock(&kvm->srcu);
3620 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3621 if (r < 0)
3622 goto out;
3623 /* Set up identity-mapping pagetable for EPT in real mode */
3624 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3625 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3626 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3627 r = kvm_write_guest_page(kvm, identity_map_pfn,
3628 &tmp, i * sizeof(tmp), sizeof(tmp));
3629 if (r < 0)
3630 goto out;
3631 }
3632 kvm->arch.ept_identity_pagetable_done = true;
3633 ret = 1;
3634 out:
3635 srcu_read_unlock(&kvm->srcu, idx);
3636 return ret;
3637 }
3638
3639 static void seg_setup(int seg)
3640 {
3641 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3642 unsigned int ar;
3643
3644 vmcs_write16(sf->selector, 0);
3645 vmcs_writel(sf->base, 0);
3646 vmcs_write32(sf->limit, 0xffff);
3647 if (enable_unrestricted_guest) {
3648 ar = 0x93;
3649 if (seg == VCPU_SREG_CS)
3650 ar |= 0x08; /* code segment */
3651 } else
3652 ar = 0xf3;
3653
3654 vmcs_write32(sf->ar_bytes, ar);
3655 }
3656
3657 static int alloc_apic_access_page(struct kvm *kvm)
3658 {
3659 struct page *page;
3660 struct kvm_userspace_memory_region kvm_userspace_mem;
3661 int r = 0;
3662
3663 mutex_lock(&kvm->slots_lock);
3664 if (kvm->arch.apic_access_page)
3665 goto out;
3666 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3667 kvm_userspace_mem.flags = 0;
3668 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3669 kvm_userspace_mem.memory_size = PAGE_SIZE;
3670 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3671 if (r)
3672 goto out;
3673
3674 page = gfn_to_page(kvm, 0xfee00);
3675 if (is_error_page(page)) {
3676 r = -EFAULT;
3677 goto out;
3678 }
3679
3680 kvm->arch.apic_access_page = page;
3681 out:
3682 mutex_unlock(&kvm->slots_lock);
3683 return r;
3684 }
3685
3686 static int alloc_identity_pagetable(struct kvm *kvm)
3687 {
3688 struct page *page;
3689 struct kvm_userspace_memory_region kvm_userspace_mem;
3690 int r = 0;
3691
3692 mutex_lock(&kvm->slots_lock);
3693 if (kvm->arch.ept_identity_pagetable)
3694 goto out;
3695 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3696 kvm_userspace_mem.flags = 0;
3697 kvm_userspace_mem.guest_phys_addr =
3698 kvm->arch.ept_identity_map_addr;
3699 kvm_userspace_mem.memory_size = PAGE_SIZE;
3700 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3701 if (r)
3702 goto out;
3703
3704 page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3705 if (is_error_page(page)) {
3706 r = -EFAULT;
3707 goto out;
3708 }
3709
3710 kvm->arch.ept_identity_pagetable = page;
3711 out:
3712 mutex_unlock(&kvm->slots_lock);
3713 return r;
3714 }
3715
3716 static void allocate_vpid(struct vcpu_vmx *vmx)
3717 {
3718 int vpid;
3719
3720 vmx->vpid = 0;
3721 if (!enable_vpid)
3722 return;
3723 spin_lock(&vmx_vpid_lock);
3724 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3725 if (vpid < VMX_NR_VPIDS) {
3726 vmx->vpid = vpid;
3727 __set_bit(vpid, vmx_vpid_bitmap);
3728 }
3729 spin_unlock(&vmx_vpid_lock);
3730 }
3731
3732 static void free_vpid(struct vcpu_vmx *vmx)
3733 {
3734 if (!enable_vpid)
3735 return;
3736 spin_lock(&vmx_vpid_lock);
3737 if (vmx->vpid != 0)
3738 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3739 spin_unlock(&vmx_vpid_lock);
3740 }
3741
3742 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
3743 {
3744 int f = sizeof(unsigned long);
3745
3746 if (!cpu_has_vmx_msr_bitmap())
3747 return;
3748
3749 /*
3750 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3751 * have the write-low and read-high bitmap offsets the wrong way round.
3752 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3753 */
3754 if (msr <= 0x1fff) {
3755 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
3756 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
3757 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3758 msr &= 0x1fff;
3759 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
3760 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
3761 }
3762 }
3763
3764 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3765 {
3766 if (!longmode_only)
3767 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
3768 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
3769 }
3770
3771 /*
3772 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3773 * will not change in the lifetime of the guest.
3774 * Note that host-state that does change is set elsewhere. E.g., host-state
3775 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3776 */
3777 static void vmx_set_constant_host_state(void)
3778 {
3779 u32 low32, high32;
3780 unsigned long tmpl;
3781 struct desc_ptr dt;
3782
3783 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
3784 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
3785 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
3786
3787 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
3788 #ifdef CONFIG_X86_64
3789 /*
3790 * Load null selectors, so we can avoid reloading them in
3791 * __vmx_load_host_state(), in case userspace uses the null selectors
3792 * too (the expected case).
3793 */
3794 vmcs_write16(HOST_DS_SELECTOR, 0);
3795 vmcs_write16(HOST_ES_SELECTOR, 0);
3796 #else
3797 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3798 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3799 #endif
3800 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3801 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
3802
3803 native_store_idt(&dt);
3804 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
3805
3806 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
3807
3808 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3809 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3810 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3811 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
3812
3813 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3814 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3815 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3816 }
3817 }
3818
3819 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3820 {
3821 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3822 if (enable_ept)
3823 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
3824 if (is_guest_mode(&vmx->vcpu))
3825 vmx->vcpu.arch.cr4_guest_owned_bits &=
3826 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
3827 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3828 }
3829
3830 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3831 {
3832 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3833 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3834 exec_control &= ~CPU_BASED_TPR_SHADOW;
3835 #ifdef CONFIG_X86_64
3836 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3837 CPU_BASED_CR8_LOAD_EXITING;
3838 #endif
3839 }
3840 if (!enable_ept)
3841 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3842 CPU_BASED_CR3_LOAD_EXITING |
3843 CPU_BASED_INVLPG_EXITING;
3844 return exec_control;
3845 }
3846
3847 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3848 {
3849 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3850 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3851 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3852 if (vmx->vpid == 0)
3853 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3854 if (!enable_ept) {
3855 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3856 enable_unrestricted_guest = 0;
3857 /* Enable INVPCID for non-ept guests may cause performance regression. */
3858 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
3859 }
3860 if (!enable_unrestricted_guest)
3861 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3862 if (!ple_gap)
3863 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3864 return exec_control;
3865 }
3866
3867 static void ept_set_mmio_spte_mask(void)
3868 {
3869 /*
3870 * EPT Misconfigurations can be generated if the value of bits 2:0
3871 * of an EPT paging-structure entry is 110b (write/execute).
3872 * Also, magic bits (0xffull << 49) is set to quickly identify mmio
3873 * spte.
3874 */
3875 kvm_mmu_set_mmio_spte_mask(0xffull << 49 | 0x6ull);
3876 }
3877
3878 /*
3879 * Sets up the vmcs for emulated real mode.
3880 */
3881 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
3882 {
3883 #ifdef CONFIG_X86_64
3884 unsigned long a;
3885 #endif
3886 int i;
3887
3888 /* I/O */
3889 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
3890 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
3891
3892 if (cpu_has_vmx_msr_bitmap())
3893 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
3894
3895 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
3896
3897 /* Control */
3898 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
3899 vmcs_config.pin_based_exec_ctrl);
3900
3901 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
3902
3903 if (cpu_has_secondary_exec_ctrls()) {
3904 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
3905 vmx_secondary_exec_control(vmx));
3906 }
3907
3908 if (ple_gap) {
3909 vmcs_write32(PLE_GAP, ple_gap);
3910 vmcs_write32(PLE_WINDOW, ple_window);
3911 }
3912
3913 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
3914 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
3915 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
3916
3917 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
3918 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
3919 vmx_set_constant_host_state();
3920 #ifdef CONFIG_X86_64
3921 rdmsrl(MSR_FS_BASE, a);
3922 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
3923 rdmsrl(MSR_GS_BASE, a);
3924 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
3925 #else
3926 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
3927 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
3928 #endif
3929
3930 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
3931 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
3932 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
3933 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
3934 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
3935
3936 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3937 u32 msr_low, msr_high;
3938 u64 host_pat;
3939 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
3940 host_pat = msr_low | ((u64) msr_high << 32);
3941 /* Write the default value follow host pat */
3942 vmcs_write64(GUEST_IA32_PAT, host_pat);
3943 /* Keep arch.pat sync with GUEST_IA32_PAT */
3944 vmx->vcpu.arch.pat = host_pat;
3945 }
3946
3947 for (i = 0; i < NR_VMX_MSR; ++i) {
3948 u32 index = vmx_msr_index[i];
3949 u32 data_low, data_high;
3950 int j = vmx->nmsrs;
3951
3952 if (rdmsr_safe(index, &data_low, &data_high) < 0)
3953 continue;
3954 if (wrmsr_safe(index, data_low, data_high) < 0)
3955 continue;
3956 vmx->guest_msrs[j].index = i;
3957 vmx->guest_msrs[j].data = 0;
3958 vmx->guest_msrs[j].mask = -1ull;
3959 ++vmx->nmsrs;
3960 }
3961
3962 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
3963
3964 /* 22.2.1, 20.8.1 */
3965 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
3966
3967 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
3968 set_cr4_guest_host_mask(vmx);
3969
3970 return 0;
3971 }
3972
3973 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
3974 {
3975 struct vcpu_vmx *vmx = to_vmx(vcpu);
3976 u64 msr;
3977 int ret;
3978
3979 vmx->rmode.vm86_active = 0;
3980
3981 vmx->soft_vnmi_blocked = 0;
3982
3983 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
3984 kvm_set_cr8(&vmx->vcpu, 0);
3985 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
3986 if (kvm_vcpu_is_bsp(&vmx->vcpu))
3987 msr |= MSR_IA32_APICBASE_BSP;
3988 kvm_set_apic_base(&vmx->vcpu, msr);
3989
3990 vmx_segment_cache_clear(vmx);
3991
3992 seg_setup(VCPU_SREG_CS);
3993 /*
3994 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
3995 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
3996 */
3997 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
3998 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
3999 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
4000 } else {
4001 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
4002 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
4003 }
4004
4005 seg_setup(VCPU_SREG_DS);
4006 seg_setup(VCPU_SREG_ES);
4007 seg_setup(VCPU_SREG_FS);
4008 seg_setup(VCPU_SREG_GS);
4009 seg_setup(VCPU_SREG_SS);
4010
4011 vmcs_write16(GUEST_TR_SELECTOR, 0);
4012 vmcs_writel(GUEST_TR_BASE, 0);
4013 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4014 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4015
4016 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4017 vmcs_writel(GUEST_LDTR_BASE, 0);
4018 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4019 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4020
4021 vmcs_write32(GUEST_SYSENTER_CS, 0);
4022 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4023 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4024
4025 vmcs_writel(GUEST_RFLAGS, 0x02);
4026 if (kvm_vcpu_is_bsp(&vmx->vcpu))
4027 kvm_rip_write(vcpu, 0xfff0);
4028 else
4029 kvm_rip_write(vcpu, 0);
4030
4031 vmcs_writel(GUEST_GDTR_BASE, 0);
4032 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4033
4034 vmcs_writel(GUEST_IDTR_BASE, 0);
4035 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4036
4037 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4038 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4039 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4040
4041 /* Special registers */
4042 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4043
4044 setup_msrs(vmx);
4045
4046 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4047
4048 if (cpu_has_vmx_tpr_shadow()) {
4049 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4050 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4051 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4052 __pa(vmx->vcpu.arch.apic->regs));
4053 vmcs_write32(TPR_THRESHOLD, 0);
4054 }
4055
4056 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4057 vmcs_write64(APIC_ACCESS_ADDR,
4058 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
4059
4060 if (vmx->vpid != 0)
4061 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4062
4063 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4064 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
4065 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
4066 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
4067 vmx_set_cr4(&vmx->vcpu, 0);
4068 vmx_set_efer(&vmx->vcpu, 0);
4069 vmx_fpu_activate(&vmx->vcpu);
4070 update_exception_bitmap(&vmx->vcpu);
4071
4072 vpid_sync_context(vmx);
4073
4074 ret = 0;
4075
4076 /* HACK: Don't enable emulation on guest boot/reset */
4077 vmx->emulation_required = 0;
4078
4079 return ret;
4080 }
4081
4082 /*
4083 * In nested virtualization, check if L1 asked to exit on external interrupts.
4084 * For most existing hypervisors, this will always return true.
4085 */
4086 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4087 {
4088 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4089 PIN_BASED_EXT_INTR_MASK;
4090 }
4091
4092 static void enable_irq_window(struct kvm_vcpu *vcpu)
4093 {
4094 u32 cpu_based_vm_exec_control;
4095 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4096 /*
4097 * We get here if vmx_interrupt_allowed() said we can't
4098 * inject to L1 now because L2 must run. Ask L2 to exit
4099 * right after entry, so we can inject to L1 more promptly.
4100 */
4101 kvm_make_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
4102 return;
4103 }
4104
4105 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4106 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4107 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4108 }
4109
4110 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4111 {
4112 u32 cpu_based_vm_exec_control;
4113
4114 if (!cpu_has_virtual_nmis()) {
4115 enable_irq_window(vcpu);
4116 return;
4117 }
4118
4119 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4120 enable_irq_window(vcpu);
4121 return;
4122 }
4123 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4124 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4125 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4126 }
4127
4128 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4129 {
4130 struct vcpu_vmx *vmx = to_vmx(vcpu);
4131 uint32_t intr;
4132 int irq = vcpu->arch.interrupt.nr;
4133
4134 trace_kvm_inj_virq(irq);
4135
4136 ++vcpu->stat.irq_injections;
4137 if (vmx->rmode.vm86_active) {
4138 int inc_eip = 0;
4139 if (vcpu->arch.interrupt.soft)
4140 inc_eip = vcpu->arch.event_exit_inst_len;
4141 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
4142 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4143 return;
4144 }
4145 intr = irq | INTR_INFO_VALID_MASK;
4146 if (vcpu->arch.interrupt.soft) {
4147 intr |= INTR_TYPE_SOFT_INTR;
4148 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4149 vmx->vcpu.arch.event_exit_inst_len);
4150 } else
4151 intr |= INTR_TYPE_EXT_INTR;
4152 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4153 }
4154
4155 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4156 {
4157 struct vcpu_vmx *vmx = to_vmx(vcpu);
4158
4159 if (is_guest_mode(vcpu))
4160 return;
4161
4162 if (!cpu_has_virtual_nmis()) {
4163 /*
4164 * Tracking the NMI-blocked state in software is built upon
4165 * finding the next open IRQ window. This, in turn, depends on
4166 * well-behaving guests: They have to keep IRQs disabled at
4167 * least as long as the NMI handler runs. Otherwise we may
4168 * cause NMI nesting, maybe breaking the guest. But as this is
4169 * highly unlikely, we can live with the residual risk.
4170 */
4171 vmx->soft_vnmi_blocked = 1;
4172 vmx->vnmi_blocked_time = 0;
4173 }
4174
4175 ++vcpu->stat.nmi_injections;
4176 vmx->nmi_known_unmasked = false;
4177 if (vmx->rmode.vm86_active) {
4178 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4179 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4180 return;
4181 }
4182 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4183 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4184 }
4185
4186 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4187 {
4188 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4189 return 0;
4190
4191 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4192 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4193 | GUEST_INTR_STATE_NMI));
4194 }
4195
4196 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4197 {
4198 if (!cpu_has_virtual_nmis())
4199 return to_vmx(vcpu)->soft_vnmi_blocked;
4200 if (to_vmx(vcpu)->nmi_known_unmasked)
4201 return false;
4202 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4203 }
4204
4205 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4206 {
4207 struct vcpu_vmx *vmx = to_vmx(vcpu);
4208
4209 if (!cpu_has_virtual_nmis()) {
4210 if (vmx->soft_vnmi_blocked != masked) {
4211 vmx->soft_vnmi_blocked = masked;
4212 vmx->vnmi_blocked_time = 0;
4213 }
4214 } else {
4215 vmx->nmi_known_unmasked = !masked;
4216 if (masked)
4217 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4218 GUEST_INTR_STATE_NMI);
4219 else
4220 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4221 GUEST_INTR_STATE_NMI);
4222 }
4223 }
4224
4225 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4226 {
4227 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4228 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4229 if (to_vmx(vcpu)->nested.nested_run_pending ||
4230 (vmcs12->idt_vectoring_info_field &
4231 VECTORING_INFO_VALID_MASK))
4232 return 0;
4233 nested_vmx_vmexit(vcpu);
4234 vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT;
4235 vmcs12->vm_exit_intr_info = 0;
4236 /* fall through to normal code, but now in L1, not L2 */
4237 }
4238
4239 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4240 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4241 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4242 }
4243
4244 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4245 {
4246 int ret;
4247 struct kvm_userspace_memory_region tss_mem = {
4248 .slot = TSS_PRIVATE_MEMSLOT,
4249 .guest_phys_addr = addr,
4250 .memory_size = PAGE_SIZE * 3,
4251 .flags = 0,
4252 };
4253
4254 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
4255 if (ret)
4256 return ret;
4257 kvm->arch.tss_addr = addr;
4258 if (!init_rmode_tss(kvm))
4259 return -ENOMEM;
4260
4261 return 0;
4262 }
4263
4264 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4265 int vec, u32 err_code)
4266 {
4267 /*
4268 * Instruction with address size override prefix opcode 0x67
4269 * Cause the #SS fault with 0 error code in VM86 mode.
4270 */
4271 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
4272 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
4273 return 1;
4274 /*
4275 * Forward all other exceptions that are valid in real mode.
4276 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4277 * the required debugging infrastructure rework.
4278 */
4279 switch (vec) {
4280 case DB_VECTOR:
4281 if (vcpu->guest_debug &
4282 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4283 return 0;
4284 kvm_queue_exception(vcpu, vec);
4285 return 1;
4286 case BP_VECTOR:
4287 /*
4288 * Update instruction length as we may reinject the exception
4289 * from user space while in guest debugging mode.
4290 */
4291 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4292 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4293 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4294 return 0;
4295 /* fall through */
4296 case DE_VECTOR:
4297 case OF_VECTOR:
4298 case BR_VECTOR:
4299 case UD_VECTOR:
4300 case DF_VECTOR:
4301 case SS_VECTOR:
4302 case GP_VECTOR:
4303 case MF_VECTOR:
4304 kvm_queue_exception(vcpu, vec);
4305 return 1;
4306 }
4307 return 0;
4308 }
4309
4310 /*
4311 * Trigger machine check on the host. We assume all the MSRs are already set up
4312 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4313 * We pass a fake environment to the machine check handler because we want
4314 * the guest to be always treated like user space, no matter what context
4315 * it used internally.
4316 */
4317 static void kvm_machine_check(void)
4318 {
4319 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4320 struct pt_regs regs = {
4321 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4322 .flags = X86_EFLAGS_IF,
4323 };
4324
4325 do_machine_check(&regs, 0);
4326 #endif
4327 }
4328
4329 static int handle_machine_check(struct kvm_vcpu *vcpu)
4330 {
4331 /* already handled by vcpu_run */
4332 return 1;
4333 }
4334
4335 static int handle_exception(struct kvm_vcpu *vcpu)
4336 {
4337 struct vcpu_vmx *vmx = to_vmx(vcpu);
4338 struct kvm_run *kvm_run = vcpu->run;
4339 u32 intr_info, ex_no, error_code;
4340 unsigned long cr2, rip, dr6;
4341 u32 vect_info;
4342 enum emulation_result er;
4343
4344 vect_info = vmx->idt_vectoring_info;
4345 intr_info = vmx->exit_intr_info;
4346
4347 if (is_machine_check(intr_info))
4348 return handle_machine_check(vcpu);
4349
4350 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
4351 return 1; /* already handled by vmx_vcpu_run() */
4352
4353 if (is_no_device(intr_info)) {
4354 vmx_fpu_activate(vcpu);
4355 return 1;
4356 }
4357
4358 if (is_invalid_opcode(intr_info)) {
4359 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
4360 if (er != EMULATE_DONE)
4361 kvm_queue_exception(vcpu, UD_VECTOR);
4362 return 1;
4363 }
4364
4365 error_code = 0;
4366 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4367 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4368
4369 /*
4370 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4371 * MMIO, it is better to report an internal error.
4372 * See the comments in vmx_handle_exit.
4373 */
4374 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4375 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4376 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4377 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4378 vcpu->run->internal.ndata = 2;
4379 vcpu->run->internal.data[0] = vect_info;
4380 vcpu->run->internal.data[1] = intr_info;
4381 return 0;
4382 }
4383
4384 if (is_page_fault(intr_info)) {
4385 /* EPT won't cause page fault directly */
4386 BUG_ON(enable_ept);
4387 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4388 trace_kvm_page_fault(cr2, error_code);
4389
4390 if (kvm_event_needs_reinjection(vcpu))
4391 kvm_mmu_unprotect_page_virt(vcpu, cr2);
4392 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4393 }
4394
4395 if (vmx->rmode.vm86_active &&
4396 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
4397 error_code)) {
4398 if (vcpu->arch.halt_request) {
4399 vcpu->arch.halt_request = 0;
4400 return kvm_emulate_halt(vcpu);
4401 }
4402 return 1;
4403 }
4404
4405 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4406 switch (ex_no) {
4407 case DB_VECTOR:
4408 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4409 if (!(vcpu->guest_debug &
4410 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4411 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4412 kvm_queue_exception(vcpu, DB_VECTOR);
4413 return 1;
4414 }
4415 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4416 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4417 /* fall through */
4418 case BP_VECTOR:
4419 /*
4420 * Update instruction length as we may reinject #BP from
4421 * user space while in guest debugging mode. Reading it for
4422 * #DB as well causes no harm, it is not used in that case.
4423 */
4424 vmx->vcpu.arch.event_exit_inst_len =
4425 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4426 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4427 rip = kvm_rip_read(vcpu);
4428 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4429 kvm_run->debug.arch.exception = ex_no;
4430 break;
4431 default:
4432 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4433 kvm_run->ex.exception = ex_no;
4434 kvm_run->ex.error_code = error_code;
4435 break;
4436 }
4437 return 0;
4438 }
4439
4440 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4441 {
4442 ++vcpu->stat.irq_exits;
4443 return 1;
4444 }
4445
4446 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4447 {
4448 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4449 return 0;
4450 }
4451
4452 static int handle_io(struct kvm_vcpu *vcpu)
4453 {
4454 unsigned long exit_qualification;
4455 int size, in, string;
4456 unsigned port;
4457
4458 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4459 string = (exit_qualification & 16) != 0;
4460 in = (exit_qualification & 8) != 0;
4461
4462 ++vcpu->stat.io_exits;
4463
4464 if (string || in)
4465 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4466
4467 port = exit_qualification >> 16;
4468 size = (exit_qualification & 7) + 1;
4469 skip_emulated_instruction(vcpu);
4470
4471 return kvm_fast_pio_out(vcpu, size, port);
4472 }
4473
4474 static void
4475 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4476 {
4477 /*
4478 * Patch in the VMCALL instruction:
4479 */
4480 hypercall[0] = 0x0f;
4481 hypercall[1] = 0x01;
4482 hypercall[2] = 0xc1;
4483 }
4484
4485 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4486 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4487 {
4488 if (to_vmx(vcpu)->nested.vmxon &&
4489 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4490 return 1;
4491
4492 if (is_guest_mode(vcpu)) {
4493 /*
4494 * We get here when L2 changed cr0 in a way that did not change
4495 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4496 * but did change L0 shadowed bits. This can currently happen
4497 * with the TS bit: L0 may want to leave TS on (for lazy fpu
4498 * loading) while pretending to allow the guest to change it.
4499 */
4500 if (kvm_set_cr0(vcpu, (val & vcpu->arch.cr0_guest_owned_bits) |
4501 (vcpu->arch.cr0 & ~vcpu->arch.cr0_guest_owned_bits)))
4502 return 1;
4503 vmcs_writel(CR0_READ_SHADOW, val);
4504 return 0;
4505 } else
4506 return kvm_set_cr0(vcpu, val);
4507 }
4508
4509 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4510 {
4511 if (is_guest_mode(vcpu)) {
4512 if (kvm_set_cr4(vcpu, (val & vcpu->arch.cr4_guest_owned_bits) |
4513 (vcpu->arch.cr4 & ~vcpu->arch.cr4_guest_owned_bits)))
4514 return 1;
4515 vmcs_writel(CR4_READ_SHADOW, val);
4516 return 0;
4517 } else
4518 return kvm_set_cr4(vcpu, val);
4519 }
4520
4521 /* called to set cr0 as approriate for clts instruction exit. */
4522 static void handle_clts(struct kvm_vcpu *vcpu)
4523 {
4524 if (is_guest_mode(vcpu)) {
4525 /*
4526 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4527 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4528 * just pretend it's off (also in arch.cr0 for fpu_activate).
4529 */
4530 vmcs_writel(CR0_READ_SHADOW,
4531 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4532 vcpu->arch.cr0 &= ~X86_CR0_TS;
4533 } else
4534 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4535 }
4536
4537 static int handle_cr(struct kvm_vcpu *vcpu)
4538 {
4539 unsigned long exit_qualification, val;
4540 int cr;
4541 int reg;
4542 int err;
4543
4544 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4545 cr = exit_qualification & 15;
4546 reg = (exit_qualification >> 8) & 15;
4547 switch ((exit_qualification >> 4) & 3) {
4548 case 0: /* mov to cr */
4549 val = kvm_register_read(vcpu, reg);
4550 trace_kvm_cr_write(cr, val);
4551 switch (cr) {
4552 case 0:
4553 err = handle_set_cr0(vcpu, val);
4554 kvm_complete_insn_gp(vcpu, err);
4555 return 1;
4556 case 3:
4557 err = kvm_set_cr3(vcpu, val);
4558 kvm_complete_insn_gp(vcpu, err);
4559 return 1;
4560 case 4:
4561 err = handle_set_cr4(vcpu, val);
4562 kvm_complete_insn_gp(vcpu, err);
4563 return 1;
4564 case 8: {
4565 u8 cr8_prev = kvm_get_cr8(vcpu);
4566 u8 cr8 = kvm_register_read(vcpu, reg);
4567 err = kvm_set_cr8(vcpu, cr8);
4568 kvm_complete_insn_gp(vcpu, err);
4569 if (irqchip_in_kernel(vcpu->kvm))
4570 return 1;
4571 if (cr8_prev <= cr8)
4572 return 1;
4573 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4574 return 0;
4575 }
4576 }
4577 break;
4578 case 2: /* clts */
4579 handle_clts(vcpu);
4580 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4581 skip_emulated_instruction(vcpu);
4582 vmx_fpu_activate(vcpu);
4583 return 1;
4584 case 1: /*mov from cr*/
4585 switch (cr) {
4586 case 3:
4587 val = kvm_read_cr3(vcpu);
4588 kvm_register_write(vcpu, reg, val);
4589 trace_kvm_cr_read(cr, val);
4590 skip_emulated_instruction(vcpu);
4591 return 1;
4592 case 8:
4593 val = kvm_get_cr8(vcpu);
4594 kvm_register_write(vcpu, reg, val);
4595 trace_kvm_cr_read(cr, val);
4596 skip_emulated_instruction(vcpu);
4597 return 1;
4598 }
4599 break;
4600 case 3: /* lmsw */
4601 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4602 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4603 kvm_lmsw(vcpu, val);
4604
4605 skip_emulated_instruction(vcpu);
4606 return 1;
4607 default:
4608 break;
4609 }
4610 vcpu->run->exit_reason = 0;
4611 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4612 (int)(exit_qualification >> 4) & 3, cr);
4613 return 0;
4614 }
4615
4616 static int handle_dr(struct kvm_vcpu *vcpu)
4617 {
4618 unsigned long exit_qualification;
4619 int dr, reg;
4620
4621 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4622 if (!kvm_require_cpl(vcpu, 0))
4623 return 1;
4624 dr = vmcs_readl(GUEST_DR7);
4625 if (dr & DR7_GD) {
4626 /*
4627 * As the vm-exit takes precedence over the debug trap, we
4628 * need to emulate the latter, either for the host or the
4629 * guest debugging itself.
4630 */
4631 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4632 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4633 vcpu->run->debug.arch.dr7 = dr;
4634 vcpu->run->debug.arch.pc =
4635 vmcs_readl(GUEST_CS_BASE) +
4636 vmcs_readl(GUEST_RIP);
4637 vcpu->run->debug.arch.exception = DB_VECTOR;
4638 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
4639 return 0;
4640 } else {
4641 vcpu->arch.dr7 &= ~DR7_GD;
4642 vcpu->arch.dr6 |= DR6_BD;
4643 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4644 kvm_queue_exception(vcpu, DB_VECTOR);
4645 return 1;
4646 }
4647 }
4648
4649 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4650 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4651 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4652 if (exit_qualification & TYPE_MOV_FROM_DR) {
4653 unsigned long val;
4654 if (!kvm_get_dr(vcpu, dr, &val))
4655 kvm_register_write(vcpu, reg, val);
4656 } else
4657 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
4658 skip_emulated_instruction(vcpu);
4659 return 1;
4660 }
4661
4662 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4663 {
4664 vmcs_writel(GUEST_DR7, val);
4665 }
4666
4667 static int handle_cpuid(struct kvm_vcpu *vcpu)
4668 {
4669 kvm_emulate_cpuid(vcpu);
4670 return 1;
4671 }
4672
4673 static int handle_rdmsr(struct kvm_vcpu *vcpu)
4674 {
4675 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4676 u64 data;
4677
4678 if (vmx_get_msr(vcpu, ecx, &data)) {
4679 trace_kvm_msr_read_ex(ecx);
4680 kvm_inject_gp(vcpu, 0);
4681 return 1;
4682 }
4683
4684 trace_kvm_msr_read(ecx, data);
4685
4686 /* FIXME: handling of bits 32:63 of rax, rdx */
4687 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4688 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
4689 skip_emulated_instruction(vcpu);
4690 return 1;
4691 }
4692
4693 static int handle_wrmsr(struct kvm_vcpu *vcpu)
4694 {
4695 struct msr_data msr;
4696 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4697 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4698 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
4699
4700 msr.data = data;
4701 msr.index = ecx;
4702 msr.host_initiated = false;
4703 if (vmx_set_msr(vcpu, &msr) != 0) {
4704 trace_kvm_msr_write_ex(ecx, data);
4705 kvm_inject_gp(vcpu, 0);
4706 return 1;
4707 }
4708
4709 trace_kvm_msr_write(ecx, data);
4710 skip_emulated_instruction(vcpu);
4711 return 1;
4712 }
4713
4714 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
4715 {
4716 kvm_make_request(KVM_REQ_EVENT, vcpu);
4717 return 1;
4718 }
4719
4720 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
4721 {
4722 u32 cpu_based_vm_exec_control;
4723
4724 /* clear pending irq */
4725 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4726 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4727 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4728
4729 kvm_make_request(KVM_REQ_EVENT, vcpu);
4730
4731 ++vcpu->stat.irq_window_exits;
4732
4733 /*
4734 * If the user space waits to inject interrupts, exit as soon as
4735 * possible
4736 */
4737 if (!irqchip_in_kernel(vcpu->kvm) &&
4738 vcpu->run->request_interrupt_window &&
4739 !kvm_cpu_has_interrupt(vcpu)) {
4740 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
4741 return 0;
4742 }
4743 return 1;
4744 }
4745
4746 static int handle_halt(struct kvm_vcpu *vcpu)
4747 {
4748 skip_emulated_instruction(vcpu);
4749 return kvm_emulate_halt(vcpu);
4750 }
4751
4752 static int handle_vmcall(struct kvm_vcpu *vcpu)
4753 {
4754 skip_emulated_instruction(vcpu);
4755 kvm_emulate_hypercall(vcpu);
4756 return 1;
4757 }
4758
4759 static int handle_invd(struct kvm_vcpu *vcpu)
4760 {
4761 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4762 }
4763
4764 static int handle_invlpg(struct kvm_vcpu *vcpu)
4765 {
4766 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4767
4768 kvm_mmu_invlpg(vcpu, exit_qualification);
4769 skip_emulated_instruction(vcpu);
4770 return 1;
4771 }
4772
4773 static int handle_rdpmc(struct kvm_vcpu *vcpu)
4774 {
4775 int err;
4776
4777 err = kvm_rdpmc(vcpu);
4778 kvm_complete_insn_gp(vcpu, err);
4779
4780 return 1;
4781 }
4782
4783 static int handle_wbinvd(struct kvm_vcpu *vcpu)
4784 {
4785 skip_emulated_instruction(vcpu);
4786 kvm_emulate_wbinvd(vcpu);
4787 return 1;
4788 }
4789
4790 static int handle_xsetbv(struct kvm_vcpu *vcpu)
4791 {
4792 u64 new_bv = kvm_read_edx_eax(vcpu);
4793 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4794
4795 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4796 skip_emulated_instruction(vcpu);
4797 return 1;
4798 }
4799
4800 static int handle_apic_access(struct kvm_vcpu *vcpu)
4801 {
4802 if (likely(fasteoi)) {
4803 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4804 int access_type, offset;
4805
4806 access_type = exit_qualification & APIC_ACCESS_TYPE;
4807 offset = exit_qualification & APIC_ACCESS_OFFSET;
4808 /*
4809 * Sane guest uses MOV to write EOI, with written value
4810 * not cared. So make a short-circuit here by avoiding
4811 * heavy instruction emulation.
4812 */
4813 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
4814 (offset == APIC_EOI)) {
4815 kvm_lapic_set_eoi(vcpu);
4816 skip_emulated_instruction(vcpu);
4817 return 1;
4818 }
4819 }
4820 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4821 }
4822
4823 static int handle_task_switch(struct kvm_vcpu *vcpu)
4824 {
4825 struct vcpu_vmx *vmx = to_vmx(vcpu);
4826 unsigned long exit_qualification;
4827 bool has_error_code = false;
4828 u32 error_code = 0;
4829 u16 tss_selector;
4830 int reason, type, idt_v, idt_index;
4831
4832 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
4833 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
4834 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
4835
4836 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4837
4838 reason = (u32)exit_qualification >> 30;
4839 if (reason == TASK_SWITCH_GATE && idt_v) {
4840 switch (type) {
4841 case INTR_TYPE_NMI_INTR:
4842 vcpu->arch.nmi_injected = false;
4843 vmx_set_nmi_mask(vcpu, true);
4844 break;
4845 case INTR_TYPE_EXT_INTR:
4846 case INTR_TYPE_SOFT_INTR:
4847 kvm_clear_interrupt_queue(vcpu);
4848 break;
4849 case INTR_TYPE_HARD_EXCEPTION:
4850 if (vmx->idt_vectoring_info &
4851 VECTORING_INFO_DELIVER_CODE_MASK) {
4852 has_error_code = true;
4853 error_code =
4854 vmcs_read32(IDT_VECTORING_ERROR_CODE);
4855 }
4856 /* fall through */
4857 case INTR_TYPE_SOFT_EXCEPTION:
4858 kvm_clear_exception_queue(vcpu);
4859 break;
4860 default:
4861 break;
4862 }
4863 }
4864 tss_selector = exit_qualification;
4865
4866 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
4867 type != INTR_TYPE_EXT_INTR &&
4868 type != INTR_TYPE_NMI_INTR))
4869 skip_emulated_instruction(vcpu);
4870
4871 if (kvm_task_switch(vcpu, tss_selector,
4872 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
4873 has_error_code, error_code) == EMULATE_FAIL) {
4874 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4875 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4876 vcpu->run->internal.ndata = 0;
4877 return 0;
4878 }
4879
4880 /* clear all local breakpoint enable flags */
4881 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
4882
4883 /*
4884 * TODO: What about debug traps on tss switch?
4885 * Are we supposed to inject them and update dr6?
4886 */
4887
4888 return 1;
4889 }
4890
4891 static int handle_ept_violation(struct kvm_vcpu *vcpu)
4892 {
4893 unsigned long exit_qualification;
4894 gpa_t gpa;
4895 u32 error_code;
4896 int gla_validity;
4897
4898 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4899
4900 gla_validity = (exit_qualification >> 7) & 0x3;
4901 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
4902 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
4903 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4904 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
4905 vmcs_readl(GUEST_LINEAR_ADDRESS));
4906 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
4907 (long unsigned int)exit_qualification);
4908 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4909 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
4910 return 0;
4911 }
4912
4913 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4914 trace_kvm_page_fault(gpa, exit_qualification);
4915
4916 /* It is a write fault? */
4917 error_code = exit_qualification & (1U << 1);
4918 /* ept page table is present? */
4919 error_code |= (exit_qualification >> 3) & 0x1;
4920
4921 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
4922 }
4923
4924 static u64 ept_rsvd_mask(u64 spte, int level)
4925 {
4926 int i;
4927 u64 mask = 0;
4928
4929 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
4930 mask |= (1ULL << i);
4931
4932 if (level > 2)
4933 /* bits 7:3 reserved */
4934 mask |= 0xf8;
4935 else if (level == 2) {
4936 if (spte & (1ULL << 7))
4937 /* 2MB ref, bits 20:12 reserved */
4938 mask |= 0x1ff000;
4939 else
4940 /* bits 6:3 reserved */
4941 mask |= 0x78;
4942 }
4943
4944 return mask;
4945 }
4946
4947 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
4948 int level)
4949 {
4950 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
4951
4952 /* 010b (write-only) */
4953 WARN_ON((spte & 0x7) == 0x2);
4954
4955 /* 110b (write/execute) */
4956 WARN_ON((spte & 0x7) == 0x6);
4957
4958 /* 100b (execute-only) and value not supported by logical processor */
4959 if (!cpu_has_vmx_ept_execute_only())
4960 WARN_ON((spte & 0x7) == 0x4);
4961
4962 /* not 000b */
4963 if ((spte & 0x7)) {
4964 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
4965
4966 if (rsvd_bits != 0) {
4967 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
4968 __func__, rsvd_bits);
4969 WARN_ON(1);
4970 }
4971
4972 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
4973 u64 ept_mem_type = (spte & 0x38) >> 3;
4974
4975 if (ept_mem_type == 2 || ept_mem_type == 3 ||
4976 ept_mem_type == 7) {
4977 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
4978 __func__, ept_mem_type);
4979 WARN_ON(1);
4980 }
4981 }
4982 }
4983 }
4984
4985 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
4986 {
4987 u64 sptes[4];
4988 int nr_sptes, i, ret;
4989 gpa_t gpa;
4990
4991 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4992
4993 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
4994 if (likely(ret == 1))
4995 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
4996 EMULATE_DONE;
4997 if (unlikely(!ret))
4998 return 1;
4999
5000 /* It is the real ept misconfig */
5001 printk(KERN_ERR "EPT: Misconfiguration.\n");
5002 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5003
5004 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5005
5006 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5007 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5008
5009 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5010 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
5011
5012 return 0;
5013 }
5014
5015 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5016 {
5017 u32 cpu_based_vm_exec_control;
5018
5019 /* clear pending NMI */
5020 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5021 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5022 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5023 ++vcpu->stat.nmi_window_exits;
5024 kvm_make_request(KVM_REQ_EVENT, vcpu);
5025
5026 return 1;
5027 }
5028
5029 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5030 {
5031 struct vcpu_vmx *vmx = to_vmx(vcpu);
5032 enum emulation_result err = EMULATE_DONE;
5033 int ret = 1;
5034 u32 cpu_exec_ctrl;
5035 bool intr_window_requested;
5036 unsigned count = 130;
5037
5038 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5039 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
5040
5041 while (!guest_state_valid(vcpu) && count-- != 0) {
5042 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5043 return handle_interrupt_window(&vmx->vcpu);
5044
5045 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5046 return 1;
5047
5048 err = emulate_instruction(vcpu, 0);
5049
5050 if (err == EMULATE_DO_MMIO) {
5051 ret = 0;
5052 goto out;
5053 }
5054
5055 if (err != EMULATE_DONE) {
5056 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5057 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5058 vcpu->run->internal.ndata = 0;
5059 return 0;
5060 }
5061
5062 if (signal_pending(current))
5063 goto out;
5064 if (need_resched())
5065 schedule();
5066 }
5067
5068 vmx->emulation_required = !guest_state_valid(vcpu);
5069 out:
5070 return ret;
5071 }
5072
5073 /*
5074 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5075 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5076 */
5077 static int handle_pause(struct kvm_vcpu *vcpu)
5078 {
5079 skip_emulated_instruction(vcpu);
5080 kvm_vcpu_on_spin(vcpu);
5081
5082 return 1;
5083 }
5084
5085 static int handle_invalid_op(struct kvm_vcpu *vcpu)
5086 {
5087 kvm_queue_exception(vcpu, UD_VECTOR);
5088 return 1;
5089 }
5090
5091 /*
5092 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5093 * We could reuse a single VMCS for all the L2 guests, but we also want the
5094 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5095 * allows keeping them loaded on the processor, and in the future will allow
5096 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5097 * every entry if they never change.
5098 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5099 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5100 *
5101 * The following functions allocate and free a vmcs02 in this pool.
5102 */
5103
5104 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5105 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5106 {
5107 struct vmcs02_list *item;
5108 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5109 if (item->vmptr == vmx->nested.current_vmptr) {
5110 list_move(&item->list, &vmx->nested.vmcs02_pool);
5111 return &item->vmcs02;
5112 }
5113
5114 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5115 /* Recycle the least recently used VMCS. */
5116 item = list_entry(vmx->nested.vmcs02_pool.prev,
5117 struct vmcs02_list, list);
5118 item->vmptr = vmx->nested.current_vmptr;
5119 list_move(&item->list, &vmx->nested.vmcs02_pool);
5120 return &item->vmcs02;
5121 }
5122
5123 /* Create a new VMCS */
5124 item = (struct vmcs02_list *)
5125 kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
5126 if (!item)
5127 return NULL;
5128 item->vmcs02.vmcs = alloc_vmcs();
5129 if (!item->vmcs02.vmcs) {
5130 kfree(item);
5131 return NULL;
5132 }
5133 loaded_vmcs_init(&item->vmcs02);
5134 item->vmptr = vmx->nested.current_vmptr;
5135 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5136 vmx->nested.vmcs02_num++;
5137 return &item->vmcs02;
5138 }
5139
5140 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5141 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5142 {
5143 struct vmcs02_list *item;
5144 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5145 if (item->vmptr == vmptr) {
5146 free_loaded_vmcs(&item->vmcs02);
5147 list_del(&item->list);
5148 kfree(item);
5149 vmx->nested.vmcs02_num--;
5150 return;
5151 }
5152 }
5153
5154 /*
5155 * Free all VMCSs saved for this vcpu, except the one pointed by
5156 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5157 * currently used, if running L2), and vmcs01 when running L2.
5158 */
5159 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5160 {
5161 struct vmcs02_list *item, *n;
5162 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5163 if (vmx->loaded_vmcs != &item->vmcs02)
5164 free_loaded_vmcs(&item->vmcs02);
5165 list_del(&item->list);
5166 kfree(item);
5167 }
5168 vmx->nested.vmcs02_num = 0;
5169
5170 if (vmx->loaded_vmcs != &vmx->vmcs01)
5171 free_loaded_vmcs(&vmx->vmcs01);
5172 }
5173
5174 /*
5175 * Emulate the VMXON instruction.
5176 * Currently, we just remember that VMX is active, and do not save or even
5177 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5178 * do not currently need to store anything in that guest-allocated memory
5179 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5180 * argument is different from the VMXON pointer (which the spec says they do).
5181 */
5182 static int handle_vmon(struct kvm_vcpu *vcpu)
5183 {
5184 struct kvm_segment cs;
5185 struct vcpu_vmx *vmx = to_vmx(vcpu);
5186
5187 /* The Intel VMX Instruction Reference lists a bunch of bits that
5188 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5189 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5190 * Otherwise, we should fail with #UD. We test these now:
5191 */
5192 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5193 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5194 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5195 kvm_queue_exception(vcpu, UD_VECTOR);
5196 return 1;
5197 }
5198
5199 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5200 if (is_long_mode(vcpu) && !cs.l) {
5201 kvm_queue_exception(vcpu, UD_VECTOR);
5202 return 1;
5203 }
5204
5205 if (vmx_get_cpl(vcpu)) {
5206 kvm_inject_gp(vcpu, 0);
5207 return 1;
5208 }
5209
5210 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5211 vmx->nested.vmcs02_num = 0;
5212
5213 vmx->nested.vmxon = true;
5214
5215 skip_emulated_instruction(vcpu);
5216 return 1;
5217 }
5218
5219 /*
5220 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5221 * for running VMX instructions (except VMXON, whose prerequisites are
5222 * slightly different). It also specifies what exception to inject otherwise.
5223 */
5224 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5225 {
5226 struct kvm_segment cs;
5227 struct vcpu_vmx *vmx = to_vmx(vcpu);
5228
5229 if (!vmx->nested.vmxon) {
5230 kvm_queue_exception(vcpu, UD_VECTOR);
5231 return 0;
5232 }
5233
5234 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5235 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5236 (is_long_mode(vcpu) && !cs.l)) {
5237 kvm_queue_exception(vcpu, UD_VECTOR);
5238 return 0;
5239 }
5240
5241 if (vmx_get_cpl(vcpu)) {
5242 kvm_inject_gp(vcpu, 0);
5243 return 0;
5244 }
5245
5246 return 1;
5247 }
5248
5249 /*
5250 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5251 * just stops using VMX.
5252 */
5253 static void free_nested(struct vcpu_vmx *vmx)
5254 {
5255 if (!vmx->nested.vmxon)
5256 return;
5257 vmx->nested.vmxon = false;
5258 if (vmx->nested.current_vmptr != -1ull) {
5259 kunmap(vmx->nested.current_vmcs12_page);
5260 nested_release_page(vmx->nested.current_vmcs12_page);
5261 vmx->nested.current_vmptr = -1ull;
5262 vmx->nested.current_vmcs12 = NULL;
5263 }
5264 /* Unpin physical memory we referred to in current vmcs02 */
5265 if (vmx->nested.apic_access_page) {
5266 nested_release_page(vmx->nested.apic_access_page);
5267 vmx->nested.apic_access_page = 0;
5268 }
5269
5270 nested_free_all_saved_vmcss(vmx);
5271 }
5272
5273 /* Emulate the VMXOFF instruction */
5274 static int handle_vmoff(struct kvm_vcpu *vcpu)
5275 {
5276 if (!nested_vmx_check_permission(vcpu))
5277 return 1;
5278 free_nested(to_vmx(vcpu));
5279 skip_emulated_instruction(vcpu);
5280 return 1;
5281 }
5282
5283 /*
5284 * Decode the memory-address operand of a vmx instruction, as recorded on an
5285 * exit caused by such an instruction (run by a guest hypervisor).
5286 * On success, returns 0. When the operand is invalid, returns 1 and throws
5287 * #UD or #GP.
5288 */
5289 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5290 unsigned long exit_qualification,
5291 u32 vmx_instruction_info, gva_t *ret)
5292 {
5293 /*
5294 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5295 * Execution", on an exit, vmx_instruction_info holds most of the
5296 * addressing components of the operand. Only the displacement part
5297 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5298 * For how an actual address is calculated from all these components,
5299 * refer to Vol. 1, "Operand Addressing".
5300 */
5301 int scaling = vmx_instruction_info & 3;
5302 int addr_size = (vmx_instruction_info >> 7) & 7;
5303 bool is_reg = vmx_instruction_info & (1u << 10);
5304 int seg_reg = (vmx_instruction_info >> 15) & 7;
5305 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5306 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5307 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5308 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5309
5310 if (is_reg) {
5311 kvm_queue_exception(vcpu, UD_VECTOR);
5312 return 1;
5313 }
5314
5315 /* Addr = segment_base + offset */
5316 /* offset = base + [index * scale] + displacement */
5317 *ret = vmx_get_segment_base(vcpu, seg_reg);
5318 if (base_is_valid)
5319 *ret += kvm_register_read(vcpu, base_reg);
5320 if (index_is_valid)
5321 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5322 *ret += exit_qualification; /* holds the displacement */
5323
5324 if (addr_size == 1) /* 32 bit */
5325 *ret &= 0xffffffff;
5326
5327 /*
5328 * TODO: throw #GP (and return 1) in various cases that the VM*
5329 * instructions require it - e.g., offset beyond segment limit,
5330 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5331 * address, and so on. Currently these are not checked.
5332 */
5333 return 0;
5334 }
5335
5336 /*
5337 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5338 * set the success or error code of an emulated VMX instruction, as specified
5339 * by Vol 2B, VMX Instruction Reference, "Conventions".
5340 */
5341 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5342 {
5343 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5344 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5345 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5346 }
5347
5348 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5349 {
5350 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5351 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5352 X86_EFLAGS_SF | X86_EFLAGS_OF))
5353 | X86_EFLAGS_CF);
5354 }
5355
5356 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5357 u32 vm_instruction_error)
5358 {
5359 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5360 /*
5361 * failValid writes the error number to the current VMCS, which
5362 * can't be done there isn't a current VMCS.
5363 */
5364 nested_vmx_failInvalid(vcpu);
5365 return;
5366 }
5367 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5368 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5369 X86_EFLAGS_SF | X86_EFLAGS_OF))
5370 | X86_EFLAGS_ZF);
5371 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5372 }
5373
5374 /* Emulate the VMCLEAR instruction */
5375 static int handle_vmclear(struct kvm_vcpu *vcpu)
5376 {
5377 struct vcpu_vmx *vmx = to_vmx(vcpu);
5378 gva_t gva;
5379 gpa_t vmptr;
5380 struct vmcs12 *vmcs12;
5381 struct page *page;
5382 struct x86_exception e;
5383
5384 if (!nested_vmx_check_permission(vcpu))
5385 return 1;
5386
5387 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5388 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5389 return 1;
5390
5391 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5392 sizeof(vmptr), &e)) {
5393 kvm_inject_page_fault(vcpu, &e);
5394 return 1;
5395 }
5396
5397 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5398 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5399 skip_emulated_instruction(vcpu);
5400 return 1;
5401 }
5402
5403 if (vmptr == vmx->nested.current_vmptr) {
5404 kunmap(vmx->nested.current_vmcs12_page);
5405 nested_release_page(vmx->nested.current_vmcs12_page);
5406 vmx->nested.current_vmptr = -1ull;
5407 vmx->nested.current_vmcs12 = NULL;
5408 }
5409
5410 page = nested_get_page(vcpu, vmptr);
5411 if (page == NULL) {
5412 /*
5413 * For accurate processor emulation, VMCLEAR beyond available
5414 * physical memory should do nothing at all. However, it is
5415 * possible that a nested vmx bug, not a guest hypervisor bug,
5416 * resulted in this case, so let's shut down before doing any
5417 * more damage:
5418 */
5419 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5420 return 1;
5421 }
5422 vmcs12 = kmap(page);
5423 vmcs12->launch_state = 0;
5424 kunmap(page);
5425 nested_release_page(page);
5426
5427 nested_free_vmcs02(vmx, vmptr);
5428
5429 skip_emulated_instruction(vcpu);
5430 nested_vmx_succeed(vcpu);
5431 return 1;
5432 }
5433
5434 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5435
5436 /* Emulate the VMLAUNCH instruction */
5437 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5438 {
5439 return nested_vmx_run(vcpu, true);
5440 }
5441
5442 /* Emulate the VMRESUME instruction */
5443 static int handle_vmresume(struct kvm_vcpu *vcpu)
5444 {
5445
5446 return nested_vmx_run(vcpu, false);
5447 }
5448
5449 enum vmcs_field_type {
5450 VMCS_FIELD_TYPE_U16 = 0,
5451 VMCS_FIELD_TYPE_U64 = 1,
5452 VMCS_FIELD_TYPE_U32 = 2,
5453 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5454 };
5455
5456 static inline int vmcs_field_type(unsigned long field)
5457 {
5458 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
5459 return VMCS_FIELD_TYPE_U32;
5460 return (field >> 13) & 0x3 ;
5461 }
5462
5463 static inline int vmcs_field_readonly(unsigned long field)
5464 {
5465 return (((field >> 10) & 0x3) == 1);
5466 }
5467
5468 /*
5469 * Read a vmcs12 field. Since these can have varying lengths and we return
5470 * one type, we chose the biggest type (u64) and zero-extend the return value
5471 * to that size. Note that the caller, handle_vmread, might need to use only
5472 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5473 * 64-bit fields are to be returned).
5474 */
5475 static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5476 unsigned long field, u64 *ret)
5477 {
5478 short offset = vmcs_field_to_offset(field);
5479 char *p;
5480
5481 if (offset < 0)
5482 return 0;
5483
5484 p = ((char *)(get_vmcs12(vcpu))) + offset;
5485
5486 switch (vmcs_field_type(field)) {
5487 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5488 *ret = *((natural_width *)p);
5489 return 1;
5490 case VMCS_FIELD_TYPE_U16:
5491 *ret = *((u16 *)p);
5492 return 1;
5493 case VMCS_FIELD_TYPE_U32:
5494 *ret = *((u32 *)p);
5495 return 1;
5496 case VMCS_FIELD_TYPE_U64:
5497 *ret = *((u64 *)p);
5498 return 1;
5499 default:
5500 return 0; /* can never happen. */
5501 }
5502 }
5503
5504 /*
5505 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5506 * used before) all generate the same failure when it is missing.
5507 */
5508 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5509 {
5510 struct vcpu_vmx *vmx = to_vmx(vcpu);
5511 if (vmx->nested.current_vmptr == -1ull) {
5512 nested_vmx_failInvalid(vcpu);
5513 skip_emulated_instruction(vcpu);
5514 return 0;
5515 }
5516 return 1;
5517 }
5518
5519 static int handle_vmread(struct kvm_vcpu *vcpu)
5520 {
5521 unsigned long field;
5522 u64 field_value;
5523 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5524 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5525 gva_t gva = 0;
5526
5527 if (!nested_vmx_check_permission(vcpu) ||
5528 !nested_vmx_check_vmcs12(vcpu))
5529 return 1;
5530
5531 /* Decode instruction info and find the field to read */
5532 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5533 /* Read the field, zero-extended to a u64 field_value */
5534 if (!vmcs12_read_any(vcpu, field, &field_value)) {
5535 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5536 skip_emulated_instruction(vcpu);
5537 return 1;
5538 }
5539 /*
5540 * Now copy part of this value to register or memory, as requested.
5541 * Note that the number of bits actually copied is 32 or 64 depending
5542 * on the guest's mode (32 or 64 bit), not on the given field's length.
5543 */
5544 if (vmx_instruction_info & (1u << 10)) {
5545 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5546 field_value);
5547 } else {
5548 if (get_vmx_mem_address(vcpu, exit_qualification,
5549 vmx_instruction_info, &gva))
5550 return 1;
5551 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5552 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5553 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5554 }
5555
5556 nested_vmx_succeed(vcpu);
5557 skip_emulated_instruction(vcpu);
5558 return 1;
5559 }
5560
5561
5562 static int handle_vmwrite(struct kvm_vcpu *vcpu)
5563 {
5564 unsigned long field;
5565 gva_t gva;
5566 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5567 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5568 char *p;
5569 short offset;
5570 /* The value to write might be 32 or 64 bits, depending on L1's long
5571 * mode, and eventually we need to write that into a field of several
5572 * possible lengths. The code below first zero-extends the value to 64
5573 * bit (field_value), and then copies only the approriate number of
5574 * bits into the vmcs12 field.
5575 */
5576 u64 field_value = 0;
5577 struct x86_exception e;
5578
5579 if (!nested_vmx_check_permission(vcpu) ||
5580 !nested_vmx_check_vmcs12(vcpu))
5581 return 1;
5582
5583 if (vmx_instruction_info & (1u << 10))
5584 field_value = kvm_register_read(vcpu,
5585 (((vmx_instruction_info) >> 3) & 0xf));
5586 else {
5587 if (get_vmx_mem_address(vcpu, exit_qualification,
5588 vmx_instruction_info, &gva))
5589 return 1;
5590 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5591 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5592 kvm_inject_page_fault(vcpu, &e);
5593 return 1;
5594 }
5595 }
5596
5597
5598 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5599 if (vmcs_field_readonly(field)) {
5600 nested_vmx_failValid(vcpu,
5601 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5602 skip_emulated_instruction(vcpu);
5603 return 1;
5604 }
5605
5606 offset = vmcs_field_to_offset(field);
5607 if (offset < 0) {
5608 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5609 skip_emulated_instruction(vcpu);
5610 return 1;
5611 }
5612 p = ((char *) get_vmcs12(vcpu)) + offset;
5613
5614 switch (vmcs_field_type(field)) {
5615 case VMCS_FIELD_TYPE_U16:
5616 *(u16 *)p = field_value;
5617 break;
5618 case VMCS_FIELD_TYPE_U32:
5619 *(u32 *)p = field_value;
5620 break;
5621 case VMCS_FIELD_TYPE_U64:
5622 *(u64 *)p = field_value;
5623 break;
5624 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5625 *(natural_width *)p = field_value;
5626 break;
5627 default:
5628 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5629 skip_emulated_instruction(vcpu);
5630 return 1;
5631 }
5632
5633 nested_vmx_succeed(vcpu);
5634 skip_emulated_instruction(vcpu);
5635 return 1;
5636 }
5637
5638 /* Emulate the VMPTRLD instruction */
5639 static int handle_vmptrld(struct kvm_vcpu *vcpu)
5640 {
5641 struct vcpu_vmx *vmx = to_vmx(vcpu);
5642 gva_t gva;
5643 gpa_t vmptr;
5644 struct x86_exception e;
5645
5646 if (!nested_vmx_check_permission(vcpu))
5647 return 1;
5648
5649 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5650 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5651 return 1;
5652
5653 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5654 sizeof(vmptr), &e)) {
5655 kvm_inject_page_fault(vcpu, &e);
5656 return 1;
5657 }
5658
5659 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5660 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5661 skip_emulated_instruction(vcpu);
5662 return 1;
5663 }
5664
5665 if (vmx->nested.current_vmptr != vmptr) {
5666 struct vmcs12 *new_vmcs12;
5667 struct page *page;
5668 page = nested_get_page(vcpu, vmptr);
5669 if (page == NULL) {
5670 nested_vmx_failInvalid(vcpu);
5671 skip_emulated_instruction(vcpu);
5672 return 1;
5673 }
5674 new_vmcs12 = kmap(page);
5675 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5676 kunmap(page);
5677 nested_release_page_clean(page);
5678 nested_vmx_failValid(vcpu,
5679 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5680 skip_emulated_instruction(vcpu);
5681 return 1;
5682 }
5683 if (vmx->nested.current_vmptr != -1ull) {
5684 kunmap(vmx->nested.current_vmcs12_page);
5685 nested_release_page(vmx->nested.current_vmcs12_page);
5686 }
5687
5688 vmx->nested.current_vmptr = vmptr;
5689 vmx->nested.current_vmcs12 = new_vmcs12;
5690 vmx->nested.current_vmcs12_page = page;
5691 }
5692
5693 nested_vmx_succeed(vcpu);
5694 skip_emulated_instruction(vcpu);
5695 return 1;
5696 }
5697
5698 /* Emulate the VMPTRST instruction */
5699 static int handle_vmptrst(struct kvm_vcpu *vcpu)
5700 {
5701 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5702 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5703 gva_t vmcs_gva;
5704 struct x86_exception e;
5705
5706 if (!nested_vmx_check_permission(vcpu))
5707 return 1;
5708
5709 if (get_vmx_mem_address(vcpu, exit_qualification,
5710 vmx_instruction_info, &vmcs_gva))
5711 return 1;
5712 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5713 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5714 (void *)&to_vmx(vcpu)->nested.current_vmptr,
5715 sizeof(u64), &e)) {
5716 kvm_inject_page_fault(vcpu, &e);
5717 return 1;
5718 }
5719 nested_vmx_succeed(vcpu);
5720 skip_emulated_instruction(vcpu);
5721 return 1;
5722 }
5723
5724 /*
5725 * The exit handlers return 1 if the exit was handled fully and guest execution
5726 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5727 * to be done to userspace and return 0.
5728 */
5729 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5730 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
5731 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
5732 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
5733 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
5734 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
5735 [EXIT_REASON_CR_ACCESS] = handle_cr,
5736 [EXIT_REASON_DR_ACCESS] = handle_dr,
5737 [EXIT_REASON_CPUID] = handle_cpuid,
5738 [EXIT_REASON_MSR_READ] = handle_rdmsr,
5739 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
5740 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
5741 [EXIT_REASON_HLT] = handle_halt,
5742 [EXIT_REASON_INVD] = handle_invd,
5743 [EXIT_REASON_INVLPG] = handle_invlpg,
5744 [EXIT_REASON_RDPMC] = handle_rdpmc,
5745 [EXIT_REASON_VMCALL] = handle_vmcall,
5746 [EXIT_REASON_VMCLEAR] = handle_vmclear,
5747 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
5748 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
5749 [EXIT_REASON_VMPTRST] = handle_vmptrst,
5750 [EXIT_REASON_VMREAD] = handle_vmread,
5751 [EXIT_REASON_VMRESUME] = handle_vmresume,
5752 [EXIT_REASON_VMWRITE] = handle_vmwrite,
5753 [EXIT_REASON_VMOFF] = handle_vmoff,
5754 [EXIT_REASON_VMON] = handle_vmon,
5755 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5756 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
5757 [EXIT_REASON_WBINVD] = handle_wbinvd,
5758 [EXIT_REASON_XSETBV] = handle_xsetbv,
5759 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
5760 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
5761 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5762 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
5763 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
5764 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
5765 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
5766 };
5767
5768 static const int kvm_vmx_max_exit_handlers =
5769 ARRAY_SIZE(kvm_vmx_exit_handlers);
5770
5771 /*
5772 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5773 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5774 * disinterest in the current event (read or write a specific MSR) by using an
5775 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5776 */
5777 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5778 struct vmcs12 *vmcs12, u32 exit_reason)
5779 {
5780 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
5781 gpa_t bitmap;
5782
5783 if (!nested_cpu_has(get_vmcs12(vcpu), CPU_BASED_USE_MSR_BITMAPS))
5784 return 1;
5785
5786 /*
5787 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5788 * for the four combinations of read/write and low/high MSR numbers.
5789 * First we need to figure out which of the four to use:
5790 */
5791 bitmap = vmcs12->msr_bitmap;
5792 if (exit_reason == EXIT_REASON_MSR_WRITE)
5793 bitmap += 2048;
5794 if (msr_index >= 0xc0000000) {
5795 msr_index -= 0xc0000000;
5796 bitmap += 1024;
5797 }
5798
5799 /* Then read the msr_index'th bit from this bitmap: */
5800 if (msr_index < 1024*8) {
5801 unsigned char b;
5802 kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1);
5803 return 1 & (b >> (msr_index & 7));
5804 } else
5805 return 1; /* let L1 handle the wrong parameter */
5806 }
5807
5808 /*
5809 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5810 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5811 * intercept (via guest_host_mask etc.) the current event.
5812 */
5813 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
5814 struct vmcs12 *vmcs12)
5815 {
5816 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5817 int cr = exit_qualification & 15;
5818 int reg = (exit_qualification >> 8) & 15;
5819 unsigned long val = kvm_register_read(vcpu, reg);
5820
5821 switch ((exit_qualification >> 4) & 3) {
5822 case 0: /* mov to cr */
5823 switch (cr) {
5824 case 0:
5825 if (vmcs12->cr0_guest_host_mask &
5826 (val ^ vmcs12->cr0_read_shadow))
5827 return 1;
5828 break;
5829 case 3:
5830 if ((vmcs12->cr3_target_count >= 1 &&
5831 vmcs12->cr3_target_value0 == val) ||
5832 (vmcs12->cr3_target_count >= 2 &&
5833 vmcs12->cr3_target_value1 == val) ||
5834 (vmcs12->cr3_target_count >= 3 &&
5835 vmcs12->cr3_target_value2 == val) ||
5836 (vmcs12->cr3_target_count >= 4 &&
5837 vmcs12->cr3_target_value3 == val))
5838 return 0;
5839 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
5840 return 1;
5841 break;
5842 case 4:
5843 if (vmcs12->cr4_guest_host_mask &
5844 (vmcs12->cr4_read_shadow ^ val))
5845 return 1;
5846 break;
5847 case 8:
5848 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
5849 return 1;
5850 break;
5851 }
5852 break;
5853 case 2: /* clts */
5854 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
5855 (vmcs12->cr0_read_shadow & X86_CR0_TS))
5856 return 1;
5857 break;
5858 case 1: /* mov from cr */
5859 switch (cr) {
5860 case 3:
5861 if (vmcs12->cpu_based_vm_exec_control &
5862 CPU_BASED_CR3_STORE_EXITING)
5863 return 1;
5864 break;
5865 case 8:
5866 if (vmcs12->cpu_based_vm_exec_control &
5867 CPU_BASED_CR8_STORE_EXITING)
5868 return 1;
5869 break;
5870 }
5871 break;
5872 case 3: /* lmsw */
5873 /*
5874 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
5875 * cr0. Other attempted changes are ignored, with no exit.
5876 */
5877 if (vmcs12->cr0_guest_host_mask & 0xe &
5878 (val ^ vmcs12->cr0_read_shadow))
5879 return 1;
5880 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
5881 !(vmcs12->cr0_read_shadow & 0x1) &&
5882 (val & 0x1))
5883 return 1;
5884 break;
5885 }
5886 return 0;
5887 }
5888
5889 /*
5890 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
5891 * should handle it ourselves in L0 (and then continue L2). Only call this
5892 * when in is_guest_mode (L2).
5893 */
5894 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
5895 {
5896 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
5897 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5898 struct vcpu_vmx *vmx = to_vmx(vcpu);
5899 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5900
5901 if (vmx->nested.nested_run_pending)
5902 return 0;
5903
5904 if (unlikely(vmx->fail)) {
5905 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
5906 vmcs_read32(VM_INSTRUCTION_ERROR));
5907 return 1;
5908 }
5909
5910 switch (exit_reason) {
5911 case EXIT_REASON_EXCEPTION_NMI:
5912 if (!is_exception(intr_info))
5913 return 0;
5914 else if (is_page_fault(intr_info))
5915 return enable_ept;
5916 return vmcs12->exception_bitmap &
5917 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
5918 case EXIT_REASON_EXTERNAL_INTERRUPT:
5919 return 0;
5920 case EXIT_REASON_TRIPLE_FAULT:
5921 return 1;
5922 case EXIT_REASON_PENDING_INTERRUPT:
5923 case EXIT_REASON_NMI_WINDOW:
5924 /*
5925 * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
5926 * (aka Interrupt Window Exiting) only when L1 turned it on,
5927 * so if we got a PENDING_INTERRUPT exit, this must be for L1.
5928 * Same for NMI Window Exiting.
5929 */
5930 return 1;
5931 case EXIT_REASON_TASK_SWITCH:
5932 return 1;
5933 case EXIT_REASON_CPUID:
5934 return 1;
5935 case EXIT_REASON_HLT:
5936 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
5937 case EXIT_REASON_INVD:
5938 return 1;
5939 case EXIT_REASON_INVLPG:
5940 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
5941 case EXIT_REASON_RDPMC:
5942 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
5943 case EXIT_REASON_RDTSC:
5944 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
5945 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
5946 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
5947 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
5948 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
5949 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
5950 /*
5951 * VMX instructions trap unconditionally. This allows L1 to
5952 * emulate them for its L2 guest, i.e., allows 3-level nesting!
5953 */
5954 return 1;
5955 case EXIT_REASON_CR_ACCESS:
5956 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
5957 case EXIT_REASON_DR_ACCESS:
5958 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
5959 case EXIT_REASON_IO_INSTRUCTION:
5960 /* TODO: support IO bitmaps */
5961 return 1;
5962 case EXIT_REASON_MSR_READ:
5963 case EXIT_REASON_MSR_WRITE:
5964 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
5965 case EXIT_REASON_INVALID_STATE:
5966 return 1;
5967 case EXIT_REASON_MWAIT_INSTRUCTION:
5968 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5969 case EXIT_REASON_MONITOR_INSTRUCTION:
5970 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
5971 case EXIT_REASON_PAUSE_INSTRUCTION:
5972 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
5973 nested_cpu_has2(vmcs12,
5974 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
5975 case EXIT_REASON_MCE_DURING_VMENTRY:
5976 return 0;
5977 case EXIT_REASON_TPR_BELOW_THRESHOLD:
5978 return 1;
5979 case EXIT_REASON_APIC_ACCESS:
5980 return nested_cpu_has2(vmcs12,
5981 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
5982 case EXIT_REASON_EPT_VIOLATION:
5983 case EXIT_REASON_EPT_MISCONFIG:
5984 return 0;
5985 case EXIT_REASON_WBINVD:
5986 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
5987 case EXIT_REASON_XSETBV:
5988 return 1;
5989 default:
5990 return 1;
5991 }
5992 }
5993
5994 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5995 {
5996 *info1 = vmcs_readl(EXIT_QUALIFICATION);
5997 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5998 }
5999
6000 /*
6001 * The guest has exited. See if we can fix it or if we need userspace
6002 * assistance.
6003 */
6004 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6005 {
6006 struct vcpu_vmx *vmx = to_vmx(vcpu);
6007 u32 exit_reason = vmx->exit_reason;
6008 u32 vectoring_info = vmx->idt_vectoring_info;
6009
6010 /* If guest state is invalid, start emulating */
6011 if (vmx->emulation_required && emulate_invalid_guest_state)
6012 return handle_invalid_guest_state(vcpu);
6013
6014 /*
6015 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
6016 * we did not inject a still-pending event to L1 now because of
6017 * nested_run_pending, we need to re-enable this bit.
6018 */
6019 if (vmx->nested.nested_run_pending)
6020 kvm_make_request(KVM_REQ_EVENT, vcpu);
6021
6022 if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
6023 exit_reason == EXIT_REASON_VMRESUME))
6024 vmx->nested.nested_run_pending = 1;
6025 else
6026 vmx->nested.nested_run_pending = 0;
6027
6028 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
6029 nested_vmx_vmexit(vcpu);
6030 return 1;
6031 }
6032
6033 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6034 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6035 vcpu->run->fail_entry.hardware_entry_failure_reason
6036 = exit_reason;
6037 return 0;
6038 }
6039
6040 if (unlikely(vmx->fail)) {
6041 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6042 vcpu->run->fail_entry.hardware_entry_failure_reason
6043 = vmcs_read32(VM_INSTRUCTION_ERROR);
6044 return 0;
6045 }
6046
6047 /*
6048 * Note:
6049 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6050 * delivery event since it indicates guest is accessing MMIO.
6051 * The vm-exit can be triggered again after return to guest that
6052 * will cause infinite loop.
6053 */
6054 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
6055 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
6056 exit_reason != EXIT_REASON_EPT_VIOLATION &&
6057 exit_reason != EXIT_REASON_TASK_SWITCH)) {
6058 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6059 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6060 vcpu->run->internal.ndata = 2;
6061 vcpu->run->internal.data[0] = vectoring_info;
6062 vcpu->run->internal.data[1] = exit_reason;
6063 return 0;
6064 }
6065
6066 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6067 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
6068 get_vmcs12(vcpu), vcpu)))) {
6069 if (vmx_interrupt_allowed(vcpu)) {
6070 vmx->soft_vnmi_blocked = 0;
6071 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
6072 vcpu->arch.nmi_pending) {
6073 /*
6074 * This CPU don't support us in finding the end of an
6075 * NMI-blocked window if the guest runs with IRQs
6076 * disabled. So we pull the trigger after 1 s of
6077 * futile waiting, but inform the user about this.
6078 */
6079 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6080 "state on VCPU %d after 1 s timeout\n",
6081 __func__, vcpu->vcpu_id);
6082 vmx->soft_vnmi_blocked = 0;
6083 }
6084 }
6085
6086 if (exit_reason < kvm_vmx_max_exit_handlers
6087 && kvm_vmx_exit_handlers[exit_reason])
6088 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6089 else {
6090 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6091 vcpu->run->hw.hardware_exit_reason = exit_reason;
6092 }
6093 return 0;
6094 }
6095
6096 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6097 {
6098 if (irr == -1 || tpr < irr) {
6099 vmcs_write32(TPR_THRESHOLD, 0);
6100 return;
6101 }
6102
6103 vmcs_write32(TPR_THRESHOLD, irr);
6104 }
6105
6106 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
6107 {
6108 u32 exit_intr_info;
6109
6110 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6111 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6112 return;
6113
6114 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6115 exit_intr_info = vmx->exit_intr_info;
6116
6117 /* Handle machine checks before interrupts are enabled */
6118 if (is_machine_check(exit_intr_info))
6119 kvm_machine_check();
6120
6121 /* We need to handle NMIs before interrupts are enabled */
6122 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
6123 (exit_intr_info & INTR_INFO_VALID_MASK)) {
6124 kvm_before_handle_nmi(&vmx->vcpu);
6125 asm("int $2");
6126 kvm_after_handle_nmi(&vmx->vcpu);
6127 }
6128 }
6129
6130 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6131 {
6132 u32 exit_intr_info;
6133 bool unblock_nmi;
6134 u8 vector;
6135 bool idtv_info_valid;
6136
6137 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6138
6139 if (cpu_has_virtual_nmis()) {
6140 if (vmx->nmi_known_unmasked)
6141 return;
6142 /*
6143 * Can't use vmx->exit_intr_info since we're not sure what
6144 * the exit reason is.
6145 */
6146 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6147 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6148 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6149 /*
6150 * SDM 3: 27.7.1.2 (September 2008)
6151 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6152 * a guest IRET fault.
6153 * SDM 3: 23.2.2 (September 2008)
6154 * Bit 12 is undefined in any of the following cases:
6155 * If the VM exit sets the valid bit in the IDT-vectoring
6156 * information field.
6157 * If the VM exit is due to a double fault.
6158 */
6159 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6160 vector != DF_VECTOR && !idtv_info_valid)
6161 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6162 GUEST_INTR_STATE_NMI);
6163 else
6164 vmx->nmi_known_unmasked =
6165 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6166 & GUEST_INTR_STATE_NMI);
6167 } else if (unlikely(vmx->soft_vnmi_blocked))
6168 vmx->vnmi_blocked_time +=
6169 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
6170 }
6171
6172 static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
6173 u32 idt_vectoring_info,
6174 int instr_len_field,
6175 int error_code_field)
6176 {
6177 u8 vector;
6178 int type;
6179 bool idtv_info_valid;
6180
6181 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6182
6183 vmx->vcpu.arch.nmi_injected = false;
6184 kvm_clear_exception_queue(&vmx->vcpu);
6185 kvm_clear_interrupt_queue(&vmx->vcpu);
6186
6187 if (!idtv_info_valid)
6188 return;
6189
6190 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6191
6192 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6193 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6194
6195 switch (type) {
6196 case INTR_TYPE_NMI_INTR:
6197 vmx->vcpu.arch.nmi_injected = true;
6198 /*
6199 * SDM 3: 27.7.1.2 (September 2008)
6200 * Clear bit "block by NMI" before VM entry if a NMI
6201 * delivery faulted.
6202 */
6203 vmx_set_nmi_mask(&vmx->vcpu, false);
6204 break;
6205 case INTR_TYPE_SOFT_EXCEPTION:
6206 vmx->vcpu.arch.event_exit_inst_len =
6207 vmcs_read32(instr_len_field);
6208 /* fall through */
6209 case INTR_TYPE_HARD_EXCEPTION:
6210 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6211 u32 err = vmcs_read32(error_code_field);
6212 kvm_queue_exception_e(&vmx->vcpu, vector, err);
6213 } else
6214 kvm_queue_exception(&vmx->vcpu, vector);
6215 break;
6216 case INTR_TYPE_SOFT_INTR:
6217 vmx->vcpu.arch.event_exit_inst_len =
6218 vmcs_read32(instr_len_field);
6219 /* fall through */
6220 case INTR_TYPE_EXT_INTR:
6221 kvm_queue_interrupt(&vmx->vcpu, vector,
6222 type == INTR_TYPE_SOFT_INTR);
6223 break;
6224 default:
6225 break;
6226 }
6227 }
6228
6229 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6230 {
6231 if (is_guest_mode(&vmx->vcpu))
6232 return;
6233 __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
6234 VM_EXIT_INSTRUCTION_LEN,
6235 IDT_VECTORING_ERROR_CODE);
6236 }
6237
6238 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6239 {
6240 if (is_guest_mode(vcpu))
6241 return;
6242 __vmx_complete_interrupts(to_vmx(vcpu),
6243 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6244 VM_ENTRY_INSTRUCTION_LEN,
6245 VM_ENTRY_EXCEPTION_ERROR_CODE);
6246
6247 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6248 }
6249
6250 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6251 {
6252 int i, nr_msrs;
6253 struct perf_guest_switch_msr *msrs;
6254
6255 msrs = perf_guest_get_msrs(&nr_msrs);
6256
6257 if (!msrs)
6258 return;
6259
6260 for (i = 0; i < nr_msrs; i++)
6261 if (msrs[i].host == msrs[i].guest)
6262 clear_atomic_switch_msr(vmx, msrs[i].msr);
6263 else
6264 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6265 msrs[i].host);
6266 }
6267
6268 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6269 {
6270 struct vcpu_vmx *vmx = to_vmx(vcpu);
6271 unsigned long debugctlmsr;
6272
6273 if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending) {
6274 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6275 if (vmcs12->idt_vectoring_info_field &
6276 VECTORING_INFO_VALID_MASK) {
6277 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6278 vmcs12->idt_vectoring_info_field);
6279 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6280 vmcs12->vm_exit_instruction_len);
6281 if (vmcs12->idt_vectoring_info_field &
6282 VECTORING_INFO_DELIVER_CODE_MASK)
6283 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6284 vmcs12->idt_vectoring_error_code);
6285 }
6286 }
6287
6288 /* Record the guest's net vcpu time for enforced NMI injections. */
6289 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
6290 vmx->entry_time = ktime_get();
6291
6292 /* Don't enter VMX if guest state is invalid, let the exit handler
6293 start emulation until we arrive back to a valid state */
6294 if (vmx->emulation_required && emulate_invalid_guest_state)
6295 return;
6296
6297 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6298 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6299 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6300 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6301
6302 /* When single-stepping over STI and MOV SS, we must clear the
6303 * corresponding interruptibility bits in the guest state. Otherwise
6304 * vmentry fails as it then expects bit 14 (BS) in pending debug
6305 * exceptions being set, but that's not correct for the guest debugging
6306 * case. */
6307 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6308 vmx_set_interrupt_shadow(vcpu, 0);
6309
6310 atomic_switch_perf_msrs(vmx);
6311 debugctlmsr = get_debugctlmsr();
6312
6313 vmx->__launched = vmx->loaded_vmcs->launched;
6314 asm(
6315 /* Store host registers */
6316 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
6317 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
6318 "push %%" _ASM_CX " \n\t"
6319 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
6320 "je 1f \n\t"
6321 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
6322 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
6323 "1: \n\t"
6324 /* Reload cr2 if changed */
6325 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
6326 "mov %%cr2, %%" _ASM_DX " \n\t"
6327 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
6328 "je 2f \n\t"
6329 "mov %%" _ASM_AX", %%cr2 \n\t"
6330 "2: \n\t"
6331 /* Check if vmlaunch of vmresume is needed */
6332 "cmpl $0, %c[launched](%0) \n\t"
6333 /* Load guest registers. Don't clobber flags. */
6334 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
6335 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
6336 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
6337 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
6338 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
6339 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
6340 #ifdef CONFIG_X86_64
6341 "mov %c[r8](%0), %%r8 \n\t"
6342 "mov %c[r9](%0), %%r9 \n\t"
6343 "mov %c[r10](%0), %%r10 \n\t"
6344 "mov %c[r11](%0), %%r11 \n\t"
6345 "mov %c[r12](%0), %%r12 \n\t"
6346 "mov %c[r13](%0), %%r13 \n\t"
6347 "mov %c[r14](%0), %%r14 \n\t"
6348 "mov %c[r15](%0), %%r15 \n\t"
6349 #endif
6350 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
6351
6352 /* Enter guest mode */
6353 "jne 1f \n\t"
6354 __ex(ASM_VMX_VMLAUNCH) "\n\t"
6355 "jmp 2f \n\t"
6356 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
6357 "2: "
6358 /* Save guest registers, load host registers, keep flags */
6359 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
6360 "pop %0 \n\t"
6361 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
6362 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
6363 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
6364 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
6365 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
6366 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
6367 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
6368 #ifdef CONFIG_X86_64
6369 "mov %%r8, %c[r8](%0) \n\t"
6370 "mov %%r9, %c[r9](%0) \n\t"
6371 "mov %%r10, %c[r10](%0) \n\t"
6372 "mov %%r11, %c[r11](%0) \n\t"
6373 "mov %%r12, %c[r12](%0) \n\t"
6374 "mov %%r13, %c[r13](%0) \n\t"
6375 "mov %%r14, %c[r14](%0) \n\t"
6376 "mov %%r15, %c[r15](%0) \n\t"
6377 #endif
6378 "mov %%cr2, %%" _ASM_AX " \n\t"
6379 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
6380
6381 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
6382 "setbe %c[fail](%0) \n\t"
6383 ".pushsection .rodata \n\t"
6384 ".global vmx_return \n\t"
6385 "vmx_return: " _ASM_PTR " 2b \n\t"
6386 ".popsection"
6387 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
6388 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
6389 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
6390 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
6391 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
6392 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
6393 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
6394 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
6395 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
6396 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
6397 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
6398 #ifdef CONFIG_X86_64
6399 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
6400 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
6401 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
6402 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
6403 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
6404 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
6405 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
6406 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6407 #endif
6408 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
6409 [wordsize]"i"(sizeof(ulong))
6410 : "cc", "memory"
6411 #ifdef CONFIG_X86_64
6412 , "rax", "rbx", "rdi", "rsi"
6413 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
6414 #else
6415 , "eax", "ebx", "edi", "esi"
6416 #endif
6417 );
6418
6419 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6420 if (debugctlmsr)
6421 update_debugctlmsr(debugctlmsr);
6422
6423 #ifndef CONFIG_X86_64
6424 /*
6425 * The sysexit path does not restore ds/es, so we must set them to
6426 * a reasonable value ourselves.
6427 *
6428 * We can't defer this to vmx_load_host_state() since that function
6429 * may be executed in interrupt context, which saves and restore segments
6430 * around it, nullifying its effect.
6431 */
6432 loadsegment(ds, __USER_DS);
6433 loadsegment(es, __USER_DS);
6434 #endif
6435
6436 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6437 | (1 << VCPU_EXREG_RFLAGS)
6438 | (1 << VCPU_EXREG_CPL)
6439 | (1 << VCPU_EXREG_PDPTR)
6440 | (1 << VCPU_EXREG_SEGMENTS)
6441 | (1 << VCPU_EXREG_CR3));
6442 vcpu->arch.regs_dirty = 0;
6443
6444 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6445
6446 if (is_guest_mode(vcpu)) {
6447 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6448 vmcs12->idt_vectoring_info_field = vmx->idt_vectoring_info;
6449 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
6450 vmcs12->idt_vectoring_error_code =
6451 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6452 vmcs12->vm_exit_instruction_len =
6453 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6454 }
6455 }
6456
6457 vmx->loaded_vmcs->launched = 1;
6458
6459 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
6460 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
6461
6462 vmx_complete_atomic_exit(vmx);
6463 vmx_recover_nmi_blocking(vmx);
6464 vmx_complete_interrupts(vmx);
6465 }
6466
6467 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6468 {
6469 struct vcpu_vmx *vmx = to_vmx(vcpu);
6470
6471 free_vpid(vmx);
6472 free_nested(vmx);
6473 free_loaded_vmcs(vmx->loaded_vmcs);
6474 kfree(vmx->guest_msrs);
6475 kvm_vcpu_uninit(vcpu);
6476 kmem_cache_free(kvm_vcpu_cache, vmx);
6477 }
6478
6479 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6480 {
6481 int err;
6482 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
6483 int cpu;
6484
6485 if (!vmx)
6486 return ERR_PTR(-ENOMEM);
6487
6488 allocate_vpid(vmx);
6489
6490 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6491 if (err)
6492 goto free_vcpu;
6493
6494 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
6495 err = -ENOMEM;
6496 if (!vmx->guest_msrs) {
6497 goto uninit_vcpu;
6498 }
6499
6500 vmx->loaded_vmcs = &vmx->vmcs01;
6501 vmx->loaded_vmcs->vmcs = alloc_vmcs();
6502 if (!vmx->loaded_vmcs->vmcs)
6503 goto free_msrs;
6504 if (!vmm_exclusive)
6505 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
6506 loaded_vmcs_init(vmx->loaded_vmcs);
6507 if (!vmm_exclusive)
6508 kvm_cpu_vmxoff();
6509
6510 cpu = get_cpu();
6511 vmx_vcpu_load(&vmx->vcpu, cpu);
6512 vmx->vcpu.cpu = cpu;
6513 err = vmx_vcpu_setup(vmx);
6514 vmx_vcpu_put(&vmx->vcpu);
6515 put_cpu();
6516 if (err)
6517 goto free_vmcs;
6518 if (vm_need_virtualize_apic_accesses(kvm))
6519 err = alloc_apic_access_page(kvm);
6520 if (err)
6521 goto free_vmcs;
6522
6523 if (enable_ept) {
6524 if (!kvm->arch.ept_identity_map_addr)
6525 kvm->arch.ept_identity_map_addr =
6526 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
6527 err = -ENOMEM;
6528 if (alloc_identity_pagetable(kvm) != 0)
6529 goto free_vmcs;
6530 if (!init_rmode_identity_map(kvm))
6531 goto free_vmcs;
6532 }
6533
6534 vmx->nested.current_vmptr = -1ull;
6535 vmx->nested.current_vmcs12 = NULL;
6536
6537 return &vmx->vcpu;
6538
6539 free_vmcs:
6540 free_loaded_vmcs(vmx->loaded_vmcs);
6541 free_msrs:
6542 kfree(vmx->guest_msrs);
6543 uninit_vcpu:
6544 kvm_vcpu_uninit(&vmx->vcpu);
6545 free_vcpu:
6546 free_vpid(vmx);
6547 kmem_cache_free(kvm_vcpu_cache, vmx);
6548 return ERR_PTR(err);
6549 }
6550
6551 static void __init vmx_check_processor_compat(void *rtn)
6552 {
6553 struct vmcs_config vmcs_conf;
6554
6555 *(int *)rtn = 0;
6556 if (setup_vmcs_config(&vmcs_conf) < 0)
6557 *(int *)rtn = -EIO;
6558 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6559 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6560 smp_processor_id());
6561 *(int *)rtn = -EIO;
6562 }
6563 }
6564
6565 static int get_ept_level(void)
6566 {
6567 return VMX_EPT_DEFAULT_GAW + 1;
6568 }
6569
6570 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6571 {
6572 u64 ret;
6573
6574 /* For VT-d and EPT combination
6575 * 1. MMIO: always map as UC
6576 * 2. EPT with VT-d:
6577 * a. VT-d without snooping control feature: can't guarantee the
6578 * result, try to trust guest.
6579 * b. VT-d with snooping control feature: snooping control feature of
6580 * VT-d engine can guarantee the cache correctness. Just set it
6581 * to WB to keep consistent with host. So the same as item 3.
6582 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
6583 * consistent with host MTRR
6584 */
6585 if (is_mmio)
6586 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
6587 else if (vcpu->kvm->arch.iommu_domain &&
6588 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
6589 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
6590 VMX_EPT_MT_EPTE_SHIFT;
6591 else
6592 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
6593 | VMX_EPT_IPAT_BIT;
6594
6595 return ret;
6596 }
6597
6598 static int vmx_get_lpage_level(void)
6599 {
6600 if (enable_ept && !cpu_has_vmx_ept_1g_page())
6601 return PT_DIRECTORY_LEVEL;
6602 else
6603 /* For shadow and EPT supported 1GB page */
6604 return PT_PDPE_LEVEL;
6605 }
6606
6607 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6608 {
6609 struct kvm_cpuid_entry2 *best;
6610 struct vcpu_vmx *vmx = to_vmx(vcpu);
6611 u32 exec_control;
6612
6613 vmx->rdtscp_enabled = false;
6614 if (vmx_rdtscp_supported()) {
6615 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6616 if (exec_control & SECONDARY_EXEC_RDTSCP) {
6617 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
6618 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
6619 vmx->rdtscp_enabled = true;
6620 else {
6621 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6622 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6623 exec_control);
6624 }
6625 }
6626 }
6627
6628 /* Exposing INVPCID only when PCID is exposed */
6629 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
6630 if (vmx_invpcid_supported() &&
6631 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
6632 guest_cpuid_has_pcid(vcpu)) {
6633 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6634 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
6635 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6636 exec_control);
6637 } else {
6638 if (cpu_has_secondary_exec_ctrls()) {
6639 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6640 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
6641 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6642 exec_control);
6643 }
6644 if (best)
6645 best->ebx &= ~bit(X86_FEATURE_INVPCID);
6646 }
6647 }
6648
6649 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
6650 {
6651 if (func == 1 && nested)
6652 entry->ecx |= bit(X86_FEATURE_VMX);
6653 }
6654
6655 /*
6656 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6657 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6658 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6659 * guest in a way that will both be appropriate to L1's requests, and our
6660 * needs. In addition to modifying the active vmcs (which is vmcs02), this
6661 * function also has additional necessary side-effects, like setting various
6662 * vcpu->arch fields.
6663 */
6664 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6665 {
6666 struct vcpu_vmx *vmx = to_vmx(vcpu);
6667 u32 exec_control;
6668
6669 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
6670 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
6671 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
6672 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
6673 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
6674 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
6675 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
6676 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
6677 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
6678 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
6679 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
6680 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
6681 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
6682 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
6683 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
6684 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
6685 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
6686 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
6687 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
6688 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
6689 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
6690 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
6691 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
6692 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
6693 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
6694 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
6695 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
6696 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
6697 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
6698 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
6699 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
6700 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
6701 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
6702 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
6703 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
6704 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
6705
6706 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
6707 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6708 vmcs12->vm_entry_intr_info_field);
6709 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6710 vmcs12->vm_entry_exception_error_code);
6711 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6712 vmcs12->vm_entry_instruction_len);
6713 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
6714 vmcs12->guest_interruptibility_info);
6715 vmcs_write32(GUEST_ACTIVITY_STATE, vmcs12->guest_activity_state);
6716 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
6717 vmcs_writel(GUEST_DR7, vmcs12->guest_dr7);
6718 vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
6719 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
6720 vmcs12->guest_pending_dbg_exceptions);
6721 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
6722 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
6723
6724 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6725
6726 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
6727 (vmcs_config.pin_based_exec_ctrl |
6728 vmcs12->pin_based_vm_exec_control));
6729
6730 /*
6731 * Whether page-faults are trapped is determined by a combination of
6732 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
6733 * If enable_ept, L0 doesn't care about page faults and we should
6734 * set all of these to L1's desires. However, if !enable_ept, L0 does
6735 * care about (at least some) page faults, and because it is not easy
6736 * (if at all possible?) to merge L0 and L1's desires, we simply ask
6737 * to exit on each and every L2 page fault. This is done by setting
6738 * MASK=MATCH=0 and (see below) EB.PF=1.
6739 * Note that below we don't need special code to set EB.PF beyond the
6740 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
6741 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
6742 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
6743 *
6744 * A problem with this approach (when !enable_ept) is that L1 may be
6745 * injected with more page faults than it asked for. This could have
6746 * caused problems, but in practice existing hypervisors don't care.
6747 * To fix this, we will need to emulate the PFEC checking (on the L1
6748 * page tables), using walk_addr(), when injecting PFs to L1.
6749 */
6750 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
6751 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
6752 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
6753 enable_ept ? vmcs12->page_fault_error_code_match : 0);
6754
6755 if (cpu_has_secondary_exec_ctrls()) {
6756 u32 exec_control = vmx_secondary_exec_control(vmx);
6757 if (!vmx->rdtscp_enabled)
6758 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6759 /* Take the following fields only from vmcs12 */
6760 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6761 if (nested_cpu_has(vmcs12,
6762 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
6763 exec_control |= vmcs12->secondary_vm_exec_control;
6764
6765 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
6766 /*
6767 * Translate L1 physical address to host physical
6768 * address for vmcs02. Keep the page pinned, so this
6769 * physical address remains valid. We keep a reference
6770 * to it so we can release it later.
6771 */
6772 if (vmx->nested.apic_access_page) /* shouldn't happen */
6773 nested_release_page(vmx->nested.apic_access_page);
6774 vmx->nested.apic_access_page =
6775 nested_get_page(vcpu, vmcs12->apic_access_addr);
6776 /*
6777 * If translation failed, no matter: This feature asks
6778 * to exit when accessing the given address, and if it
6779 * can never be accessed, this feature won't do
6780 * anything anyway.
6781 */
6782 if (!vmx->nested.apic_access_page)
6783 exec_control &=
6784 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6785 else
6786 vmcs_write64(APIC_ACCESS_ADDR,
6787 page_to_phys(vmx->nested.apic_access_page));
6788 }
6789
6790 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6791 }
6792
6793
6794 /*
6795 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
6796 * Some constant fields are set here by vmx_set_constant_host_state().
6797 * Other fields are different per CPU, and will be set later when
6798 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
6799 */
6800 vmx_set_constant_host_state();
6801
6802 /*
6803 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
6804 * entry, but only if the current (host) sp changed from the value
6805 * we wrote last (vmx->host_rsp). This cache is no longer relevant
6806 * if we switch vmcs, and rather than hold a separate cache per vmcs,
6807 * here we just force the write to happen on entry.
6808 */
6809 vmx->host_rsp = 0;
6810
6811 exec_control = vmx_exec_control(vmx); /* L0's desires */
6812 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
6813 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6814 exec_control &= ~CPU_BASED_TPR_SHADOW;
6815 exec_control |= vmcs12->cpu_based_vm_exec_control;
6816 /*
6817 * Merging of IO and MSR bitmaps not currently supported.
6818 * Rather, exit every time.
6819 */
6820 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
6821 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
6822 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
6823
6824 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6825
6826 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
6827 * bitwise-or of what L1 wants to trap for L2, and what we want to
6828 * trap. Note that CR0.TS also needs updating - we do this later.
6829 */
6830 update_exception_bitmap(vcpu);
6831 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
6832 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6833
6834 /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
6835 vmcs_write32(VM_EXIT_CONTROLS,
6836 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
6837 vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
6838 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
6839
6840 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
6841 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
6842 else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
6843 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
6844
6845
6846 set_cr4_guest_host_mask(vmx);
6847
6848 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
6849 vmcs_write64(TSC_OFFSET,
6850 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
6851 else
6852 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
6853
6854 if (enable_vpid) {
6855 /*
6856 * Trivially support vpid by letting L2s share their parent
6857 * L1's vpid. TODO: move to a more elaborate solution, giving
6858 * each L2 its own vpid and exposing the vpid feature to L1.
6859 */
6860 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
6861 vmx_flush_tlb(vcpu);
6862 }
6863
6864 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
6865 vcpu->arch.efer = vmcs12->guest_ia32_efer;
6866 if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
6867 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6868 else
6869 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6870 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
6871 vmx_set_efer(vcpu, vcpu->arch.efer);
6872
6873 /*
6874 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
6875 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
6876 * The CR0_READ_SHADOW is what L2 should have expected to read given
6877 * the specifications by L1; It's not enough to take
6878 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
6879 * have more bits than L1 expected.
6880 */
6881 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
6882 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
6883
6884 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
6885 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
6886
6887 /* shadow page tables on either EPT or shadow page tables */
6888 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
6889 kvm_mmu_reset_context(vcpu);
6890
6891 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
6892 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
6893 }
6894
6895 /*
6896 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
6897 * for running an L2 nested guest.
6898 */
6899 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
6900 {
6901 struct vmcs12 *vmcs12;
6902 struct vcpu_vmx *vmx = to_vmx(vcpu);
6903 int cpu;
6904 struct loaded_vmcs *vmcs02;
6905
6906 if (!nested_vmx_check_permission(vcpu) ||
6907 !nested_vmx_check_vmcs12(vcpu))
6908 return 1;
6909
6910 skip_emulated_instruction(vcpu);
6911 vmcs12 = get_vmcs12(vcpu);
6912
6913 /*
6914 * The nested entry process starts with enforcing various prerequisites
6915 * on vmcs12 as required by the Intel SDM, and act appropriately when
6916 * they fail: As the SDM explains, some conditions should cause the
6917 * instruction to fail, while others will cause the instruction to seem
6918 * to succeed, but return an EXIT_REASON_INVALID_STATE.
6919 * To speed up the normal (success) code path, we should avoid checking
6920 * for misconfigurations which will anyway be caught by the processor
6921 * when using the merged vmcs02.
6922 */
6923 if (vmcs12->launch_state == launch) {
6924 nested_vmx_failValid(vcpu,
6925 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
6926 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
6927 return 1;
6928 }
6929
6930 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
6931 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
6932 /*TODO: Also verify bits beyond physical address width are 0*/
6933 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6934 return 1;
6935 }
6936
6937 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
6938 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
6939 /*TODO: Also verify bits beyond physical address width are 0*/
6940 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6941 return 1;
6942 }
6943
6944 if (vmcs12->vm_entry_msr_load_count > 0 ||
6945 vmcs12->vm_exit_msr_load_count > 0 ||
6946 vmcs12->vm_exit_msr_store_count > 0) {
6947 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
6948 __func__);
6949 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6950 return 1;
6951 }
6952
6953 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
6954 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
6955 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
6956 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
6957 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
6958 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
6959 !vmx_control_verify(vmcs12->vm_exit_controls,
6960 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
6961 !vmx_control_verify(vmcs12->vm_entry_controls,
6962 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
6963 {
6964 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6965 return 1;
6966 }
6967
6968 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6969 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6970 nested_vmx_failValid(vcpu,
6971 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
6972 return 1;
6973 }
6974
6975 if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6976 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6977 nested_vmx_entry_failure(vcpu, vmcs12,
6978 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
6979 return 1;
6980 }
6981 if (vmcs12->vmcs_link_pointer != -1ull) {
6982 nested_vmx_entry_failure(vcpu, vmcs12,
6983 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
6984 return 1;
6985 }
6986
6987 /*
6988 * We're finally done with prerequisite checking, and can start with
6989 * the nested entry.
6990 */
6991
6992 vmcs02 = nested_get_current_vmcs02(vmx);
6993 if (!vmcs02)
6994 return -ENOMEM;
6995
6996 enter_guest_mode(vcpu);
6997
6998 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
6999
7000 cpu = get_cpu();
7001 vmx->loaded_vmcs = vmcs02;
7002 vmx_vcpu_put(vcpu);
7003 vmx_vcpu_load(vcpu, cpu);
7004 vcpu->cpu = cpu;
7005 put_cpu();
7006
7007 vmcs12->launch_state = 1;
7008
7009 prepare_vmcs02(vcpu, vmcs12);
7010
7011 /*
7012 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
7013 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
7014 * returned as far as L1 is concerned. It will only return (and set
7015 * the success flag) when L2 exits (see nested_vmx_vmexit()).
7016 */
7017 return 1;
7018 }
7019
7020 /*
7021 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
7022 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
7023 * This function returns the new value we should put in vmcs12.guest_cr0.
7024 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
7025 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
7026 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
7027 * didn't trap the bit, because if L1 did, so would L0).
7028 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
7029 * been modified by L2, and L1 knows it. So just leave the old value of
7030 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
7031 * isn't relevant, because if L0 traps this bit it can set it to anything.
7032 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
7033 * changed these bits, and therefore they need to be updated, but L0
7034 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
7035 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
7036 */
7037 static inline unsigned long
7038 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7039 {
7040 return
7041 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
7042 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
7043 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
7044 vcpu->arch.cr0_guest_owned_bits));
7045 }
7046
7047 static inline unsigned long
7048 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7049 {
7050 return
7051 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
7052 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
7053 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
7054 vcpu->arch.cr4_guest_owned_bits));
7055 }
7056
7057 /*
7058 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
7059 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
7060 * and this function updates it to reflect the changes to the guest state while
7061 * L2 was running (and perhaps made some exits which were handled directly by L0
7062 * without going back to L1), and to reflect the exit reason.
7063 * Note that we do not have to copy here all VMCS fields, just those that
7064 * could have changed by the L2 guest or the exit - i.e., the guest-state and
7065 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
7066 * which already writes to vmcs12 directly.
7067 */
7068 void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7069 {
7070 /* update guest state fields: */
7071 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
7072 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
7073
7074 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
7075 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7076 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
7077 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
7078
7079 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
7080 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
7081 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
7082 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
7083 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
7084 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
7085 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
7086 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
7087 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
7088 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
7089 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
7090 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
7091 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
7092 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
7093 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
7094 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
7095 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
7096 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
7097 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
7098 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
7099 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
7100 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
7101 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
7102 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
7103 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
7104 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
7105 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
7106 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
7107 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
7108 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
7109 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
7110 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
7111 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
7112 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
7113 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
7114 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
7115
7116 vmcs12->guest_activity_state = vmcs_read32(GUEST_ACTIVITY_STATE);
7117 vmcs12->guest_interruptibility_info =
7118 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
7119 vmcs12->guest_pending_dbg_exceptions =
7120 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
7121
7122 /* TODO: These cannot have changed unless we have MSR bitmaps and
7123 * the relevant bit asks not to trap the change */
7124 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
7125 if (vmcs12->vm_entry_controls & VM_EXIT_SAVE_IA32_PAT)
7126 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
7127 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
7128 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
7129 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
7130
7131 /* update exit information fields: */
7132
7133 vmcs12->vm_exit_reason = vmcs_read32(VM_EXIT_REASON);
7134 vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7135
7136 vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7137 vmcs12->vm_exit_intr_error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
7138 vmcs12->idt_vectoring_info_field =
7139 vmcs_read32(IDT_VECTORING_INFO_FIELD);
7140 vmcs12->idt_vectoring_error_code =
7141 vmcs_read32(IDT_VECTORING_ERROR_CODE);
7142 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
7143 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7144
7145 /* clear vm-entry fields which are to be cleared on exit */
7146 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
7147 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
7148 }
7149
7150 /*
7151 * A part of what we need to when the nested L2 guest exits and we want to
7152 * run its L1 parent, is to reset L1's guest state to the host state specified
7153 * in vmcs12.
7154 * This function is to be called not only on normal nested exit, but also on
7155 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
7156 * Failures During or After Loading Guest State").
7157 * This function should be called when the active VMCS is L1's (vmcs01).
7158 */
7159 void load_vmcs12_host_state(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7160 {
7161 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
7162 vcpu->arch.efer = vmcs12->host_ia32_efer;
7163 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
7164 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7165 else
7166 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7167 vmx_set_efer(vcpu, vcpu->arch.efer);
7168
7169 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
7170 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
7171 /*
7172 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
7173 * actually changed, because it depends on the current state of
7174 * fpu_active (which may have changed).
7175 * Note that vmx_set_cr0 refers to efer set above.
7176 */
7177 kvm_set_cr0(vcpu, vmcs12->host_cr0);
7178 /*
7179 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
7180 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
7181 * but we also need to update cr0_guest_host_mask and exception_bitmap.
7182 */
7183 update_exception_bitmap(vcpu);
7184 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
7185 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7186
7187 /*
7188 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
7189 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
7190 */
7191 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
7192 kvm_set_cr4(vcpu, vmcs12->host_cr4);
7193
7194 /* shadow page tables on either EPT or shadow page tables */
7195 kvm_set_cr3(vcpu, vmcs12->host_cr3);
7196 kvm_mmu_reset_context(vcpu);
7197
7198 if (enable_vpid) {
7199 /*
7200 * Trivially support vpid by letting L2s share their parent
7201 * L1's vpid. TODO: move to a more elaborate solution, giving
7202 * each L2 its own vpid and exposing the vpid feature to L1.
7203 */
7204 vmx_flush_tlb(vcpu);
7205 }
7206
7207
7208 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
7209 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
7210 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
7211 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
7212 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
7213 vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
7214 vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
7215 vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
7216 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
7217 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
7218 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
7219 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
7220 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
7221 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
7222 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
7223
7224 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
7225 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
7226 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7227 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
7228 vmcs12->host_ia32_perf_global_ctrl);
7229 }
7230
7231 /*
7232 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
7233 * and modify vmcs12 to make it see what it would expect to see there if
7234 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
7235 */
7236 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
7237 {
7238 struct vcpu_vmx *vmx = to_vmx(vcpu);
7239 int cpu;
7240 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7241
7242 leave_guest_mode(vcpu);
7243 prepare_vmcs12(vcpu, vmcs12);
7244
7245 cpu = get_cpu();
7246 vmx->loaded_vmcs = &vmx->vmcs01;
7247 vmx_vcpu_put(vcpu);
7248 vmx_vcpu_load(vcpu, cpu);
7249 vcpu->cpu = cpu;
7250 put_cpu();
7251
7252 /* if no vmcs02 cache requested, remove the one we used */
7253 if (VMCS02_POOL_SIZE == 0)
7254 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
7255
7256 load_vmcs12_host_state(vcpu, vmcs12);
7257
7258 /* Update TSC_OFFSET if TSC was changed while L2 ran */
7259 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7260
7261 /* This is needed for same reason as it was needed in prepare_vmcs02 */
7262 vmx->host_rsp = 0;
7263
7264 /* Unpin physical memory we referred to in vmcs02 */
7265 if (vmx->nested.apic_access_page) {
7266 nested_release_page(vmx->nested.apic_access_page);
7267 vmx->nested.apic_access_page = 0;
7268 }
7269
7270 /*
7271 * Exiting from L2 to L1, we're now back to L1 which thinks it just
7272 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
7273 * success or failure flag accordingly.
7274 */
7275 if (unlikely(vmx->fail)) {
7276 vmx->fail = 0;
7277 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
7278 } else
7279 nested_vmx_succeed(vcpu);
7280 }
7281
7282 /*
7283 * L1's failure to enter L2 is a subset of a normal exit, as explained in
7284 * 23.7 "VM-entry failures during or after loading guest state" (this also
7285 * lists the acceptable exit-reason and exit-qualification parameters).
7286 * It should only be called before L2 actually succeeded to run, and when
7287 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
7288 */
7289 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
7290 struct vmcs12 *vmcs12,
7291 u32 reason, unsigned long qualification)
7292 {
7293 load_vmcs12_host_state(vcpu, vmcs12);
7294 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
7295 vmcs12->exit_qualification = qualification;
7296 nested_vmx_succeed(vcpu);
7297 }
7298
7299 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7300 struct x86_instruction_info *info,
7301 enum x86_intercept_stage stage)
7302 {
7303 return X86EMUL_CONTINUE;
7304 }
7305
7306 static struct kvm_x86_ops vmx_x86_ops = {
7307 .cpu_has_kvm_support = cpu_has_kvm_support,
7308 .disabled_by_bios = vmx_disabled_by_bios,
7309 .hardware_setup = hardware_setup,
7310 .hardware_unsetup = hardware_unsetup,
7311 .check_processor_compatibility = vmx_check_processor_compat,
7312 .hardware_enable = hardware_enable,
7313 .hardware_disable = hardware_disable,
7314 .cpu_has_accelerated_tpr = report_flexpriority,
7315
7316 .vcpu_create = vmx_create_vcpu,
7317 .vcpu_free = vmx_free_vcpu,
7318 .vcpu_reset = vmx_vcpu_reset,
7319
7320 .prepare_guest_switch = vmx_save_host_state,
7321 .vcpu_load = vmx_vcpu_load,
7322 .vcpu_put = vmx_vcpu_put,
7323
7324 .update_db_bp_intercept = update_exception_bitmap,
7325 .get_msr = vmx_get_msr,
7326 .set_msr = vmx_set_msr,
7327 .get_segment_base = vmx_get_segment_base,
7328 .get_segment = vmx_get_segment,
7329 .set_segment = vmx_set_segment,
7330 .get_cpl = vmx_get_cpl,
7331 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
7332 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
7333 .decache_cr3 = vmx_decache_cr3,
7334 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
7335 .set_cr0 = vmx_set_cr0,
7336 .set_cr3 = vmx_set_cr3,
7337 .set_cr4 = vmx_set_cr4,
7338 .set_efer = vmx_set_efer,
7339 .get_idt = vmx_get_idt,
7340 .set_idt = vmx_set_idt,
7341 .get_gdt = vmx_get_gdt,
7342 .set_gdt = vmx_set_gdt,
7343 .set_dr7 = vmx_set_dr7,
7344 .cache_reg = vmx_cache_reg,
7345 .get_rflags = vmx_get_rflags,
7346 .set_rflags = vmx_set_rflags,
7347 .fpu_activate = vmx_fpu_activate,
7348 .fpu_deactivate = vmx_fpu_deactivate,
7349
7350 .tlb_flush = vmx_flush_tlb,
7351
7352 .run = vmx_vcpu_run,
7353 .handle_exit = vmx_handle_exit,
7354 .skip_emulated_instruction = skip_emulated_instruction,
7355 .set_interrupt_shadow = vmx_set_interrupt_shadow,
7356 .get_interrupt_shadow = vmx_get_interrupt_shadow,
7357 .patch_hypercall = vmx_patch_hypercall,
7358 .set_irq = vmx_inject_irq,
7359 .set_nmi = vmx_inject_nmi,
7360 .queue_exception = vmx_queue_exception,
7361 .cancel_injection = vmx_cancel_injection,
7362 .interrupt_allowed = vmx_interrupt_allowed,
7363 .nmi_allowed = vmx_nmi_allowed,
7364 .get_nmi_mask = vmx_get_nmi_mask,
7365 .set_nmi_mask = vmx_set_nmi_mask,
7366 .enable_nmi_window = enable_nmi_window,
7367 .enable_irq_window = enable_irq_window,
7368 .update_cr8_intercept = update_cr8_intercept,
7369
7370 .set_tss_addr = vmx_set_tss_addr,
7371 .get_tdp_level = get_ept_level,
7372 .get_mt_mask = vmx_get_mt_mask,
7373
7374 .get_exit_info = vmx_get_exit_info,
7375
7376 .get_lpage_level = vmx_get_lpage_level,
7377
7378 .cpuid_update = vmx_cpuid_update,
7379
7380 .rdtscp_supported = vmx_rdtscp_supported,
7381 .invpcid_supported = vmx_invpcid_supported,
7382
7383 .set_supported_cpuid = vmx_set_supported_cpuid,
7384
7385 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
7386
7387 .set_tsc_khz = vmx_set_tsc_khz,
7388 .read_tsc_offset = vmx_read_tsc_offset,
7389 .write_tsc_offset = vmx_write_tsc_offset,
7390 .adjust_tsc_offset = vmx_adjust_tsc_offset,
7391 .compute_tsc_offset = vmx_compute_tsc_offset,
7392 .read_l1_tsc = vmx_read_l1_tsc,
7393
7394 .set_tdp_cr3 = vmx_set_cr3,
7395
7396 .check_intercept = vmx_check_intercept,
7397 };
7398
7399 static int __init vmx_init(void)
7400 {
7401 int r, i;
7402
7403 rdmsrl_safe(MSR_EFER, &host_efer);
7404
7405 for (i = 0; i < NR_VMX_MSR; ++i)
7406 kvm_define_shared_msr(i, vmx_msr_index[i]);
7407
7408 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
7409 if (!vmx_io_bitmap_a)
7410 return -ENOMEM;
7411
7412 r = -ENOMEM;
7413
7414 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
7415 if (!vmx_io_bitmap_b)
7416 goto out;
7417
7418 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
7419 if (!vmx_msr_bitmap_legacy)
7420 goto out1;
7421
7422
7423 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
7424 if (!vmx_msr_bitmap_longmode)
7425 goto out2;
7426
7427
7428 /*
7429 * Allow direct access to the PC debug port (it is often used for I/O
7430 * delays, but the vmexits simply slow things down).
7431 */
7432 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
7433 clear_bit(0x80, vmx_io_bitmap_a);
7434
7435 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
7436
7437 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
7438 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
7439
7440 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7441
7442 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7443 __alignof__(struct vcpu_vmx), THIS_MODULE);
7444 if (r)
7445 goto out3;
7446
7447 #ifdef CONFIG_KEXEC
7448 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
7449 crash_vmclear_local_loaded_vmcss);
7450 #endif
7451
7452 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
7453 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
7454 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
7455 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
7456 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
7457 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
7458
7459 if (enable_ept) {
7460 kvm_mmu_set_mask_ptes(0ull,
7461 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
7462 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
7463 0ull, VMX_EPT_EXECUTABLE_MASK);
7464 ept_set_mmio_spte_mask();
7465 kvm_enable_tdp();
7466 } else
7467 kvm_disable_tdp();
7468
7469 return 0;
7470
7471 out3:
7472 free_page((unsigned long)vmx_msr_bitmap_longmode);
7473 out2:
7474 free_page((unsigned long)vmx_msr_bitmap_legacy);
7475 out1:
7476 free_page((unsigned long)vmx_io_bitmap_b);
7477 out:
7478 free_page((unsigned long)vmx_io_bitmap_a);
7479 return r;
7480 }
7481
7482 static void __exit vmx_exit(void)
7483 {
7484 free_page((unsigned long)vmx_msr_bitmap_legacy);
7485 free_page((unsigned long)vmx_msr_bitmap_longmode);
7486 free_page((unsigned long)vmx_io_bitmap_b);
7487 free_page((unsigned long)vmx_io_bitmap_a);
7488
7489 #ifdef CONFIG_KEXEC
7490 rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
7491 synchronize_rcu();
7492 #endif
7493
7494 kvm_exit();
7495 }
7496
7497 module_init(vmx_init)
7498 module_exit(vmx_exit)
CRIS linux kernel tree