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Linux 3.8-rc7
[cris-mirror.git] / arch / x86 / pci / mmconfig-shared.c
blobfb29968a7cd54c164286a09f9f8721144180f3d0
1 /*
2 * mmconfig-shared.c - Low-level direct PCI config space access via
3 * MMCONFIG - common code between i386 and x86-64.
4 *
5 * This code does:
6 * - known chipset handling
7 * - ACPI decoding and validation
8 *
9 * Per-architecture code takes care of the mappings and accesses
10 * themselves.
11 */
12
13 #include <linux/pci.h>
14 #include <linux/init.h>
15 #include <linux/acpi.h>
16 #include <linux/sfi_acpi.h>
17 #include <linux/bitmap.h>
18 #include <linux/dmi.h>
19 #include <linux/slab.h>
20 #include <linux/mutex.h>
21 #include <linux/rculist.h>
22 #include <asm/e820.h>
23 #include <asm/pci_x86.h>
24 #include <asm/acpi.h>
25
26 #define PREFIX "PCI: "
27
28 /* Indicate if the mmcfg resources have been placed into the resource table. */
29 static bool pci_mmcfg_running_state;
30 static bool pci_mmcfg_arch_init_failed;
31 static DEFINE_MUTEX(pci_mmcfg_lock);
32
33 LIST_HEAD(pci_mmcfg_list);
34
35 static __init void pci_mmconfig_remove(struct pci_mmcfg_region *cfg)
36 {
37 if (cfg->res.parent)
38 release_resource(&cfg->res);
39 list_del(&cfg->list);
40 kfree(cfg);
41 }
42
43 static __init void free_all_mmcfg(void)
44 {
45 struct pci_mmcfg_region *cfg, *tmp;
46
47 pci_mmcfg_arch_free();
48 list_for_each_entry_safe(cfg, tmp, &pci_mmcfg_list, list)
49 pci_mmconfig_remove(cfg);
50 }
51
52 static void list_add_sorted(struct pci_mmcfg_region *new)
53 {
54 struct pci_mmcfg_region *cfg;
55
56 /* keep list sorted by segment and starting bus number */
57 list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list) {
58 if (cfg->segment > new->segment ||
59 (cfg->segment == new->segment &&
60 cfg->start_bus >= new->start_bus)) {
61 list_add_tail_rcu(&new->list, &cfg->list);
62 return;
63 }
64 }
65 list_add_tail_rcu(&new->list, &pci_mmcfg_list);
66 }
67
68 static struct pci_mmcfg_region *pci_mmconfig_alloc(int segment, int start,
69 int end, u64 addr)
70 {
71 struct pci_mmcfg_region *new;
72 struct resource *res;
73
74 if (addr == 0)
75 return NULL;
76
77 new = kzalloc(sizeof(*new), GFP_KERNEL);
78 if (!new)
79 return NULL;
80
81 new->address = addr;
82 new->segment = segment;
83 new->start_bus = start;
84 new->end_bus = end;
85
86 res = &new->res;
87 res->start = addr + PCI_MMCFG_BUS_OFFSET(start);
88 res->end = addr + PCI_MMCFG_BUS_OFFSET(end + 1) - 1;
89 res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
90 snprintf(new->name, PCI_MMCFG_RESOURCE_NAME_LEN,
91 "PCI MMCONFIG %04x [bus %02x-%02x]", segment, start, end);
92 res->name = new->name;
93
94 return new;
95 }
96
97 static __init struct pci_mmcfg_region *pci_mmconfig_add(int segment, int start,
98 int end, u64 addr)
99 {
100 struct pci_mmcfg_region *new;
101
102 new = pci_mmconfig_alloc(segment, start, end, addr);
103 if (new) {
104 mutex_lock(&pci_mmcfg_lock);
105 list_add_sorted(new);
106 mutex_unlock(&pci_mmcfg_lock);
107
108 pr_info(PREFIX
109 "MMCONFIG for domain %04x [bus %02x-%02x] at %pR "
110 "(base %#lx)\n",
111 segment, start, end, &new->res, (unsigned long)addr);
112 }
113
114 return new;
115 }
116
117 struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus)
118 {
119 struct pci_mmcfg_region *cfg;
120
121 list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list)
122 if (cfg->segment == segment &&
123 cfg->start_bus <= bus && bus <= cfg->end_bus)
124 return cfg;
125
126 return NULL;
127 }
128
129 static const char __init *pci_mmcfg_e7520(void)
130 {
131 u32 win;
132 raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0xce, 2, &win);
133
134 win = win & 0xf000;
135 if (win == 0x0000 || win == 0xf000)
136 return NULL;
137
138 if (pci_mmconfig_add(0, 0, 255, win << 16) == NULL)
139 return NULL;
140
141 return "Intel Corporation E7520 Memory Controller Hub";
142 }
143
144 static const char __init *pci_mmcfg_intel_945(void)
145 {
146 u32 pciexbar, mask = 0, len = 0;
147
148 raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0x48, 4, &pciexbar);
149
150 /* Enable bit */
151 if (!(pciexbar & 1))
152 return NULL;
153
154 /* Size bits */
155 switch ((pciexbar >> 1) & 3) {
156 case 0:
157 mask = 0xf0000000U;
158 len = 0x10000000U;
159 break;
160 case 1:
161 mask = 0xf8000000U;
162 len = 0x08000000U;
163 break;
164 case 2:
165 mask = 0xfc000000U;
166 len = 0x04000000U;
167 break;
168 default:
169 return NULL;
170 }
171
172 /* Errata #2, things break when not aligned on a 256Mb boundary */
173 /* Can only happen in 64M/128M mode */
174
175 if ((pciexbar & mask) & 0x0fffffffU)
176 return NULL;
177
178 /* Don't hit the APIC registers and their friends */
179 if ((pciexbar & mask) >= 0xf0000000U)
180 return NULL;
181
182 if (pci_mmconfig_add(0, 0, (len >> 20) - 1, pciexbar & mask) == NULL)
183 return NULL;
184
185 return "Intel Corporation 945G/GZ/P/PL Express Memory Controller Hub";
186 }
187
188 static const char __init *pci_mmcfg_amd_fam10h(void)
189 {
190 u32 low, high, address;
191 u64 base, msr;
192 int i;
193 unsigned segnbits = 0, busnbits, end_bus;
194
195 if (!(pci_probe & PCI_CHECK_ENABLE_AMD_MMCONF))
196 return NULL;
197
198 address = MSR_FAM10H_MMIO_CONF_BASE;
199 if (rdmsr_safe(address, &low, &high))
200 return NULL;
201
202 msr = high;
203 msr <<= 32;
204 msr |= low;
205
206 /* mmconfig is not enable */
207 if (!(msr & FAM10H_MMIO_CONF_ENABLE))
208 return NULL;
209
210 base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
211
212 busnbits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
213 FAM10H_MMIO_CONF_BUSRANGE_MASK;
214
215 /*
216 * only handle bus 0 ?
217 * need to skip it
218 */
219 if (!busnbits)
220 return NULL;
221
222 if (busnbits > 8) {
223 segnbits = busnbits - 8;
224 busnbits = 8;
225 }
226
227 end_bus = (1 << busnbits) - 1;
228 for (i = 0; i < (1 << segnbits); i++)
229 if (pci_mmconfig_add(i, 0, end_bus,
230 base + (1<<28) * i) == NULL) {
231 free_all_mmcfg();
232 return NULL;
233 }
234
235 return "AMD Family 10h NB";
236 }
237
238 static bool __initdata mcp55_checked;
239 static const char __init *pci_mmcfg_nvidia_mcp55(void)
240 {
241 int bus;
242 int mcp55_mmconf_found = 0;
243
244 static const u32 extcfg_regnum = 0x90;
245 static const u32 extcfg_regsize = 4;
246 static const u32 extcfg_enable_mask = 1<<31;
247 static const u32 extcfg_start_mask = 0xff<<16;
248 static const int extcfg_start_shift = 16;
249 static const u32 extcfg_size_mask = 0x3<<28;
250 static const int extcfg_size_shift = 28;
251 static const int extcfg_sizebus[] = {0x100, 0x80, 0x40, 0x20};
252 static const u32 extcfg_base_mask[] = {0x7ff8, 0x7ffc, 0x7ffe, 0x7fff};
253 static const int extcfg_base_lshift = 25;
254
255 /*
256 * do check if amd fam10h already took over
257 */
258 if (!acpi_disabled || !list_empty(&pci_mmcfg_list) || mcp55_checked)
259 return NULL;
260
261 mcp55_checked = true;
262 for (bus = 0; bus < 256; bus++) {
263 u64 base;
264 u32 l, extcfg;
265 u16 vendor, device;
266 int start, size_index, end;
267
268 raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), 0, 4, &l);
269 vendor = l & 0xffff;
270 device = (l >> 16) & 0xffff;
271
272 if (PCI_VENDOR_ID_NVIDIA != vendor || 0x0369 != device)
273 continue;
274
275 raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), extcfg_regnum,
276 extcfg_regsize, &extcfg);
277
278 if (!(extcfg & extcfg_enable_mask))
279 continue;
280
281 size_index = (extcfg & extcfg_size_mask) >> extcfg_size_shift;
282 base = extcfg & extcfg_base_mask[size_index];
283 /* base could > 4G */
284 base <<= extcfg_base_lshift;
285 start = (extcfg & extcfg_start_mask) >> extcfg_start_shift;
286 end = start + extcfg_sizebus[size_index] - 1;
287 if (pci_mmconfig_add(0, start, end, base) == NULL)
288 continue;
289 mcp55_mmconf_found++;
290 }
291
292 if (!mcp55_mmconf_found)
293 return NULL;
294
295 return "nVidia MCP55";
296 }
297
298 struct pci_mmcfg_hostbridge_probe {
299 u32 bus;
300 u32 devfn;
301 u32 vendor;
302 u32 device;
303 const char *(*probe)(void);
304 };
305
306 static struct pci_mmcfg_hostbridge_probe pci_mmcfg_probes[] __initdata = {
307 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
308 PCI_DEVICE_ID_INTEL_E7520_MCH, pci_mmcfg_e7520 },
309 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
310 PCI_DEVICE_ID_INTEL_82945G_HB, pci_mmcfg_intel_945 },
311 { 0, PCI_DEVFN(0x18, 0), PCI_VENDOR_ID_AMD,
312 0x1200, pci_mmcfg_amd_fam10h },
313 { 0xff, PCI_DEVFN(0, 0), PCI_VENDOR_ID_AMD,
314 0x1200, pci_mmcfg_amd_fam10h },
315 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_NVIDIA,
316 0x0369, pci_mmcfg_nvidia_mcp55 },
317 };
318
319 static void __init pci_mmcfg_check_end_bus_number(void)
320 {
321 struct pci_mmcfg_region *cfg, *cfgx;
322
323 /* Fixup overlaps */
324 list_for_each_entry(cfg, &pci_mmcfg_list, list) {
325 if (cfg->end_bus < cfg->start_bus)
326 cfg->end_bus = 255;
327
328 /* Don't access the list head ! */
329 if (cfg->list.next == &pci_mmcfg_list)
330 break;
331
332 cfgx = list_entry(cfg->list.next, typeof(*cfg), list);
333 if (cfg->end_bus >= cfgx->start_bus)
334 cfg->end_bus = cfgx->start_bus - 1;
335 }
336 }
337
338 static int __init pci_mmcfg_check_hostbridge(void)
339 {
340 u32 l;
341 u32 bus, devfn;
342 u16 vendor, device;
343 int i;
344 const char *name;
345
346 if (!raw_pci_ops)
347 return 0;
348
349 free_all_mmcfg();
350
351 for (i = 0; i < ARRAY_SIZE(pci_mmcfg_probes); i++) {
352 bus = pci_mmcfg_probes[i].bus;
353 devfn = pci_mmcfg_probes[i].devfn;
354 raw_pci_ops->read(0, bus, devfn, 0, 4, &l);
355 vendor = l & 0xffff;
356 device = (l >> 16) & 0xffff;
357
358 name = NULL;
359 if (pci_mmcfg_probes[i].vendor == vendor &&
360 pci_mmcfg_probes[i].device == device)
361 name = pci_mmcfg_probes[i].probe();
362
363 if (name)
364 pr_info(PREFIX "%s with MMCONFIG support\n", name);
365 }
366
367 /* some end_bus_number is crazy, fix it */
368 pci_mmcfg_check_end_bus_number();
369
370 return !list_empty(&pci_mmcfg_list);
371 }
372
373 static acpi_status check_mcfg_resource(struct acpi_resource *res, void *data)
374 {
375 struct resource *mcfg_res = data;
376 struct acpi_resource_address64 address;
377 acpi_status status;
378
379 if (res->type == ACPI_RESOURCE_TYPE_FIXED_MEMORY32) {
380 struct acpi_resource_fixed_memory32 *fixmem32 =
381 &res->data.fixed_memory32;
382 if (!fixmem32)
383 return AE_OK;
384 if ((mcfg_res->start >= fixmem32->address) &&
385 (mcfg_res->end < (fixmem32->address +
386 fixmem32->address_length))) {
387 mcfg_res->flags = 1;
388 return AE_CTRL_TERMINATE;
389 }
390 }
391 if ((res->type != ACPI_RESOURCE_TYPE_ADDRESS32) &&
392 (res->type != ACPI_RESOURCE_TYPE_ADDRESS64))
393 return AE_OK;
394
395 status = acpi_resource_to_address64(res, &address);
396 if (ACPI_FAILURE(status) ||
397 (address.address_length <= 0) ||
398 (address.resource_type != ACPI_MEMORY_RANGE))
399 return AE_OK;
400
401 if ((mcfg_res->start >= address.minimum) &&
402 (mcfg_res->end < (address.minimum + address.address_length))) {
403 mcfg_res->flags = 1;
404 return AE_CTRL_TERMINATE;
405 }
406 return AE_OK;
407 }
408
409 static acpi_status find_mboard_resource(acpi_handle handle, u32 lvl,
410 void *context, void **rv)
411 {
412 struct resource *mcfg_res = context;
413
414 acpi_walk_resources(handle, METHOD_NAME__CRS,
415 check_mcfg_resource, context);
416
417 if (mcfg_res->flags)
418 return AE_CTRL_TERMINATE;
419
420 return AE_OK;
421 }
422
423 static int is_acpi_reserved(u64 start, u64 end, unsigned not_used)
424 {
425 struct resource mcfg_res;
426
427 mcfg_res.start = start;
428 mcfg_res.end = end - 1;
429 mcfg_res.flags = 0;
430
431 acpi_get_devices("PNP0C01", find_mboard_resource, &mcfg_res, NULL);
432
433 if (!mcfg_res.flags)
434 acpi_get_devices("PNP0C02", find_mboard_resource, &mcfg_res,
435 NULL);
436
437 return mcfg_res.flags;
438 }
439
440 typedef int (*check_reserved_t)(u64 start, u64 end, unsigned type);
441
442 static int __ref is_mmconf_reserved(check_reserved_t is_reserved,
443 struct pci_mmcfg_region *cfg,
444 struct device *dev, int with_e820)
445 {
446 u64 addr = cfg->res.start;
447 u64 size = resource_size(&cfg->res);
448 u64 old_size = size;
449 int num_buses;
450 char *method = with_e820 ? "E820" : "ACPI motherboard resources";
451
452 while (!is_reserved(addr, addr + size, E820_RESERVED)) {
453 size >>= 1;
454 if (size < (16UL<<20))
455 break;
456 }
457
458 if (size < (16UL<<20) && size != old_size)
459 return 0;
460
461 if (dev)
462 dev_info(dev, "MMCONFIG at %pR reserved in %s\n",
463 &cfg->res, method);
464 else
465 pr_info(PREFIX "MMCONFIG at %pR reserved in %s\n",
466 &cfg->res, method);
467
468 if (old_size != size) {
469 /* update end_bus */
470 cfg->end_bus = cfg->start_bus + ((size>>20) - 1);
471 num_buses = cfg->end_bus - cfg->start_bus + 1;
472 cfg->res.end = cfg->res.start +
473 PCI_MMCFG_BUS_OFFSET(num_buses) - 1;
474 snprintf(cfg->name, PCI_MMCFG_RESOURCE_NAME_LEN,
475 "PCI MMCONFIG %04x [bus %02x-%02x]",
476 cfg->segment, cfg->start_bus, cfg->end_bus);
477
478 if (dev)
479 dev_info(dev,
480 "MMCONFIG "
481 "at %pR (base %#lx) (size reduced!)\n",
482 &cfg->res, (unsigned long) cfg->address);
483 else
484 pr_info(PREFIX
485 "MMCONFIG for %04x [bus%02x-%02x] "
486 "at %pR (base %#lx) (size reduced!)\n",
487 cfg->segment, cfg->start_bus, cfg->end_bus,
488 &cfg->res, (unsigned long) cfg->address);
489 }
490
491 return 1;
492 }
493
494 static int __ref pci_mmcfg_check_reserved(struct device *dev,
495 struct pci_mmcfg_region *cfg, int early)
496 {
497 if (!early && !acpi_disabled) {
498 if (is_mmconf_reserved(is_acpi_reserved, cfg, dev, 0))
499 return 1;
500
501 if (dev)
502 dev_info(dev, FW_INFO
503 "MMCONFIG at %pR not reserved in "
504 "ACPI motherboard resources\n",
505 &cfg->res);
506 else
507 pr_info(FW_INFO PREFIX
508 "MMCONFIG at %pR not reserved in "
509 "ACPI motherboard resources\n",
510 &cfg->res);
511 }
512
513 /*
514 * e820_all_mapped() is marked as __init.
515 * All entries from ACPI MCFG table have been checked at boot time.
516 * For MCFG information constructed from hotpluggable host bridge's
517 * _CBA method, just assume it's reserved.
518 */
519 if (pci_mmcfg_running_state)
520 return 1;
521
522 /* Don't try to do this check unless configuration
523 type 1 is available. how about type 2 ?*/
524 if (raw_pci_ops)
525 return is_mmconf_reserved(e820_all_mapped, cfg, dev, 1);
526
527 return 0;
528 }
529
530 static void __init pci_mmcfg_reject_broken(int early)
531 {
532 struct pci_mmcfg_region *cfg;
533
534 list_for_each_entry(cfg, &pci_mmcfg_list, list) {
535 if (pci_mmcfg_check_reserved(NULL, cfg, early) == 0) {
536 pr_info(PREFIX "not using MMCONFIG\n");
537 free_all_mmcfg();
538 return;
539 }
540 }
541 }
542
543 static int __init acpi_mcfg_check_entry(struct acpi_table_mcfg *mcfg,
544 struct acpi_mcfg_allocation *cfg)
545 {
546 int year;
547
548 if (cfg->address < 0xFFFFFFFF)
549 return 0;
550
551 if (!strcmp(mcfg->header.oem_id, "SGI") ||
552 !strcmp(mcfg->header.oem_id, "SGI2"))
553 return 0;
554
555 if (mcfg->header.revision >= 1) {
556 if (dmi_get_date(DMI_BIOS_DATE, &year, NULL, NULL) &&
557 year >= 2010)
558 return 0;
559 }
560
561 pr_err(PREFIX "MCFG region for %04x [bus %02x-%02x] at %#llx "
562 "is above 4GB, ignored\n", cfg->pci_segment,
563 cfg->start_bus_number, cfg->end_bus_number, cfg->address);
564 return -EINVAL;
565 }
566
567 static int __init pci_parse_mcfg(struct acpi_table_header *header)
568 {
569 struct acpi_table_mcfg *mcfg;
570 struct acpi_mcfg_allocation *cfg_table, *cfg;
571 unsigned long i;
572 int entries;
573
574 if (!header)
575 return -EINVAL;
576
577 mcfg = (struct acpi_table_mcfg *)header;
578
579 /* how many config structures do we have */
580 free_all_mmcfg();
581 entries = 0;
582 i = header->length - sizeof(struct acpi_table_mcfg);
583 while (i >= sizeof(struct acpi_mcfg_allocation)) {
584 entries++;
585 i -= sizeof(struct acpi_mcfg_allocation);
586 }
587 if (entries == 0) {
588 pr_err(PREFIX "MMCONFIG has no entries\n");
589 return -ENODEV;
590 }
591
592 cfg_table = (struct acpi_mcfg_allocation *) &mcfg[1];
593 for (i = 0; i < entries; i++) {
594 cfg = &cfg_table[i];
595 if (acpi_mcfg_check_entry(mcfg, cfg)) {
596 free_all_mmcfg();
597 return -ENODEV;
598 }
599
600 if (pci_mmconfig_add(cfg->pci_segment, cfg->start_bus_number,
601 cfg->end_bus_number, cfg->address) == NULL) {
602 pr_warn(PREFIX "no memory for MCFG entries\n");
603 free_all_mmcfg();
604 return -ENOMEM;
605 }
606 }
607
608 return 0;
609 }
610
611 static void __init __pci_mmcfg_init(int early)
612 {
613 pci_mmcfg_reject_broken(early);
614 if (list_empty(&pci_mmcfg_list))
615 return;
616
617 if (pcibios_last_bus < 0) {
618 const struct pci_mmcfg_region *cfg;
619
620 list_for_each_entry(cfg, &pci_mmcfg_list, list) {
621 if (cfg->segment)
622 break;
623 pcibios_last_bus = cfg->end_bus;
624 }
625 }
626
627 if (pci_mmcfg_arch_init())
628 pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF;
629 else {
630 free_all_mmcfg();
631 pci_mmcfg_arch_init_failed = true;
632 }
633 }
634
635 static int __initdata known_bridge;
636
637 void __init pci_mmcfg_early_init(void)
638 {
639 if (pci_probe & PCI_PROBE_MMCONF) {
640 if (pci_mmcfg_check_hostbridge())
641 known_bridge = 1;
642 else
643 acpi_sfi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg);
644 __pci_mmcfg_init(1);
645 }
646 }
647
648 void __init pci_mmcfg_late_init(void)
649 {
650 /* MMCONFIG disabled */
651 if ((pci_probe & PCI_PROBE_MMCONF) == 0)
652 return;
653
654 if (known_bridge)
655 return;
656
657 /* MMCONFIG hasn't been enabled yet, try again */
658 if (pci_probe & PCI_PROBE_MASK & ~PCI_PROBE_MMCONF) {
659 acpi_sfi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg);
660 __pci_mmcfg_init(0);
661 }
662 }
663
664 static int __init pci_mmcfg_late_insert_resources(void)
665 {
666 struct pci_mmcfg_region *cfg;
667
668 pci_mmcfg_running_state = true;
669
670 /* If we are not using MMCONFIG, don't insert the resources. */
671 if ((pci_probe & PCI_PROBE_MMCONF) == 0)
672 return 1;
673
674 /*
675 * Attempt to insert the mmcfg resources but not with the busy flag
676 * marked so it won't cause request errors when __request_region is
677 * called.
678 */
679 list_for_each_entry(cfg, &pci_mmcfg_list, list)
680 if (!cfg->res.parent)
681 insert_resource(&iomem_resource, &cfg->res);
682
683 return 0;
684 }
685
686 /*
687 * Perform MMCONFIG resource insertion after PCI initialization to allow for
688 * misprogrammed MCFG tables that state larger sizes but actually conflict
689 * with other system resources.
690 */
691 late_initcall(pci_mmcfg_late_insert_resources);
692
693 /* Add MMCFG information for host bridges */
694 int pci_mmconfig_insert(struct device *dev, u16 seg, u8 start, u8 end,
695 phys_addr_t addr)
696 {
697 int rc;
698 struct resource *tmp = NULL;
699 struct pci_mmcfg_region *cfg;
700
701 if (!(pci_probe & PCI_PROBE_MMCONF) || pci_mmcfg_arch_init_failed)
702 return -ENODEV;
703
704 if (start > end)
705 return -EINVAL;
706
707 mutex_lock(&pci_mmcfg_lock);
708 cfg = pci_mmconfig_lookup(seg, start);
709 if (cfg) {
710 if (cfg->end_bus < end)
711 dev_info(dev, FW_INFO
712 "MMCONFIG for "
713 "domain %04x [bus %02x-%02x] "
714 "only partially covers this bridge\n",
715 cfg->segment, cfg->start_bus, cfg->end_bus);
716 mutex_unlock(&pci_mmcfg_lock);
717 return -EEXIST;
718 }
719
720 if (!addr) {
721 mutex_unlock(&pci_mmcfg_lock);
722 return -EINVAL;
723 }
724
725 rc = -EBUSY;
726 cfg = pci_mmconfig_alloc(seg, start, end, addr);
727 if (cfg == NULL) {
728 dev_warn(dev, "fail to add MMCONFIG (out of memory)\n");
729 rc = -ENOMEM;
730 } else if (!pci_mmcfg_check_reserved(dev, cfg, 0)) {
731 dev_warn(dev, FW_BUG "MMCONFIG %pR isn't reserved\n",
732 &cfg->res);
733 } else {
734 /* Insert resource if it's not in boot stage */
735 if (pci_mmcfg_running_state)
736 tmp = insert_resource_conflict(&iomem_resource,
737 &cfg->res);
738
739 if (tmp) {
740 dev_warn(dev,
741 "MMCONFIG %pR conflicts with "
742 "%s %pR\n",
743 &cfg->res, tmp->name, tmp);
744 } else if (pci_mmcfg_arch_map(cfg)) {
745 dev_warn(dev, "fail to map MMCONFIG %pR.\n",
746 &cfg->res);
747 } else {
748 list_add_sorted(cfg);
749 dev_info(dev, "MMCONFIG at %pR (base %#lx)\n",
750 &cfg->res, (unsigned long)addr);
751 cfg = NULL;
752 rc = 0;
753 }
754 }
755
756 if (cfg) {
757 if (cfg->res.parent)
758 release_resource(&cfg->res);
759 kfree(cfg);
760 }
761
762 mutex_unlock(&pci_mmcfg_lock);
763
764 return rc;
765 }
766
767 /* Delete MMCFG information for host bridges */
768 int pci_mmconfig_delete(u16 seg, u8 start, u8 end)
769 {
770 struct pci_mmcfg_region *cfg;
771
772 mutex_lock(&pci_mmcfg_lock);
773 list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list)
774 if (cfg->segment == seg && cfg->start_bus == start &&
775 cfg->end_bus == end) {
776 list_del_rcu(&cfg->list);
777 synchronize_rcu();
778 pci_mmcfg_arch_unmap(cfg);
779 if (cfg->res.parent)
780 release_resource(&cfg->res);
781 mutex_unlock(&pci_mmcfg_lock);
782 kfree(cfg);
783 return 0;
784 }
785 mutex_unlock(&pci_mmcfg_lock);
786
787 return -ENOENT;
788 }
CRIS linux kernel tree