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Linux 3.8-rc7
[cris-mirror.git] / sound / pci / cs4281.c
blob6a86950699415527261c4d938bbe7cfaca328010
1 /*
2 * Driver for Cirrus Logic CS4281 based PCI soundcard
3 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>,
4 *
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 */
21
22 #include <asm/io.h>
23 #include <linux/delay.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/pci.h>
27 #include <linux/slab.h>
28 #include <linux/gameport.h>
29 #include <linux/module.h>
30 #include <sound/core.h>
31 #include <sound/control.h>
32 #include <sound/pcm.h>
33 #include <sound/rawmidi.h>
34 #include <sound/ac97_codec.h>
35 #include <sound/tlv.h>
36 #include <sound/opl3.h>
37 #include <sound/initval.h>
38
39
40 MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
41 MODULE_DESCRIPTION("Cirrus Logic CS4281");
42 MODULE_LICENSE("GPL");
43 MODULE_SUPPORTED_DEVICE("{{Cirrus Logic,CS4281}}");
44
45 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
46 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
47 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */
48 static bool dual_codec[SNDRV_CARDS]; /* dual codec */
49
50 module_param_array(index, int, NULL, 0444);
51 MODULE_PARM_DESC(index, "Index value for CS4281 soundcard.");
52 module_param_array(id, charp, NULL, 0444);
53 MODULE_PARM_DESC(id, "ID string for CS4281 soundcard.");
54 module_param_array(enable, bool, NULL, 0444);
55 MODULE_PARM_DESC(enable, "Enable CS4281 soundcard.");
56 module_param_array(dual_codec, bool, NULL, 0444);
57 MODULE_PARM_DESC(dual_codec, "Secondary Codec ID (0 = disabled).");
58
59 /*
60 * Direct registers
61 */
62
63 #define CS4281_BA0_SIZE 0x1000
64 #define CS4281_BA1_SIZE 0x10000
65
66 /*
67 * BA0 registers
68 */
69 #define BA0_HISR 0x0000 /* Host Interrupt Status Register */
70 #define BA0_HISR_INTENA (1<<31) /* Internal Interrupt Enable Bit */
71 #define BA0_HISR_MIDI (1<<22) /* MIDI port interrupt */
72 #define BA0_HISR_FIFOI (1<<20) /* FIFO polled interrupt */
73 #define BA0_HISR_DMAI (1<<18) /* DMA interrupt (half or end) */
74 #define BA0_HISR_FIFO(c) (1<<(12+(c))) /* FIFO channel interrupt */
75 #define BA0_HISR_DMA(c) (1<<(8+(c))) /* DMA channel interrupt */
76 #define BA0_HISR_GPPI (1<<5) /* General Purpose Input (Primary chip) */
77 #define BA0_HISR_GPSI (1<<4) /* General Purpose Input (Secondary chip) */
78 #define BA0_HISR_GP3I (1<<3) /* GPIO3 pin Interrupt */
79 #define BA0_HISR_GP1I (1<<2) /* GPIO1 pin Interrupt */
80 #define BA0_HISR_VUPI (1<<1) /* VOLUP pin Interrupt */
81 #define BA0_HISR_VDNI (1<<0) /* VOLDN pin Interrupt */
82
83 #define BA0_HICR 0x0008 /* Host Interrupt Control Register */
84 #define BA0_HICR_CHGM (1<<1) /* INTENA Change Mask */
85 #define BA0_HICR_IEV (1<<0) /* INTENA Value */
86 #define BA0_HICR_EOI (3<<0) /* End of Interrupt command */
87
88 #define BA0_HIMR 0x000c /* Host Interrupt Mask Register */
89 /* Use same contants as for BA0_HISR */
90
91 #define BA0_IIER 0x0010 /* ISA Interrupt Enable Register */
92
93 #define BA0_HDSR0 0x00f0 /* Host DMA Engine 0 Status Register */
94 #define BA0_HDSR1 0x00f4 /* Host DMA Engine 1 Status Register */
95 #define BA0_HDSR2 0x00f8 /* Host DMA Engine 2 Status Register */
96 #define BA0_HDSR3 0x00fc /* Host DMA Engine 3 Status Register */
97
98 #define BA0_HDSR_CH1P (1<<25) /* Channel 1 Pending */
99 #define BA0_HDSR_CH2P (1<<24) /* Channel 2 Pending */
100 #define BA0_HDSR_DHTC (1<<17) /* DMA Half Terminal Count */
101 #define BA0_HDSR_DTC (1<<16) /* DMA Terminal Count */
102 #define BA0_HDSR_DRUN (1<<15) /* DMA Running */
103 #define BA0_HDSR_RQ (1<<7) /* Pending Request */
104
105 #define BA0_DCA0 0x0110 /* Host DMA Engine 0 Current Address */
106 #define BA0_DCC0 0x0114 /* Host DMA Engine 0 Current Count */
107 #define BA0_DBA0 0x0118 /* Host DMA Engine 0 Base Address */
108 #define BA0_DBC0 0x011c /* Host DMA Engine 0 Base Count */
109 #define BA0_DCA1 0x0120 /* Host DMA Engine 1 Current Address */
110 #define BA0_DCC1 0x0124 /* Host DMA Engine 1 Current Count */
111 #define BA0_DBA1 0x0128 /* Host DMA Engine 1 Base Address */
112 #define BA0_DBC1 0x012c /* Host DMA Engine 1 Base Count */
113 #define BA0_DCA2 0x0130 /* Host DMA Engine 2 Current Address */
114 #define BA0_DCC2 0x0134 /* Host DMA Engine 2 Current Count */
115 #define BA0_DBA2 0x0138 /* Host DMA Engine 2 Base Address */
116 #define BA0_DBC2 0x013c /* Host DMA Engine 2 Base Count */
117 #define BA0_DCA3 0x0140 /* Host DMA Engine 3 Current Address */
118 #define BA0_DCC3 0x0144 /* Host DMA Engine 3 Current Count */
119 #define BA0_DBA3 0x0148 /* Host DMA Engine 3 Base Address */
120 #define BA0_DBC3 0x014c /* Host DMA Engine 3 Base Count */
121 #define BA0_DMR0 0x0150 /* Host DMA Engine 0 Mode */
122 #define BA0_DCR0 0x0154 /* Host DMA Engine 0 Command */
123 #define BA0_DMR1 0x0158 /* Host DMA Engine 1 Mode */
124 #define BA0_DCR1 0x015c /* Host DMA Engine 1 Command */
125 #define BA0_DMR2 0x0160 /* Host DMA Engine 2 Mode */
126 #define BA0_DCR2 0x0164 /* Host DMA Engine 2 Command */
127 #define BA0_DMR3 0x0168 /* Host DMA Engine 3 Mode */
128 #define BA0_DCR3 0x016c /* Host DMA Engine 3 Command */
129
130 #define BA0_DMR_DMA (1<<29) /* Enable DMA mode */
131 #define BA0_DMR_POLL (1<<28) /* Enable poll mode */
132 #define BA0_DMR_TBC (1<<25) /* Transfer By Channel */
133 #define BA0_DMR_CBC (1<<24) /* Count By Channel (0 = frame resolution) */
134 #define BA0_DMR_SWAPC (1<<22) /* Swap Left/Right Channels */
135 #define BA0_DMR_SIZE20 (1<<20) /* Sample is 20-bit */
136 #define BA0_DMR_USIGN (1<<19) /* Unsigned */
137 #define BA0_DMR_BEND (1<<18) /* Big Endian */
138 #define BA0_DMR_MONO (1<<17) /* Mono */
139 #define BA0_DMR_SIZE8 (1<<16) /* Sample is 8-bit */
140 #define BA0_DMR_TYPE_DEMAND (0<<6)
141 #define BA0_DMR_TYPE_SINGLE (1<<6)
142 #define BA0_DMR_TYPE_BLOCK (2<<6)
143 #define BA0_DMR_TYPE_CASCADE (3<<6) /* Not supported */
144 #define BA0_DMR_DEC (1<<5) /* Access Increment (0) or Decrement (1) */
145 #define BA0_DMR_AUTO (1<<4) /* Auto-Initialize */
146 #define BA0_DMR_TR_VERIFY (0<<2) /* Verify Transfer */
147 #define BA0_DMR_TR_WRITE (1<<2) /* Write Transfer */
148 #define BA0_DMR_TR_READ (2<<2) /* Read Transfer */
149
150 #define BA0_DCR_HTCIE (1<<17) /* Half Terminal Count Interrupt */
151 #define BA0_DCR_TCIE (1<<16) /* Terminal Count Interrupt */
152 #define BA0_DCR_MSK (1<<0) /* DMA Mask bit */
153
154 #define BA0_FCR0 0x0180 /* FIFO Control 0 */
155 #define BA0_FCR1 0x0184 /* FIFO Control 1 */
156 #define BA0_FCR2 0x0188 /* FIFO Control 2 */
157 #define BA0_FCR3 0x018c /* FIFO Control 3 */
158
159 #define BA0_FCR_FEN (1<<31) /* FIFO Enable bit */
160 #define BA0_FCR_DACZ (1<<30) /* DAC Zero */
161 #define BA0_FCR_PSH (1<<29) /* Previous Sample Hold */
162 #define BA0_FCR_RS(x) (((x)&0x1f)<<24) /* Right Slot Mapping */
163 #define BA0_FCR_LS(x) (((x)&0x1f)<<16) /* Left Slot Mapping */
164 #define BA0_FCR_SZ(x) (((x)&0x7f)<<8) /* FIFO buffer size (in samples) */
165 #define BA0_FCR_OF(x) (((x)&0x7f)<<0) /* FIFO starting offset (in samples) */
166
167 #define BA0_FPDR0 0x0190 /* FIFO Polled Data 0 */
168 #define BA0_FPDR1 0x0194 /* FIFO Polled Data 1 */
169 #define BA0_FPDR2 0x0198 /* FIFO Polled Data 2 */
170 #define BA0_FPDR3 0x019c /* FIFO Polled Data 3 */
171
172 #define BA0_FCHS 0x020c /* FIFO Channel Status */
173 #define BA0_FCHS_RCO(x) (1<<(7+(((x)&3)<<3))) /* Right Channel Out */
174 #define BA0_FCHS_LCO(x) (1<<(6+(((x)&3)<<3))) /* Left Channel Out */
175 #define BA0_FCHS_MRP(x) (1<<(5+(((x)&3)<<3))) /* Move Read Pointer */
176 #define BA0_FCHS_FE(x) (1<<(4+(((x)&3)<<3))) /* FIFO Empty */
177 #define BA0_FCHS_FF(x) (1<<(3+(((x)&3)<<3))) /* FIFO Full */
178 #define BA0_FCHS_IOR(x) (1<<(2+(((x)&3)<<3))) /* Internal Overrun Flag */
179 #define BA0_FCHS_RCI(x) (1<<(1+(((x)&3)<<3))) /* Right Channel In */
180 #define BA0_FCHS_LCI(x) (1<<(0+(((x)&3)<<3))) /* Left Channel In */
181
182 #define BA0_FSIC0 0x0210 /* FIFO Status and Interrupt Control 0 */
183 #define BA0_FSIC1 0x0214 /* FIFO Status and Interrupt Control 1 */
184 #define BA0_FSIC2 0x0218 /* FIFO Status and Interrupt Control 2 */
185 #define BA0_FSIC3 0x021c /* FIFO Status and Interrupt Control 3 */
186
187 #define BA0_FSIC_FIC(x) (((x)&0x7f)<<24) /* FIFO Interrupt Count */
188 #define BA0_FSIC_FORIE (1<<23) /* FIFO OverRun Interrupt Enable */
189 #define BA0_FSIC_FURIE (1<<22) /* FIFO UnderRun Interrupt Enable */
190 #define BA0_FSIC_FSCIE (1<<16) /* FIFO Sample Count Interrupt Enable */
191 #define BA0_FSIC_FSC(x) (((x)&0x7f)<<8) /* FIFO Sample Count */
192 #define BA0_FSIC_FOR (1<<7) /* FIFO OverRun */
193 #define BA0_FSIC_FUR (1<<6) /* FIFO UnderRun */
194 #define BA0_FSIC_FSCR (1<<0) /* FIFO Sample Count Reached */
195
196 #define BA0_PMCS 0x0344 /* Power Management Control/Status */
197 #define BA0_CWPR 0x03e0 /* Configuration Write Protect */
198
199 #define BA0_EPPMC 0x03e4 /* Extended PCI Power Management Control */
200 #define BA0_EPPMC_FPDN (1<<14) /* Full Power DowN */
201
202 #define BA0_GPIOR 0x03e8 /* GPIO Pin Interface Register */
203
204 #define BA0_SPMC 0x03ec /* Serial Port Power Management Control (& ASDIN2 enable) */
205 #define BA0_SPMC_GIPPEN (1<<15) /* GP INT Primary PME# Enable */
206 #define BA0_SPMC_GISPEN (1<<14) /* GP INT Secondary PME# Enable */
207 #define BA0_SPMC_EESPD (1<<9) /* EEPROM Serial Port Disable */
208 #define BA0_SPMC_ASDI2E (1<<8) /* ASDIN2 Enable */
209 #define BA0_SPMC_ASDO (1<<7) /* Asynchronous ASDOUT Assertion */
210 #define BA0_SPMC_WUP2 (1<<3) /* Wakeup for Secondary Input */
211 #define BA0_SPMC_WUP1 (1<<2) /* Wakeup for Primary Input */
212 #define BA0_SPMC_ASYNC (1<<1) /* Asynchronous ASYNC Assertion */
213 #define BA0_SPMC_RSTN (1<<0) /* Reset Not! */
214
215 #define BA0_CFLR 0x03f0 /* Configuration Load Register (EEPROM or BIOS) */
216 #define BA0_CFLR_DEFAULT 0x00000001 /* CFLR must be in AC97 link mode */
217 #define BA0_IISR 0x03f4 /* ISA Interrupt Select */
218 #define BA0_TMS 0x03f8 /* Test Register */
219 #define BA0_SSVID 0x03fc /* Subsystem ID register */
220
221 #define BA0_CLKCR1 0x0400 /* Clock Control Register 1 */
222 #define BA0_CLKCR1_CLKON (1<<25) /* Read Only */
223 #define BA0_CLKCR1_DLLRDY (1<<24) /* DLL Ready */
224 #define BA0_CLKCR1_DLLOS (1<<6) /* DLL Output Select */
225 #define BA0_CLKCR1_SWCE (1<<5) /* Clock Enable */
226 #define BA0_CLKCR1_DLLP (1<<4) /* DLL PowerUp */
227 #define BA0_CLKCR1_DLLSS (((x)&3)<<3) /* DLL Source Select */
228
229 #define BA0_FRR 0x0410 /* Feature Reporting Register */
230 #define BA0_SLT12O 0x041c /* Slot 12 GPIO Output Register for AC-Link */
231
232 #define BA0_SERMC 0x0420 /* Serial Port Master Control */
233 #define BA0_SERMC_FCRN (1<<27) /* Force Codec Ready Not */
234 #define BA0_SERMC_ODSEN2 (1<<25) /* On-Demand Support Enable ASDIN2 */
235 #define BA0_SERMC_ODSEN1 (1<<24) /* On-Demand Support Enable ASDIN1 */
236 #define BA0_SERMC_SXLB (1<<21) /* ASDIN2 to ASDOUT Loopback */
237 #define BA0_SERMC_SLB (1<<20) /* ASDOUT to ASDIN2 Loopback */
238 #define BA0_SERMC_LOVF (1<<19) /* Loopback Output Valid Frame bit */
239 #define BA0_SERMC_TCID(x) (((x)&3)<<16) /* Target Secondary Codec ID */
240 #define BA0_SERMC_PXLB (5<<1) /* Primary Port External Loopback */
241 #define BA0_SERMC_PLB (4<<1) /* Primary Port Internal Loopback */
242 #define BA0_SERMC_PTC (7<<1) /* Port Timing Configuration */
243 #define BA0_SERMC_PTC_AC97 (1<<1) /* AC97 mode */
244 #define BA0_SERMC_MSPE (1<<0) /* Master Serial Port Enable */
245
246 #define BA0_SERC1 0x0428 /* Serial Port Configuration 1 */
247 #define BA0_SERC1_SO1F(x) (((x)&7)>>1) /* Primary Output Port Format */
248 #define BA0_SERC1_AC97 (1<<1)
249 #define BA0_SERC1_SO1EN (1<<0) /* Primary Output Port Enable */
250
251 #define BA0_SERC2 0x042c /* Serial Port Configuration 2 */
252 #define BA0_SERC2_SI1F(x) (((x)&7)>>1) /* Primary Input Port Format */
253 #define BA0_SERC2_AC97 (1<<1)
254 #define BA0_SERC2_SI1EN (1<<0) /* Primary Input Port Enable */
255
256 #define BA0_SLT12M 0x045c /* Slot 12 Monitor Register for Primary AC-Link */
257
258 #define BA0_ACCTL 0x0460 /* AC'97 Control */
259 #define BA0_ACCTL_TC (1<<6) /* Target Codec */
260 #define BA0_ACCTL_CRW (1<<4) /* 0=Write, 1=Read Command */
261 #define BA0_ACCTL_DCV (1<<3) /* Dynamic Command Valid */
262 #define BA0_ACCTL_VFRM (1<<2) /* Valid Frame */
263 #define BA0_ACCTL_ESYN (1<<1) /* Enable Sync */
264
265 #define BA0_ACSTS 0x0464 /* AC'97 Status */
266 #define BA0_ACSTS_VSTS (1<<1) /* Valid Status */
267 #define BA0_ACSTS_CRDY (1<<0) /* Codec Ready */
268
269 #define BA0_ACOSV 0x0468 /* AC'97 Output Slot Valid */
270 #define BA0_ACOSV_SLV(x) (1<<((x)-3))
271
272 #define BA0_ACCAD 0x046c /* AC'97 Command Address */
273 #define BA0_ACCDA 0x0470 /* AC'97 Command Data */
274
275 #define BA0_ACISV 0x0474 /* AC'97 Input Slot Valid */
276 #define BA0_ACISV_SLV(x) (1<<((x)-3))
277
278 #define BA0_ACSAD 0x0478 /* AC'97 Status Address */
279 #define BA0_ACSDA 0x047c /* AC'97 Status Data */
280 #define BA0_JSPT 0x0480 /* Joystick poll/trigger */
281 #define BA0_JSCTL 0x0484 /* Joystick control */
282 #define BA0_JSC1 0x0488 /* Joystick control */
283 #define BA0_JSC2 0x048c /* Joystick control */
284 #define BA0_JSIO 0x04a0
285
286 #define BA0_MIDCR 0x0490 /* MIDI Control */
287 #define BA0_MIDCR_MRST (1<<5) /* Reset MIDI Interface */
288 #define BA0_MIDCR_MLB (1<<4) /* MIDI Loop Back Enable */
289 #define BA0_MIDCR_TIE (1<<3) /* MIDI Transmuit Interrupt Enable */
290 #define BA0_MIDCR_RIE (1<<2) /* MIDI Receive Interrupt Enable */
291 #define BA0_MIDCR_RXE (1<<1) /* MIDI Receive Enable */
292 #define BA0_MIDCR_TXE (1<<0) /* MIDI Transmit Enable */
293
294 #define BA0_MIDCMD 0x0494 /* MIDI Command (wo) */
295
296 #define BA0_MIDSR 0x0494 /* MIDI Status (ro) */
297 #define BA0_MIDSR_RDA (1<<15) /* Sticky bit (RBE 1->0) */
298 #define BA0_MIDSR_TBE (1<<14) /* Sticky bit (TBF 0->1) */
299 #define BA0_MIDSR_RBE (1<<7) /* Receive Buffer Empty */
300 #define BA0_MIDSR_TBF (1<<6) /* Transmit Buffer Full */
301
302 #define BA0_MIDWP 0x0498 /* MIDI Write */
303 #define BA0_MIDRP 0x049c /* MIDI Read (ro) */
304
305 #define BA0_AODSD1 0x04a8 /* AC'97 On-Demand Slot Disable for primary link (ro) */
306 #define BA0_AODSD1_NDS(x) (1<<((x)-3))
307
308 #define BA0_AODSD2 0x04ac /* AC'97 On-Demand Slot Disable for secondary link (ro) */
309 #define BA0_AODSD2_NDS(x) (1<<((x)-3))
310
311 #define BA0_CFGI 0x04b0 /* Configure Interface (EEPROM interface) */
312 #define BA0_SLT12M2 0x04dc /* Slot 12 Monitor Register 2 for secondary AC-link */
313 #define BA0_ACSTS2 0x04e4 /* AC'97 Status Register 2 */
314 #define BA0_ACISV2 0x04f4 /* AC'97 Input Slot Valid Register 2 */
315 #define BA0_ACSAD2 0x04f8 /* AC'97 Status Address Register 2 */
316 #define BA0_ACSDA2 0x04fc /* AC'97 Status Data Register 2 */
317 #define BA0_FMSR 0x0730 /* FM Synthesis Status (ro) */
318 #define BA0_B0AP 0x0730 /* FM Bank 0 Address Port (wo) */
319 #define BA0_FMDP 0x0734 /* FM Data Port */
320 #define BA0_B1AP 0x0738 /* FM Bank 1 Address Port */
321 #define BA0_B1DP 0x073c /* FM Bank 1 Data Port */
322
323 #define BA0_SSPM 0x0740 /* Sound System Power Management */
324 #define BA0_SSPM_MIXEN (1<<6) /* Playback SRC + FM/Wavetable MIX */
325 #define BA0_SSPM_CSRCEN (1<<5) /* Capture Sample Rate Converter Enable */
326 #define BA0_SSPM_PSRCEN (1<<4) /* Playback Sample Rate Converter Enable */
327 #define BA0_SSPM_JSEN (1<<3) /* Joystick Enable */
328 #define BA0_SSPM_ACLEN (1<<2) /* Serial Port Engine and AC-Link Enable */
329 #define BA0_SSPM_FMEN (1<<1) /* FM Synthesis Block Enable */
330
331 #define BA0_DACSR 0x0744 /* DAC Sample Rate - Playback SRC */
332 #define BA0_ADCSR 0x0748 /* ADC Sample Rate - Capture SRC */
333
334 #define BA0_SSCR 0x074c /* Sound System Control Register */
335 #define BA0_SSCR_HVS1 (1<<23) /* Hardwave Volume Step (0=1,1=2) */
336 #define BA0_SSCR_MVCS (1<<19) /* Master Volume Codec Select */
337 #define BA0_SSCR_MVLD (1<<18) /* Master Volume Line Out Disable */
338 #define BA0_SSCR_MVAD (1<<17) /* Master Volume Alternate Out Disable */
339 #define BA0_SSCR_MVMD (1<<16) /* Master Volume Mono Out Disable */
340 #define BA0_SSCR_XLPSRC (1<<8) /* External SRC Loopback Mode */
341 #define BA0_SSCR_LPSRC (1<<7) /* SRC Loopback Mode */
342 #define BA0_SSCR_CDTX (1<<5) /* CD Transfer Data */
343 #define BA0_SSCR_HVC (1<<3) /* Harware Volume Control Enable */
344
345 #define BA0_FMLVC 0x0754 /* FM Synthesis Left Volume Control */
346 #define BA0_FMRVC 0x0758 /* FM Synthesis Right Volume Control */
347 #define BA0_SRCSA 0x075c /* SRC Slot Assignments */
348 #define BA0_PPLVC 0x0760 /* PCM Playback Left Volume Control */
349 #define BA0_PPRVC 0x0764 /* PCM Playback Right Volume Control */
350 #define BA0_PASR 0x0768 /* playback sample rate */
351 #define BA0_CASR 0x076C /* capture sample rate */
352
353 /* Source Slot Numbers - Playback */
354 #define SRCSLOT_LEFT_PCM_PLAYBACK 0
355 #define SRCSLOT_RIGHT_PCM_PLAYBACK 1
356 #define SRCSLOT_PHONE_LINE_1_DAC 2
357 #define SRCSLOT_CENTER_PCM_PLAYBACK 3
358 #define SRCSLOT_LEFT_SURROUND_PCM_PLAYBACK 4
359 #define SRCSLOT_RIGHT_SURROUND_PCM_PLAYBACK 5
360 #define SRCSLOT_LFE_PCM_PLAYBACK 6
361 #define SRCSLOT_PHONE_LINE_2_DAC 7
362 #define SRCSLOT_HEADSET_DAC 8
363 #define SRCSLOT_LEFT_WT 29 /* invalid for BA0_SRCSA */
364 #define SRCSLOT_RIGHT_WT 30 /* invalid for BA0_SRCSA */
365
366 /* Source Slot Numbers - Capture */
367 #define SRCSLOT_LEFT_PCM_RECORD 10
368 #define SRCSLOT_RIGHT_PCM_RECORD 11
369 #define SRCSLOT_PHONE_LINE_1_ADC 12
370 #define SRCSLOT_MIC_ADC 13
371 #define SRCSLOT_PHONE_LINE_2_ADC 17
372 #define SRCSLOT_HEADSET_ADC 18
373 #define SRCSLOT_SECONDARY_LEFT_PCM_RECORD 20
374 #define SRCSLOT_SECONDARY_RIGHT_PCM_RECORD 21
375 #define SRCSLOT_SECONDARY_PHONE_LINE_1_ADC 22
376 #define SRCSLOT_SECONDARY_MIC_ADC 23
377 #define SRCSLOT_SECONDARY_PHONE_LINE_2_ADC 27
378 #define SRCSLOT_SECONDARY_HEADSET_ADC 28
379
380 /* Source Slot Numbers - Others */
381 #define SRCSLOT_POWER_DOWN 31
382
383 /* MIDI modes */
384 #define CS4281_MODE_OUTPUT (1<<0)
385 #define CS4281_MODE_INPUT (1<<1)
386
387 /* joystick bits */
388 /* Bits for JSPT */
389 #define JSPT_CAX 0x00000001
390 #define JSPT_CAY 0x00000002
391 #define JSPT_CBX 0x00000004
392 #define JSPT_CBY 0x00000008
393 #define JSPT_BA1 0x00000010
394 #define JSPT_BA2 0x00000020
395 #define JSPT_BB1 0x00000040
396 #define JSPT_BB2 0x00000080
397
398 /* Bits for JSCTL */
399 #define JSCTL_SP_MASK 0x00000003
400 #define JSCTL_SP_SLOW 0x00000000
401 #define JSCTL_SP_MEDIUM_SLOW 0x00000001
402 #define JSCTL_SP_MEDIUM_FAST 0x00000002
403 #define JSCTL_SP_FAST 0x00000003
404 #define JSCTL_ARE 0x00000004
405
406 /* Data register pairs masks */
407 #define JSC1_Y1V_MASK 0x0000FFFF
408 #define JSC1_X1V_MASK 0xFFFF0000
409 #define JSC1_Y1V_SHIFT 0
410 #define JSC1_X1V_SHIFT 16
411 #define JSC2_Y2V_MASK 0x0000FFFF
412 #define JSC2_X2V_MASK 0xFFFF0000
413 #define JSC2_Y2V_SHIFT 0
414 #define JSC2_X2V_SHIFT 16
415
416 /* JS GPIO */
417 #define JSIO_DAX 0x00000001
418 #define JSIO_DAY 0x00000002
419 #define JSIO_DBX 0x00000004
420 #define JSIO_DBY 0x00000008
421 #define JSIO_AXOE 0x00000010
422 #define JSIO_AYOE 0x00000020
423 #define JSIO_BXOE 0x00000040
424 #define JSIO_BYOE 0x00000080
425
426 /*
427 *
428 */
429
430 struct cs4281_dma {
431 struct snd_pcm_substream *substream;
432 unsigned int regDBA; /* offset to DBA register */
433 unsigned int regDCA; /* offset to DCA register */
434 unsigned int regDBC; /* offset to DBC register */
435 unsigned int regDCC; /* offset to DCC register */
436 unsigned int regDMR; /* offset to DMR register */
437 unsigned int regDCR; /* offset to DCR register */
438 unsigned int regHDSR; /* offset to HDSR register */
439 unsigned int regFCR; /* offset to FCR register */
440 unsigned int regFSIC; /* offset to FSIC register */
441 unsigned int valDMR; /* DMA mode */
442 unsigned int valDCR; /* DMA command */
443 unsigned int valFCR; /* FIFO control */
444 unsigned int fifo_offset; /* FIFO offset within BA1 */
445 unsigned char left_slot; /* FIFO left slot */
446 unsigned char right_slot; /* FIFO right slot */
447 int frag; /* period number */
448 };
449
450 #define SUSPEND_REGISTERS 20
451
452 struct cs4281 {
453 int irq;
454
455 void __iomem *ba0; /* virtual (accessible) address */
456 void __iomem *ba1; /* virtual (accessible) address */
457 unsigned long ba0_addr;
458 unsigned long ba1_addr;
459
460 int dual_codec;
461
462 struct snd_ac97_bus *ac97_bus;
463 struct snd_ac97 *ac97;
464 struct snd_ac97 *ac97_secondary;
465
466 struct pci_dev *pci;
467 struct snd_card *card;
468 struct snd_pcm *pcm;
469 struct snd_rawmidi *rmidi;
470 struct snd_rawmidi_substream *midi_input;
471 struct snd_rawmidi_substream *midi_output;
472
473 struct cs4281_dma dma[4];
474
475 unsigned char src_left_play_slot;
476 unsigned char src_right_play_slot;
477 unsigned char src_left_rec_slot;
478 unsigned char src_right_rec_slot;
479
480 unsigned int spurious_dhtc_irq;
481 unsigned int spurious_dtc_irq;
482
483 spinlock_t reg_lock;
484 unsigned int midcr;
485 unsigned int uartm;
486
487 struct gameport *gameport;
488
489 #ifdef CONFIG_PM_SLEEP
490 u32 suspend_regs[SUSPEND_REGISTERS];
491 #endif
492
493 };
494
495 static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id);
496
497 static DEFINE_PCI_DEVICE_TABLE(snd_cs4281_ids) = {
498 { PCI_VDEVICE(CIRRUS, 0x6005), 0, }, /* CS4281 */
499 { 0, }
500 };
501
502 MODULE_DEVICE_TABLE(pci, snd_cs4281_ids);
503
504 /*
505 * constants
506 */
507
508 #define CS4281_FIFO_SIZE 32
509
510 /*
511 * common I/O routines
512 */
513
514 static inline void snd_cs4281_pokeBA0(struct cs4281 *chip, unsigned long offset,
515 unsigned int val)
516 {
517 writel(val, chip->ba0 + offset);
518 }
519
520 static inline unsigned int snd_cs4281_peekBA0(struct cs4281 *chip, unsigned long offset)
521 {
522 return readl(chip->ba0 + offset);
523 }
524
525 static void snd_cs4281_ac97_write(struct snd_ac97 *ac97,
526 unsigned short reg, unsigned short val)
527 {
528 /*
529 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
530 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
531 * 3. Write ACCTL = Control Register = 460h for initiating the write
532 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h
533 * 5. if DCV not cleared, break and return error
534 */
535 struct cs4281 *chip = ac97->private_data;
536 int count;
537
538 /*
539 * Setup the AC97 control registers on the CS461x to send the
540 * appropriate command to the AC97 to perform the read.
541 * ACCAD = Command Address Register = 46Ch
542 * ACCDA = Command Data Register = 470h
543 * ACCTL = Control Register = 460h
544 * set DCV - will clear when process completed
545 * reset CRW - Write command
546 * set VFRM - valid frame enabled
547 * set ESYN - ASYNC generation enabled
548 * set RSTN - ARST# inactive, AC97 codec not reset
549 */
550 snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg);
551 snd_cs4281_pokeBA0(chip, BA0_ACCDA, val);
552 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_VFRM |
553 BA0_ACCTL_ESYN | (ac97->num ? BA0_ACCTL_TC : 0));
554 for (count = 0; count < 2000; count++) {
555 /*
556 * First, we want to wait for a short time.
557 */
558 udelay(10);
559 /*
560 * Now, check to see if the write has completed.
561 * ACCTL = 460h, DCV should be reset by now and 460h = 07h
562 */
563 if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV)) {
564 return;
565 }
566 }
567 snd_printk(KERN_ERR "AC'97 write problem, reg = 0x%x, val = 0x%x\n", reg, val);
568 }
569
570 static unsigned short snd_cs4281_ac97_read(struct snd_ac97 *ac97,
571 unsigned short reg)
572 {
573 struct cs4281 *chip = ac97->private_data;
574 int count;
575 unsigned short result;
576 // FIXME: volatile is necessary in the following due to a bug of
577 // some gcc versions
578 volatile int ac97_num = ((volatile struct snd_ac97 *)ac97)->num;
579
580 /*
581 * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
582 * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
583 * 3. Write ACCTL = Control Register = 460h for initiating the write
584 * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h
585 * 5. if DCV not cleared, break and return error
586 * 6. Read ACSTS = Status Register = 464h, check VSTS bit
587 */
588
589 snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA);
590
591 /*
592 * Setup the AC97 control registers on the CS461x to send the
593 * appropriate command to the AC97 to perform the read.
594 * ACCAD = Command Address Register = 46Ch
595 * ACCDA = Command Data Register = 470h
596 * ACCTL = Control Register = 460h
597 * set DCV - will clear when process completed
598 * set CRW - Read command
599 * set VFRM - valid frame enabled
600 * set ESYN - ASYNC generation enabled
601 * set RSTN - ARST# inactive, AC97 codec not reset
602 */
603
604 snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg);
605 snd_cs4281_pokeBA0(chip, BA0_ACCDA, 0);
606 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_CRW |
607 BA0_ACCTL_VFRM | BA0_ACCTL_ESYN |
608 (ac97_num ? BA0_ACCTL_TC : 0));
609
610
611 /*
612 * Wait for the read to occur.
613 */
614 for (count = 0; count < 500; count++) {
615 /*
616 * First, we want to wait for a short time.
617 */
618 udelay(10);
619 /*
620 * Now, check to see if the read has completed.
621 * ACCTL = 460h, DCV should be reset by now and 460h = 17h
622 */
623 if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV))
624 goto __ok1;
625 }
626
627 snd_printk(KERN_ERR "AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg);
628 result = 0xffff;
629 goto __end;
630
631 __ok1:
632 /*
633 * Wait for the valid status bit to go active.
634 */
635 for (count = 0; count < 100; count++) {
636 /*
637 * Read the AC97 status register.
638 * ACSTS = Status Register = 464h
639 * VSTS - Valid Status
640 */
641 if (snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSTS2 : BA0_ACSTS) & BA0_ACSTS_VSTS)
642 goto __ok2;
643 udelay(10);
644 }
645
646 snd_printk(KERN_ERR "AC'97 read problem (ACSTS_VSTS), reg = 0x%x\n", reg);
647 result = 0xffff;
648 goto __end;
649
650 __ok2:
651 /*
652 * Read the data returned from the AC97 register.
653 * ACSDA = Status Data Register = 474h
654 */
655 result = snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA);
656
657 __end:
658 return result;
659 }
660
661 /*
662 * PCM part
663 */
664
665 static int snd_cs4281_trigger(struct snd_pcm_substream *substream, int cmd)
666 {
667 struct cs4281_dma *dma = substream->runtime->private_data;
668 struct cs4281 *chip = snd_pcm_substream_chip(substream);
669
670 spin_lock(&chip->reg_lock);
671 switch (cmd) {
672 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
673 dma->valDCR |= BA0_DCR_MSK;
674 dma->valFCR |= BA0_FCR_FEN;
675 break;
676 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
677 dma->valDCR &= ~BA0_DCR_MSK;
678 dma->valFCR &= ~BA0_FCR_FEN;
679 break;
680 case SNDRV_PCM_TRIGGER_START:
681 case SNDRV_PCM_TRIGGER_RESUME:
682 snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR & ~BA0_DMR_DMA);
683 dma->valDMR |= BA0_DMR_DMA;
684 dma->valDCR &= ~BA0_DCR_MSK;
685 dma->valFCR |= BA0_FCR_FEN;
686 break;
687 case SNDRV_PCM_TRIGGER_STOP:
688 case SNDRV_PCM_TRIGGER_SUSPEND:
689 dma->valDMR &= ~(BA0_DMR_DMA|BA0_DMR_POLL);
690 dma->valDCR |= BA0_DCR_MSK;
691 dma->valFCR &= ~BA0_FCR_FEN;
692 /* Leave wave playback FIFO enabled for FM */
693 if (dma->regFCR != BA0_FCR0)
694 dma->valFCR &= ~BA0_FCR_FEN;
695 break;
696 default:
697 spin_unlock(&chip->reg_lock);
698 return -EINVAL;
699 }
700 snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR);
701 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR);
702 snd_cs4281_pokeBA0(chip, dma->regDCR, dma->valDCR);
703 spin_unlock(&chip->reg_lock);
704 return 0;
705 }
706
707 static unsigned int snd_cs4281_rate(unsigned int rate, unsigned int *real_rate)
708 {
709 unsigned int val = ~0;
710
711 if (real_rate)
712 *real_rate = rate;
713 /* special "hardcoded" rates */
714 switch (rate) {
715 case 8000: return 5;
716 case 11025: return 4;
717 case 16000: return 3;
718 case 22050: return 2;
719 case 44100: return 1;
720 case 48000: return 0;
721 default:
722 goto __variable;
723 }
724 __variable:
725 val = 1536000 / rate;
726 if (real_rate)
727 *real_rate = 1536000 / val;
728 return val;
729 }
730
731 static void snd_cs4281_mode(struct cs4281 *chip, struct cs4281_dma *dma,
732 struct snd_pcm_runtime *runtime,
733 int capture, int src)
734 {
735 int rec_mono;
736
737 dma->valDMR = BA0_DMR_TYPE_SINGLE | BA0_DMR_AUTO |
738 (capture ? BA0_DMR_TR_WRITE : BA0_DMR_TR_READ);
739 if (runtime->channels == 1)
740 dma->valDMR |= BA0_DMR_MONO;
741 if (snd_pcm_format_unsigned(runtime->format) > 0)
742 dma->valDMR |= BA0_DMR_USIGN;
743 if (snd_pcm_format_big_endian(runtime->format) > 0)
744 dma->valDMR |= BA0_DMR_BEND;
745 switch (snd_pcm_format_width(runtime->format)) {
746 case 8: dma->valDMR |= BA0_DMR_SIZE8;
747 if (runtime->channels == 1)
748 dma->valDMR |= BA0_DMR_SWAPC;
749 break;
750 case 32: dma->valDMR |= BA0_DMR_SIZE20; break;
751 }
752 dma->frag = 0; /* for workaround */
753 dma->valDCR = BA0_DCR_TCIE | BA0_DCR_MSK;
754 if (runtime->buffer_size != runtime->period_size)
755 dma->valDCR |= BA0_DCR_HTCIE;
756 /* Initialize DMA */
757 snd_cs4281_pokeBA0(chip, dma->regDBA, runtime->dma_addr);
758 snd_cs4281_pokeBA0(chip, dma->regDBC, runtime->buffer_size - 1);
759 rec_mono = (chip->dma[1].valDMR & BA0_DMR_MONO) == BA0_DMR_MONO;
760 snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) |
761 (chip->src_right_play_slot << 8) |
762 (chip->src_left_rec_slot << 16) |
763 ((rec_mono ? 31 : chip->src_right_rec_slot) << 24));
764 if (!src)
765 goto __skip_src;
766 if (!capture) {
767 if (dma->left_slot == chip->src_left_play_slot) {
768 unsigned int val = snd_cs4281_rate(runtime->rate, NULL);
769 snd_BUG_ON(dma->right_slot != chip->src_right_play_slot);
770 snd_cs4281_pokeBA0(chip, BA0_DACSR, val);
771 }
772 } else {
773 if (dma->left_slot == chip->src_left_rec_slot) {
774 unsigned int val = snd_cs4281_rate(runtime->rate, NULL);
775 snd_BUG_ON(dma->right_slot != chip->src_right_rec_slot);
776 snd_cs4281_pokeBA0(chip, BA0_ADCSR, val);
777 }
778 }
779 __skip_src:
780 /* Deactivate wave playback FIFO before changing slot assignments */
781 if (dma->regFCR == BA0_FCR0)
782 snd_cs4281_pokeBA0(chip, dma->regFCR, snd_cs4281_peekBA0(chip, dma->regFCR) & ~BA0_FCR_FEN);
783 /* Initialize FIFO */
784 dma->valFCR = BA0_FCR_LS(dma->left_slot) |
785 BA0_FCR_RS(capture && (dma->valDMR & BA0_DMR_MONO) ? 31 : dma->right_slot) |
786 BA0_FCR_SZ(CS4281_FIFO_SIZE) |
787 BA0_FCR_OF(dma->fifo_offset);
788 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | (capture ? BA0_FCR_PSH : 0));
789 /* Activate FIFO again for FM playback */
790 if (dma->regFCR == BA0_FCR0)
791 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | BA0_FCR_FEN);
792 /* Clear FIFO Status and Interrupt Control Register */
793 snd_cs4281_pokeBA0(chip, dma->regFSIC, 0);
794 }
795
796 static int snd_cs4281_hw_params(struct snd_pcm_substream *substream,
797 struct snd_pcm_hw_params *hw_params)
798 {
799 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
800 }
801
802 static int snd_cs4281_hw_free(struct snd_pcm_substream *substream)
803 {
804 return snd_pcm_lib_free_pages(substream);
805 }
806
807 static int snd_cs4281_playback_prepare(struct snd_pcm_substream *substream)
808 {
809 struct snd_pcm_runtime *runtime = substream->runtime;
810 struct cs4281_dma *dma = runtime->private_data;
811 struct cs4281 *chip = snd_pcm_substream_chip(substream);
812
813 spin_lock_irq(&chip->reg_lock);
814 snd_cs4281_mode(chip, dma, runtime, 0, 1);
815 spin_unlock_irq(&chip->reg_lock);
816 return 0;
817 }
818
819 static int snd_cs4281_capture_prepare(struct snd_pcm_substream *substream)
820 {
821 struct snd_pcm_runtime *runtime = substream->runtime;
822 struct cs4281_dma *dma = runtime->private_data;
823 struct cs4281 *chip = snd_pcm_substream_chip(substream);
824
825 spin_lock_irq(&chip->reg_lock);
826 snd_cs4281_mode(chip, dma, runtime, 1, 1);
827 spin_unlock_irq(&chip->reg_lock);
828 return 0;
829 }
830
831 static snd_pcm_uframes_t snd_cs4281_pointer(struct snd_pcm_substream *substream)
832 {
833 struct snd_pcm_runtime *runtime = substream->runtime;
834 struct cs4281_dma *dma = runtime->private_data;
835 struct cs4281 *chip = snd_pcm_substream_chip(substream);
836
837 /*
838 printk(KERN_DEBUG "DCC = 0x%x, buffer_size = 0x%x, jiffies = %li\n",
839 snd_cs4281_peekBA0(chip, dma->regDCC), runtime->buffer_size,
840 jiffies);
841 */
842 return runtime->buffer_size -
843 snd_cs4281_peekBA0(chip, dma->regDCC) - 1;
844 }
845
846 static struct snd_pcm_hardware snd_cs4281_playback =
847 {
848 .info = SNDRV_PCM_INFO_MMAP |
849 SNDRV_PCM_INFO_INTERLEAVED |
850 SNDRV_PCM_INFO_MMAP_VALID |
851 SNDRV_PCM_INFO_PAUSE |
852 SNDRV_PCM_INFO_RESUME,
853 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8 |
854 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_S16_LE |
855 SNDRV_PCM_FMTBIT_U16_BE | SNDRV_PCM_FMTBIT_S16_BE |
856 SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_S32_LE |
857 SNDRV_PCM_FMTBIT_U32_BE | SNDRV_PCM_FMTBIT_S32_BE,
858 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
859 .rate_min = 4000,
860 .rate_max = 48000,
861 .channels_min = 1,
862 .channels_max = 2,
863 .buffer_bytes_max = (512*1024),
864 .period_bytes_min = 64,
865 .period_bytes_max = (512*1024),
866 .periods_min = 1,
867 .periods_max = 2,
868 .fifo_size = CS4281_FIFO_SIZE,
869 };
870
871 static struct snd_pcm_hardware snd_cs4281_capture =
872 {
873 .info = SNDRV_PCM_INFO_MMAP |
874 SNDRV_PCM_INFO_INTERLEAVED |
875 SNDRV_PCM_INFO_MMAP_VALID |
876 SNDRV_PCM_INFO_PAUSE |
877 SNDRV_PCM_INFO_RESUME,
878 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8 |
879 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_S16_LE |
880 SNDRV_PCM_FMTBIT_U16_BE | SNDRV_PCM_FMTBIT_S16_BE |
881 SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_S32_LE |
882 SNDRV_PCM_FMTBIT_U32_BE | SNDRV_PCM_FMTBIT_S32_BE,
883 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
884 .rate_min = 4000,
885 .rate_max = 48000,
886 .channels_min = 1,
887 .channels_max = 2,
888 .buffer_bytes_max = (512*1024),
889 .period_bytes_min = 64,
890 .period_bytes_max = (512*1024),
891 .periods_min = 1,
892 .periods_max = 2,
893 .fifo_size = CS4281_FIFO_SIZE,
894 };
895
896 static int snd_cs4281_playback_open(struct snd_pcm_substream *substream)
897 {
898 struct cs4281 *chip = snd_pcm_substream_chip(substream);
899 struct snd_pcm_runtime *runtime = substream->runtime;
900 struct cs4281_dma *dma;
901
902 dma = &chip->dma[0];
903 dma->substream = substream;
904 dma->left_slot = 0;
905 dma->right_slot = 1;
906 runtime->private_data = dma;
907 runtime->hw = snd_cs4281_playback;
908 /* should be detected from the AC'97 layer, but it seems
909 that although CS4297A rev B reports 18-bit ADC resolution,
910 samples are 20-bit */
911 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
912 return 0;
913 }
914
915 static int snd_cs4281_capture_open(struct snd_pcm_substream *substream)
916 {
917 struct cs4281 *chip = snd_pcm_substream_chip(substream);
918 struct snd_pcm_runtime *runtime = substream->runtime;
919 struct cs4281_dma *dma;
920
921 dma = &chip->dma[1];
922 dma->substream = substream;
923 dma->left_slot = 10;
924 dma->right_slot = 11;
925 runtime->private_data = dma;
926 runtime->hw = snd_cs4281_capture;
927 /* should be detected from the AC'97 layer, but it seems
928 that although CS4297A rev B reports 18-bit ADC resolution,
929 samples are 20-bit */
930 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
931 return 0;
932 }
933
934 static int snd_cs4281_playback_close(struct snd_pcm_substream *substream)
935 {
936 struct cs4281_dma *dma = substream->runtime->private_data;
937
938 dma->substream = NULL;
939 return 0;
940 }
941
942 static int snd_cs4281_capture_close(struct snd_pcm_substream *substream)
943 {
944 struct cs4281_dma *dma = substream->runtime->private_data;
945
946 dma->substream = NULL;
947 return 0;
948 }
949
950 static struct snd_pcm_ops snd_cs4281_playback_ops = {
951 .open = snd_cs4281_playback_open,
952 .close = snd_cs4281_playback_close,
953 .ioctl = snd_pcm_lib_ioctl,
954 .hw_params = snd_cs4281_hw_params,
955 .hw_free = snd_cs4281_hw_free,
956 .prepare = snd_cs4281_playback_prepare,
957 .trigger = snd_cs4281_trigger,
958 .pointer = snd_cs4281_pointer,
959 };
960
961 static struct snd_pcm_ops snd_cs4281_capture_ops = {
962 .open = snd_cs4281_capture_open,
963 .close = snd_cs4281_capture_close,
964 .ioctl = snd_pcm_lib_ioctl,
965 .hw_params = snd_cs4281_hw_params,
966 .hw_free = snd_cs4281_hw_free,
967 .prepare = snd_cs4281_capture_prepare,
968 .trigger = snd_cs4281_trigger,
969 .pointer = snd_cs4281_pointer,
970 };
971
972 static int snd_cs4281_pcm(struct cs4281 *chip, int device,
973 struct snd_pcm **rpcm)
974 {
975 struct snd_pcm *pcm;
976 int err;
977
978 if (rpcm)
979 *rpcm = NULL;
980 err = snd_pcm_new(chip->card, "CS4281", device, 1, 1, &pcm);
981 if (err < 0)
982 return err;
983
984 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs4281_playback_ops);
985 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs4281_capture_ops);
986
987 pcm->private_data = chip;
988 pcm->info_flags = 0;
989 strcpy(pcm->name, "CS4281");
990 chip->pcm = pcm;
991
992 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
993 snd_dma_pci_data(chip->pci), 64*1024, 512*1024);
994
995 if (rpcm)
996 *rpcm = pcm;
997 return 0;
998 }
999
1000 /*
1001 * Mixer section
1002 */
1003
1004 #define CS_VOL_MASK 0x1f
1005
1006 static int snd_cs4281_info_volume(struct snd_kcontrol *kcontrol,
1007 struct snd_ctl_elem_info *uinfo)
1008 {
1009 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1010 uinfo->count = 2;
1011 uinfo->value.integer.min = 0;
1012 uinfo->value.integer.max = CS_VOL_MASK;
1013 return 0;
1014 }
1015
1016 static int snd_cs4281_get_volume(struct snd_kcontrol *kcontrol,
1017 struct snd_ctl_elem_value *ucontrol)
1018 {
1019 struct cs4281 *chip = snd_kcontrol_chip(kcontrol);
1020 int regL = (kcontrol->private_value >> 16) & 0xffff;
1021 int regR = kcontrol->private_value & 0xffff;
1022 int volL, volR;
1023
1024 volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK);
1025 volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK);
1026
1027 ucontrol->value.integer.value[0] = volL;
1028 ucontrol->value.integer.value[1] = volR;
1029 return 0;
1030 }
1031
1032 static int snd_cs4281_put_volume(struct snd_kcontrol *kcontrol,
1033 struct snd_ctl_elem_value *ucontrol)
1034 {
1035 struct cs4281 *chip = snd_kcontrol_chip(kcontrol);
1036 int change = 0;
1037 int regL = (kcontrol->private_value >> 16) & 0xffff;
1038 int regR = kcontrol->private_value & 0xffff;
1039 int volL, volR;
1040
1041 volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK);
1042 volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK);
1043
1044 if (ucontrol->value.integer.value[0] != volL) {
1045 volL = CS_VOL_MASK - (ucontrol->value.integer.value[0] & CS_VOL_MASK);
1046 snd_cs4281_pokeBA0(chip, regL, volL);
1047 change = 1;
1048 }
1049 if (ucontrol->value.integer.value[1] != volR) {
1050 volR = CS_VOL_MASK - (ucontrol->value.integer.value[1] & CS_VOL_MASK);
1051 snd_cs4281_pokeBA0(chip, regR, volR);
1052 change = 1;
1053 }
1054 return change;
1055 }
1056
1057 static const DECLARE_TLV_DB_SCALE(db_scale_dsp, -4650, 150, 0);
1058
1059 static struct snd_kcontrol_new snd_cs4281_fm_vol =
1060 {
1061 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1062 .name = "Synth Playback Volume",
1063 .info = snd_cs4281_info_volume,
1064 .get = snd_cs4281_get_volume,
1065 .put = snd_cs4281_put_volume,
1066 .private_value = ((BA0_FMLVC << 16) | BA0_FMRVC),
1067 .tlv = { .p = db_scale_dsp },
1068 };
1069
1070 static struct snd_kcontrol_new snd_cs4281_pcm_vol =
1071 {
1072 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1073 .name = "PCM Stream Playback Volume",
1074 .info = snd_cs4281_info_volume,
1075 .get = snd_cs4281_get_volume,
1076 .put = snd_cs4281_put_volume,
1077 .private_value = ((BA0_PPLVC << 16) | BA0_PPRVC),
1078 .tlv = { .p = db_scale_dsp },
1079 };
1080
1081 static void snd_cs4281_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1082 {
1083 struct cs4281 *chip = bus->private_data;
1084 chip->ac97_bus = NULL;
1085 }
1086
1087 static void snd_cs4281_mixer_free_ac97(struct snd_ac97 *ac97)
1088 {
1089 struct cs4281 *chip = ac97->private_data;
1090 if (ac97->num)
1091 chip->ac97_secondary = NULL;
1092 else
1093 chip->ac97 = NULL;
1094 }
1095
1096 static int snd_cs4281_mixer(struct cs4281 *chip)
1097 {
1098 struct snd_card *card = chip->card;
1099 struct snd_ac97_template ac97;
1100 int err;
1101 static struct snd_ac97_bus_ops ops = {
1102 .write = snd_cs4281_ac97_write,
1103 .read = snd_cs4281_ac97_read,
1104 };
1105
1106 if ((err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus)) < 0)
1107 return err;
1108 chip->ac97_bus->private_free = snd_cs4281_mixer_free_ac97_bus;
1109
1110 memset(&ac97, 0, sizeof(ac97));
1111 ac97.private_data = chip;
1112 ac97.private_free = snd_cs4281_mixer_free_ac97;
1113 if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97)) < 0)
1114 return err;
1115 if (chip->dual_codec) {
1116 ac97.num = 1;
1117 if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97_secondary)) < 0)
1118 return err;
1119 }
1120 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_fm_vol, chip))) < 0)
1121 return err;
1122 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_pcm_vol, chip))) < 0)
1123 return err;
1124 return 0;
1125 }
1126
1127
1128 /*
1129 * proc interface
1130 */
1131
1132 static void snd_cs4281_proc_read(struct snd_info_entry *entry,
1133 struct snd_info_buffer *buffer)
1134 {
1135 struct cs4281 *chip = entry->private_data;
1136
1137 snd_iprintf(buffer, "Cirrus Logic CS4281\n\n");
1138 snd_iprintf(buffer, "Spurious half IRQs : %u\n", chip->spurious_dhtc_irq);
1139 snd_iprintf(buffer, "Spurious end IRQs : %u\n", chip->spurious_dtc_irq);
1140 }
1141
1142 static ssize_t snd_cs4281_BA0_read(struct snd_info_entry *entry,
1143 void *file_private_data,
1144 struct file *file, char __user *buf,
1145 size_t count, loff_t pos)
1146 {
1147 struct cs4281 *chip = entry->private_data;
1148
1149 if (copy_to_user_fromio(buf, chip->ba0 + pos, count))
1150 return -EFAULT;
1151 return count;
1152 }
1153
1154 static ssize_t snd_cs4281_BA1_read(struct snd_info_entry *entry,
1155 void *file_private_data,
1156 struct file *file, char __user *buf,
1157 size_t count, loff_t pos)
1158 {
1159 struct cs4281 *chip = entry->private_data;
1160
1161 if (copy_to_user_fromio(buf, chip->ba1 + pos, count))
1162 return -EFAULT;
1163 return count;
1164 }
1165
1166 static struct snd_info_entry_ops snd_cs4281_proc_ops_BA0 = {
1167 .read = snd_cs4281_BA0_read,
1168 };
1169
1170 static struct snd_info_entry_ops snd_cs4281_proc_ops_BA1 = {
1171 .read = snd_cs4281_BA1_read,
1172 };
1173
1174 static void snd_cs4281_proc_init(struct cs4281 *chip)
1175 {
1176 struct snd_info_entry *entry;
1177
1178 if (! snd_card_proc_new(chip->card, "cs4281", &entry))
1179 snd_info_set_text_ops(entry, chip, snd_cs4281_proc_read);
1180 if (! snd_card_proc_new(chip->card, "cs4281_BA0", &entry)) {
1181 entry->content = SNDRV_INFO_CONTENT_DATA;
1182 entry->private_data = chip;
1183 entry->c.ops = &snd_cs4281_proc_ops_BA0;
1184 entry->size = CS4281_BA0_SIZE;
1185 }
1186 if (! snd_card_proc_new(chip->card, "cs4281_BA1", &entry)) {
1187 entry->content = SNDRV_INFO_CONTENT_DATA;
1188 entry->private_data = chip;
1189 entry->c.ops = &snd_cs4281_proc_ops_BA1;
1190 entry->size = CS4281_BA1_SIZE;
1191 }
1192 }
1193
1194 /*
1195 * joystick support
1196 */
1197
1198 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
1199
1200 static void snd_cs4281_gameport_trigger(struct gameport *gameport)
1201 {
1202 struct cs4281 *chip = gameport_get_port_data(gameport);
1203
1204 if (snd_BUG_ON(!chip))
1205 return;
1206 snd_cs4281_pokeBA0(chip, BA0_JSPT, 0xff);
1207 }
1208
1209 static unsigned char snd_cs4281_gameport_read(struct gameport *gameport)
1210 {
1211 struct cs4281 *chip = gameport_get_port_data(gameport);
1212
1213 if (snd_BUG_ON(!chip))
1214 return 0;
1215 return snd_cs4281_peekBA0(chip, BA0_JSPT);
1216 }
1217
1218 #ifdef COOKED_MODE
1219 static int snd_cs4281_gameport_cooked_read(struct gameport *gameport,
1220 int *axes, int *buttons)
1221 {
1222 struct cs4281 *chip = gameport_get_port_data(gameport);
1223 unsigned js1, js2, jst;
1224
1225 if (snd_BUG_ON(!chip))
1226 return 0;
1227
1228 js1 = snd_cs4281_peekBA0(chip, BA0_JSC1);
1229 js2 = snd_cs4281_peekBA0(chip, BA0_JSC2);
1230 jst = snd_cs4281_peekBA0(chip, BA0_JSPT);
1231
1232 *buttons = (~jst >> 4) & 0x0F;
1233
1234 axes[0] = ((js1 & JSC1_Y1V_MASK) >> JSC1_Y1V_SHIFT) & 0xFFFF;
1235 axes[1] = ((js1 & JSC1_X1V_MASK) >> JSC1_X1V_SHIFT) & 0xFFFF;
1236 axes[2] = ((js2 & JSC2_Y2V_MASK) >> JSC2_Y2V_SHIFT) & 0xFFFF;
1237 axes[3] = ((js2 & JSC2_X2V_MASK) >> JSC2_X2V_SHIFT) & 0xFFFF;
1238
1239 for (jst = 0; jst < 4; ++jst)
1240 if (axes[jst] == 0xFFFF) axes[jst] = -1;
1241 return 0;
1242 }
1243 #else
1244 #define snd_cs4281_gameport_cooked_read NULL
1245 #endif
1246
1247 static int snd_cs4281_gameport_open(struct gameport *gameport, int mode)
1248 {
1249 switch (mode) {
1250 #ifdef COOKED_MODE
1251 case GAMEPORT_MODE_COOKED:
1252 return 0;
1253 #endif
1254 case GAMEPORT_MODE_RAW:
1255 return 0;
1256 default:
1257 return -1;
1258 }
1259 return 0;
1260 }
1261
1262 static int snd_cs4281_create_gameport(struct cs4281 *chip)
1263 {
1264 struct gameport *gp;
1265
1266 chip->gameport = gp = gameport_allocate_port();
1267 if (!gp) {
1268 printk(KERN_ERR "cs4281: cannot allocate memory for gameport\n");
1269 return -ENOMEM;
1270 }
1271
1272 gameport_set_name(gp, "CS4281 Gameport");
1273 gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
1274 gameport_set_dev_parent(gp, &chip->pci->dev);
1275 gp->open = snd_cs4281_gameport_open;
1276 gp->read = snd_cs4281_gameport_read;
1277 gp->trigger = snd_cs4281_gameport_trigger;
1278 gp->cooked_read = snd_cs4281_gameport_cooked_read;
1279 gameport_set_port_data(gp, chip);
1280
1281 snd_cs4281_pokeBA0(chip, BA0_JSIO, 0xFF); // ?
1282 snd_cs4281_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW);
1283
1284 gameport_register_port(gp);
1285
1286 return 0;
1287 }
1288
1289 static void snd_cs4281_free_gameport(struct cs4281 *chip)
1290 {
1291 if (chip->gameport) {
1292 gameport_unregister_port(chip->gameport);
1293 chip->gameport = NULL;
1294 }
1295 }
1296 #else
1297 static inline int snd_cs4281_create_gameport(struct cs4281 *chip) { return -ENOSYS; }
1298 static inline void snd_cs4281_free_gameport(struct cs4281 *chip) { }
1299 #endif /* CONFIG_GAMEPORT || (MODULE && CONFIG_GAMEPORT_MODULE) */
1300
1301 static int snd_cs4281_free(struct cs4281 *chip)
1302 {
1303 snd_cs4281_free_gameport(chip);
1304
1305 if (chip->irq >= 0)
1306 synchronize_irq(chip->irq);
1307
1308 /* Mask interrupts */
1309 snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff);
1310 /* Stop the DLL Clock logic. */
1311 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
1312 /* Sound System Power Management - Turn Everything OFF */
1313 snd_cs4281_pokeBA0(chip, BA0_SSPM, 0);
1314 /* PCI interface - D3 state */
1315 pci_set_power_state(chip->pci, 3);
1316
1317 if (chip->irq >= 0)
1318 free_irq(chip->irq, chip);
1319 if (chip->ba0)
1320 iounmap(chip->ba0);
1321 if (chip->ba1)
1322 iounmap(chip->ba1);
1323 pci_release_regions(chip->pci);
1324 pci_disable_device(chip->pci);
1325
1326 kfree(chip);
1327 return 0;
1328 }
1329
1330 static int snd_cs4281_dev_free(struct snd_device *device)
1331 {
1332 struct cs4281 *chip = device->device_data;
1333 return snd_cs4281_free(chip);
1334 }
1335
1336 static int snd_cs4281_chip_init(struct cs4281 *chip); /* defined below */
1337
1338 static int snd_cs4281_create(struct snd_card *card,
1339 struct pci_dev *pci,
1340 struct cs4281 **rchip,
1341 int dual_codec)
1342 {
1343 struct cs4281 *chip;
1344 unsigned int tmp;
1345 int err;
1346 static struct snd_device_ops ops = {
1347 .dev_free = snd_cs4281_dev_free,
1348 };
1349
1350 *rchip = NULL;
1351 if ((err = pci_enable_device(pci)) < 0)
1352 return err;
1353 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1354 if (chip == NULL) {
1355 pci_disable_device(pci);
1356 return -ENOMEM;
1357 }
1358 spin_lock_init(&chip->reg_lock);
1359 chip->card = card;
1360 chip->pci = pci;
1361 chip->irq = -1;
1362 pci_set_master(pci);
1363 if (dual_codec < 0 || dual_codec > 3) {
1364 snd_printk(KERN_ERR "invalid dual_codec option %d\n", dual_codec);
1365 dual_codec = 0;
1366 }
1367 chip->dual_codec = dual_codec;
1368
1369 if ((err = pci_request_regions(pci, "CS4281")) < 0) {
1370 kfree(chip);
1371 pci_disable_device(pci);
1372 return err;
1373 }
1374 chip->ba0_addr = pci_resource_start(pci, 0);
1375 chip->ba1_addr = pci_resource_start(pci, 1);
1376
1377 chip->ba0 = pci_ioremap_bar(pci, 0);
1378 chip->ba1 = pci_ioremap_bar(pci, 1);
1379 if (!chip->ba0 || !chip->ba1) {
1380 snd_cs4281_free(chip);
1381 return -ENOMEM;
1382 }
1383
1384 if (request_irq(pci->irq, snd_cs4281_interrupt, IRQF_SHARED,
1385 KBUILD_MODNAME, chip)) {
1386 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
1387 snd_cs4281_free(chip);
1388 return -ENOMEM;
1389 }
1390 chip->irq = pci->irq;
1391
1392 tmp = snd_cs4281_chip_init(chip);
1393 if (tmp) {
1394 snd_cs4281_free(chip);
1395 return tmp;
1396 }
1397
1398 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
1399 snd_cs4281_free(chip);
1400 return err;
1401 }
1402
1403 snd_cs4281_proc_init(chip);
1404
1405 snd_card_set_dev(card, &pci->dev);
1406
1407 *rchip = chip;
1408 return 0;
1409 }
1410
1411 static int snd_cs4281_chip_init(struct cs4281 *chip)
1412 {
1413 unsigned int tmp;
1414 unsigned long end_time;
1415 int retry_count = 2;
1416
1417 /* Having EPPMC.FPDN=1 prevent proper chip initialisation */
1418 tmp = snd_cs4281_peekBA0(chip, BA0_EPPMC);
1419 if (tmp & BA0_EPPMC_FPDN)
1420 snd_cs4281_pokeBA0(chip, BA0_EPPMC, tmp & ~BA0_EPPMC_FPDN);
1421
1422 __retry:
1423 tmp = snd_cs4281_peekBA0(chip, BA0_CFLR);
1424 if (tmp != BA0_CFLR_DEFAULT) {
1425 snd_cs4281_pokeBA0(chip, BA0_CFLR, BA0_CFLR_DEFAULT);
1426 tmp = snd_cs4281_peekBA0(chip, BA0_CFLR);
1427 if (tmp != BA0_CFLR_DEFAULT) {
1428 snd_printk(KERN_ERR "CFLR setup failed (0x%x)\n", tmp);
1429 return -EIO;
1430 }
1431 }
1432
1433 /* Set the 'Configuration Write Protect' register
1434 * to 4281h. Allows vendor-defined configuration
1435 * space between 0e4h and 0ffh to be written. */
1436 snd_cs4281_pokeBA0(chip, BA0_CWPR, 0x4281);
1437
1438 if ((tmp = snd_cs4281_peekBA0(chip, BA0_SERC1)) != (BA0_SERC1_SO1EN | BA0_SERC1_AC97)) {
1439 snd_printk(KERN_ERR "SERC1 AC'97 check failed (0x%x)\n", tmp);
1440 return -EIO;
1441 }
1442 if ((tmp = snd_cs4281_peekBA0(chip, BA0_SERC2)) != (BA0_SERC2_SI1EN | BA0_SERC2_AC97)) {
1443 snd_printk(KERN_ERR "SERC2 AC'97 check failed (0x%x)\n", tmp);
1444 return -EIO;
1445 }
1446
1447 /* Sound System Power Management */
1448 snd_cs4281_pokeBA0(chip, BA0_SSPM, BA0_SSPM_MIXEN | BA0_SSPM_CSRCEN |
1449 BA0_SSPM_PSRCEN | BA0_SSPM_JSEN |
1450 BA0_SSPM_ACLEN | BA0_SSPM_FMEN);
1451
1452 /* Serial Port Power Management */
1453 /* Blast the clock control register to zero so that the
1454 * PLL starts out in a known state, and blast the master serial
1455 * port control register to zero so that the serial ports also
1456 * start out in a known state. */
1457 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
1458 snd_cs4281_pokeBA0(chip, BA0_SERMC, 0);
1459
1460 /* Make ESYN go to zero to turn off
1461 * the Sync pulse on the AC97 link. */
1462 snd_cs4281_pokeBA0(chip, BA0_ACCTL, 0);
1463 udelay(50);
1464
1465 /* Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
1466 * spec) and then drive it high. This is done for non AC97 modes since
1467 * there might be logic external to the CS4281 that uses the ARST# line
1468 * for a reset. */
1469 snd_cs4281_pokeBA0(chip, BA0_SPMC, 0);
1470 udelay(50);
1471 snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN);
1472 msleep(50);
1473
1474 if (chip->dual_codec)
1475 snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN | BA0_SPMC_ASDI2E);
1476
1477 /*
1478 * Set the serial port timing configuration.
1479 */
1480 snd_cs4281_pokeBA0(chip, BA0_SERMC,
1481 (chip->dual_codec ? BA0_SERMC_TCID(chip->dual_codec) : BA0_SERMC_TCID(1)) |
1482 BA0_SERMC_PTC_AC97 | BA0_SERMC_MSPE);
1483
1484 /*
1485 * Start the DLL Clock logic.
1486 */
1487 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_DLLP);
1488 msleep(50);
1489 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_SWCE | BA0_CLKCR1_DLLP);
1490
1491 /*
1492 * Wait for the DLL ready signal from the clock logic.
1493 */
1494 end_time = jiffies + HZ;
1495 do {
1496 /*
1497 * Read the AC97 status register to see if we've seen a CODEC
1498 * signal from the AC97 codec.
1499 */
1500 if (snd_cs4281_peekBA0(chip, BA0_CLKCR1) & BA0_CLKCR1_DLLRDY)
1501 goto __ok0;
1502 schedule_timeout_uninterruptible(1);
1503 } while (time_after_eq(end_time, jiffies));
1504
1505 snd_printk(KERN_ERR "DLLRDY not seen\n");
1506 return -EIO;
1507
1508 __ok0:
1509
1510 /*
1511 * The first thing we do here is to enable sync generation. As soon
1512 * as we start receiving bit clock, we'll start producing the SYNC
1513 * signal.
1514 */
1515 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_ESYN);
1516
1517 /*
1518 * Wait for the codec ready signal from the AC97 codec.
1519 */
1520 end_time = jiffies + HZ;
1521 do {
1522 /*
1523 * Read the AC97 status register to see if we've seen a CODEC
1524 * signal from the AC97 codec.
1525 */
1526 if (snd_cs4281_peekBA0(chip, BA0_ACSTS) & BA0_ACSTS_CRDY)
1527 goto __ok1;
1528 schedule_timeout_uninterruptible(1);
1529 } while (time_after_eq(end_time, jiffies));
1530
1531 snd_printk(KERN_ERR "never read codec ready from AC'97 (0x%x)\n", snd_cs4281_peekBA0(chip, BA0_ACSTS));
1532 return -EIO;
1533
1534 __ok1:
1535 if (chip->dual_codec) {
1536 end_time = jiffies + HZ;
1537 do {
1538 if (snd_cs4281_peekBA0(chip, BA0_ACSTS2) & BA0_ACSTS_CRDY)
1539 goto __codec2_ok;
1540 schedule_timeout_uninterruptible(1);
1541 } while (time_after_eq(end_time, jiffies));
1542 snd_printk(KERN_INFO "secondary codec doesn't respond. disable it...\n");
1543 chip->dual_codec = 0;
1544 __codec2_ok: ;
1545 }
1546
1547 /*
1548 * Assert the valid frame signal so that we can start sending commands
1549 * to the AC97 codec.
1550 */
1551
1552 snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_VFRM | BA0_ACCTL_ESYN);
1553
1554 /*
1555 * Wait until we've sampled input slots 3 and 4 as valid, meaning that
1556 * the codec is pumping ADC data across the AC-link.
1557 */
1558
1559 end_time = jiffies + HZ;
1560 do {
1561 /*
1562 * Read the input slot valid register and see if input slots 3
1563 * 4 are valid yet.
1564 */
1565 if ((snd_cs4281_peekBA0(chip, BA0_ACISV) & (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4))) == (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4)))
1566 goto __ok2;
1567 schedule_timeout_uninterruptible(1);
1568 } while (time_after_eq(end_time, jiffies));
1569
1570 if (--retry_count > 0)
1571 goto __retry;
1572 snd_printk(KERN_ERR "never read ISV3 and ISV4 from AC'97\n");
1573 return -EIO;
1574
1575 __ok2:
1576
1577 /*
1578 * Now, assert valid frame and the slot 3 and 4 valid bits. This will
1579 * commense the transfer of digital audio data to the AC97 codec.
1580 */
1581 snd_cs4281_pokeBA0(chip, BA0_ACOSV, BA0_ACOSV_SLV(3) | BA0_ACOSV_SLV(4));
1582
1583 /*
1584 * Initialize DMA structures
1585 */
1586 for (tmp = 0; tmp < 4; tmp++) {
1587 struct cs4281_dma *dma = &chip->dma[tmp];
1588 dma->regDBA = BA0_DBA0 + (tmp * 0x10);
1589 dma->regDCA = BA0_DCA0 + (tmp * 0x10);
1590 dma->regDBC = BA0_DBC0 + (tmp * 0x10);
1591 dma->regDCC = BA0_DCC0 + (tmp * 0x10);
1592 dma->regDMR = BA0_DMR0 + (tmp * 8);
1593 dma->regDCR = BA0_DCR0 + (tmp * 8);
1594 dma->regHDSR = BA0_HDSR0 + (tmp * 4);
1595 dma->regFCR = BA0_FCR0 + (tmp * 4);
1596 dma->regFSIC = BA0_FSIC0 + (tmp * 4);
1597 dma->fifo_offset = tmp * CS4281_FIFO_SIZE;
1598 snd_cs4281_pokeBA0(chip, dma->regFCR,
1599 BA0_FCR_LS(31) |
1600 BA0_FCR_RS(31) |
1601 BA0_FCR_SZ(CS4281_FIFO_SIZE) |
1602 BA0_FCR_OF(dma->fifo_offset));
1603 }
1604
1605 chip->src_left_play_slot = 0; /* AC'97 left PCM playback (3) */
1606 chip->src_right_play_slot = 1; /* AC'97 right PCM playback (4) */
1607 chip->src_left_rec_slot = 10; /* AC'97 left PCM record (3) */
1608 chip->src_right_rec_slot = 11; /* AC'97 right PCM record (4) */
1609
1610 /* Activate wave playback FIFO for FM playback */
1611 chip->dma[0].valFCR = BA0_FCR_FEN | BA0_FCR_LS(0) |
1612 BA0_FCR_RS(1) |
1613 BA0_FCR_SZ(CS4281_FIFO_SIZE) |
1614 BA0_FCR_OF(chip->dma[0].fifo_offset);
1615 snd_cs4281_pokeBA0(chip, chip->dma[0].regFCR, chip->dma[0].valFCR);
1616 snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) |
1617 (chip->src_right_play_slot << 8) |
1618 (chip->src_left_rec_slot << 16) |
1619 (chip->src_right_rec_slot << 24));
1620
1621 /* Initialize digital volume */
1622 snd_cs4281_pokeBA0(chip, BA0_PPLVC, 0);
1623 snd_cs4281_pokeBA0(chip, BA0_PPRVC, 0);
1624
1625 /* Enable IRQs */
1626 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1627 /* Unmask interrupts */
1628 snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff & ~(
1629 BA0_HISR_MIDI |
1630 BA0_HISR_DMAI |
1631 BA0_HISR_DMA(0) |
1632 BA0_HISR_DMA(1) |
1633 BA0_HISR_DMA(2) |
1634 BA0_HISR_DMA(3)));
1635 synchronize_irq(chip->irq);
1636
1637 return 0;
1638 }
1639
1640 /*
1641 * MIDI section
1642 */
1643
1644 static void snd_cs4281_midi_reset(struct cs4281 *chip)
1645 {
1646 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr | BA0_MIDCR_MRST);
1647 udelay(100);
1648 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1649 }
1650
1651 static int snd_cs4281_midi_input_open(struct snd_rawmidi_substream *substream)
1652 {
1653 struct cs4281 *chip = substream->rmidi->private_data;
1654
1655 spin_lock_irq(&chip->reg_lock);
1656 chip->midcr |= BA0_MIDCR_RXE;
1657 chip->midi_input = substream;
1658 if (!(chip->uartm & CS4281_MODE_OUTPUT)) {
1659 snd_cs4281_midi_reset(chip);
1660 } else {
1661 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1662 }
1663 spin_unlock_irq(&chip->reg_lock);
1664 return 0;
1665 }
1666
1667 static int snd_cs4281_midi_input_close(struct snd_rawmidi_substream *substream)
1668 {
1669 struct cs4281 *chip = substream->rmidi->private_data;
1670
1671 spin_lock_irq(&chip->reg_lock);
1672 chip->midcr &= ~(BA0_MIDCR_RXE | BA0_MIDCR_RIE);
1673 chip->midi_input = NULL;
1674 if (!(chip->uartm & CS4281_MODE_OUTPUT)) {
1675 snd_cs4281_midi_reset(chip);
1676 } else {
1677 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1678 }
1679 chip->uartm &= ~CS4281_MODE_INPUT;
1680 spin_unlock_irq(&chip->reg_lock);
1681 return 0;
1682 }
1683
1684 static int snd_cs4281_midi_output_open(struct snd_rawmidi_substream *substream)
1685 {
1686 struct cs4281 *chip = substream->rmidi->private_data;
1687
1688 spin_lock_irq(&chip->reg_lock);
1689 chip->uartm |= CS4281_MODE_OUTPUT;
1690 chip->midcr |= BA0_MIDCR_TXE;
1691 chip->midi_output = substream;
1692 if (!(chip->uartm & CS4281_MODE_INPUT)) {
1693 snd_cs4281_midi_reset(chip);
1694 } else {
1695 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1696 }
1697 spin_unlock_irq(&chip->reg_lock);
1698 return 0;
1699 }
1700
1701 static int snd_cs4281_midi_output_close(struct snd_rawmidi_substream *substream)
1702 {
1703 struct cs4281 *chip = substream->rmidi->private_data;
1704
1705 spin_lock_irq(&chip->reg_lock);
1706 chip->midcr &= ~(BA0_MIDCR_TXE | BA0_MIDCR_TIE);
1707 chip->midi_output = NULL;
1708 if (!(chip->uartm & CS4281_MODE_INPUT)) {
1709 snd_cs4281_midi_reset(chip);
1710 } else {
1711 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1712 }
1713 chip->uartm &= ~CS4281_MODE_OUTPUT;
1714 spin_unlock_irq(&chip->reg_lock);
1715 return 0;
1716 }
1717
1718 static void snd_cs4281_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1719 {
1720 unsigned long flags;
1721 struct cs4281 *chip = substream->rmidi->private_data;
1722
1723 spin_lock_irqsave(&chip->reg_lock, flags);
1724 if (up) {
1725 if ((chip->midcr & BA0_MIDCR_RIE) == 0) {
1726 chip->midcr |= BA0_MIDCR_RIE;
1727 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1728 }
1729 } else {
1730 if (chip->midcr & BA0_MIDCR_RIE) {
1731 chip->midcr &= ~BA0_MIDCR_RIE;
1732 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1733 }
1734 }
1735 spin_unlock_irqrestore(&chip->reg_lock, flags);
1736 }
1737
1738 static void snd_cs4281_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1739 {
1740 unsigned long flags;
1741 struct cs4281 *chip = substream->rmidi->private_data;
1742 unsigned char byte;
1743
1744 spin_lock_irqsave(&chip->reg_lock, flags);
1745 if (up) {
1746 if ((chip->midcr & BA0_MIDCR_TIE) == 0) {
1747 chip->midcr |= BA0_MIDCR_TIE;
1748 /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
1749 while ((chip->midcr & BA0_MIDCR_TIE) &&
1750 (snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) {
1751 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
1752 chip->midcr &= ~BA0_MIDCR_TIE;
1753 } else {
1754 snd_cs4281_pokeBA0(chip, BA0_MIDWP, byte);
1755 }
1756 }
1757 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1758 }
1759 } else {
1760 if (chip->midcr & BA0_MIDCR_TIE) {
1761 chip->midcr &= ~BA0_MIDCR_TIE;
1762 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1763 }
1764 }
1765 spin_unlock_irqrestore(&chip->reg_lock, flags);
1766 }
1767
1768 static struct snd_rawmidi_ops snd_cs4281_midi_output =
1769 {
1770 .open = snd_cs4281_midi_output_open,
1771 .close = snd_cs4281_midi_output_close,
1772 .trigger = snd_cs4281_midi_output_trigger,
1773 };
1774
1775 static struct snd_rawmidi_ops snd_cs4281_midi_input =
1776 {
1777 .open = snd_cs4281_midi_input_open,
1778 .close = snd_cs4281_midi_input_close,
1779 .trigger = snd_cs4281_midi_input_trigger,
1780 };
1781
1782 static int snd_cs4281_midi(struct cs4281 *chip, int device,
1783 struct snd_rawmidi **rrawmidi)
1784 {
1785 struct snd_rawmidi *rmidi;
1786 int err;
1787
1788 if (rrawmidi)
1789 *rrawmidi = NULL;
1790 if ((err = snd_rawmidi_new(chip->card, "CS4281", device, 1, 1, &rmidi)) < 0)
1791 return err;
1792 strcpy(rmidi->name, "CS4281");
1793 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_cs4281_midi_output);
1794 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_cs4281_midi_input);
1795 rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX;
1796 rmidi->private_data = chip;
1797 chip->rmidi = rmidi;
1798 if (rrawmidi)
1799 *rrawmidi = rmidi;
1800 return 0;
1801 }
1802
1803 /*
1804 * Interrupt handler
1805 */
1806
1807 static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id)
1808 {
1809 struct cs4281 *chip = dev_id;
1810 unsigned int status, dma, val;
1811 struct cs4281_dma *cdma;
1812
1813 if (chip == NULL)
1814 return IRQ_NONE;
1815 status = snd_cs4281_peekBA0(chip, BA0_HISR);
1816 if ((status & 0x7fffffff) == 0) {
1817 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1818 return IRQ_NONE;
1819 }
1820
1821 if (status & (BA0_HISR_DMA(0)|BA0_HISR_DMA(1)|BA0_HISR_DMA(2)|BA0_HISR_DMA(3))) {
1822 for (dma = 0; dma < 4; dma++)
1823 if (status & BA0_HISR_DMA(dma)) {
1824 cdma = &chip->dma[dma];
1825 spin_lock(&chip->reg_lock);
1826 /* ack DMA IRQ */
1827 val = snd_cs4281_peekBA0(chip, cdma->regHDSR);
1828 /* workaround, sometimes CS4281 acknowledges */
1829 /* end or middle transfer position twice */
1830 cdma->frag++;
1831 if ((val & BA0_HDSR_DHTC) && !(cdma->frag & 1)) {
1832 cdma->frag--;
1833 chip->spurious_dhtc_irq++;
1834 spin_unlock(&chip->reg_lock);
1835 continue;
1836 }
1837 if ((val & BA0_HDSR_DTC) && (cdma->frag & 1)) {
1838 cdma->frag--;
1839 chip->spurious_dtc_irq++;
1840 spin_unlock(&chip->reg_lock);
1841 continue;
1842 }
1843 spin_unlock(&chip->reg_lock);
1844 snd_pcm_period_elapsed(cdma->substream);
1845 }
1846 }
1847
1848 if ((status & BA0_HISR_MIDI) && chip->rmidi) {
1849 unsigned char c;
1850
1851 spin_lock(&chip->reg_lock);
1852 while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_RBE) == 0) {
1853 c = snd_cs4281_peekBA0(chip, BA0_MIDRP);
1854 if ((chip->midcr & BA0_MIDCR_RIE) == 0)
1855 continue;
1856 snd_rawmidi_receive(chip->midi_input, &c, 1);
1857 }
1858 while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) {
1859 if ((chip->midcr & BA0_MIDCR_TIE) == 0)
1860 break;
1861 if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) {
1862 chip->midcr &= ~BA0_MIDCR_TIE;
1863 snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1864 break;
1865 }
1866 snd_cs4281_pokeBA0(chip, BA0_MIDWP, c);
1867 }
1868 spin_unlock(&chip->reg_lock);
1869 }
1870
1871 /* EOI to the PCI part... reenables interrupts */
1872 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
1873
1874 return IRQ_HANDLED;
1875 }
1876
1877
1878 /*
1879 * OPL3 command
1880 */
1881 static void snd_cs4281_opl3_command(struct snd_opl3 *opl3, unsigned short cmd,
1882 unsigned char val)
1883 {
1884 unsigned long flags;
1885 struct cs4281 *chip = opl3->private_data;
1886 void __iomem *port;
1887
1888 if (cmd & OPL3_RIGHT)
1889 port = chip->ba0 + BA0_B1AP; /* right port */
1890 else
1891 port = chip->ba0 + BA0_B0AP; /* left port */
1892
1893 spin_lock_irqsave(&opl3->reg_lock, flags);
1894
1895 writel((unsigned int)cmd, port);
1896 udelay(10);
1897
1898 writel((unsigned int)val, port + 4);
1899 udelay(30);
1900
1901 spin_unlock_irqrestore(&opl3->reg_lock, flags);
1902 }
1903
1904 static int snd_cs4281_probe(struct pci_dev *pci,
1905 const struct pci_device_id *pci_id)
1906 {
1907 static int dev;
1908 struct snd_card *card;
1909 struct cs4281 *chip;
1910 struct snd_opl3 *opl3;
1911 int err;
1912
1913 if (dev >= SNDRV_CARDS)
1914 return -ENODEV;
1915 if (!enable[dev]) {
1916 dev++;
1917 return -ENOENT;
1918 }
1919
1920 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
1921 if (err < 0)
1922 return err;
1923
1924 if ((err = snd_cs4281_create(card, pci, &chip, dual_codec[dev])) < 0) {
1925 snd_card_free(card);
1926 return err;
1927 }
1928 card->private_data = chip;
1929
1930 if ((err = snd_cs4281_mixer(chip)) < 0) {
1931 snd_card_free(card);
1932 return err;
1933 }
1934 if ((err = snd_cs4281_pcm(chip, 0, NULL)) < 0) {
1935 snd_card_free(card);
1936 return err;
1937 }
1938 if ((err = snd_cs4281_midi(chip, 0, NULL)) < 0) {
1939 snd_card_free(card);
1940 return err;
1941 }
1942 if ((err = snd_opl3_new(card, OPL3_HW_OPL3_CS4281, &opl3)) < 0) {
1943 snd_card_free(card);
1944 return err;
1945 }
1946 opl3->private_data = chip;
1947 opl3->command = snd_cs4281_opl3_command;
1948 snd_opl3_init(opl3);
1949 if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
1950 snd_card_free(card);
1951 return err;
1952 }
1953 snd_cs4281_create_gameport(chip);
1954 strcpy(card->driver, "CS4281");
1955 strcpy(card->shortname, "Cirrus Logic CS4281");
1956 sprintf(card->longname, "%s at 0x%lx, irq %d",
1957 card->shortname,
1958 chip->ba0_addr,
1959 chip->irq);
1960
1961 if ((err = snd_card_register(card)) < 0) {
1962 snd_card_free(card);
1963 return err;
1964 }
1965
1966 pci_set_drvdata(pci, card);
1967 dev++;
1968 return 0;
1969 }
1970
1971 static void snd_cs4281_remove(struct pci_dev *pci)
1972 {
1973 snd_card_free(pci_get_drvdata(pci));
1974 pci_set_drvdata(pci, NULL);
1975 }
1976
1977 /*
1978 * Power Management
1979 */
1980 #ifdef CONFIG_PM_SLEEP
1981
1982 static int saved_regs[SUSPEND_REGISTERS] = {
1983 BA0_JSCTL,
1984 BA0_GPIOR,
1985 BA0_SSCR,
1986 BA0_MIDCR,
1987 BA0_SRCSA,
1988 BA0_PASR,
1989 BA0_CASR,
1990 BA0_DACSR,
1991 BA0_ADCSR,
1992 BA0_FMLVC,
1993 BA0_FMRVC,
1994 BA0_PPLVC,
1995 BA0_PPRVC,
1996 };
1997
1998 #define CLKCR1_CKRA 0x00010000L
1999
2000 static int cs4281_suspend(struct device *dev)
2001 {
2002 struct pci_dev *pci = to_pci_dev(dev);
2003 struct snd_card *card = dev_get_drvdata(dev);
2004 struct cs4281 *chip = card->private_data;
2005 u32 ulCLK;
2006 unsigned int i;
2007
2008 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2009 snd_pcm_suspend_all(chip->pcm);
2010
2011 snd_ac97_suspend(chip->ac97);
2012 snd_ac97_suspend(chip->ac97_secondary);
2013
2014 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2015 ulCLK |= CLKCR1_CKRA;
2016 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2017
2018 /* Disable interrupts. */
2019 snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_CHGM);
2020
2021 /* remember the status registers */
2022 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
2023 if (saved_regs[i])
2024 chip->suspend_regs[i] = snd_cs4281_peekBA0(chip, saved_regs[i]);
2025
2026 /* Turn off the serial ports. */
2027 snd_cs4281_pokeBA0(chip, BA0_SERMC, 0);
2028
2029 /* Power off FM, Joystick, AC link, */
2030 snd_cs4281_pokeBA0(chip, BA0_SSPM, 0);
2031
2032 /* DLL off. */
2033 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
2034
2035 /* AC link off. */
2036 snd_cs4281_pokeBA0(chip, BA0_SPMC, 0);
2037
2038 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2039 ulCLK &= ~CLKCR1_CKRA;
2040 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2041
2042 pci_disable_device(pci);
2043 pci_save_state(pci);
2044 pci_set_power_state(pci, PCI_D3hot);
2045 return 0;
2046 }
2047
2048 static int cs4281_resume(struct device *dev)
2049 {
2050 struct pci_dev *pci = to_pci_dev(dev);
2051 struct snd_card *card = dev_get_drvdata(dev);
2052 struct cs4281 *chip = card->private_data;
2053 unsigned int i;
2054 u32 ulCLK;
2055
2056 pci_set_power_state(pci, PCI_D0);
2057 pci_restore_state(pci);
2058 if (pci_enable_device(pci) < 0) {
2059 printk(KERN_ERR "cs4281: pci_enable_device failed, "
2060 "disabling device\n");
2061 snd_card_disconnect(card);
2062 return -EIO;
2063 }
2064 pci_set_master(pci);
2065
2066 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2067 ulCLK |= CLKCR1_CKRA;
2068 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2069
2070 snd_cs4281_chip_init(chip);
2071
2072 /* restore the status registers */
2073 for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
2074 if (saved_regs[i])
2075 snd_cs4281_pokeBA0(chip, saved_regs[i], chip->suspend_regs[i]);
2076
2077 snd_ac97_resume(chip->ac97);
2078 snd_ac97_resume(chip->ac97_secondary);
2079
2080 ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
2081 ulCLK &= ~CLKCR1_CKRA;
2082 snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
2083
2084 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2085 return 0;
2086 }
2087
2088 static SIMPLE_DEV_PM_OPS(cs4281_pm, cs4281_suspend, cs4281_resume);
2089 #define CS4281_PM_OPS &cs4281_pm
2090 #else
2091 #define CS4281_PM_OPS NULL
2092 #endif /* CONFIG_PM_SLEEP */
2093
2094 static struct pci_driver cs4281_driver = {
2095 .name = KBUILD_MODNAME,
2096 .id_table = snd_cs4281_ids,
2097 .probe = snd_cs4281_probe,
2098 .remove = snd_cs4281_remove,
2099 .driver = {
2100 .pm = CS4281_PM_OPS,
2101 },
2102 };
2103
2104 module_pci_driver(cs4281_driver);
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